phy-omap-control.c 9.0 KB

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  1. // SPDX-License-Identifier: GPL-2.0-or-later
  2. /*
  3. * omap-control-phy.c - The PHY part of control module.
  4. *
  5. * Copyright (C) 2013 Texas Instruments Incorporated - http://www.ti.com
  6. * Author: Kishon Vijay Abraham I <kishon@ti.com>
  7. */
  8. #include <linux/module.h>
  9. #include <linux/platform_device.h>
  10. #include <linux/slab.h>
  11. #include <linux/of.h>
  12. #include <linux/of_device.h>
  13. #include <linux/err.h>
  14. #include <linux/io.h>
  15. #include <linux/clk.h>
  16. #include <linux/phy/omap_control_phy.h>
  17. /**
  18. * omap_control_pcie_pcs - set the PCS delay count
  19. * @dev: the control module device
  20. * @delay: 8 bit delay value
  21. */
  22. void omap_control_pcie_pcs(struct device *dev, u8 delay)
  23. {
  24. u32 val;
  25. struct omap_control_phy *control_phy;
  26. if (IS_ERR(dev) || !dev) {
  27. pr_err("%s: invalid device\n", __func__);
  28. return;
  29. }
  30. control_phy = dev_get_drvdata(dev);
  31. if (!control_phy) {
  32. dev_err(dev, "%s: invalid control phy device\n", __func__);
  33. return;
  34. }
  35. if (control_phy->type != OMAP_CTRL_TYPE_PCIE) {
  36. dev_err(dev, "%s: unsupported operation\n", __func__);
  37. return;
  38. }
  39. val = readl(control_phy->pcie_pcs);
  40. val &= ~(OMAP_CTRL_PCIE_PCS_MASK <<
  41. OMAP_CTRL_PCIE_PCS_DELAY_COUNT_SHIFT);
  42. val |= (delay << OMAP_CTRL_PCIE_PCS_DELAY_COUNT_SHIFT);
  43. writel(val, control_phy->pcie_pcs);
  44. }
  45. EXPORT_SYMBOL_GPL(omap_control_pcie_pcs);
  46. /**
  47. * omap_control_phy_power - power on/off the phy using control module reg
  48. * @dev: the control module device
  49. * @on: 0 or 1, based on powering on or off the PHY
  50. */
  51. void omap_control_phy_power(struct device *dev, int on)
  52. {
  53. u32 val;
  54. unsigned long rate;
  55. struct omap_control_phy *control_phy;
  56. if (IS_ERR(dev) || !dev) {
  57. pr_err("%s: invalid device\n", __func__);
  58. return;
  59. }
  60. control_phy = dev_get_drvdata(dev);
  61. if (!control_phy) {
  62. dev_err(dev, "%s: invalid control phy device\n", __func__);
  63. return;
  64. }
  65. if (control_phy->type == OMAP_CTRL_TYPE_OTGHS)
  66. return;
  67. val = readl(control_phy->power);
  68. switch (control_phy->type) {
  69. case OMAP_CTRL_TYPE_USB2:
  70. if (on)
  71. val &= ~OMAP_CTRL_DEV_PHY_PD;
  72. else
  73. val |= OMAP_CTRL_DEV_PHY_PD;
  74. break;
  75. case OMAP_CTRL_TYPE_PCIE:
  76. case OMAP_CTRL_TYPE_PIPE3:
  77. rate = clk_get_rate(control_phy->sys_clk);
  78. rate = rate/1000000;
  79. if (on) {
  80. val &= ~(OMAP_CTRL_PIPE3_PHY_PWRCTL_CLK_CMD_MASK |
  81. OMAP_CTRL_PIPE3_PHY_PWRCTL_CLK_FREQ_MASK);
  82. val |= OMAP_CTRL_PIPE3_PHY_TX_RX_POWERON <<
  83. OMAP_CTRL_PIPE3_PHY_PWRCTL_CLK_CMD_SHIFT;
  84. val |= rate <<
  85. OMAP_CTRL_PIPE3_PHY_PWRCTL_CLK_FREQ_SHIFT;
  86. } else {
  87. val &= ~OMAP_CTRL_PIPE3_PHY_PWRCTL_CLK_CMD_MASK;
  88. val |= OMAP_CTRL_PIPE3_PHY_TX_RX_POWEROFF <<
  89. OMAP_CTRL_PIPE3_PHY_PWRCTL_CLK_CMD_SHIFT;
  90. }
  91. break;
  92. case OMAP_CTRL_TYPE_DRA7USB2:
  93. if (on)
  94. val &= ~OMAP_CTRL_USB2_PHY_PD;
  95. else
  96. val |= OMAP_CTRL_USB2_PHY_PD;
  97. break;
  98. case OMAP_CTRL_TYPE_AM437USB2:
  99. if (on) {
  100. val &= ~(AM437X_CTRL_USB2_PHY_PD |
  101. AM437X_CTRL_USB2_OTG_PD);
  102. val |= (AM437X_CTRL_USB2_OTGVDET_EN |
  103. AM437X_CTRL_USB2_OTGSESSEND_EN);
  104. } else {
  105. val &= ~(AM437X_CTRL_USB2_OTGVDET_EN |
  106. AM437X_CTRL_USB2_OTGSESSEND_EN);
  107. val |= (AM437X_CTRL_USB2_PHY_PD |
  108. AM437X_CTRL_USB2_OTG_PD);
  109. }
  110. break;
  111. default:
  112. dev_err(dev, "%s: type %d not recognized\n",
  113. __func__, control_phy->type);
  114. break;
  115. }
  116. writel(val, control_phy->power);
  117. }
  118. EXPORT_SYMBOL_GPL(omap_control_phy_power);
  119. /**
  120. * omap_control_usb_host_mode - set AVALID, VBUSVALID and ID pin in grounded
  121. * @ctrl_phy: struct omap_control_phy *
  122. *
  123. * Writes to the mailbox register to notify the usb core that a usb
  124. * device has been connected.
  125. */
  126. static void omap_control_usb_host_mode(struct omap_control_phy *ctrl_phy)
  127. {
  128. u32 val;
  129. val = readl(ctrl_phy->otghs_control);
  130. val &= ~(OMAP_CTRL_DEV_IDDIG | OMAP_CTRL_DEV_SESSEND);
  131. val |= OMAP_CTRL_DEV_AVALID | OMAP_CTRL_DEV_VBUSVALID;
  132. writel(val, ctrl_phy->otghs_control);
  133. }
  134. /**
  135. * omap_control_usb_device_mode - set AVALID, VBUSVALID and ID pin in high
  136. * impedance
  137. * @ctrl_phy: struct omap_control_phy *
  138. *
  139. * Writes to the mailbox register to notify the usb core that it has been
  140. * connected to a usb host.
  141. */
  142. static void omap_control_usb_device_mode(struct omap_control_phy *ctrl_phy)
  143. {
  144. u32 val;
  145. val = readl(ctrl_phy->otghs_control);
  146. val &= ~OMAP_CTRL_DEV_SESSEND;
  147. val |= OMAP_CTRL_DEV_IDDIG | OMAP_CTRL_DEV_AVALID |
  148. OMAP_CTRL_DEV_VBUSVALID;
  149. writel(val, ctrl_phy->otghs_control);
  150. }
  151. /**
  152. * omap_control_usb_set_sessionend - Enable SESSIONEND and IDIG to high
  153. * impedance
  154. * @ctrl_phy: struct omap_control_phy *
  155. *
  156. * Writes to the mailbox register to notify the usb core it's now in
  157. * disconnected state.
  158. */
  159. static void omap_control_usb_set_sessionend(struct omap_control_phy *ctrl_phy)
  160. {
  161. u32 val;
  162. val = readl(ctrl_phy->otghs_control);
  163. val &= ~(OMAP_CTRL_DEV_AVALID | OMAP_CTRL_DEV_VBUSVALID);
  164. val |= OMAP_CTRL_DEV_IDDIG | OMAP_CTRL_DEV_SESSEND;
  165. writel(val, ctrl_phy->otghs_control);
  166. }
  167. /**
  168. * omap_control_usb_set_mode - Calls to functions to set USB in one of host mode
  169. * or device mode or to denote disconnected state
  170. * @dev: the control module device
  171. * @mode: The mode to which usb should be configured
  172. *
  173. * This is an API to write to the mailbox register to notify the usb core that
  174. * a usb device has been connected.
  175. */
  176. void omap_control_usb_set_mode(struct device *dev,
  177. enum omap_control_usb_mode mode)
  178. {
  179. struct omap_control_phy *ctrl_phy;
  180. if (IS_ERR(dev) || !dev)
  181. return;
  182. ctrl_phy = dev_get_drvdata(dev);
  183. if (!ctrl_phy) {
  184. dev_err(dev, "Invalid control phy device\n");
  185. return;
  186. }
  187. if (ctrl_phy->type != OMAP_CTRL_TYPE_OTGHS)
  188. return;
  189. switch (mode) {
  190. case USB_MODE_HOST:
  191. omap_control_usb_host_mode(ctrl_phy);
  192. break;
  193. case USB_MODE_DEVICE:
  194. omap_control_usb_device_mode(ctrl_phy);
  195. break;
  196. case USB_MODE_DISCONNECT:
  197. omap_control_usb_set_sessionend(ctrl_phy);
  198. break;
  199. default:
  200. dev_vdbg(dev, "invalid omap control usb mode\n");
  201. }
  202. }
  203. EXPORT_SYMBOL_GPL(omap_control_usb_set_mode);
  204. static const enum omap_control_phy_type otghs_data = OMAP_CTRL_TYPE_OTGHS;
  205. static const enum omap_control_phy_type usb2_data = OMAP_CTRL_TYPE_USB2;
  206. static const enum omap_control_phy_type pipe3_data = OMAP_CTRL_TYPE_PIPE3;
  207. static const enum omap_control_phy_type pcie_data = OMAP_CTRL_TYPE_PCIE;
  208. static const enum omap_control_phy_type dra7usb2_data = OMAP_CTRL_TYPE_DRA7USB2;
  209. static const enum omap_control_phy_type am437usb2_data = OMAP_CTRL_TYPE_AM437USB2;
  210. static const struct of_device_id omap_control_phy_id_table[] = {
  211. {
  212. .compatible = "ti,control-phy-otghs",
  213. .data = &otghs_data,
  214. },
  215. {
  216. .compatible = "ti,control-phy-usb2",
  217. .data = &usb2_data,
  218. },
  219. {
  220. .compatible = "ti,control-phy-pipe3",
  221. .data = &pipe3_data,
  222. },
  223. {
  224. .compatible = "ti,control-phy-pcie",
  225. .data = &pcie_data,
  226. },
  227. {
  228. .compatible = "ti,control-phy-usb2-dra7",
  229. .data = &dra7usb2_data,
  230. },
  231. {
  232. .compatible = "ti,control-phy-usb2-am437",
  233. .data = &am437usb2_data,
  234. },
  235. {},
  236. };
  237. MODULE_DEVICE_TABLE(of, omap_control_phy_id_table);
  238. static int omap_control_phy_probe(struct platform_device *pdev)
  239. {
  240. struct resource *res;
  241. const struct of_device_id *of_id;
  242. struct omap_control_phy *control_phy;
  243. of_id = of_match_device(omap_control_phy_id_table, &pdev->dev);
  244. if (!of_id)
  245. return -EINVAL;
  246. control_phy = devm_kzalloc(&pdev->dev, sizeof(*control_phy),
  247. GFP_KERNEL);
  248. if (!control_phy)
  249. return -ENOMEM;
  250. control_phy->dev = &pdev->dev;
  251. control_phy->type = *(enum omap_control_phy_type *)of_id->data;
  252. if (control_phy->type == OMAP_CTRL_TYPE_OTGHS) {
  253. res = platform_get_resource_byname(pdev, IORESOURCE_MEM,
  254. "otghs_control");
  255. control_phy->otghs_control = devm_ioremap_resource(
  256. &pdev->dev, res);
  257. if (IS_ERR(control_phy->otghs_control))
  258. return PTR_ERR(control_phy->otghs_control);
  259. } else {
  260. res = platform_get_resource_byname(pdev, IORESOURCE_MEM,
  261. "power");
  262. control_phy->power = devm_ioremap_resource(&pdev->dev, res);
  263. if (IS_ERR(control_phy->power)) {
  264. dev_err(&pdev->dev, "Couldn't get power register\n");
  265. return PTR_ERR(control_phy->power);
  266. }
  267. }
  268. if (control_phy->type == OMAP_CTRL_TYPE_PIPE3 ||
  269. control_phy->type == OMAP_CTRL_TYPE_PCIE) {
  270. control_phy->sys_clk = devm_clk_get(control_phy->dev,
  271. "sys_clkin");
  272. if (IS_ERR(control_phy->sys_clk)) {
  273. pr_err("%s: unable to get sys_clkin\n", __func__);
  274. return -EINVAL;
  275. }
  276. }
  277. if (control_phy->type == OMAP_CTRL_TYPE_PCIE) {
  278. res = platform_get_resource_byname(pdev, IORESOURCE_MEM,
  279. "pcie_pcs");
  280. control_phy->pcie_pcs = devm_ioremap_resource(&pdev->dev, res);
  281. if (IS_ERR(control_phy->pcie_pcs))
  282. return PTR_ERR(control_phy->pcie_pcs);
  283. }
  284. dev_set_drvdata(control_phy->dev, control_phy);
  285. return 0;
  286. }
  287. static struct platform_driver omap_control_phy_driver = {
  288. .probe = omap_control_phy_probe,
  289. .driver = {
  290. .name = "omap-control-phy",
  291. .of_match_table = omap_control_phy_id_table,
  292. },
  293. };
  294. static int __init omap_control_phy_init(void)
  295. {
  296. return platform_driver_register(&omap_control_phy_driver);
  297. }
  298. subsys_initcall(omap_control_phy_init);
  299. static void __exit omap_control_phy_exit(void)
  300. {
  301. platform_driver_unregister(&omap_control_phy_driver);
  302. }
  303. module_exit(omap_control_phy_exit);
  304. MODULE_ALIAS("platform:omap_control_phy");
  305. MODULE_AUTHOR("Texas Instruments Inc.");
  306. MODULE_DESCRIPTION("OMAP Control Module PHY Driver");
  307. MODULE_LICENSE("GPL v2");