phy-j721e-wiz.c 25 KB

1234567891011121314151617181920212223242526272829303132333435363738394041424344454647484950515253545556575859606162636465666768697071727374757677787980818283848586878889909192939495969798991001011021031041051061071081091101111121131141151161171181191201211221231241251261271281291301311321331341351361371381391401411421431441451461471481491501511521531541551561571581591601611621631641651661671681691701711721731741751761771781791801811821831841851861871881891901911921931941951961971981992002012022032042052062072082092102112122132142152162172182192202212222232242252262272282292302312322332342352362372382392402412422432442452462472482492502512522532542552562572582592602612622632642652662672682692702712722732742752762772782792802812822832842852862872882892902912922932942952962972982993003013023033043053063073083093103113123133143153163173183193203213223233243253263273283293303313323333343353363373383393403413423433443453463473483493503513523533543553563573583593603613623633643653663673683693703713723733743753763773783793803813823833843853863873883893903913923933943953963973983994004014024034044054064074084094104114124134144154164174184194204214224234244254264274284294304314324334344354364374384394404414424434444454464474484494504514524534544554564574584594604614624634644654664674684694704714724734744754764774784794804814824834844854864874884894904914924934944954964974984995005015025035045055065075085095105115125135145155165175185195205215225235245255265275285295305315325335345355365375385395405415425435445455465475485495505515525535545555565575585595605615625635645655665675685695705715725735745755765775785795805815825835845855865875885895905915925935945955965975985996006016026036046056066076086096106116126136146156166176186196206216226236246256266276286296306316326336346356366376386396406416426436446456466476486496506516526536546556566576586596606616626636646656666676686696706716726736746756766776786796806816826836846856866876886896906916926936946956966976986997007017027037047057067077087097107117127137147157167177187197207217227237247257267277287297307317327337347357367377387397407417427437447457467477487497507517527537547557567577587597607617627637647657667677687697707717727737747757767777787797807817827837847857867877887897907917927937947957967977987998008018028038048058068078088098108118128138148158168178188198208218228238248258268278288298308318328338348358368378388398408418428438448458468478488498508518528538548558568578588598608618628638648658668678688698708718728738748758768778788798808818828838848858868878888898908918928938948958968978988999009019029039049059069079089099109119129139149159169179189199209219229239249259269279289299309319329339349359369379389399409419429439449459469479489499509519529539549559569579589599609619629639649659669679689699709719729739749759769779789799809819829839849859869879889899909919929939949959969979989991000100110021003100410051006100710081009101010111012101310141015101610171018
  1. // SPDX-License-Identifier: GPL-2.0
  2. /**
  3. * Wrapper driver for SERDES used in J721E
  4. *
  5. * Copyright (C) 2019 Texas Instruments Incorporated - http://www.ti.com/
  6. * Author: Kishon Vijay Abraham I <kishon@ti.com>
  7. */
  8. #include <dt-bindings/phy/phy.h>
  9. #include <linux/clk.h>
  10. #include <linux/clk-provider.h>
  11. #include <linux/gpio.h>
  12. #include <linux/gpio/consumer.h>
  13. #include <linux/io.h>
  14. #include <linux/module.h>
  15. #include <linux/mux/consumer.h>
  16. #include <linux/of_address.h>
  17. #include <linux/of_platform.h>
  18. #include <linux/platform_device.h>
  19. #include <linux/pm_runtime.h>
  20. #include <linux/regmap.h>
  21. #include <linux/reset-controller.h>
  22. #define WIZ_SERDES_CTRL 0x404
  23. #define WIZ_SERDES_TOP_CTRL 0x408
  24. #define WIZ_SERDES_RST 0x40c
  25. #define WIZ_SERDES_TYPEC 0x410
  26. #define WIZ_LANECTL(n) (0x480 + (0x40 * (n)))
  27. #define WIZ_MAX_LANES 4
  28. #define WIZ_MUX_NUM_CLOCKS 3
  29. #define WIZ_DIV_NUM_CLOCKS_16G 2
  30. #define WIZ_DIV_NUM_CLOCKS_10G 1
  31. #define WIZ_SERDES_TYPEC_LN10_SWAP BIT(30)
  32. enum wiz_lane_standard_mode {
  33. LANE_MODE_GEN1,
  34. LANE_MODE_GEN2,
  35. LANE_MODE_GEN3,
  36. LANE_MODE_GEN4,
  37. };
  38. enum wiz_refclk_mux_sel {
  39. PLL0_REFCLK,
  40. PLL1_REFCLK,
  41. REFCLK_DIG,
  42. };
  43. enum wiz_refclk_div_sel {
  44. CMN_REFCLK_DIG_DIV,
  45. CMN_REFCLK1_DIG_DIV,
  46. };
  47. static const struct reg_field por_en = REG_FIELD(WIZ_SERDES_CTRL, 31, 31);
  48. static const struct reg_field phy_reset_n = REG_FIELD(WIZ_SERDES_RST, 31, 31);
  49. static const struct reg_field pll1_refclk_mux_sel =
  50. REG_FIELD(WIZ_SERDES_RST, 29, 29);
  51. static const struct reg_field pll0_refclk_mux_sel =
  52. REG_FIELD(WIZ_SERDES_RST, 28, 28);
  53. static const struct reg_field refclk_dig_sel_16g =
  54. REG_FIELD(WIZ_SERDES_RST, 24, 25);
  55. static const struct reg_field refclk_dig_sel_10g =
  56. REG_FIELD(WIZ_SERDES_RST, 24, 24);
  57. static const struct reg_field pma_cmn_refclk_int_mode =
  58. REG_FIELD(WIZ_SERDES_TOP_CTRL, 28, 29);
  59. static const struct reg_field pma_cmn_refclk_mode =
  60. REG_FIELD(WIZ_SERDES_TOP_CTRL, 30, 31);
  61. static const struct reg_field pma_cmn_refclk_dig_div =
  62. REG_FIELD(WIZ_SERDES_TOP_CTRL, 26, 27);
  63. static const struct reg_field pma_cmn_refclk1_dig_div =
  64. REG_FIELD(WIZ_SERDES_TOP_CTRL, 24, 25);
  65. static const struct reg_field p_enable[WIZ_MAX_LANES] = {
  66. REG_FIELD(WIZ_LANECTL(0), 30, 31),
  67. REG_FIELD(WIZ_LANECTL(1), 30, 31),
  68. REG_FIELD(WIZ_LANECTL(2), 30, 31),
  69. REG_FIELD(WIZ_LANECTL(3), 30, 31),
  70. };
  71. enum p_enable { P_ENABLE = 2, P_ENABLE_FORCE = 1, P_ENABLE_DISABLE = 0 };
  72. static const struct reg_field p_align[WIZ_MAX_LANES] = {
  73. REG_FIELD(WIZ_LANECTL(0), 29, 29),
  74. REG_FIELD(WIZ_LANECTL(1), 29, 29),
  75. REG_FIELD(WIZ_LANECTL(2), 29, 29),
  76. REG_FIELD(WIZ_LANECTL(3), 29, 29),
  77. };
  78. static const struct reg_field p_raw_auto_start[WIZ_MAX_LANES] = {
  79. REG_FIELD(WIZ_LANECTL(0), 28, 28),
  80. REG_FIELD(WIZ_LANECTL(1), 28, 28),
  81. REG_FIELD(WIZ_LANECTL(2), 28, 28),
  82. REG_FIELD(WIZ_LANECTL(3), 28, 28),
  83. };
  84. static const struct reg_field p_standard_mode[WIZ_MAX_LANES] = {
  85. REG_FIELD(WIZ_LANECTL(0), 24, 25),
  86. REG_FIELD(WIZ_LANECTL(1), 24, 25),
  87. REG_FIELD(WIZ_LANECTL(2), 24, 25),
  88. REG_FIELD(WIZ_LANECTL(3), 24, 25),
  89. };
  90. static const struct reg_field typec_ln10_swap =
  91. REG_FIELD(WIZ_SERDES_TYPEC, 30, 30);
  92. struct wiz_clk_mux {
  93. struct clk_hw hw;
  94. struct regmap_field *field;
  95. u32 *table;
  96. struct clk_init_data clk_data;
  97. };
  98. #define to_wiz_clk_mux(_hw) container_of(_hw, struct wiz_clk_mux, hw)
  99. struct wiz_clk_divider {
  100. struct clk_hw hw;
  101. struct regmap_field *field;
  102. const struct clk_div_table *table;
  103. struct clk_init_data clk_data;
  104. };
  105. #define to_wiz_clk_div(_hw) container_of(_hw, struct wiz_clk_divider, hw)
  106. struct wiz_clk_mux_sel {
  107. struct regmap_field *field;
  108. u32 table[4];
  109. const char *node_name;
  110. };
  111. struct wiz_clk_div_sel {
  112. struct regmap_field *field;
  113. const struct clk_div_table *table;
  114. const char *node_name;
  115. };
  116. static struct wiz_clk_mux_sel clk_mux_sel_16g[] = {
  117. {
  118. /*
  119. * Mux value to be configured for each of the input clocks
  120. * in the order populated in device tree
  121. */
  122. .table = { 1, 0 },
  123. .node_name = "pll0-refclk",
  124. },
  125. {
  126. .table = { 1, 0 },
  127. .node_name = "pll1-refclk",
  128. },
  129. {
  130. .table = { 1, 3, 0, 2 },
  131. .node_name = "refclk-dig",
  132. },
  133. };
  134. static struct wiz_clk_mux_sel clk_mux_sel_10g[] = {
  135. {
  136. /*
  137. * Mux value to be configured for each of the input clocks
  138. * in the order populated in device tree
  139. */
  140. .table = { 1, 0 },
  141. .node_name = "pll0-refclk",
  142. },
  143. {
  144. .table = { 1, 0 },
  145. .node_name = "pll1-refclk",
  146. },
  147. {
  148. .table = { 1, 0 },
  149. .node_name = "refclk-dig",
  150. },
  151. };
  152. static const struct clk_div_table clk_div_table[] = {
  153. { .val = 0, .div = 1, },
  154. { .val = 1, .div = 2, },
  155. { .val = 2, .div = 4, },
  156. { .val = 3, .div = 8, },
  157. { /* sentinel */ },
  158. };
  159. static struct wiz_clk_div_sel clk_div_sel[] = {
  160. {
  161. .table = clk_div_table,
  162. .node_name = "cmn-refclk-dig-div",
  163. },
  164. {
  165. .table = clk_div_table,
  166. .node_name = "cmn-refclk1-dig-div",
  167. },
  168. };
  169. enum wiz_type {
  170. J721E_WIZ_16G,
  171. J721E_WIZ_10G,
  172. };
  173. #define WIZ_TYPEC_DIR_DEBOUNCE_MIN 100 /* ms */
  174. #define WIZ_TYPEC_DIR_DEBOUNCE_MAX 1000
  175. struct wiz {
  176. struct regmap *regmap;
  177. enum wiz_type type;
  178. struct wiz_clk_mux_sel *clk_mux_sel;
  179. struct wiz_clk_div_sel *clk_div_sel;
  180. unsigned int clk_div_sel_num;
  181. struct regmap_field *por_en;
  182. struct regmap_field *phy_reset_n;
  183. struct regmap_field *p_enable[WIZ_MAX_LANES];
  184. struct regmap_field *p_align[WIZ_MAX_LANES];
  185. struct regmap_field *p_raw_auto_start[WIZ_MAX_LANES];
  186. struct regmap_field *p_standard_mode[WIZ_MAX_LANES];
  187. struct regmap_field *pma_cmn_refclk_int_mode;
  188. struct regmap_field *pma_cmn_refclk_mode;
  189. struct regmap_field *pma_cmn_refclk_dig_div;
  190. struct regmap_field *pma_cmn_refclk1_dig_div;
  191. struct regmap_field *typec_ln10_swap;
  192. struct device *dev;
  193. u32 num_lanes;
  194. struct platform_device *serdes_pdev;
  195. struct reset_controller_dev wiz_phy_reset_dev;
  196. struct gpio_desc *gpio_typec_dir;
  197. int typec_dir_delay;
  198. u32 lane_phy_type[WIZ_MAX_LANES];
  199. };
  200. static int wiz_reset(struct wiz *wiz)
  201. {
  202. int ret;
  203. ret = regmap_field_write(wiz->por_en, 0x1);
  204. if (ret)
  205. return ret;
  206. mdelay(1);
  207. ret = regmap_field_write(wiz->por_en, 0x0);
  208. if (ret)
  209. return ret;
  210. return 0;
  211. }
  212. static int wiz_mode_select(struct wiz *wiz)
  213. {
  214. u32 num_lanes = wiz->num_lanes;
  215. enum wiz_lane_standard_mode mode;
  216. int ret;
  217. int i;
  218. for (i = 0; i < num_lanes; i++) {
  219. if (wiz->lane_phy_type[i] == PHY_TYPE_DP)
  220. mode = LANE_MODE_GEN1;
  221. else
  222. mode = LANE_MODE_GEN4;
  223. ret = regmap_field_write(wiz->p_standard_mode[i], mode);
  224. if (ret)
  225. return ret;
  226. }
  227. return 0;
  228. }
  229. static int wiz_init_raw_interface(struct wiz *wiz, bool enable)
  230. {
  231. u32 num_lanes = wiz->num_lanes;
  232. int i;
  233. int ret;
  234. for (i = 0; i < num_lanes; i++) {
  235. ret = regmap_field_write(wiz->p_align[i], enable);
  236. if (ret)
  237. return ret;
  238. ret = regmap_field_write(wiz->p_raw_auto_start[i], enable);
  239. if (ret)
  240. return ret;
  241. }
  242. return 0;
  243. }
  244. static int wiz_init(struct wiz *wiz)
  245. {
  246. struct device *dev = wiz->dev;
  247. int ret;
  248. ret = wiz_reset(wiz);
  249. if (ret) {
  250. dev_err(dev, "WIZ reset failed\n");
  251. return ret;
  252. }
  253. ret = wiz_mode_select(wiz);
  254. if (ret) {
  255. dev_err(dev, "WIZ mode select failed\n");
  256. return ret;
  257. }
  258. ret = wiz_init_raw_interface(wiz, true);
  259. if (ret) {
  260. dev_err(dev, "WIZ interface initialization failed\n");
  261. return ret;
  262. }
  263. return 0;
  264. }
  265. static int wiz_regfield_init(struct wiz *wiz)
  266. {
  267. struct wiz_clk_mux_sel *clk_mux_sel;
  268. struct wiz_clk_div_sel *clk_div_sel;
  269. struct regmap *regmap = wiz->regmap;
  270. int num_lanes = wiz->num_lanes;
  271. struct device *dev = wiz->dev;
  272. int i;
  273. wiz->por_en = devm_regmap_field_alloc(dev, regmap, por_en);
  274. if (IS_ERR(wiz->por_en)) {
  275. dev_err(dev, "POR_EN reg field init failed\n");
  276. return PTR_ERR(wiz->por_en);
  277. }
  278. wiz->phy_reset_n = devm_regmap_field_alloc(dev, regmap,
  279. phy_reset_n);
  280. if (IS_ERR(wiz->phy_reset_n)) {
  281. dev_err(dev, "PHY_RESET_N reg field init failed\n");
  282. return PTR_ERR(wiz->phy_reset_n);
  283. }
  284. wiz->pma_cmn_refclk_int_mode =
  285. devm_regmap_field_alloc(dev, regmap, pma_cmn_refclk_int_mode);
  286. if (IS_ERR(wiz->pma_cmn_refclk_int_mode)) {
  287. dev_err(dev, "PMA_CMN_REFCLK_INT_MODE reg field init failed\n");
  288. return PTR_ERR(wiz->pma_cmn_refclk_int_mode);
  289. }
  290. wiz->pma_cmn_refclk_mode =
  291. devm_regmap_field_alloc(dev, regmap, pma_cmn_refclk_mode);
  292. if (IS_ERR(wiz->pma_cmn_refclk_mode)) {
  293. dev_err(dev, "PMA_CMN_REFCLK_MODE reg field init failed\n");
  294. return PTR_ERR(wiz->pma_cmn_refclk_mode);
  295. }
  296. clk_div_sel = &wiz->clk_div_sel[CMN_REFCLK_DIG_DIV];
  297. clk_div_sel->field = devm_regmap_field_alloc(dev, regmap,
  298. pma_cmn_refclk_dig_div);
  299. if (IS_ERR(clk_div_sel->field)) {
  300. dev_err(dev, "PMA_CMN_REFCLK_DIG_DIV reg field init failed\n");
  301. return PTR_ERR(clk_div_sel->field);
  302. }
  303. if (wiz->type == J721E_WIZ_16G) {
  304. clk_div_sel = &wiz->clk_div_sel[CMN_REFCLK1_DIG_DIV];
  305. clk_div_sel->field =
  306. devm_regmap_field_alloc(dev, regmap,
  307. pma_cmn_refclk1_dig_div);
  308. if (IS_ERR(clk_div_sel->field)) {
  309. dev_err(dev, "PMA_CMN_REFCLK1_DIG_DIV reg field init failed\n");
  310. return PTR_ERR(clk_div_sel->field);
  311. }
  312. }
  313. clk_mux_sel = &wiz->clk_mux_sel[PLL0_REFCLK];
  314. clk_mux_sel->field = devm_regmap_field_alloc(dev, regmap,
  315. pll0_refclk_mux_sel);
  316. if (IS_ERR(clk_mux_sel->field)) {
  317. dev_err(dev, "PLL0_REFCLK_SEL reg field init failed\n");
  318. return PTR_ERR(clk_mux_sel->field);
  319. }
  320. clk_mux_sel = &wiz->clk_mux_sel[PLL1_REFCLK];
  321. clk_mux_sel->field = devm_regmap_field_alloc(dev, regmap,
  322. pll1_refclk_mux_sel);
  323. if (IS_ERR(clk_mux_sel->field)) {
  324. dev_err(dev, "PLL1_REFCLK_SEL reg field init failed\n");
  325. return PTR_ERR(clk_mux_sel->field);
  326. }
  327. clk_mux_sel = &wiz->clk_mux_sel[REFCLK_DIG];
  328. if (wiz->type == J721E_WIZ_10G)
  329. clk_mux_sel->field =
  330. devm_regmap_field_alloc(dev, regmap,
  331. refclk_dig_sel_10g);
  332. else
  333. clk_mux_sel->field =
  334. devm_regmap_field_alloc(dev, regmap,
  335. refclk_dig_sel_16g);
  336. if (IS_ERR(clk_mux_sel->field)) {
  337. dev_err(dev, "REFCLK_DIG_SEL reg field init failed\n");
  338. return PTR_ERR(clk_mux_sel->field);
  339. }
  340. for (i = 0; i < num_lanes; i++) {
  341. wiz->p_enable[i] = devm_regmap_field_alloc(dev, regmap,
  342. p_enable[i]);
  343. if (IS_ERR(wiz->p_enable[i])) {
  344. dev_err(dev, "P%d_ENABLE reg field init failed\n", i);
  345. return PTR_ERR(wiz->p_enable[i]);
  346. }
  347. wiz->p_align[i] = devm_regmap_field_alloc(dev, regmap,
  348. p_align[i]);
  349. if (IS_ERR(wiz->p_align[i])) {
  350. dev_err(dev, "P%d_ALIGN reg field init failed\n", i);
  351. return PTR_ERR(wiz->p_align[i]);
  352. }
  353. wiz->p_raw_auto_start[i] =
  354. devm_regmap_field_alloc(dev, regmap, p_raw_auto_start[i]);
  355. if (IS_ERR(wiz->p_raw_auto_start[i])) {
  356. dev_err(dev, "P%d_RAW_AUTO_START reg field init fail\n",
  357. i);
  358. return PTR_ERR(wiz->p_raw_auto_start[i]);
  359. }
  360. wiz->p_standard_mode[i] =
  361. devm_regmap_field_alloc(dev, regmap, p_standard_mode[i]);
  362. if (IS_ERR(wiz->p_standard_mode[i])) {
  363. dev_err(dev, "P%d_STANDARD_MODE reg field init fail\n",
  364. i);
  365. return PTR_ERR(wiz->p_standard_mode[i]);
  366. }
  367. }
  368. wiz->typec_ln10_swap = devm_regmap_field_alloc(dev, regmap,
  369. typec_ln10_swap);
  370. if (IS_ERR(wiz->typec_ln10_swap)) {
  371. dev_err(dev, "LN10_SWAP reg field init failed\n");
  372. return PTR_ERR(wiz->typec_ln10_swap);
  373. }
  374. return 0;
  375. }
  376. static u8 wiz_clk_mux_get_parent(struct clk_hw *hw)
  377. {
  378. struct wiz_clk_mux *mux = to_wiz_clk_mux(hw);
  379. struct regmap_field *field = mux->field;
  380. unsigned int val;
  381. regmap_field_read(field, &val);
  382. return clk_mux_val_to_index(hw, mux->table, 0, val);
  383. }
  384. static int wiz_clk_mux_set_parent(struct clk_hw *hw, u8 index)
  385. {
  386. struct wiz_clk_mux *mux = to_wiz_clk_mux(hw);
  387. struct regmap_field *field = mux->field;
  388. int val;
  389. val = mux->table[index];
  390. return regmap_field_write(field, val);
  391. }
  392. static const struct clk_ops wiz_clk_mux_ops = {
  393. .set_parent = wiz_clk_mux_set_parent,
  394. .get_parent = wiz_clk_mux_get_parent,
  395. };
  396. static int wiz_mux_clk_register(struct wiz *wiz, struct device_node *node,
  397. struct regmap_field *field, u32 *table)
  398. {
  399. struct device *dev = wiz->dev;
  400. struct clk_init_data *init;
  401. const char **parent_names;
  402. unsigned int num_parents;
  403. struct wiz_clk_mux *mux;
  404. char clk_name[100];
  405. struct clk *clk;
  406. int ret;
  407. mux = devm_kzalloc(dev, sizeof(*mux), GFP_KERNEL);
  408. if (!mux)
  409. return -ENOMEM;
  410. num_parents = of_clk_get_parent_count(node);
  411. if (num_parents < 2) {
  412. dev_err(dev, "SERDES clock must have parents\n");
  413. return -EINVAL;
  414. }
  415. parent_names = devm_kzalloc(dev, (sizeof(char *) * num_parents),
  416. GFP_KERNEL);
  417. if (!parent_names)
  418. return -ENOMEM;
  419. of_clk_parent_fill(node, parent_names, num_parents);
  420. snprintf(clk_name, sizeof(clk_name), "%s_%s", dev_name(dev),
  421. node->name);
  422. init = &mux->clk_data;
  423. init->ops = &wiz_clk_mux_ops;
  424. init->flags = CLK_SET_RATE_NO_REPARENT;
  425. init->parent_names = parent_names;
  426. init->num_parents = num_parents;
  427. init->name = clk_name;
  428. mux->field = field;
  429. mux->table = table;
  430. mux->hw.init = init;
  431. clk = devm_clk_register(dev, &mux->hw);
  432. if (IS_ERR(clk))
  433. return PTR_ERR(clk);
  434. ret = of_clk_add_provider(node, of_clk_src_simple_get, clk);
  435. if (ret)
  436. dev_err(dev, "Failed to add clock provider: %s\n", clk_name);
  437. return ret;
  438. }
  439. static unsigned long wiz_clk_div_recalc_rate(struct clk_hw *hw,
  440. unsigned long parent_rate)
  441. {
  442. struct wiz_clk_divider *div = to_wiz_clk_div(hw);
  443. struct regmap_field *field = div->field;
  444. int val;
  445. regmap_field_read(field, &val);
  446. return divider_recalc_rate(hw, parent_rate, val, div->table, 0x0, 2);
  447. }
  448. static long wiz_clk_div_round_rate(struct clk_hw *hw, unsigned long rate,
  449. unsigned long *prate)
  450. {
  451. struct wiz_clk_divider *div = to_wiz_clk_div(hw);
  452. return divider_round_rate(hw, rate, prate, div->table, 2, 0x0);
  453. }
  454. static int wiz_clk_div_set_rate(struct clk_hw *hw, unsigned long rate,
  455. unsigned long parent_rate)
  456. {
  457. struct wiz_clk_divider *div = to_wiz_clk_div(hw);
  458. struct regmap_field *field = div->field;
  459. int val;
  460. val = divider_get_val(rate, parent_rate, div->table, 2, 0x0);
  461. if (val < 0)
  462. return val;
  463. return regmap_field_write(field, val);
  464. }
  465. static const struct clk_ops wiz_clk_div_ops = {
  466. .recalc_rate = wiz_clk_div_recalc_rate,
  467. .round_rate = wiz_clk_div_round_rate,
  468. .set_rate = wiz_clk_div_set_rate,
  469. };
  470. static int wiz_div_clk_register(struct wiz *wiz, struct device_node *node,
  471. struct regmap_field *field,
  472. const struct clk_div_table *table)
  473. {
  474. struct device *dev = wiz->dev;
  475. struct wiz_clk_divider *div;
  476. struct clk_init_data *init;
  477. const char **parent_names;
  478. char clk_name[100];
  479. struct clk *clk;
  480. int ret;
  481. div = devm_kzalloc(dev, sizeof(*div), GFP_KERNEL);
  482. if (!div)
  483. return -ENOMEM;
  484. snprintf(clk_name, sizeof(clk_name), "%s_%s", dev_name(dev),
  485. node->name);
  486. parent_names = devm_kzalloc(dev, sizeof(char *), GFP_KERNEL);
  487. if (!parent_names)
  488. return -ENOMEM;
  489. of_clk_parent_fill(node, parent_names, 1);
  490. init = &div->clk_data;
  491. init->ops = &wiz_clk_div_ops;
  492. init->flags = 0;
  493. init->parent_names = parent_names;
  494. init->num_parents = 1;
  495. init->name = clk_name;
  496. div->field = field;
  497. div->table = table;
  498. div->hw.init = init;
  499. clk = devm_clk_register(dev, &div->hw);
  500. if (IS_ERR(clk))
  501. return PTR_ERR(clk);
  502. ret = of_clk_add_provider(node, of_clk_src_simple_get, clk);
  503. if (ret)
  504. dev_err(dev, "Failed to add clock provider: %s\n", clk_name);
  505. return ret;
  506. }
  507. static void wiz_clock_cleanup(struct wiz *wiz, struct device_node *node)
  508. {
  509. struct wiz_clk_mux_sel *clk_mux_sel = wiz->clk_mux_sel;
  510. struct device_node *clk_node;
  511. int i;
  512. for (i = 0; i < WIZ_MUX_NUM_CLOCKS; i++) {
  513. clk_node = of_get_child_by_name(node, clk_mux_sel[i].node_name);
  514. of_clk_del_provider(clk_node);
  515. of_node_put(clk_node);
  516. }
  517. for (i = 0; i < wiz->clk_div_sel_num; i++) {
  518. clk_node = of_get_child_by_name(node, clk_div_sel[i].node_name);
  519. of_clk_del_provider(clk_node);
  520. of_node_put(clk_node);
  521. }
  522. }
  523. static int wiz_clock_init(struct wiz *wiz, struct device_node *node)
  524. {
  525. struct wiz_clk_mux_sel *clk_mux_sel = wiz->clk_mux_sel;
  526. struct device *dev = wiz->dev;
  527. struct device_node *clk_node;
  528. const char *node_name;
  529. unsigned long rate;
  530. struct clk *clk;
  531. int ret;
  532. int i;
  533. clk = devm_clk_get(dev, "core_ref_clk");
  534. if (IS_ERR(clk)) {
  535. dev_err(dev, "core_ref_clk clock not found\n");
  536. ret = PTR_ERR(clk);
  537. return ret;
  538. }
  539. rate = clk_get_rate(clk);
  540. if (rate >= 100000000)
  541. regmap_field_write(wiz->pma_cmn_refclk_int_mode, 0x1);
  542. else
  543. regmap_field_write(wiz->pma_cmn_refclk_int_mode, 0x3);
  544. clk = devm_clk_get(dev, "ext_ref_clk");
  545. if (IS_ERR(clk)) {
  546. dev_err(dev, "ext_ref_clk clock not found\n");
  547. ret = PTR_ERR(clk);
  548. return ret;
  549. }
  550. rate = clk_get_rate(clk);
  551. if (rate >= 100000000)
  552. regmap_field_write(wiz->pma_cmn_refclk_mode, 0x0);
  553. else
  554. regmap_field_write(wiz->pma_cmn_refclk_mode, 0x2);
  555. for (i = 0; i < WIZ_MUX_NUM_CLOCKS; i++) {
  556. node_name = clk_mux_sel[i].node_name;
  557. clk_node = of_get_child_by_name(node, node_name);
  558. if (!clk_node) {
  559. dev_err(dev, "Unable to get %s node\n", node_name);
  560. ret = -EINVAL;
  561. goto err;
  562. }
  563. ret = wiz_mux_clk_register(wiz, clk_node, clk_mux_sel[i].field,
  564. clk_mux_sel[i].table);
  565. if (ret) {
  566. dev_err(dev, "Failed to register %s clock\n",
  567. node_name);
  568. of_node_put(clk_node);
  569. goto err;
  570. }
  571. of_node_put(clk_node);
  572. }
  573. for (i = 0; i < wiz->clk_div_sel_num; i++) {
  574. node_name = clk_div_sel[i].node_name;
  575. clk_node = of_get_child_by_name(node, node_name);
  576. if (!clk_node) {
  577. dev_err(dev, "Unable to get %s node\n", node_name);
  578. ret = -EINVAL;
  579. goto err;
  580. }
  581. ret = wiz_div_clk_register(wiz, clk_node, clk_div_sel[i].field,
  582. clk_div_sel[i].table);
  583. if (ret) {
  584. dev_err(dev, "Failed to register %s clock\n",
  585. node_name);
  586. of_node_put(clk_node);
  587. goto err;
  588. }
  589. of_node_put(clk_node);
  590. }
  591. return 0;
  592. err:
  593. wiz_clock_cleanup(wiz, node);
  594. return ret;
  595. }
  596. static int wiz_phy_reset_assert(struct reset_controller_dev *rcdev,
  597. unsigned long id)
  598. {
  599. struct device *dev = rcdev->dev;
  600. struct wiz *wiz = dev_get_drvdata(dev);
  601. int ret = 0;
  602. if (id == 0) {
  603. ret = regmap_field_write(wiz->phy_reset_n, false);
  604. return ret;
  605. }
  606. ret = regmap_field_write(wiz->p_enable[id - 1], P_ENABLE_DISABLE);
  607. return ret;
  608. }
  609. static int wiz_phy_reset_deassert(struct reset_controller_dev *rcdev,
  610. unsigned long id)
  611. {
  612. struct device *dev = rcdev->dev;
  613. struct wiz *wiz = dev_get_drvdata(dev);
  614. int ret;
  615. /* if typec-dir gpio was specified, set LN10 SWAP bit based on that */
  616. if (id == 0 && wiz->gpio_typec_dir) {
  617. if (wiz->typec_dir_delay)
  618. msleep_interruptible(wiz->typec_dir_delay);
  619. if (gpiod_get_value_cansleep(wiz->gpio_typec_dir))
  620. regmap_field_write(wiz->typec_ln10_swap, 1);
  621. else
  622. regmap_field_write(wiz->typec_ln10_swap, 0);
  623. }
  624. if (id == 0) {
  625. ret = regmap_field_write(wiz->phy_reset_n, true);
  626. return ret;
  627. }
  628. if (wiz->lane_phy_type[id - 1] == PHY_TYPE_DP)
  629. ret = regmap_field_write(wiz->p_enable[id - 1], P_ENABLE);
  630. else
  631. ret = regmap_field_write(wiz->p_enable[id - 1], P_ENABLE_FORCE);
  632. return ret;
  633. }
  634. static const struct reset_control_ops wiz_phy_reset_ops = {
  635. .assert = wiz_phy_reset_assert,
  636. .deassert = wiz_phy_reset_deassert,
  637. };
  638. static const struct regmap_config wiz_regmap_config = {
  639. .reg_bits = 32,
  640. .val_bits = 32,
  641. .reg_stride = 4,
  642. .fast_io = true,
  643. };
  644. static const struct of_device_id wiz_id_table[] = {
  645. {
  646. .compatible = "ti,j721e-wiz-16g", .data = (void *)J721E_WIZ_16G
  647. },
  648. {
  649. .compatible = "ti,j721e-wiz-10g", .data = (void *)J721E_WIZ_10G
  650. },
  651. {}
  652. };
  653. MODULE_DEVICE_TABLE(of, wiz_id_table);
  654. static int wiz_get_lane_phy_types(struct device *dev, struct wiz *wiz)
  655. {
  656. struct device_node *serdes, *subnode;
  657. serdes = of_get_child_by_name(dev->of_node, "serdes");
  658. if (!serdes) {
  659. dev_err(dev, "%s: Getting \"serdes\"-node failed\n", __func__);
  660. return -EINVAL;
  661. }
  662. for_each_child_of_node(serdes, subnode) {
  663. u32 reg, num_lanes = 1, phy_type = PHY_NONE;
  664. int ret, i;
  665. ret = of_property_read_u32(subnode, "reg", &reg);
  666. if (ret) {
  667. dev_err(dev,
  668. "%s: Reading \"reg\" from \"%s\" failed: %d\n",
  669. __func__, subnode->name, ret);
  670. return ret;
  671. }
  672. of_property_read_u32(subnode, "cdns,num-lanes", &num_lanes);
  673. of_property_read_u32(subnode, "cdns,phy-type", &phy_type);
  674. dev_dbg(dev, "%s: Lanes %u-%u have phy-type %u\n", __func__,
  675. reg, reg + num_lanes - 1, phy_type);
  676. for (i = reg; i < reg + num_lanes; i++)
  677. wiz->lane_phy_type[i] = phy_type;
  678. }
  679. return 0;
  680. }
  681. static int wiz_probe(struct platform_device *pdev)
  682. {
  683. struct reset_controller_dev *phy_reset_dev;
  684. struct device *dev = &pdev->dev;
  685. struct device_node *node = dev->of_node;
  686. struct platform_device *serdes_pdev;
  687. struct device_node *child_node;
  688. struct regmap *regmap;
  689. struct resource res;
  690. void __iomem *base;
  691. struct wiz *wiz;
  692. u32 num_lanes;
  693. int ret;
  694. wiz = devm_kzalloc(dev, sizeof(*wiz), GFP_KERNEL);
  695. if (!wiz)
  696. return -ENOMEM;
  697. wiz->type = (enum wiz_type)of_device_get_match_data(dev);
  698. child_node = of_get_child_by_name(node, "serdes");
  699. if (!child_node) {
  700. dev_err(dev, "Failed to get SERDES child DT node\n");
  701. return -ENODEV;
  702. }
  703. ret = of_address_to_resource(child_node, 0, &res);
  704. if (ret) {
  705. dev_err(dev, "Failed to get memory resource\n");
  706. goto err_addr_to_resource;
  707. }
  708. base = devm_ioremap(dev, res.start, resource_size(&res));
  709. if (!base) {
  710. ret = -ENOMEM;
  711. goto err_addr_to_resource;
  712. }
  713. regmap = devm_regmap_init_mmio(dev, base, &wiz_regmap_config);
  714. if (IS_ERR(regmap)) {
  715. dev_err(dev, "Failed to initialize regmap\n");
  716. ret = PTR_ERR(regmap);
  717. goto err_addr_to_resource;
  718. }
  719. ret = of_property_read_u32(node, "num-lanes", &num_lanes);
  720. if (ret) {
  721. dev_err(dev, "Failed to read num-lanes property\n");
  722. goto err_addr_to_resource;
  723. }
  724. if (num_lanes > WIZ_MAX_LANES) {
  725. dev_err(dev, "Cannot support %d lanes\n", num_lanes);
  726. ret = -ENODEV;
  727. goto err_addr_to_resource;
  728. }
  729. wiz->gpio_typec_dir = devm_gpiod_get_optional(dev, "typec-dir",
  730. GPIOD_IN);
  731. if (IS_ERR(wiz->gpio_typec_dir)) {
  732. ret = PTR_ERR(wiz->gpio_typec_dir);
  733. if (ret != -EPROBE_DEFER)
  734. dev_err(dev, "Failed to request typec-dir gpio: %d\n",
  735. ret);
  736. goto err_addr_to_resource;
  737. }
  738. if (wiz->gpio_typec_dir) {
  739. ret = of_property_read_u32(node, "typec-dir-debounce-ms",
  740. &wiz->typec_dir_delay);
  741. if (ret && ret != -EINVAL) {
  742. dev_err(dev, "Invalid typec-dir-debounce property\n");
  743. goto err_addr_to_resource;
  744. }
  745. /* use min. debounce from Type-C spec if not provided in DT */
  746. if (ret == -EINVAL)
  747. wiz->typec_dir_delay = WIZ_TYPEC_DIR_DEBOUNCE_MIN;
  748. if (wiz->typec_dir_delay < WIZ_TYPEC_DIR_DEBOUNCE_MIN ||
  749. wiz->typec_dir_delay > WIZ_TYPEC_DIR_DEBOUNCE_MAX) {
  750. ret = -EINVAL;
  751. dev_err(dev, "Invalid typec-dir-debounce property\n");
  752. goto err_addr_to_resource;
  753. }
  754. }
  755. ret = wiz_get_lane_phy_types(dev, wiz);
  756. if (ret)
  757. return ret;
  758. wiz->dev = dev;
  759. wiz->regmap = regmap;
  760. wiz->num_lanes = num_lanes;
  761. if (wiz->type == J721E_WIZ_10G)
  762. wiz->clk_mux_sel = clk_mux_sel_10g;
  763. else
  764. wiz->clk_mux_sel = clk_mux_sel_16g;
  765. wiz->clk_div_sel = clk_div_sel;
  766. if (wiz->type == J721E_WIZ_10G)
  767. wiz->clk_div_sel_num = WIZ_DIV_NUM_CLOCKS_10G;
  768. else
  769. wiz->clk_div_sel_num = WIZ_DIV_NUM_CLOCKS_16G;
  770. platform_set_drvdata(pdev, wiz);
  771. ret = wiz_regfield_init(wiz);
  772. if (ret) {
  773. dev_err(dev, "Failed to initialize regfields\n");
  774. goto err_addr_to_resource;
  775. }
  776. phy_reset_dev = &wiz->wiz_phy_reset_dev;
  777. phy_reset_dev->dev = dev;
  778. phy_reset_dev->ops = &wiz_phy_reset_ops,
  779. phy_reset_dev->owner = THIS_MODULE,
  780. phy_reset_dev->of_node = node;
  781. /* Reset for each of the lane and one for the entire SERDES */
  782. phy_reset_dev->nr_resets = num_lanes + 1;
  783. ret = devm_reset_controller_register(dev, phy_reset_dev);
  784. if (ret < 0) {
  785. dev_warn(dev, "Failed to register reset controller\n");
  786. goto err_addr_to_resource;
  787. }
  788. pm_runtime_enable(dev);
  789. ret = pm_runtime_get_sync(dev);
  790. if (ret < 0) {
  791. dev_err(dev, "pm_runtime_get_sync failed\n");
  792. goto err_get_sync;
  793. }
  794. ret = wiz_clock_init(wiz, node);
  795. if (ret < 0) {
  796. dev_warn(dev, "Failed to initialize clocks\n");
  797. goto err_get_sync;
  798. }
  799. ret = wiz_init(wiz);
  800. if (ret) {
  801. dev_err(dev, "WIZ initialization failed\n");
  802. goto err_wiz_init;
  803. }
  804. serdes_pdev = of_platform_device_create(child_node, NULL, dev);
  805. if (!serdes_pdev) {
  806. dev_WARN(dev, "Unable to create SERDES platform device\n");
  807. ret = -ENOMEM;
  808. goto err_wiz_init;
  809. }
  810. wiz->serdes_pdev = serdes_pdev;
  811. of_node_put(child_node);
  812. return 0;
  813. err_wiz_init:
  814. wiz_clock_cleanup(wiz, node);
  815. err_get_sync:
  816. pm_runtime_put(dev);
  817. pm_runtime_disable(dev);
  818. err_addr_to_resource:
  819. of_node_put(child_node);
  820. return ret;
  821. }
  822. static int wiz_remove(struct platform_device *pdev)
  823. {
  824. struct device *dev = &pdev->dev;
  825. struct device_node *node = dev->of_node;
  826. struct platform_device *serdes_pdev;
  827. struct wiz *wiz;
  828. wiz = dev_get_drvdata(dev);
  829. serdes_pdev = wiz->serdes_pdev;
  830. of_platform_device_destroy(&serdes_pdev->dev, NULL);
  831. wiz_clock_cleanup(wiz, node);
  832. pm_runtime_put(dev);
  833. pm_runtime_disable(dev);
  834. return 0;
  835. }
  836. static struct platform_driver wiz_driver = {
  837. .probe = wiz_probe,
  838. .remove = wiz_remove,
  839. .driver = {
  840. .name = "wiz",
  841. .of_match_table = wiz_id_table,
  842. },
  843. };
  844. module_platform_driver(wiz_driver);
  845. MODULE_AUTHOR("Texas Instruments Inc.");
  846. MODULE_DESCRIPTION("TI J721E WIZ driver");
  847. MODULE_LICENSE("GPL v2");