phy-gmii-sel.c 10 KB

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  1. // SPDX-License-Identifier: GPL-2.0
  2. /*
  3. * Texas Instruments CPSW Port's PHY Interface Mode selection Driver
  4. *
  5. * Copyright (C) 2018 Texas Instruments Incorporated - http://www.ti.com/
  6. *
  7. * Based on cpsw-phy-sel.c driver created by Mugunthan V N <mugunthanvnm@ti.com>
  8. */
  9. #include <linux/platform_device.h>
  10. #include <linux/module.h>
  11. #include <linux/mfd/syscon.h>
  12. #include <linux/of.h>
  13. #include <linux/of_address.h>
  14. #include <linux/of_net.h>
  15. #include <linux/phy.h>
  16. #include <linux/phy/phy.h>
  17. #include <linux/regmap.h>
  18. /* AM33xx SoC specific definitions for the CONTROL port */
  19. #define AM33XX_GMII_SEL_MODE_MII 0
  20. #define AM33XX_GMII_SEL_MODE_RMII 1
  21. #define AM33XX_GMII_SEL_MODE_RGMII 2
  22. enum {
  23. PHY_GMII_SEL_PORT_MODE = 0,
  24. PHY_GMII_SEL_RGMII_ID_MODE,
  25. PHY_GMII_SEL_RMII_IO_CLK_EN,
  26. PHY_GMII_SEL_LAST,
  27. };
  28. struct phy_gmii_sel_phy_priv {
  29. struct phy_gmii_sel_priv *priv;
  30. u32 id;
  31. struct phy *if_phy;
  32. int rmii_clock_external;
  33. int phy_if_mode;
  34. struct regmap_field *fields[PHY_GMII_SEL_LAST];
  35. };
  36. struct phy_gmii_sel_soc_data {
  37. u32 num_ports;
  38. u32 features;
  39. const struct reg_field (*regfields)[PHY_GMII_SEL_LAST];
  40. bool use_of_data;
  41. };
  42. struct phy_gmii_sel_priv {
  43. struct device *dev;
  44. const struct phy_gmii_sel_soc_data *soc_data;
  45. struct regmap *regmap;
  46. struct phy_provider *phy_provider;
  47. struct phy_gmii_sel_phy_priv *if_phys;
  48. u32 num_ports;
  49. u32 reg_offset;
  50. };
  51. static int phy_gmii_sel_mode(struct phy *phy, enum phy_mode mode, int submode)
  52. {
  53. struct phy_gmii_sel_phy_priv *if_phy = phy_get_drvdata(phy);
  54. const struct phy_gmii_sel_soc_data *soc_data = if_phy->priv->soc_data;
  55. struct device *dev = if_phy->priv->dev;
  56. struct regmap_field *regfield;
  57. int ret, rgmii_id = 0;
  58. u32 gmii_sel_mode = 0;
  59. if (mode != PHY_MODE_ETHERNET)
  60. return -EINVAL;
  61. switch (submode) {
  62. case PHY_INTERFACE_MODE_RMII:
  63. gmii_sel_mode = AM33XX_GMII_SEL_MODE_RMII;
  64. break;
  65. case PHY_INTERFACE_MODE_RGMII:
  66. case PHY_INTERFACE_MODE_RGMII_RXID:
  67. gmii_sel_mode = AM33XX_GMII_SEL_MODE_RGMII;
  68. break;
  69. case PHY_INTERFACE_MODE_RGMII_ID:
  70. case PHY_INTERFACE_MODE_RGMII_TXID:
  71. gmii_sel_mode = AM33XX_GMII_SEL_MODE_RGMII;
  72. rgmii_id = 1;
  73. break;
  74. case PHY_INTERFACE_MODE_MII:
  75. case PHY_INTERFACE_MODE_GMII:
  76. gmii_sel_mode = AM33XX_GMII_SEL_MODE_MII;
  77. break;
  78. default:
  79. dev_warn(dev, "port%u: unsupported mode: \"%s\"\n",
  80. if_phy->id, phy_modes(submode));
  81. return -EINVAL;
  82. }
  83. if_phy->phy_if_mode = submode;
  84. dev_dbg(dev, "%s id:%u mode:%u rgmii_id:%d rmii_clk_ext:%d\n",
  85. __func__, if_phy->id, submode, rgmii_id,
  86. if_phy->rmii_clock_external);
  87. regfield = if_phy->fields[PHY_GMII_SEL_PORT_MODE];
  88. ret = regmap_field_write(regfield, gmii_sel_mode);
  89. if (ret) {
  90. dev_err(dev, "port%u: set mode fail %d", if_phy->id, ret);
  91. return ret;
  92. }
  93. if (soc_data->features & BIT(PHY_GMII_SEL_RGMII_ID_MODE) &&
  94. if_phy->fields[PHY_GMII_SEL_RGMII_ID_MODE]) {
  95. regfield = if_phy->fields[PHY_GMII_SEL_RGMII_ID_MODE];
  96. ret = regmap_field_write(regfield, rgmii_id);
  97. if (ret)
  98. return ret;
  99. }
  100. if (soc_data->features & BIT(PHY_GMII_SEL_RMII_IO_CLK_EN) &&
  101. if_phy->fields[PHY_GMII_SEL_RMII_IO_CLK_EN]) {
  102. regfield = if_phy->fields[PHY_GMII_SEL_RMII_IO_CLK_EN];
  103. ret = regmap_field_write(regfield,
  104. if_phy->rmii_clock_external);
  105. }
  106. return 0;
  107. }
  108. static const
  109. struct reg_field phy_gmii_sel_fields_am33xx[][PHY_GMII_SEL_LAST] = {
  110. {
  111. [PHY_GMII_SEL_PORT_MODE] = REG_FIELD(0x650, 0, 1),
  112. [PHY_GMII_SEL_RGMII_ID_MODE] = REG_FIELD(0x650, 4, 4),
  113. [PHY_GMII_SEL_RMII_IO_CLK_EN] = REG_FIELD(0x650, 6, 6),
  114. },
  115. {
  116. [PHY_GMII_SEL_PORT_MODE] = REG_FIELD(0x650, 2, 3),
  117. [PHY_GMII_SEL_RGMII_ID_MODE] = REG_FIELD(0x650, 5, 5),
  118. [PHY_GMII_SEL_RMII_IO_CLK_EN] = REG_FIELD(0x650, 7, 7),
  119. },
  120. };
  121. static const
  122. struct phy_gmii_sel_soc_data phy_gmii_sel_soc_am33xx = {
  123. .num_ports = 2,
  124. .features = BIT(PHY_GMII_SEL_RGMII_ID_MODE) |
  125. BIT(PHY_GMII_SEL_RMII_IO_CLK_EN),
  126. .regfields = phy_gmii_sel_fields_am33xx,
  127. };
  128. static const
  129. struct reg_field phy_gmii_sel_fields_dra7[][PHY_GMII_SEL_LAST] = {
  130. {
  131. [PHY_GMII_SEL_PORT_MODE] = REG_FIELD(0x554, 0, 1),
  132. },
  133. {
  134. [PHY_GMII_SEL_PORT_MODE] = REG_FIELD(0x554, 4, 5),
  135. },
  136. };
  137. static const
  138. struct phy_gmii_sel_soc_data phy_gmii_sel_soc_dra7 = {
  139. .num_ports = 2,
  140. .regfields = phy_gmii_sel_fields_dra7,
  141. };
  142. static const
  143. struct phy_gmii_sel_soc_data phy_gmii_sel_soc_dm814 = {
  144. .num_ports = 2,
  145. .features = BIT(PHY_GMII_SEL_RGMII_ID_MODE),
  146. .regfields = phy_gmii_sel_fields_am33xx,
  147. };
  148. static const
  149. struct reg_field phy_gmii_sel_fields_am654[][PHY_GMII_SEL_LAST] = {
  150. { [PHY_GMII_SEL_PORT_MODE] = REG_FIELD(0x0, 0, 2), },
  151. { [PHY_GMII_SEL_PORT_MODE] = REG_FIELD(0x4, 0, 2), },
  152. { [PHY_GMII_SEL_PORT_MODE] = REG_FIELD(0x8, 0, 2), },
  153. { [PHY_GMII_SEL_PORT_MODE] = REG_FIELD(0xC, 0, 2), },
  154. { [PHY_GMII_SEL_PORT_MODE] = REG_FIELD(0x10, 0, 2), },
  155. { [PHY_GMII_SEL_PORT_MODE] = REG_FIELD(0x14, 0, 2), },
  156. { [PHY_GMII_SEL_PORT_MODE] = REG_FIELD(0x18, 0, 2), },
  157. { [PHY_GMII_SEL_PORT_MODE] = REG_FIELD(0x1C, 0, 2), },
  158. };
  159. static const
  160. struct phy_gmii_sel_soc_data phy_gmii_sel_soc_am654 = {
  161. .use_of_data = true,
  162. .regfields = phy_gmii_sel_fields_am654,
  163. };
  164. static const struct of_device_id phy_gmii_sel_id_table[] = {
  165. {
  166. .compatible = "ti,am3352-phy-gmii-sel",
  167. .data = &phy_gmii_sel_soc_am33xx,
  168. },
  169. {
  170. .compatible = "ti,dra7xx-phy-gmii-sel",
  171. .data = &phy_gmii_sel_soc_dra7,
  172. },
  173. {
  174. .compatible = "ti,am43xx-phy-gmii-sel",
  175. .data = &phy_gmii_sel_soc_am33xx,
  176. },
  177. {
  178. .compatible = "ti,dm814-phy-gmii-sel",
  179. .data = &phy_gmii_sel_soc_dm814,
  180. },
  181. {
  182. .compatible = "ti,am654-phy-gmii-sel",
  183. .data = &phy_gmii_sel_soc_am654,
  184. },
  185. {}
  186. };
  187. MODULE_DEVICE_TABLE(of, phy_gmii_sel_id_table);
  188. static const struct phy_ops phy_gmii_sel_ops = {
  189. .set_mode = phy_gmii_sel_mode,
  190. .owner = THIS_MODULE,
  191. };
  192. static struct phy *phy_gmii_sel_of_xlate(struct device *dev,
  193. struct of_phandle_args *args)
  194. {
  195. struct phy_gmii_sel_priv *priv = dev_get_drvdata(dev);
  196. int phy_id = args->args[0];
  197. if (args->args_count < 1)
  198. return ERR_PTR(-EINVAL);
  199. if (!priv || !priv->if_phys)
  200. return ERR_PTR(-ENODEV);
  201. if (priv->soc_data->features & BIT(PHY_GMII_SEL_RMII_IO_CLK_EN) &&
  202. args->args_count < 2)
  203. return ERR_PTR(-EINVAL);
  204. if (phy_id > priv->num_ports)
  205. return ERR_PTR(-EINVAL);
  206. if (phy_id != priv->if_phys[phy_id - 1].id)
  207. return ERR_PTR(-EINVAL);
  208. phy_id--;
  209. if (priv->soc_data->features & BIT(PHY_GMII_SEL_RMII_IO_CLK_EN))
  210. priv->if_phys[phy_id].rmii_clock_external = args->args[1];
  211. dev_dbg(dev, "%s id:%u ext:%d\n", __func__,
  212. priv->if_phys[phy_id].id, args->args[1]);
  213. return priv->if_phys[phy_id].if_phy;
  214. }
  215. static int phy_gmii_init_phy(struct phy_gmii_sel_priv *priv, int port,
  216. struct phy_gmii_sel_phy_priv *if_phy)
  217. {
  218. const struct phy_gmii_sel_soc_data *soc_data = priv->soc_data;
  219. struct device *dev = priv->dev;
  220. const struct reg_field *fields;
  221. struct regmap_field *regfield;
  222. struct reg_field field;
  223. int ret;
  224. if_phy->id = port;
  225. if_phy->priv = priv;
  226. fields = soc_data->regfields[port - 1];
  227. field = *fields++;
  228. field.reg += priv->reg_offset;
  229. dev_dbg(dev, "%s field %x %d %d\n", __func__,
  230. field.reg, field.msb, field.lsb);
  231. regfield = devm_regmap_field_alloc(dev, priv->regmap, field);
  232. if (IS_ERR(regfield))
  233. return PTR_ERR(regfield);
  234. if_phy->fields[PHY_GMII_SEL_PORT_MODE] = regfield;
  235. field = *fields++;
  236. field.reg += priv->reg_offset;
  237. if (soc_data->features & BIT(PHY_GMII_SEL_RGMII_ID_MODE)) {
  238. regfield = devm_regmap_field_alloc(dev,
  239. priv->regmap,
  240. field);
  241. if (IS_ERR(regfield))
  242. return PTR_ERR(regfield);
  243. if_phy->fields[PHY_GMII_SEL_RGMII_ID_MODE] = regfield;
  244. dev_dbg(dev, "%s field %x %d %d\n", __func__,
  245. field.reg, field.msb, field.lsb);
  246. }
  247. field = *fields;
  248. field.reg += priv->reg_offset;
  249. if (soc_data->features & BIT(PHY_GMII_SEL_RMII_IO_CLK_EN)) {
  250. regfield = devm_regmap_field_alloc(dev,
  251. priv->regmap,
  252. field);
  253. if (IS_ERR(regfield))
  254. return PTR_ERR(regfield);
  255. if_phy->fields[PHY_GMII_SEL_RMII_IO_CLK_EN] = regfield;
  256. dev_dbg(dev, "%s field %x %d %d\n", __func__,
  257. field.reg, field.msb, field.lsb);
  258. }
  259. if_phy->if_phy = devm_phy_create(dev,
  260. priv->dev->of_node,
  261. &phy_gmii_sel_ops);
  262. if (IS_ERR(if_phy->if_phy)) {
  263. ret = PTR_ERR(if_phy->if_phy);
  264. dev_err(dev, "Failed to create phy%d %d\n", port, ret);
  265. return ret;
  266. }
  267. phy_set_drvdata(if_phy->if_phy, if_phy);
  268. return 0;
  269. }
  270. static int phy_gmii_sel_init_ports(struct phy_gmii_sel_priv *priv)
  271. {
  272. const struct phy_gmii_sel_soc_data *soc_data = priv->soc_data;
  273. struct phy_gmii_sel_phy_priv *if_phys;
  274. struct device *dev = priv->dev;
  275. int i, ret;
  276. if (soc_data->use_of_data) {
  277. const __be32 *offset;
  278. u64 size;
  279. offset = of_get_address(dev->of_node, 0, &size, NULL);
  280. if (!offset)
  281. return -EINVAL;
  282. priv->num_ports = size / sizeof(u32);
  283. if (!priv->num_ports)
  284. return -EINVAL;
  285. priv->reg_offset = __be32_to_cpu(*offset);
  286. }
  287. if_phys = devm_kcalloc(dev, priv->num_ports,
  288. sizeof(*if_phys), GFP_KERNEL);
  289. if (!if_phys)
  290. return -ENOMEM;
  291. dev_dbg(dev, "%s %d\n", __func__, priv->num_ports);
  292. for (i = 0; i < priv->num_ports; i++) {
  293. ret = phy_gmii_init_phy(priv, i + 1, &if_phys[i]);
  294. if (ret)
  295. return ret;
  296. }
  297. priv->if_phys = if_phys;
  298. return 0;
  299. }
  300. static int phy_gmii_sel_probe(struct platform_device *pdev)
  301. {
  302. struct device *dev = &pdev->dev;
  303. struct device_node *node = dev->of_node;
  304. const struct of_device_id *of_id;
  305. struct phy_gmii_sel_priv *priv;
  306. int ret;
  307. of_id = of_match_node(phy_gmii_sel_id_table, pdev->dev.of_node);
  308. if (!of_id)
  309. return -EINVAL;
  310. priv = devm_kzalloc(&pdev->dev, sizeof(*priv), GFP_KERNEL);
  311. if (!priv)
  312. return -ENOMEM;
  313. priv->dev = &pdev->dev;
  314. priv->soc_data = of_id->data;
  315. priv->num_ports = priv->soc_data->num_ports;
  316. priv->regmap = syscon_node_to_regmap(node->parent);
  317. if (IS_ERR(priv->regmap)) {
  318. ret = PTR_ERR(priv->regmap);
  319. dev_err(dev, "Failed to get syscon %d\n", ret);
  320. return ret;
  321. }
  322. ret = phy_gmii_sel_init_ports(priv);
  323. if (ret)
  324. return ret;
  325. dev_set_drvdata(&pdev->dev, priv);
  326. priv->phy_provider =
  327. devm_of_phy_provider_register(dev,
  328. phy_gmii_sel_of_xlate);
  329. if (IS_ERR(priv->phy_provider)) {
  330. ret = PTR_ERR(priv->phy_provider);
  331. dev_err(dev, "Failed to create phy provider %d\n", ret);
  332. return ret;
  333. }
  334. return 0;
  335. }
  336. static struct platform_driver phy_gmii_sel_driver = {
  337. .probe = phy_gmii_sel_probe,
  338. .driver = {
  339. .name = "phy-gmii-sel",
  340. .of_match_table = phy_gmii_sel_id_table,
  341. },
  342. };
  343. module_platform_driver(phy_gmii_sel_driver);
  344. MODULE_LICENSE("GPL v2");
  345. MODULE_AUTHOR("Grygorii Strashko <grygorii.strashko@ti.com>");
  346. MODULE_DESCRIPTION("TI CPSW Port's PHY Interface Mode selection Driver");