phy-am654-serdes.c 22 KB

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  1. // SPDX-License-Identifier: GPL-2.0
  2. /**
  3. * PCIe SERDES driver for AM654x SoC
  4. *
  5. * Copyright (C) 2018 - 2019 Texas Instruments Incorporated - http://www.ti.com/
  6. * Author: Kishon Vijay Abraham I <kishon@ti.com>
  7. */
  8. #include <dt-bindings/phy/phy.h>
  9. #include <linux/clk.h>
  10. #include <linux/clk-provider.h>
  11. #include <linux/delay.h>
  12. #include <linux/module.h>
  13. #include <linux/mfd/syscon.h>
  14. #include <linux/mux/consumer.h>
  15. #include <linux/of_address.h>
  16. #include <linux/phy/phy.h>
  17. #include <linux/platform_device.h>
  18. #include <linux/pm_runtime.h>
  19. #include <linux/regmap.h>
  20. #define CMU_R004 0x4
  21. #define CMU_R060 0x60
  22. #define CMU_R07C 0x7c
  23. #define CMU_R088 0x88
  24. #define CMU_R0D0 0xd0
  25. #define CMU_R0E8 0xe8
  26. #define LANE_R048 0x248
  27. #define LANE_R058 0x258
  28. #define LANE_R06c 0x26c
  29. #define LANE_R070 0x270
  30. #define LANE_R070 0x270
  31. #define LANE_R19C 0x39c
  32. #define COMLANE_R004 0xa04
  33. #define COMLANE_R138 0xb38
  34. #define VERSION_VAL 0x70
  35. #define COMLANE_R190 0xb90
  36. #define COMLANE_R194 0xb94
  37. #define COMRXEQ_R004 0x1404
  38. #define COMRXEQ_R008 0x1408
  39. #define COMRXEQ_R00C 0x140c
  40. #define COMRXEQ_R014 0x1414
  41. #define COMRXEQ_R018 0x1418
  42. #define COMRXEQ_R01C 0x141c
  43. #define COMRXEQ_R04C 0x144c
  44. #define COMRXEQ_R088 0x1488
  45. #define COMRXEQ_R094 0x1494
  46. #define COMRXEQ_R098 0x1498
  47. #define SERDES_CTRL 0x1fd0
  48. #define WIZ_LANEXCTL_STS 0x1fe0
  49. #define TX0_DISABLE_STATE 0x4
  50. #define TX0_SLEEP_STATE 0x5
  51. #define TX0_SNOOZE_STATE 0x6
  52. #define TX0_ENABLE_STATE 0x7
  53. #define RX0_DISABLE_STATE 0x4
  54. #define RX0_SLEEP_STATE 0x5
  55. #define RX0_SNOOZE_STATE 0x6
  56. #define RX0_ENABLE_STATE 0x7
  57. #define WIZ_PLL_CTRL 0x1ff4
  58. #define PLL_DISABLE_STATE 0x4
  59. #define PLL_SLEEP_STATE 0x5
  60. #define PLL_SNOOZE_STATE 0x6
  61. #define PLL_ENABLE_STATE 0x7
  62. #define PLL_LOCK_TIME 100000 /* in microseconds */
  63. #define SLEEP_TIME 100 /* in microseconds */
  64. #define LANE_USB3 0x0
  65. #define LANE_PCIE0_LANE0 0x1
  66. #define LANE_PCIE1_LANE0 0x0
  67. #define LANE_PCIE0_LANE1 0x1
  68. #define SERDES_NUM_CLOCKS 3
  69. #define AM654_SERDES_CTRL_CLKSEL_MASK GENMASK(7, 4)
  70. #define AM654_SERDES_CTRL_CLKSEL_SHIFT 4
  71. struct serdes_am654_clk_mux {
  72. struct clk_hw hw;
  73. struct regmap *regmap;
  74. unsigned int reg;
  75. int clk_id;
  76. struct clk_init_data clk_data;
  77. };
  78. #define to_serdes_am654_clk_mux(_hw) \
  79. container_of(_hw, struct serdes_am654_clk_mux, hw)
  80. static const struct regmap_config serdes_am654_regmap_config = {
  81. .reg_bits = 32,
  82. .val_bits = 32,
  83. .reg_stride = 4,
  84. .fast_io = true,
  85. .max_register = 0x1ffc,
  86. };
  87. enum serdes_am654_fields {
  88. /* CMU PLL Control */
  89. CMU_PLL_CTRL,
  90. LANE_PLL_CTRL_RXEQ_RXIDLE,
  91. /* CMU VCO bias current and VREG setting */
  92. AHB_PMA_CM_VCO_VBIAS_VREG,
  93. AHB_PMA_CM_VCO_BIAS_VREG,
  94. AHB_PMA_CM_SR,
  95. AHB_SSC_GEN_Z_O_20_13,
  96. /* AHB PMA Lane Configuration */
  97. AHB_PMA_LN_AGC_THSEL_VREGH,
  98. /* AGC and Signal detect threshold for Gen3 */
  99. AHB_PMA_LN_GEN3_AGC_SD_THSEL,
  100. AHB_PMA_LN_RX_SELR_GEN3,
  101. AHB_PMA_LN_TX_DRV,
  102. /* CMU Master Reset */
  103. CMU_MASTER_CDN,
  104. /* P2S ring buffer initial startup pointer difference */
  105. P2S_RBUF_PTR_DIFF,
  106. CONFIG_VERSION,
  107. /* Lane 1 Master Reset */
  108. L1_MASTER_CDN,
  109. /* CMU OK Status */
  110. CMU_OK_I_0,
  111. /* Mid-speed initial calibration control */
  112. COMRXEQ_MS_INIT_CTRL_7_0,
  113. /* High-speed initial calibration control */
  114. COMRXEQ_HS_INIT_CAL_7_0,
  115. /* Mid-speed recalibration control */
  116. COMRXEQ_MS_RECAL_CTRL_7_0,
  117. /* High-speed recalibration control */
  118. COMRXEQ_HS_RECAL_CTRL_7_0,
  119. /* ATT configuration */
  120. COMRXEQ_CSR_ATT_CONFIG,
  121. /* Edge based boost adaptation window length */
  122. COMRXEQ_CSR_EBSTADAPT_WIN_LEN,
  123. /* COMRXEQ control 3 & 4 */
  124. COMRXEQ_CTRL_3_4,
  125. /* COMRXEQ control 14, 15 and 16*/
  126. COMRXEQ_CTRL_14_15_16,
  127. /* Threshold for errors in pattern data */
  128. COMRXEQ_CSR_DLEV_ERR_THRESH,
  129. /* COMRXEQ control 25 */
  130. COMRXEQ_CTRL_25,
  131. /* Mid-speed rate change calibration control */
  132. CSR_RXEQ_RATE_CHANGE_CAL_RUN_RATE2_O,
  133. /* High-speed rate change calibration control */
  134. COMRXEQ_HS_RCHANGE_CTRL_7_0,
  135. /* Serdes reset */
  136. POR_EN,
  137. /* Tx Enable Value */
  138. TX0_ENABLE,
  139. /* Rx Enable Value */
  140. RX0_ENABLE,
  141. /* PLL Enable Value */
  142. PLL_ENABLE,
  143. /* PLL ready for use */
  144. PLL_OK,
  145. /* sentinel */
  146. MAX_FIELDS
  147. };
  148. static const struct reg_field serdes_am654_reg_fields[] = {
  149. [CMU_PLL_CTRL] = REG_FIELD(CMU_R004, 8, 15),
  150. [AHB_PMA_CM_VCO_VBIAS_VREG] = REG_FIELD(CMU_R060, 8, 15),
  151. [CMU_MASTER_CDN] = REG_FIELD(CMU_R07C, 24, 31),
  152. [AHB_PMA_CM_VCO_BIAS_VREG] = REG_FIELD(CMU_R088, 24, 31),
  153. [AHB_PMA_CM_SR] = REG_FIELD(CMU_R0D0, 24, 31),
  154. [AHB_SSC_GEN_Z_O_20_13] = REG_FIELD(CMU_R0E8, 8, 15),
  155. [LANE_PLL_CTRL_RXEQ_RXIDLE] = REG_FIELD(LANE_R048, 8, 15),
  156. [AHB_PMA_LN_AGC_THSEL_VREGH] = REG_FIELD(LANE_R058, 16, 23),
  157. [AHB_PMA_LN_GEN3_AGC_SD_THSEL] = REG_FIELD(LANE_R06c, 0, 7),
  158. [AHB_PMA_LN_RX_SELR_GEN3] = REG_FIELD(LANE_R070, 16, 23),
  159. [AHB_PMA_LN_TX_DRV] = REG_FIELD(LANE_R19C, 16, 23),
  160. [P2S_RBUF_PTR_DIFF] = REG_FIELD(COMLANE_R004, 0, 7),
  161. [CONFIG_VERSION] = REG_FIELD(COMLANE_R138, 16, 23),
  162. [L1_MASTER_CDN] = REG_FIELD(COMLANE_R190, 8, 15),
  163. [CMU_OK_I_0] = REG_FIELD(COMLANE_R194, 19, 19),
  164. [COMRXEQ_MS_INIT_CTRL_7_0] = REG_FIELD(COMRXEQ_R004, 24, 31),
  165. [COMRXEQ_HS_INIT_CAL_7_0] = REG_FIELD(COMRXEQ_R008, 0, 7),
  166. [COMRXEQ_MS_RECAL_CTRL_7_0] = REG_FIELD(COMRXEQ_R00C, 8, 15),
  167. [COMRXEQ_HS_RECAL_CTRL_7_0] = REG_FIELD(COMRXEQ_R00C, 16, 23),
  168. [COMRXEQ_CSR_ATT_CONFIG] = REG_FIELD(COMRXEQ_R014, 16, 23),
  169. [COMRXEQ_CSR_EBSTADAPT_WIN_LEN] = REG_FIELD(COMRXEQ_R018, 16, 23),
  170. [COMRXEQ_CTRL_3_4] = REG_FIELD(COMRXEQ_R01C, 8, 15),
  171. [COMRXEQ_CTRL_14_15_16] = REG_FIELD(COMRXEQ_R04C, 0, 7),
  172. [COMRXEQ_CSR_DLEV_ERR_THRESH] = REG_FIELD(COMRXEQ_R088, 16, 23),
  173. [COMRXEQ_CTRL_25] = REG_FIELD(COMRXEQ_R094, 24, 31),
  174. [CSR_RXEQ_RATE_CHANGE_CAL_RUN_RATE2_O] = REG_FIELD(COMRXEQ_R098, 8, 15),
  175. [COMRXEQ_HS_RCHANGE_CTRL_7_0] = REG_FIELD(COMRXEQ_R098, 16, 23),
  176. [POR_EN] = REG_FIELD(SERDES_CTRL, 29, 29),
  177. [TX0_ENABLE] = REG_FIELD(WIZ_LANEXCTL_STS, 29, 31),
  178. [RX0_ENABLE] = REG_FIELD(WIZ_LANEXCTL_STS, 13, 15),
  179. [PLL_ENABLE] = REG_FIELD(WIZ_PLL_CTRL, 29, 31),
  180. [PLL_OK] = REG_FIELD(WIZ_PLL_CTRL, 28, 28),
  181. };
  182. struct serdes_am654 {
  183. struct regmap *regmap;
  184. struct regmap_field *fields[MAX_FIELDS];
  185. struct device *dev;
  186. struct mux_control *control;
  187. bool busy;
  188. u32 type;
  189. struct device_node *of_node;
  190. struct clk_onecell_data clk_data;
  191. struct clk *clks[SERDES_NUM_CLOCKS];
  192. };
  193. static int serdes_am654_enable_pll(struct serdes_am654 *phy)
  194. {
  195. int ret;
  196. u32 val;
  197. ret = regmap_field_write(phy->fields[PLL_ENABLE], PLL_ENABLE_STATE);
  198. if (ret)
  199. return ret;
  200. return regmap_field_read_poll_timeout(phy->fields[PLL_OK], val, val,
  201. 1000, PLL_LOCK_TIME);
  202. }
  203. static void serdes_am654_disable_pll(struct serdes_am654 *phy)
  204. {
  205. struct device *dev = phy->dev;
  206. int ret;
  207. ret = regmap_field_write(phy->fields[PLL_ENABLE], PLL_DISABLE_STATE);
  208. if (ret)
  209. dev_err(dev, "Failed to disable PLL\n");
  210. }
  211. static int serdes_am654_enable_txrx(struct serdes_am654 *phy)
  212. {
  213. int ret = 0;
  214. /* Enable TX */
  215. ret |= regmap_field_write(phy->fields[TX0_ENABLE], TX0_ENABLE_STATE);
  216. /* Enable RX */
  217. ret |= regmap_field_write(phy->fields[RX0_ENABLE], RX0_ENABLE_STATE);
  218. if (ret)
  219. return -EIO;
  220. return 0;
  221. }
  222. static int serdes_am654_disable_txrx(struct serdes_am654 *phy)
  223. {
  224. int ret = 0;
  225. /* Disable TX */
  226. ret |= regmap_field_write(phy->fields[TX0_ENABLE], TX0_DISABLE_STATE);
  227. /* Disable RX */
  228. ret |= regmap_field_write(phy->fields[RX0_ENABLE], RX0_DISABLE_STATE);
  229. if (ret)
  230. return -EIO;
  231. return 0;
  232. }
  233. static int serdes_am654_power_on(struct phy *x)
  234. {
  235. struct serdes_am654 *phy = phy_get_drvdata(x);
  236. struct device *dev = phy->dev;
  237. int ret;
  238. u32 val;
  239. ret = serdes_am654_enable_pll(phy);
  240. if (ret) {
  241. dev_err(dev, "Failed to enable PLL\n");
  242. return ret;
  243. }
  244. ret = serdes_am654_enable_txrx(phy);
  245. if (ret) {
  246. dev_err(dev, "Failed to enable TX RX\n");
  247. return ret;
  248. }
  249. return regmap_field_read_poll_timeout(phy->fields[CMU_OK_I_0], val,
  250. val, SLEEP_TIME, PLL_LOCK_TIME);
  251. }
  252. static int serdes_am654_power_off(struct phy *x)
  253. {
  254. struct serdes_am654 *phy = phy_get_drvdata(x);
  255. serdes_am654_disable_txrx(phy);
  256. serdes_am654_disable_pll(phy);
  257. return 0;
  258. }
  259. #define SERDES_AM654_CFG(offset, a, b, val) \
  260. regmap_update_bits(phy->regmap, (offset),\
  261. GENMASK((a), (b)), (val) << (b))
  262. static int serdes_am654_usb3_init(struct serdes_am654 *phy)
  263. {
  264. SERDES_AM654_CFG(0x0000, 31, 24, 0x17);
  265. SERDES_AM654_CFG(0x0004, 15, 8, 0x02);
  266. SERDES_AM654_CFG(0x0004, 7, 0, 0x0e);
  267. SERDES_AM654_CFG(0x0008, 23, 16, 0x2e);
  268. SERDES_AM654_CFG(0x0008, 31, 24, 0x2e);
  269. SERDES_AM654_CFG(0x0060, 7, 0, 0x4b);
  270. SERDES_AM654_CFG(0x0060, 15, 8, 0x98);
  271. SERDES_AM654_CFG(0x0060, 23, 16, 0x60);
  272. SERDES_AM654_CFG(0x00d0, 31, 24, 0x45);
  273. SERDES_AM654_CFG(0x00e8, 15, 8, 0x0e);
  274. SERDES_AM654_CFG(0x0220, 7, 0, 0x34);
  275. SERDES_AM654_CFG(0x0220, 15, 8, 0x34);
  276. SERDES_AM654_CFG(0x0220, 31, 24, 0x37);
  277. SERDES_AM654_CFG(0x0224, 7, 0, 0x37);
  278. SERDES_AM654_CFG(0x0224, 15, 8, 0x37);
  279. SERDES_AM654_CFG(0x0228, 23, 16, 0x37);
  280. SERDES_AM654_CFG(0x0228, 31, 24, 0x37);
  281. SERDES_AM654_CFG(0x022c, 7, 0, 0x37);
  282. SERDES_AM654_CFG(0x022c, 15, 8, 0x37);
  283. SERDES_AM654_CFG(0x0230, 15, 8, 0x2a);
  284. SERDES_AM654_CFG(0x0230, 23, 16, 0x2a);
  285. SERDES_AM654_CFG(0x0240, 23, 16, 0x10);
  286. SERDES_AM654_CFG(0x0240, 31, 24, 0x34);
  287. SERDES_AM654_CFG(0x0244, 7, 0, 0x40);
  288. SERDES_AM654_CFG(0x0244, 23, 16, 0x34);
  289. SERDES_AM654_CFG(0x0248, 15, 8, 0x0d);
  290. SERDES_AM654_CFG(0x0258, 15, 8, 0x16);
  291. SERDES_AM654_CFG(0x0258, 23, 16, 0x84);
  292. SERDES_AM654_CFG(0x0258, 31, 24, 0xf2);
  293. SERDES_AM654_CFG(0x025c, 7, 0, 0x21);
  294. SERDES_AM654_CFG(0x0260, 7, 0, 0x27);
  295. SERDES_AM654_CFG(0x0260, 15, 8, 0x04);
  296. SERDES_AM654_CFG(0x0268, 15, 8, 0x04);
  297. SERDES_AM654_CFG(0x0288, 15, 8, 0x2c);
  298. SERDES_AM654_CFG(0x0330, 31, 24, 0xa0);
  299. SERDES_AM654_CFG(0x0338, 23, 16, 0x03);
  300. SERDES_AM654_CFG(0x0338, 31, 24, 0x00);
  301. SERDES_AM654_CFG(0x033c, 7, 0, 0x00);
  302. SERDES_AM654_CFG(0x0344, 31, 24, 0x18);
  303. SERDES_AM654_CFG(0x034c, 7, 0, 0x18);
  304. SERDES_AM654_CFG(0x039c, 23, 16, 0x3b);
  305. SERDES_AM654_CFG(0x0a04, 7, 0, 0x03);
  306. SERDES_AM654_CFG(0x0a14, 31, 24, 0x3c);
  307. SERDES_AM654_CFG(0x0a18, 15, 8, 0x3c);
  308. SERDES_AM654_CFG(0x0a38, 7, 0, 0x3e);
  309. SERDES_AM654_CFG(0x0a38, 15, 8, 0x3e);
  310. SERDES_AM654_CFG(0x0ae0, 7, 0, 0x07);
  311. SERDES_AM654_CFG(0x0b6c, 23, 16, 0xcd);
  312. SERDES_AM654_CFG(0x0b6c, 31, 24, 0x04);
  313. SERDES_AM654_CFG(0x0b98, 23, 16, 0x03);
  314. SERDES_AM654_CFG(0x1400, 7, 0, 0x3f);
  315. SERDES_AM654_CFG(0x1404, 23, 16, 0x6f);
  316. SERDES_AM654_CFG(0x1404, 31, 24, 0x6f);
  317. SERDES_AM654_CFG(0x140c, 7, 0, 0x6f);
  318. SERDES_AM654_CFG(0x140c, 15, 8, 0x6f);
  319. SERDES_AM654_CFG(0x1410, 15, 8, 0x27);
  320. SERDES_AM654_CFG(0x1414, 7, 0, 0x0c);
  321. SERDES_AM654_CFG(0x1414, 23, 16, 0x07);
  322. SERDES_AM654_CFG(0x1418, 23, 16, 0x40);
  323. SERDES_AM654_CFG(0x141c, 7, 0, 0x00);
  324. SERDES_AM654_CFG(0x141c, 15, 8, 0x1f);
  325. SERDES_AM654_CFG(0x1428, 31, 24, 0x08);
  326. SERDES_AM654_CFG(0x1434, 31, 24, 0x00);
  327. SERDES_AM654_CFG(0x1444, 7, 0, 0x94);
  328. SERDES_AM654_CFG(0x1460, 31, 24, 0x7f);
  329. SERDES_AM654_CFG(0x1464, 7, 0, 0x43);
  330. SERDES_AM654_CFG(0x1464, 23, 16, 0x6f);
  331. SERDES_AM654_CFG(0x1464, 31, 24, 0x43);
  332. SERDES_AM654_CFG(0x1484, 23, 16, 0x8f);
  333. SERDES_AM654_CFG(0x1498, 7, 0, 0x4f);
  334. SERDES_AM654_CFG(0x1498, 23, 16, 0x4f);
  335. SERDES_AM654_CFG(0x007c, 31, 24, 0x0d);
  336. SERDES_AM654_CFG(0x0b90, 15, 8, 0x0f);
  337. return 0;
  338. }
  339. static int serdes_am654_pcie_init(struct serdes_am654 *phy)
  340. {
  341. int ret = 0;
  342. ret |= regmap_field_write(phy->fields[CMU_PLL_CTRL], 0x2);
  343. ret |= regmap_field_write(phy->fields[AHB_PMA_CM_VCO_VBIAS_VREG], 0x98);
  344. ret |= regmap_field_write(phy->fields[AHB_PMA_CM_VCO_BIAS_VREG], 0x98);
  345. ret |= regmap_field_write(phy->fields[AHB_PMA_CM_SR], 0x45);
  346. ret |= regmap_field_write(phy->fields[AHB_SSC_GEN_Z_O_20_13], 0xe);
  347. ret |= regmap_field_write(phy->fields[LANE_PLL_CTRL_RXEQ_RXIDLE], 0x5);
  348. ret |= regmap_field_write(phy->fields[AHB_PMA_LN_AGC_THSEL_VREGH], 0x83);
  349. ret |= regmap_field_write(phy->fields[AHB_PMA_LN_GEN3_AGC_SD_THSEL], 0x83);
  350. ret |= regmap_field_write(phy->fields[AHB_PMA_LN_RX_SELR_GEN3], 0x81);
  351. ret |= regmap_field_write(phy->fields[AHB_PMA_LN_TX_DRV], 0x3b);
  352. ret |= regmap_field_write(phy->fields[P2S_RBUF_PTR_DIFF], 0x3);
  353. ret |= regmap_field_write(phy->fields[CONFIG_VERSION], VERSION_VAL);
  354. ret |= regmap_field_write(phy->fields[COMRXEQ_MS_INIT_CTRL_7_0], 0xf);
  355. ret |= regmap_field_write(phy->fields[COMRXEQ_HS_INIT_CAL_7_0], 0x4f);
  356. ret |= regmap_field_write(phy->fields[COMRXEQ_MS_RECAL_CTRL_7_0], 0xf);
  357. ret |= regmap_field_write(phy->fields[COMRXEQ_HS_RECAL_CTRL_7_0], 0x4f);
  358. ret |= regmap_field_write(phy->fields[COMRXEQ_CSR_ATT_CONFIG], 0x7);
  359. ret |= regmap_field_write(phy->fields[COMRXEQ_CSR_EBSTADAPT_WIN_LEN], 0x7f);
  360. ret |= regmap_field_write(phy->fields[COMRXEQ_CTRL_3_4], 0xf);
  361. ret |= regmap_field_write(phy->fields[COMRXEQ_CTRL_14_15_16], 0x9a);
  362. ret |= regmap_field_write(phy->fields[COMRXEQ_CSR_DLEV_ERR_THRESH], 0x32);
  363. ret |= regmap_field_write(phy->fields[COMRXEQ_CTRL_25], 0x80);
  364. ret |= regmap_field_write(phy->fields[CSR_RXEQ_RATE_CHANGE_CAL_RUN_RATE2_O], 0xf);
  365. ret |= regmap_field_write(phy->fields[COMRXEQ_HS_RCHANGE_CTRL_7_0], 0x4f);
  366. ret |= regmap_field_write(phy->fields[CMU_MASTER_CDN], 0x1);
  367. ret |= regmap_field_write(phy->fields[L1_MASTER_CDN], 0x2);
  368. if (ret)
  369. return -EIO;
  370. return 0;
  371. }
  372. static int serdes_am654_init(struct phy *x)
  373. {
  374. struct serdes_am654 *phy = phy_get_drvdata(x);
  375. switch (phy->type) {
  376. case PHY_TYPE_PCIE:
  377. return serdes_am654_pcie_init(phy);
  378. case PHY_TYPE_USB3:
  379. return serdes_am654_usb3_init(phy);
  380. default:
  381. return -EINVAL;
  382. }
  383. }
  384. static int serdes_am654_reset(struct phy *x)
  385. {
  386. struct serdes_am654 *phy = phy_get_drvdata(x);
  387. int ret = 0;
  388. serdes_am654_disable_pll(phy);
  389. serdes_am654_disable_txrx(phy);
  390. ret |= regmap_field_write(phy->fields[POR_EN], 0x1);
  391. mdelay(1);
  392. ret |= regmap_field_write(phy->fields[POR_EN], 0x0);
  393. if (ret)
  394. return -EIO;
  395. return 0;
  396. }
  397. static void serdes_am654_release(struct phy *x)
  398. {
  399. struct serdes_am654 *phy = phy_get_drvdata(x);
  400. phy->type = PHY_NONE;
  401. phy->busy = false;
  402. mux_control_deselect(phy->control);
  403. }
  404. static struct phy *serdes_am654_xlate(struct device *dev,
  405. struct of_phandle_args *args)
  406. {
  407. struct serdes_am654 *am654_phy;
  408. struct phy *phy;
  409. int ret;
  410. phy = of_phy_simple_xlate(dev, args);
  411. if (IS_ERR(phy))
  412. return phy;
  413. am654_phy = phy_get_drvdata(phy);
  414. if (am654_phy->busy)
  415. return ERR_PTR(-EBUSY);
  416. ret = mux_control_select(am654_phy->control, args->args[1]);
  417. if (ret) {
  418. dev_err(dev, "Failed to select SERDES Lane Function\n");
  419. return ERR_PTR(ret);
  420. }
  421. am654_phy->busy = true;
  422. am654_phy->type = args->args[0];
  423. return phy;
  424. }
  425. static const struct phy_ops ops = {
  426. .reset = serdes_am654_reset,
  427. .init = serdes_am654_init,
  428. .power_on = serdes_am654_power_on,
  429. .power_off = serdes_am654_power_off,
  430. .release = serdes_am654_release,
  431. .owner = THIS_MODULE,
  432. };
  433. #define SERDES_NUM_MUX_COMBINATIONS 16
  434. #define LICLK 0
  435. #define EXT_REFCLK 1
  436. #define RICLK 2
  437. static const int
  438. serdes_am654_mux_table[SERDES_NUM_MUX_COMBINATIONS][SERDES_NUM_CLOCKS] = {
  439. /*
  440. * Each combination maps to one of
  441. * "Figure 12-1986. SerDes Reference Clock Distribution"
  442. * in TRM.
  443. */
  444. /* Parent of CMU refclk, Left output, Right output
  445. * either of EXT_REFCLK, LICLK, RICLK
  446. */
  447. { EXT_REFCLK, EXT_REFCLK, EXT_REFCLK }, /* 0000 */
  448. { RICLK, EXT_REFCLK, EXT_REFCLK }, /* 0001 */
  449. { EXT_REFCLK, RICLK, LICLK }, /* 0010 */
  450. { RICLK, RICLK, EXT_REFCLK }, /* 0011 */
  451. { LICLK, EXT_REFCLK, EXT_REFCLK }, /* 0100 */
  452. { EXT_REFCLK, EXT_REFCLK, EXT_REFCLK }, /* 0101 */
  453. { LICLK, RICLK, LICLK }, /* 0110 */
  454. { EXT_REFCLK, RICLK, LICLK }, /* 0111 */
  455. { EXT_REFCLK, EXT_REFCLK, LICLK }, /* 1000 */
  456. { RICLK, EXT_REFCLK, LICLK }, /* 1001 */
  457. { EXT_REFCLK, RICLK, EXT_REFCLK }, /* 1010 */
  458. { RICLK, RICLK, EXT_REFCLK }, /* 1011 */
  459. { LICLK, EXT_REFCLK, LICLK }, /* 1100 */
  460. { EXT_REFCLK, EXT_REFCLK, LICLK }, /* 1101 */
  461. { LICLK, RICLK, EXT_REFCLK }, /* 1110 */
  462. { EXT_REFCLK, RICLK, EXT_REFCLK }, /* 1111 */
  463. };
  464. static u8 serdes_am654_clk_mux_get_parent(struct clk_hw *hw)
  465. {
  466. struct serdes_am654_clk_mux *mux = to_serdes_am654_clk_mux(hw);
  467. struct regmap *regmap = mux->regmap;
  468. unsigned int reg = mux->reg;
  469. unsigned int val;
  470. regmap_read(regmap, reg, &val);
  471. val &= AM654_SERDES_CTRL_CLKSEL_MASK;
  472. val >>= AM654_SERDES_CTRL_CLKSEL_SHIFT;
  473. return serdes_am654_mux_table[val][mux->clk_id];
  474. }
  475. static int serdes_am654_clk_mux_set_parent(struct clk_hw *hw, u8 index)
  476. {
  477. struct serdes_am654_clk_mux *mux = to_serdes_am654_clk_mux(hw);
  478. struct regmap *regmap = mux->regmap;
  479. const char *name = clk_hw_get_name(hw);
  480. unsigned int reg = mux->reg;
  481. int clk_id = mux->clk_id;
  482. int parents[SERDES_NUM_CLOCKS];
  483. const int *p;
  484. u32 val;
  485. int found, i;
  486. int ret;
  487. /* get existing setting */
  488. regmap_read(regmap, reg, &val);
  489. val &= AM654_SERDES_CTRL_CLKSEL_MASK;
  490. val >>= AM654_SERDES_CTRL_CLKSEL_SHIFT;
  491. for (i = 0; i < SERDES_NUM_CLOCKS; i++)
  492. parents[i] = serdes_am654_mux_table[val][i];
  493. /* change parent of this clock. others left intact */
  494. parents[clk_id] = index;
  495. /* Find the match */
  496. for (val = 0; val < SERDES_NUM_MUX_COMBINATIONS; val++) {
  497. p = serdes_am654_mux_table[val];
  498. found = 1;
  499. for (i = 0; i < SERDES_NUM_CLOCKS; i++) {
  500. if (parents[i] != p[i]) {
  501. found = 0;
  502. break;
  503. }
  504. }
  505. if (found)
  506. break;
  507. }
  508. if (!found) {
  509. /*
  510. * This can never happen, unless we missed
  511. * a valid combination in serdes_am654_mux_table.
  512. */
  513. WARN(1, "Failed to find the parent of %s clock\n", name);
  514. return -EINVAL;
  515. }
  516. val <<= AM654_SERDES_CTRL_CLKSEL_SHIFT;
  517. ret = regmap_update_bits(regmap, reg, AM654_SERDES_CTRL_CLKSEL_MASK,
  518. val);
  519. return ret;
  520. }
  521. static const struct clk_ops serdes_am654_clk_mux_ops = {
  522. .set_parent = serdes_am654_clk_mux_set_parent,
  523. .get_parent = serdes_am654_clk_mux_get_parent,
  524. };
  525. static int serdes_am654_clk_register(struct serdes_am654 *am654_phy,
  526. const char *clock_name, int clock_num)
  527. {
  528. struct device_node *node = am654_phy->of_node;
  529. struct device *dev = am654_phy->dev;
  530. struct serdes_am654_clk_mux *mux;
  531. struct device_node *regmap_node;
  532. const char **parent_names;
  533. struct clk_init_data *init;
  534. unsigned int num_parents;
  535. struct regmap *regmap;
  536. const __be32 *addr;
  537. unsigned int reg;
  538. struct clk *clk;
  539. int ret = 0;
  540. mux = devm_kzalloc(dev, sizeof(*mux), GFP_KERNEL);
  541. if (!mux)
  542. return -ENOMEM;
  543. init = &mux->clk_data;
  544. regmap_node = of_parse_phandle(node, "ti,serdes-clk", 0);
  545. if (!regmap_node) {
  546. dev_err(dev, "Fail to get serdes-clk node\n");
  547. ret = -ENODEV;
  548. goto out_put_node;
  549. }
  550. regmap = syscon_node_to_regmap(regmap_node->parent);
  551. if (IS_ERR(regmap)) {
  552. dev_err(dev, "Fail to get Syscon regmap\n");
  553. ret = PTR_ERR(regmap);
  554. goto out_put_node;
  555. }
  556. num_parents = of_clk_get_parent_count(node);
  557. if (num_parents < 2) {
  558. dev_err(dev, "SERDES clock must have parents\n");
  559. ret = -EINVAL;
  560. goto out_put_node;
  561. }
  562. parent_names = devm_kzalloc(dev, (sizeof(char *) * num_parents),
  563. GFP_KERNEL);
  564. if (!parent_names) {
  565. ret = -ENOMEM;
  566. goto out_put_node;
  567. }
  568. of_clk_parent_fill(node, parent_names, num_parents);
  569. addr = of_get_address(regmap_node, 0, NULL, NULL);
  570. if (!addr) {
  571. ret = -EINVAL;
  572. goto out_put_node;
  573. }
  574. reg = be32_to_cpu(*addr);
  575. init->ops = &serdes_am654_clk_mux_ops;
  576. init->flags = CLK_SET_RATE_NO_REPARENT;
  577. init->parent_names = parent_names;
  578. init->num_parents = num_parents;
  579. init->name = clock_name;
  580. mux->regmap = regmap;
  581. mux->reg = reg;
  582. mux->clk_id = clock_num;
  583. mux->hw.init = init;
  584. clk = devm_clk_register(dev, &mux->hw);
  585. if (IS_ERR(clk)) {
  586. ret = PTR_ERR(clk);
  587. goto out_put_node;
  588. }
  589. am654_phy->clks[clock_num] = clk;
  590. out_put_node:
  591. of_node_put(regmap_node);
  592. return ret;
  593. }
  594. static const struct of_device_id serdes_am654_id_table[] = {
  595. {
  596. .compatible = "ti,phy-am654-serdes",
  597. },
  598. {}
  599. };
  600. MODULE_DEVICE_TABLE(of, serdes_am654_id_table);
  601. static int serdes_am654_regfield_init(struct serdes_am654 *am654_phy)
  602. {
  603. struct regmap *regmap = am654_phy->regmap;
  604. struct device *dev = am654_phy->dev;
  605. int i;
  606. for (i = 0; i < MAX_FIELDS; i++) {
  607. am654_phy->fields[i] = devm_regmap_field_alloc(dev,
  608. regmap,
  609. serdes_am654_reg_fields[i]);
  610. if (IS_ERR(am654_phy->fields[i])) {
  611. dev_err(dev, "Unable to allocate regmap field %d\n", i);
  612. return PTR_ERR(am654_phy->fields[i]);
  613. }
  614. }
  615. return 0;
  616. }
  617. static int serdes_am654_probe(struct platform_device *pdev)
  618. {
  619. struct phy_provider *phy_provider;
  620. struct device *dev = &pdev->dev;
  621. struct device_node *node = dev->of_node;
  622. struct clk_onecell_data *clk_data;
  623. struct serdes_am654 *am654_phy;
  624. struct mux_control *control;
  625. const char *clock_name;
  626. struct regmap *regmap;
  627. void __iomem *base;
  628. struct phy *phy;
  629. int ret;
  630. int i;
  631. am654_phy = devm_kzalloc(dev, sizeof(*am654_phy), GFP_KERNEL);
  632. if (!am654_phy)
  633. return -ENOMEM;
  634. base = devm_platform_ioremap_resource(pdev, 0);
  635. if (IS_ERR(base))
  636. return PTR_ERR(base);
  637. regmap = devm_regmap_init_mmio(dev, base, &serdes_am654_regmap_config);
  638. if (IS_ERR(regmap)) {
  639. dev_err(dev, "Failed to initialize regmap\n");
  640. return PTR_ERR(regmap);
  641. }
  642. control = devm_mux_control_get(dev, NULL);
  643. if (IS_ERR(control))
  644. return PTR_ERR(control);
  645. am654_phy->dev = dev;
  646. am654_phy->of_node = node;
  647. am654_phy->regmap = regmap;
  648. am654_phy->control = control;
  649. am654_phy->type = PHY_NONE;
  650. ret = serdes_am654_regfield_init(am654_phy);
  651. if (ret) {
  652. dev_err(dev, "Failed to initialize regfields\n");
  653. return ret;
  654. }
  655. platform_set_drvdata(pdev, am654_phy);
  656. for (i = 0; i < SERDES_NUM_CLOCKS; i++) {
  657. ret = of_property_read_string_index(node, "clock-output-names",
  658. i, &clock_name);
  659. if (ret) {
  660. dev_err(dev, "Failed to get clock name\n");
  661. return ret;
  662. }
  663. ret = serdes_am654_clk_register(am654_phy, clock_name, i);
  664. if (ret) {
  665. dev_err(dev, "Failed to initialize clock %s\n",
  666. clock_name);
  667. return ret;
  668. }
  669. }
  670. clk_data = &am654_phy->clk_data;
  671. clk_data->clks = am654_phy->clks;
  672. clk_data->clk_num = SERDES_NUM_CLOCKS;
  673. ret = of_clk_add_provider(node, of_clk_src_onecell_get, clk_data);
  674. if (ret)
  675. return ret;
  676. pm_runtime_enable(dev);
  677. phy = devm_phy_create(dev, NULL, &ops);
  678. if (IS_ERR(phy)) {
  679. ret = PTR_ERR(phy);
  680. goto clk_err;
  681. }
  682. phy_set_drvdata(phy, am654_phy);
  683. phy_provider = devm_of_phy_provider_register(dev, serdes_am654_xlate);
  684. if (IS_ERR(phy_provider)) {
  685. ret = PTR_ERR(phy_provider);
  686. goto clk_err;
  687. }
  688. return 0;
  689. clk_err:
  690. of_clk_del_provider(node);
  691. return ret;
  692. }
  693. static int serdes_am654_remove(struct platform_device *pdev)
  694. {
  695. struct serdes_am654 *am654_phy = platform_get_drvdata(pdev);
  696. struct device_node *node = am654_phy->of_node;
  697. pm_runtime_disable(&pdev->dev);
  698. of_clk_del_provider(node);
  699. return 0;
  700. }
  701. static struct platform_driver serdes_am654_driver = {
  702. .probe = serdes_am654_probe,
  703. .remove = serdes_am654_remove,
  704. .driver = {
  705. .name = "phy-am654",
  706. .of_match_table = serdes_am654_id_table,
  707. },
  708. };
  709. module_platform_driver(serdes_am654_driver);
  710. MODULE_AUTHOR("Texas Instruments Inc.");
  711. MODULE_DESCRIPTION("TI AM654x SERDES driver");
  712. MODULE_LICENSE("GPL v2");