phy-stm32-usbphyc.c 11 KB

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  1. // SPDX-License-Identifier: GPL-2.0
  2. /*
  3. * STMicroelectronics STM32 USB PHY Controller driver
  4. *
  5. * Copyright (C) 2018 STMicroelectronics
  6. * Author(s): Amelie Delaunay <amelie.delaunay@st.com>.
  7. */
  8. #include <linux/bitfield.h>
  9. #include <linux/clk.h>
  10. #include <linux/delay.h>
  11. #include <linux/io.h>
  12. #include <linux/kernel.h>
  13. #include <linux/module.h>
  14. #include <linux/of_platform.h>
  15. #include <linux/phy/phy.h>
  16. #include <linux/reset.h>
  17. #define STM32_USBPHYC_PLL 0x0
  18. #define STM32_USBPHYC_MISC 0x8
  19. #define STM32_USBPHYC_VERSION 0x3F4
  20. /* STM32_USBPHYC_PLL bit fields */
  21. #define PLLNDIV GENMASK(6, 0)
  22. #define PLLFRACIN GENMASK(25, 10)
  23. #define PLLEN BIT(26)
  24. #define PLLSTRB BIT(27)
  25. #define PLLSTRBYP BIT(28)
  26. #define PLLFRACCTL BIT(29)
  27. #define PLLDITHEN0 BIT(30)
  28. #define PLLDITHEN1 BIT(31)
  29. /* STM32_USBPHYC_MISC bit fields */
  30. #define SWITHOST BIT(0)
  31. /* STM32_USBPHYC_VERSION bit fields */
  32. #define MINREV GENMASK(3, 0)
  33. #define MAJREV GENMASK(7, 4)
  34. static const char * const supplies_names[] = {
  35. "vdda1v1", /* 1V1 */
  36. "vdda1v8", /* 1V8 */
  37. };
  38. #define NUM_SUPPLIES ARRAY_SIZE(supplies_names)
  39. #define PLL_LOCK_TIME_US 100
  40. #define PLL_PWR_DOWN_TIME_US 5
  41. #define PLL_FVCO_MHZ 2880
  42. #define PLL_INFF_MIN_RATE_HZ 19200000
  43. #define PLL_INFF_MAX_RATE_HZ 38400000
  44. #define HZ_PER_MHZ 1000000L
  45. struct pll_params {
  46. u8 ndiv;
  47. u16 frac;
  48. };
  49. struct stm32_usbphyc_phy {
  50. struct phy *phy;
  51. struct stm32_usbphyc *usbphyc;
  52. struct regulator_bulk_data supplies[NUM_SUPPLIES];
  53. u32 index;
  54. bool active;
  55. };
  56. struct stm32_usbphyc {
  57. struct device *dev;
  58. void __iomem *base;
  59. struct clk *clk;
  60. struct reset_control *rst;
  61. struct stm32_usbphyc_phy **phys;
  62. int nphys;
  63. int switch_setup;
  64. };
  65. static inline void stm32_usbphyc_set_bits(void __iomem *reg, u32 bits)
  66. {
  67. writel_relaxed(readl_relaxed(reg) | bits, reg);
  68. }
  69. static inline void stm32_usbphyc_clr_bits(void __iomem *reg, u32 bits)
  70. {
  71. writel_relaxed(readl_relaxed(reg) & ~bits, reg);
  72. }
  73. static void stm32_usbphyc_get_pll_params(u32 clk_rate,
  74. struct pll_params *pll_params)
  75. {
  76. unsigned long long fvco, ndiv, frac;
  77. /* _
  78. * | FVCO = INFF*2*(NDIV + FRACT/2^16) when DITHER_DISABLE[1] = 1
  79. * | FVCO = 2880MHz
  80. * <
  81. * | NDIV = integer part of input bits to set the LDF
  82. * |_FRACT = fractional part of input bits to set the LDF
  83. * => PLLNDIV = integer part of (FVCO / (INFF*2))
  84. * => PLLFRACIN = fractional part of(FVCO / INFF*2) * 2^16
  85. * <=> PLLFRACIN = ((FVCO / (INFF*2)) - PLLNDIV) * 2^16
  86. */
  87. fvco = (unsigned long long)PLL_FVCO_MHZ * HZ_PER_MHZ;
  88. ndiv = fvco;
  89. do_div(ndiv, (clk_rate * 2));
  90. pll_params->ndiv = (u8)ndiv;
  91. frac = fvco * (1 << 16);
  92. do_div(frac, (clk_rate * 2));
  93. frac = frac - (ndiv * (1 << 16));
  94. pll_params->frac = (u16)frac;
  95. }
  96. static int stm32_usbphyc_pll_init(struct stm32_usbphyc *usbphyc)
  97. {
  98. struct pll_params pll_params;
  99. u32 clk_rate = clk_get_rate(usbphyc->clk);
  100. u32 ndiv, frac;
  101. u32 usbphyc_pll;
  102. if ((clk_rate < PLL_INFF_MIN_RATE_HZ) ||
  103. (clk_rate > PLL_INFF_MAX_RATE_HZ)) {
  104. dev_err(usbphyc->dev, "input clk freq (%dHz) out of range\n",
  105. clk_rate);
  106. return -EINVAL;
  107. }
  108. stm32_usbphyc_get_pll_params(clk_rate, &pll_params);
  109. ndiv = FIELD_PREP(PLLNDIV, pll_params.ndiv);
  110. frac = FIELD_PREP(PLLFRACIN, pll_params.frac);
  111. usbphyc_pll = PLLDITHEN1 | PLLDITHEN0 | PLLSTRBYP | ndiv;
  112. if (pll_params.frac)
  113. usbphyc_pll |= PLLFRACCTL | frac;
  114. writel_relaxed(usbphyc_pll, usbphyc->base + STM32_USBPHYC_PLL);
  115. dev_dbg(usbphyc->dev, "input clk freq=%dHz, ndiv=%lu, frac=%lu\n",
  116. clk_rate, FIELD_GET(PLLNDIV, usbphyc_pll),
  117. FIELD_GET(PLLFRACIN, usbphyc_pll));
  118. return 0;
  119. }
  120. static bool stm32_usbphyc_has_one_phy_active(struct stm32_usbphyc *usbphyc)
  121. {
  122. int i;
  123. for (i = 0; i < usbphyc->nphys; i++)
  124. if (usbphyc->phys[i]->active)
  125. return true;
  126. return false;
  127. }
  128. static int stm32_usbphyc_pll_enable(struct stm32_usbphyc *usbphyc)
  129. {
  130. void __iomem *pll_reg = usbphyc->base + STM32_USBPHYC_PLL;
  131. bool pllen = (readl_relaxed(pll_reg) & PLLEN);
  132. int ret;
  133. /* Check if one phy port has already configured the pll */
  134. if (pllen && stm32_usbphyc_has_one_phy_active(usbphyc))
  135. return 0;
  136. if (pllen) {
  137. stm32_usbphyc_clr_bits(pll_reg, PLLEN);
  138. /* Wait for minimum width of powerdown pulse (ENABLE = Low) */
  139. udelay(PLL_PWR_DOWN_TIME_US);
  140. }
  141. ret = stm32_usbphyc_pll_init(usbphyc);
  142. if (ret)
  143. return ret;
  144. stm32_usbphyc_set_bits(pll_reg, PLLEN);
  145. /* Wait for maximum lock time */
  146. udelay(PLL_LOCK_TIME_US);
  147. if (!(readl_relaxed(pll_reg) & PLLEN)) {
  148. dev_err(usbphyc->dev, "PLLEN not set\n");
  149. return -EIO;
  150. }
  151. return 0;
  152. }
  153. static int stm32_usbphyc_pll_disable(struct stm32_usbphyc *usbphyc)
  154. {
  155. void __iomem *pll_reg = usbphyc->base + STM32_USBPHYC_PLL;
  156. /* Check if other phy port active */
  157. if (stm32_usbphyc_has_one_phy_active(usbphyc))
  158. return 0;
  159. stm32_usbphyc_clr_bits(pll_reg, PLLEN);
  160. /* Wait for minimum width of powerdown pulse (ENABLE = Low) */
  161. udelay(PLL_PWR_DOWN_TIME_US);
  162. if (readl_relaxed(pll_reg) & PLLEN) {
  163. dev_err(usbphyc->dev, "PLL not reset\n");
  164. return -EIO;
  165. }
  166. return 0;
  167. }
  168. static int stm32_usbphyc_phy_init(struct phy *phy)
  169. {
  170. struct stm32_usbphyc_phy *usbphyc_phy = phy_get_drvdata(phy);
  171. struct stm32_usbphyc *usbphyc = usbphyc_phy->usbphyc;
  172. int ret;
  173. ret = stm32_usbphyc_pll_enable(usbphyc);
  174. if (ret)
  175. return ret;
  176. usbphyc_phy->active = true;
  177. return 0;
  178. }
  179. static int stm32_usbphyc_phy_exit(struct phy *phy)
  180. {
  181. struct stm32_usbphyc_phy *usbphyc_phy = phy_get_drvdata(phy);
  182. struct stm32_usbphyc *usbphyc = usbphyc_phy->usbphyc;
  183. usbphyc_phy->active = false;
  184. return stm32_usbphyc_pll_disable(usbphyc);
  185. }
  186. static int stm32_usbphyc_phy_power_on(struct phy *phy)
  187. {
  188. struct stm32_usbphyc_phy *usbphyc_phy = phy_get_drvdata(phy);
  189. return regulator_bulk_enable(NUM_SUPPLIES, usbphyc_phy->supplies);
  190. }
  191. static int stm32_usbphyc_phy_power_off(struct phy *phy)
  192. {
  193. struct stm32_usbphyc_phy *usbphyc_phy = phy_get_drvdata(phy);
  194. return regulator_bulk_disable(NUM_SUPPLIES, usbphyc_phy->supplies);
  195. }
  196. static const struct phy_ops stm32_usbphyc_phy_ops = {
  197. .init = stm32_usbphyc_phy_init,
  198. .exit = stm32_usbphyc_phy_exit,
  199. .power_on = stm32_usbphyc_phy_power_on,
  200. .power_off = stm32_usbphyc_phy_power_off,
  201. .owner = THIS_MODULE,
  202. };
  203. static void stm32_usbphyc_switch_setup(struct stm32_usbphyc *usbphyc,
  204. u32 utmi_switch)
  205. {
  206. if (!utmi_switch)
  207. stm32_usbphyc_clr_bits(usbphyc->base + STM32_USBPHYC_MISC,
  208. SWITHOST);
  209. else
  210. stm32_usbphyc_set_bits(usbphyc->base + STM32_USBPHYC_MISC,
  211. SWITHOST);
  212. usbphyc->switch_setup = utmi_switch;
  213. }
  214. static struct phy *stm32_usbphyc_of_xlate(struct device *dev,
  215. struct of_phandle_args *args)
  216. {
  217. struct stm32_usbphyc *usbphyc = dev_get_drvdata(dev);
  218. struct stm32_usbphyc_phy *usbphyc_phy = NULL;
  219. struct device_node *phynode = args->np;
  220. int port = 0;
  221. for (port = 0; port < usbphyc->nphys; port++) {
  222. if (phynode == usbphyc->phys[port]->phy->dev.of_node) {
  223. usbphyc_phy = usbphyc->phys[port];
  224. break;
  225. }
  226. }
  227. if (!usbphyc_phy) {
  228. dev_err(dev, "failed to find phy\n");
  229. return ERR_PTR(-EINVAL);
  230. }
  231. if (((usbphyc_phy->index == 0) && (args->args_count != 0)) ||
  232. ((usbphyc_phy->index == 1) && (args->args_count != 1))) {
  233. dev_err(dev, "invalid number of cells for phy port%d\n",
  234. usbphyc_phy->index);
  235. return ERR_PTR(-EINVAL);
  236. }
  237. /* Configure the UTMI switch for PHY port#2 */
  238. if (usbphyc_phy->index == 1) {
  239. if (usbphyc->switch_setup < 0) {
  240. stm32_usbphyc_switch_setup(usbphyc, args->args[0]);
  241. } else {
  242. if (args->args[0] != usbphyc->switch_setup) {
  243. dev_err(dev, "phy port1 already used\n");
  244. return ERR_PTR(-EBUSY);
  245. }
  246. }
  247. }
  248. return usbphyc_phy->phy;
  249. }
  250. static int stm32_usbphyc_probe(struct platform_device *pdev)
  251. {
  252. struct stm32_usbphyc *usbphyc;
  253. struct device *dev = &pdev->dev;
  254. struct device_node *child, *np = dev->of_node;
  255. struct resource *res;
  256. struct phy_provider *phy_provider;
  257. u32 version;
  258. int ret, port = 0;
  259. usbphyc = devm_kzalloc(dev, sizeof(*usbphyc), GFP_KERNEL);
  260. if (!usbphyc)
  261. return -ENOMEM;
  262. usbphyc->dev = dev;
  263. dev_set_drvdata(dev, usbphyc);
  264. res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
  265. usbphyc->base = devm_ioremap_resource(dev, res);
  266. if (IS_ERR(usbphyc->base))
  267. return PTR_ERR(usbphyc->base);
  268. usbphyc->clk = devm_clk_get(dev, NULL);
  269. if (IS_ERR(usbphyc->clk)) {
  270. ret = PTR_ERR(usbphyc->clk);
  271. dev_err(dev, "clk get failed: %d\n", ret);
  272. return ret;
  273. }
  274. ret = clk_prepare_enable(usbphyc->clk);
  275. if (ret) {
  276. dev_err(dev, "clk enable failed: %d\n", ret);
  277. return ret;
  278. }
  279. usbphyc->rst = devm_reset_control_get(dev, NULL);
  280. if (!IS_ERR(usbphyc->rst)) {
  281. reset_control_assert(usbphyc->rst);
  282. udelay(2);
  283. reset_control_deassert(usbphyc->rst);
  284. }
  285. usbphyc->switch_setup = -EINVAL;
  286. usbphyc->nphys = of_get_child_count(np);
  287. usbphyc->phys = devm_kcalloc(dev, usbphyc->nphys,
  288. sizeof(*usbphyc->phys), GFP_KERNEL);
  289. if (!usbphyc->phys) {
  290. ret = -ENOMEM;
  291. goto clk_disable;
  292. }
  293. for_each_child_of_node(np, child) {
  294. struct stm32_usbphyc_phy *usbphyc_phy;
  295. struct phy *phy;
  296. u32 index;
  297. int i;
  298. phy = devm_phy_create(dev, child, &stm32_usbphyc_phy_ops);
  299. if (IS_ERR(phy)) {
  300. ret = PTR_ERR(phy);
  301. if (ret != -EPROBE_DEFER)
  302. dev_err(dev, "failed to create phy%d: %d\n",
  303. port, ret);
  304. goto put_child;
  305. }
  306. usbphyc_phy = devm_kzalloc(dev, sizeof(*usbphyc_phy),
  307. GFP_KERNEL);
  308. if (!usbphyc_phy) {
  309. ret = -ENOMEM;
  310. goto put_child;
  311. }
  312. for (i = 0; i < NUM_SUPPLIES; i++)
  313. usbphyc_phy->supplies[i].supply = supplies_names[i];
  314. ret = devm_regulator_bulk_get(&phy->dev, NUM_SUPPLIES,
  315. usbphyc_phy->supplies);
  316. if (ret) {
  317. if (ret != -EPROBE_DEFER)
  318. dev_err(&phy->dev,
  319. "failed to get regulators: %d\n", ret);
  320. goto put_child;
  321. }
  322. ret = of_property_read_u32(child, "reg", &index);
  323. if (ret || index > usbphyc->nphys) {
  324. dev_err(&phy->dev, "invalid reg property: %d\n", ret);
  325. goto put_child;
  326. }
  327. usbphyc->phys[port] = usbphyc_phy;
  328. phy_set_bus_width(phy, 8);
  329. phy_set_drvdata(phy, usbphyc_phy);
  330. usbphyc->phys[port]->phy = phy;
  331. usbphyc->phys[port]->usbphyc = usbphyc;
  332. usbphyc->phys[port]->index = index;
  333. usbphyc->phys[port]->active = false;
  334. port++;
  335. }
  336. phy_provider = devm_of_phy_provider_register(dev,
  337. stm32_usbphyc_of_xlate);
  338. if (IS_ERR(phy_provider)) {
  339. ret = PTR_ERR(phy_provider);
  340. dev_err(dev, "failed to register phy provider: %d\n", ret);
  341. goto clk_disable;
  342. }
  343. version = readl_relaxed(usbphyc->base + STM32_USBPHYC_VERSION);
  344. dev_info(dev, "registered rev:%lu.%lu\n",
  345. FIELD_GET(MAJREV, version), FIELD_GET(MINREV, version));
  346. return 0;
  347. put_child:
  348. of_node_put(child);
  349. clk_disable:
  350. clk_disable_unprepare(usbphyc->clk);
  351. return ret;
  352. }
  353. static int stm32_usbphyc_remove(struct platform_device *pdev)
  354. {
  355. struct stm32_usbphyc *usbphyc = dev_get_drvdata(&pdev->dev);
  356. clk_disable_unprepare(usbphyc->clk);
  357. return 0;
  358. }
  359. static const struct of_device_id stm32_usbphyc_of_match[] = {
  360. { .compatible = "st,stm32mp1-usbphyc", },
  361. { },
  362. };
  363. MODULE_DEVICE_TABLE(of, stm32_usbphyc_of_match);
  364. static struct platform_driver stm32_usbphyc_driver = {
  365. .probe = stm32_usbphyc_probe,
  366. .remove = stm32_usbphyc_remove,
  367. .driver = {
  368. .of_match_table = stm32_usbphyc_of_match,
  369. .name = "stm32-usbphyc",
  370. }
  371. };
  372. module_platform_driver(stm32_usbphyc_driver);
  373. MODULE_DESCRIPTION("STMicroelectronics STM32 USBPHYC driver");
  374. MODULE_AUTHOR("Amelie Delaunay <amelie.delaunay@st.com>");
  375. MODULE_LICENSE("GPL v2");