phy-spear1340-miphy.c 8.0 KB

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  1. // SPDX-License-Identifier: GPL-2.0-only
  2. /*
  3. * ST spear1340-miphy driver
  4. *
  5. * Copyright (C) 2014 ST Microelectronics
  6. * Pratyush Anand <pratyush.anand@gmail.com>
  7. * Mohit Kumar <mohit.kumar.dhaka@gmail.com>
  8. */
  9. #include <linux/bitops.h>
  10. #include <linux/delay.h>
  11. #include <linux/dma-mapping.h>
  12. #include <linux/kernel.h>
  13. #include <linux/mfd/syscon.h>
  14. #include <linux/module.h>
  15. #include <linux/of_device.h>
  16. #include <linux/phy/phy.h>
  17. #include <linux/regmap.h>
  18. /* SPEAr1340 Registers */
  19. /* Power Management Registers */
  20. #define SPEAR1340_PCM_CFG 0x100
  21. #define SPEAR1340_PCM_CFG_SATA_POWER_EN BIT(11)
  22. #define SPEAR1340_PCM_WKUP_CFG 0x104
  23. #define SPEAR1340_SWITCH_CTR 0x108
  24. #define SPEAR1340_PERIP1_SW_RST 0x318
  25. #define SPEAR1340_PERIP1_SW_RSATA BIT(12)
  26. #define SPEAR1340_PERIP2_SW_RST 0x31C
  27. #define SPEAR1340_PERIP3_SW_RST 0x320
  28. /* PCIE - SATA configuration registers */
  29. #define SPEAR1340_PCIE_SATA_CFG 0x424
  30. /* PCIE CFG MASks */
  31. #define SPEAR1340_PCIE_CFG_DEVICE_PRESENT BIT(11)
  32. #define SPEAR1340_PCIE_CFG_POWERUP_RESET BIT(10)
  33. #define SPEAR1340_PCIE_CFG_CORE_CLK_EN BIT(9)
  34. #define SPEAR1340_PCIE_CFG_AUX_CLK_EN BIT(8)
  35. #define SPEAR1340_SATA_CFG_TX_CLK_EN BIT(4)
  36. #define SPEAR1340_SATA_CFG_RX_CLK_EN BIT(3)
  37. #define SPEAR1340_SATA_CFG_POWERUP_RESET BIT(2)
  38. #define SPEAR1340_SATA_CFG_PM_CLK_EN BIT(1)
  39. #define SPEAR1340_PCIE_SATA_SEL_PCIE (0)
  40. #define SPEAR1340_PCIE_SATA_SEL_SATA (1)
  41. #define SPEAR1340_PCIE_SATA_CFG_MASK 0xF1F
  42. #define SPEAR1340_PCIE_CFG_VAL (SPEAR1340_PCIE_SATA_SEL_PCIE | \
  43. SPEAR1340_PCIE_CFG_AUX_CLK_EN | \
  44. SPEAR1340_PCIE_CFG_CORE_CLK_EN | \
  45. SPEAR1340_PCIE_CFG_POWERUP_RESET | \
  46. SPEAR1340_PCIE_CFG_DEVICE_PRESENT)
  47. #define SPEAR1340_SATA_CFG_VAL (SPEAR1340_PCIE_SATA_SEL_SATA | \
  48. SPEAR1340_SATA_CFG_PM_CLK_EN | \
  49. SPEAR1340_SATA_CFG_POWERUP_RESET | \
  50. SPEAR1340_SATA_CFG_RX_CLK_EN | \
  51. SPEAR1340_SATA_CFG_TX_CLK_EN)
  52. #define SPEAR1340_PCIE_MIPHY_CFG 0x428
  53. #define SPEAR1340_MIPHY_OSC_BYPASS_EXT BIT(31)
  54. #define SPEAR1340_MIPHY_CLK_REF_DIV2 BIT(27)
  55. #define SPEAR1340_MIPHY_CLK_REF_DIV4 (2 << 27)
  56. #define SPEAR1340_MIPHY_CLK_REF_DIV8 (3 << 27)
  57. #define SPEAR1340_MIPHY_PLL_RATIO_TOP(x) (x << 0)
  58. #define SPEAR1340_PCIE_MIPHY_CFG_MASK 0xF80000FF
  59. #define SPEAR1340_PCIE_SATA_MIPHY_CFG_SATA \
  60. (SPEAR1340_MIPHY_OSC_BYPASS_EXT | \
  61. SPEAR1340_MIPHY_CLK_REF_DIV2 | \
  62. SPEAR1340_MIPHY_PLL_RATIO_TOP(60))
  63. #define SPEAR1340_PCIE_SATA_MIPHY_CFG_SATA_25M_CRYSTAL_CLK \
  64. (SPEAR1340_MIPHY_PLL_RATIO_TOP(120))
  65. #define SPEAR1340_PCIE_SATA_MIPHY_CFG_PCIE \
  66. (SPEAR1340_MIPHY_OSC_BYPASS_EXT | \
  67. SPEAR1340_MIPHY_PLL_RATIO_TOP(25))
  68. enum spear1340_miphy_mode {
  69. SATA,
  70. PCIE,
  71. };
  72. struct spear1340_miphy_priv {
  73. /* phy mode: 0 for SATA 1 for PCIe */
  74. enum spear1340_miphy_mode mode;
  75. /* regmap for any soc specific misc registers */
  76. struct regmap *misc;
  77. /* phy struct pointer */
  78. struct phy *phy;
  79. };
  80. static int spear1340_miphy_sata_init(struct spear1340_miphy_priv *priv)
  81. {
  82. regmap_update_bits(priv->misc, SPEAR1340_PCIE_SATA_CFG,
  83. SPEAR1340_PCIE_SATA_CFG_MASK,
  84. SPEAR1340_SATA_CFG_VAL);
  85. regmap_update_bits(priv->misc, SPEAR1340_PCIE_MIPHY_CFG,
  86. SPEAR1340_PCIE_MIPHY_CFG_MASK,
  87. SPEAR1340_PCIE_SATA_MIPHY_CFG_SATA_25M_CRYSTAL_CLK);
  88. /* Switch on sata power domain */
  89. regmap_update_bits(priv->misc, SPEAR1340_PCM_CFG,
  90. SPEAR1340_PCM_CFG_SATA_POWER_EN,
  91. SPEAR1340_PCM_CFG_SATA_POWER_EN);
  92. /* Wait for SATA power domain on */
  93. msleep(20);
  94. /* Disable PCIE SATA Controller reset */
  95. regmap_update_bits(priv->misc, SPEAR1340_PERIP1_SW_RST,
  96. SPEAR1340_PERIP1_SW_RSATA, 0);
  97. /* Wait for SATA reset de-assert completion */
  98. msleep(20);
  99. return 0;
  100. }
  101. static int spear1340_miphy_sata_exit(struct spear1340_miphy_priv *priv)
  102. {
  103. regmap_update_bits(priv->misc, SPEAR1340_PCIE_SATA_CFG,
  104. SPEAR1340_PCIE_SATA_CFG_MASK, 0);
  105. regmap_update_bits(priv->misc, SPEAR1340_PCIE_MIPHY_CFG,
  106. SPEAR1340_PCIE_MIPHY_CFG_MASK, 0);
  107. /* Enable PCIE SATA Controller reset */
  108. regmap_update_bits(priv->misc, SPEAR1340_PERIP1_SW_RST,
  109. SPEAR1340_PERIP1_SW_RSATA,
  110. SPEAR1340_PERIP1_SW_RSATA);
  111. /* Wait for SATA power domain off */
  112. msleep(20);
  113. /* Switch off sata power domain */
  114. regmap_update_bits(priv->misc, SPEAR1340_PCM_CFG,
  115. SPEAR1340_PCM_CFG_SATA_POWER_EN, 0);
  116. /* Wait for SATA reset assert completion */
  117. msleep(20);
  118. return 0;
  119. }
  120. static int spear1340_miphy_pcie_init(struct spear1340_miphy_priv *priv)
  121. {
  122. regmap_update_bits(priv->misc, SPEAR1340_PCIE_MIPHY_CFG,
  123. SPEAR1340_PCIE_MIPHY_CFG_MASK,
  124. SPEAR1340_PCIE_SATA_MIPHY_CFG_PCIE);
  125. regmap_update_bits(priv->misc, SPEAR1340_PCIE_SATA_CFG,
  126. SPEAR1340_PCIE_SATA_CFG_MASK,
  127. SPEAR1340_PCIE_CFG_VAL);
  128. return 0;
  129. }
  130. static int spear1340_miphy_pcie_exit(struct spear1340_miphy_priv *priv)
  131. {
  132. regmap_update_bits(priv->misc, SPEAR1340_PCIE_MIPHY_CFG,
  133. SPEAR1340_PCIE_MIPHY_CFG_MASK, 0);
  134. regmap_update_bits(priv->misc, SPEAR1340_PCIE_SATA_CFG,
  135. SPEAR1340_PCIE_SATA_CFG_MASK, 0);
  136. return 0;
  137. }
  138. static int spear1340_miphy_init(struct phy *phy)
  139. {
  140. struct spear1340_miphy_priv *priv = phy_get_drvdata(phy);
  141. int ret = 0;
  142. if (priv->mode == SATA)
  143. ret = spear1340_miphy_sata_init(priv);
  144. else if (priv->mode == PCIE)
  145. ret = spear1340_miphy_pcie_init(priv);
  146. return ret;
  147. }
  148. static int spear1340_miphy_exit(struct phy *phy)
  149. {
  150. struct spear1340_miphy_priv *priv = phy_get_drvdata(phy);
  151. int ret = 0;
  152. if (priv->mode == SATA)
  153. ret = spear1340_miphy_sata_exit(priv);
  154. else if (priv->mode == PCIE)
  155. ret = spear1340_miphy_pcie_exit(priv);
  156. return ret;
  157. }
  158. static const struct of_device_id spear1340_miphy_of_match[] = {
  159. { .compatible = "st,spear1340-miphy" },
  160. { },
  161. };
  162. MODULE_DEVICE_TABLE(of, spear1340_miphy_of_match);
  163. static const struct phy_ops spear1340_miphy_ops = {
  164. .init = spear1340_miphy_init,
  165. .exit = spear1340_miphy_exit,
  166. .owner = THIS_MODULE,
  167. };
  168. #ifdef CONFIG_PM_SLEEP
  169. static int spear1340_miphy_suspend(struct device *dev)
  170. {
  171. struct spear1340_miphy_priv *priv = dev_get_drvdata(dev);
  172. int ret = 0;
  173. if (priv->mode == SATA)
  174. ret = spear1340_miphy_sata_exit(priv);
  175. return ret;
  176. }
  177. static int spear1340_miphy_resume(struct device *dev)
  178. {
  179. struct spear1340_miphy_priv *priv = dev_get_drvdata(dev);
  180. int ret = 0;
  181. if (priv->mode == SATA)
  182. ret = spear1340_miphy_sata_init(priv);
  183. return ret;
  184. }
  185. #endif
  186. static SIMPLE_DEV_PM_OPS(spear1340_miphy_pm_ops, spear1340_miphy_suspend,
  187. spear1340_miphy_resume);
  188. static struct phy *spear1340_miphy_xlate(struct device *dev,
  189. struct of_phandle_args *args)
  190. {
  191. struct spear1340_miphy_priv *priv = dev_get_drvdata(dev);
  192. if (args->args_count < 1) {
  193. dev_err(dev, "DT did not pass correct no of args\n");
  194. return ERR_PTR(-ENODEV);
  195. }
  196. priv->mode = args->args[0];
  197. if (priv->mode != SATA && priv->mode != PCIE) {
  198. dev_err(dev, "DT did not pass correct phy mode\n");
  199. return ERR_PTR(-ENODEV);
  200. }
  201. return priv->phy;
  202. }
  203. static int spear1340_miphy_probe(struct platform_device *pdev)
  204. {
  205. struct device *dev = &pdev->dev;
  206. struct spear1340_miphy_priv *priv;
  207. struct phy_provider *phy_provider;
  208. priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL);
  209. if (!priv)
  210. return -ENOMEM;
  211. priv->misc =
  212. syscon_regmap_lookup_by_phandle(dev->of_node, "misc");
  213. if (IS_ERR(priv->misc)) {
  214. dev_err(dev, "failed to find misc regmap\n");
  215. return PTR_ERR(priv->misc);
  216. }
  217. priv->phy = devm_phy_create(dev, NULL, &spear1340_miphy_ops);
  218. if (IS_ERR(priv->phy)) {
  219. dev_err(dev, "failed to create SATA PCIe PHY\n");
  220. return PTR_ERR(priv->phy);
  221. }
  222. dev_set_drvdata(dev, priv);
  223. phy_set_drvdata(priv->phy, priv);
  224. phy_provider =
  225. devm_of_phy_provider_register(dev, spear1340_miphy_xlate);
  226. if (IS_ERR(phy_provider)) {
  227. dev_err(dev, "failed to register phy provider\n");
  228. return PTR_ERR(phy_provider);
  229. }
  230. return 0;
  231. }
  232. static struct platform_driver spear1340_miphy_driver = {
  233. .probe = spear1340_miphy_probe,
  234. .driver = {
  235. .name = "spear1340-miphy",
  236. .pm = &spear1340_miphy_pm_ops,
  237. .of_match_table = of_match_ptr(spear1340_miphy_of_match),
  238. },
  239. };
  240. module_platform_driver(spear1340_miphy_driver);
  241. MODULE_DESCRIPTION("ST SPEAR1340-MIPHY driver");
  242. MODULE_AUTHOR("Pratyush Anand <pratyush.anand@gmail.com>");
  243. MODULE_LICENSE("GPL v2");