phy-spear1310-miphy.c 7.4 KB

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  1. // SPDX-License-Identifier: GPL-2.0-only
  2. /*
  3. * ST SPEAr1310-miphy driver
  4. *
  5. * Copyright (C) 2014 ST Microelectronics
  6. * Pratyush Anand <pratyush.anand@gmail.com>
  7. * Mohit Kumar <mohit.kumar.dhaka@gmail.com>
  8. */
  9. #include <linux/bitops.h>
  10. #include <linux/delay.h>
  11. #include <linux/dma-mapping.h>
  12. #include <linux/kernel.h>
  13. #include <linux/mfd/syscon.h>
  14. #include <linux/module.h>
  15. #include <linux/of_device.h>
  16. #include <linux/phy/phy.h>
  17. #include <linux/regmap.h>
  18. /* SPEAr1310 Registers */
  19. #define SPEAR1310_PCIE_SATA_CFG 0x3A4
  20. #define SPEAR1310_PCIE_SATA2_SEL_PCIE (0 << 31)
  21. #define SPEAR1310_PCIE_SATA1_SEL_PCIE (0 << 30)
  22. #define SPEAR1310_PCIE_SATA0_SEL_PCIE (0 << 29)
  23. #define SPEAR1310_PCIE_SATA2_SEL_SATA BIT(31)
  24. #define SPEAR1310_PCIE_SATA1_SEL_SATA BIT(30)
  25. #define SPEAR1310_PCIE_SATA0_SEL_SATA BIT(29)
  26. #define SPEAR1310_SATA2_CFG_TX_CLK_EN BIT(27)
  27. #define SPEAR1310_SATA2_CFG_RX_CLK_EN BIT(26)
  28. #define SPEAR1310_SATA2_CFG_POWERUP_RESET BIT(25)
  29. #define SPEAR1310_SATA2_CFG_PM_CLK_EN BIT(24)
  30. #define SPEAR1310_SATA1_CFG_TX_CLK_EN BIT(23)
  31. #define SPEAR1310_SATA1_CFG_RX_CLK_EN BIT(22)
  32. #define SPEAR1310_SATA1_CFG_POWERUP_RESET BIT(21)
  33. #define SPEAR1310_SATA1_CFG_PM_CLK_EN BIT(20)
  34. #define SPEAR1310_SATA0_CFG_TX_CLK_EN BIT(19)
  35. #define SPEAR1310_SATA0_CFG_RX_CLK_EN BIT(18)
  36. #define SPEAR1310_SATA0_CFG_POWERUP_RESET BIT(17)
  37. #define SPEAR1310_SATA0_CFG_PM_CLK_EN BIT(16)
  38. #define SPEAR1310_PCIE2_CFG_DEVICE_PRESENT BIT(11)
  39. #define SPEAR1310_PCIE2_CFG_POWERUP_RESET BIT(10)
  40. #define SPEAR1310_PCIE2_CFG_CORE_CLK_EN BIT(9)
  41. #define SPEAR1310_PCIE2_CFG_AUX_CLK_EN BIT(8)
  42. #define SPEAR1310_PCIE1_CFG_DEVICE_PRESENT BIT(7)
  43. #define SPEAR1310_PCIE1_CFG_POWERUP_RESET BIT(6)
  44. #define SPEAR1310_PCIE1_CFG_CORE_CLK_EN BIT(5)
  45. #define SPEAR1310_PCIE1_CFG_AUX_CLK_EN BIT(4)
  46. #define SPEAR1310_PCIE0_CFG_DEVICE_PRESENT BIT(3)
  47. #define SPEAR1310_PCIE0_CFG_POWERUP_RESET BIT(2)
  48. #define SPEAR1310_PCIE0_CFG_CORE_CLK_EN BIT(1)
  49. #define SPEAR1310_PCIE0_CFG_AUX_CLK_EN BIT(0)
  50. #define SPEAR1310_PCIE_CFG_MASK(x) ((0xF << (x * 4)) | BIT((x + 29)))
  51. #define SPEAR1310_SATA_CFG_MASK(x) ((0xF << (x * 4 + 16)) | \
  52. BIT((x + 29)))
  53. #define SPEAR1310_PCIE_CFG_VAL(x) \
  54. (SPEAR1310_PCIE_SATA##x##_SEL_PCIE | \
  55. SPEAR1310_PCIE##x##_CFG_AUX_CLK_EN | \
  56. SPEAR1310_PCIE##x##_CFG_CORE_CLK_EN | \
  57. SPEAR1310_PCIE##x##_CFG_POWERUP_RESET | \
  58. SPEAR1310_PCIE##x##_CFG_DEVICE_PRESENT)
  59. #define SPEAR1310_SATA_CFG_VAL(x) \
  60. (SPEAR1310_PCIE_SATA##x##_SEL_SATA | \
  61. SPEAR1310_SATA##x##_CFG_PM_CLK_EN | \
  62. SPEAR1310_SATA##x##_CFG_POWERUP_RESET | \
  63. SPEAR1310_SATA##x##_CFG_RX_CLK_EN | \
  64. SPEAR1310_SATA##x##_CFG_TX_CLK_EN)
  65. #define SPEAR1310_PCIE_MIPHY_CFG_1 0x3A8
  66. #define SPEAR1310_MIPHY_DUAL_OSC_BYPASS_EXT BIT(31)
  67. #define SPEAR1310_MIPHY_DUAL_CLK_REF_DIV2 BIT(28)
  68. #define SPEAR1310_MIPHY_DUAL_PLL_RATIO_TOP(x) (x << 16)
  69. #define SPEAR1310_MIPHY_SINGLE_OSC_BYPASS_EXT BIT(15)
  70. #define SPEAR1310_MIPHY_SINGLE_CLK_REF_DIV2 BIT(12)
  71. #define SPEAR1310_MIPHY_SINGLE_PLL_RATIO_TOP(x) (x << 0)
  72. #define SPEAR1310_PCIE_SATA_MIPHY_CFG_SATA_MASK (0xFFFF)
  73. #define SPEAR1310_PCIE_SATA_MIPHY_CFG_PCIE_MASK (0xFFFF << 16)
  74. #define SPEAR1310_PCIE_SATA_MIPHY_CFG_SATA \
  75. (SPEAR1310_MIPHY_DUAL_OSC_BYPASS_EXT | \
  76. SPEAR1310_MIPHY_DUAL_CLK_REF_DIV2 | \
  77. SPEAR1310_MIPHY_DUAL_PLL_RATIO_TOP(60) | \
  78. SPEAR1310_MIPHY_SINGLE_OSC_BYPASS_EXT | \
  79. SPEAR1310_MIPHY_SINGLE_CLK_REF_DIV2 | \
  80. SPEAR1310_MIPHY_SINGLE_PLL_RATIO_TOP(60))
  81. #define SPEAR1310_PCIE_SATA_MIPHY_CFG_SATA_25M_CRYSTAL_CLK \
  82. (SPEAR1310_MIPHY_SINGLE_PLL_RATIO_TOP(120))
  83. #define SPEAR1310_PCIE_SATA_MIPHY_CFG_PCIE \
  84. (SPEAR1310_MIPHY_DUAL_OSC_BYPASS_EXT | \
  85. SPEAR1310_MIPHY_DUAL_PLL_RATIO_TOP(25) | \
  86. SPEAR1310_MIPHY_SINGLE_OSC_BYPASS_EXT | \
  87. SPEAR1310_MIPHY_SINGLE_PLL_RATIO_TOP(25))
  88. #define SPEAR1310_PCIE_MIPHY_CFG_2 0x3AC
  89. enum spear1310_miphy_mode {
  90. SATA,
  91. PCIE,
  92. };
  93. struct spear1310_miphy_priv {
  94. /* instance id of this phy */
  95. u32 id;
  96. /* phy mode: 0 for SATA 1 for PCIe */
  97. enum spear1310_miphy_mode mode;
  98. /* regmap for any soc specific misc registers */
  99. struct regmap *misc;
  100. /* phy struct pointer */
  101. struct phy *phy;
  102. };
  103. static int spear1310_miphy_pcie_init(struct spear1310_miphy_priv *priv)
  104. {
  105. u32 val;
  106. regmap_update_bits(priv->misc, SPEAR1310_PCIE_MIPHY_CFG_1,
  107. SPEAR1310_PCIE_SATA_MIPHY_CFG_PCIE_MASK,
  108. SPEAR1310_PCIE_SATA_MIPHY_CFG_PCIE);
  109. switch (priv->id) {
  110. case 0:
  111. val = SPEAR1310_PCIE_CFG_VAL(0);
  112. break;
  113. case 1:
  114. val = SPEAR1310_PCIE_CFG_VAL(1);
  115. break;
  116. case 2:
  117. val = SPEAR1310_PCIE_CFG_VAL(2);
  118. break;
  119. default:
  120. return -EINVAL;
  121. }
  122. regmap_update_bits(priv->misc, SPEAR1310_PCIE_SATA_CFG,
  123. SPEAR1310_PCIE_CFG_MASK(priv->id), val);
  124. return 0;
  125. }
  126. static int spear1310_miphy_pcie_exit(struct spear1310_miphy_priv *priv)
  127. {
  128. regmap_update_bits(priv->misc, SPEAR1310_PCIE_SATA_CFG,
  129. SPEAR1310_PCIE_CFG_MASK(priv->id), 0);
  130. regmap_update_bits(priv->misc, SPEAR1310_PCIE_MIPHY_CFG_1,
  131. SPEAR1310_PCIE_SATA_MIPHY_CFG_PCIE_MASK, 0);
  132. return 0;
  133. }
  134. static int spear1310_miphy_init(struct phy *phy)
  135. {
  136. struct spear1310_miphy_priv *priv = phy_get_drvdata(phy);
  137. int ret = 0;
  138. if (priv->mode == PCIE)
  139. ret = spear1310_miphy_pcie_init(priv);
  140. return ret;
  141. }
  142. static int spear1310_miphy_exit(struct phy *phy)
  143. {
  144. struct spear1310_miphy_priv *priv = phy_get_drvdata(phy);
  145. int ret = 0;
  146. if (priv->mode == PCIE)
  147. ret = spear1310_miphy_pcie_exit(priv);
  148. return ret;
  149. }
  150. static const struct of_device_id spear1310_miphy_of_match[] = {
  151. { .compatible = "st,spear1310-miphy" },
  152. { },
  153. };
  154. MODULE_DEVICE_TABLE(of, spear1310_miphy_of_match);
  155. static const struct phy_ops spear1310_miphy_ops = {
  156. .init = spear1310_miphy_init,
  157. .exit = spear1310_miphy_exit,
  158. .owner = THIS_MODULE,
  159. };
  160. static struct phy *spear1310_miphy_xlate(struct device *dev,
  161. struct of_phandle_args *args)
  162. {
  163. struct spear1310_miphy_priv *priv = dev_get_drvdata(dev);
  164. if (args->args_count < 1) {
  165. dev_err(dev, "DT did not pass correct no of args\n");
  166. return ERR_PTR(-ENODEV);
  167. }
  168. priv->mode = args->args[0];
  169. if (priv->mode != SATA && priv->mode != PCIE) {
  170. dev_err(dev, "DT did not pass correct phy mode\n");
  171. return ERR_PTR(-ENODEV);
  172. }
  173. return priv->phy;
  174. }
  175. static int spear1310_miphy_probe(struct platform_device *pdev)
  176. {
  177. struct device *dev = &pdev->dev;
  178. struct spear1310_miphy_priv *priv;
  179. struct phy_provider *phy_provider;
  180. priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL);
  181. if (!priv)
  182. return -ENOMEM;
  183. priv->misc =
  184. syscon_regmap_lookup_by_phandle(dev->of_node, "misc");
  185. if (IS_ERR(priv->misc)) {
  186. dev_err(dev, "failed to find misc regmap\n");
  187. return PTR_ERR(priv->misc);
  188. }
  189. if (of_property_read_u32(dev->of_node, "phy-id", &priv->id)) {
  190. dev_err(dev, "failed to find phy id\n");
  191. return -EINVAL;
  192. }
  193. priv->phy = devm_phy_create(dev, NULL, &spear1310_miphy_ops);
  194. if (IS_ERR(priv->phy)) {
  195. dev_err(dev, "failed to create SATA PCIe PHY\n");
  196. return PTR_ERR(priv->phy);
  197. }
  198. dev_set_drvdata(dev, priv);
  199. phy_set_drvdata(priv->phy, priv);
  200. phy_provider =
  201. devm_of_phy_provider_register(dev, spear1310_miphy_xlate);
  202. if (IS_ERR(phy_provider)) {
  203. dev_err(dev, "failed to register phy provider\n");
  204. return PTR_ERR(phy_provider);
  205. }
  206. return 0;
  207. }
  208. static struct platform_driver spear1310_miphy_driver = {
  209. .probe = spear1310_miphy_probe,
  210. .driver = {
  211. .name = "spear1310-miphy",
  212. .of_match_table = of_match_ptr(spear1310_miphy_of_match),
  213. },
  214. };
  215. module_platform_driver(spear1310_miphy_driver);
  216. MODULE_DESCRIPTION("ST SPEAR1310-MIPHY driver");
  217. MODULE_AUTHOR("Pratyush Anand <pratyush.anand@gmail.com>");
  218. MODULE_LICENSE("GPL v2");