phy-miphy28lp.c 33 KB

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  1. // SPDX-License-Identifier: GPL-2.0-only
  2. /*
  3. * Copyright (C) 2014 STMicroelectronics
  4. *
  5. * STMicroelectronics PHY driver MiPHY28lp (for SoC STiH407).
  6. *
  7. * Author: Alexandre Torgue <alexandre.torgue@st.com>
  8. */
  9. #include <linux/platform_device.h>
  10. #include <linux/io.h>
  11. #include <linux/kernel.h>
  12. #include <linux/module.h>
  13. #include <linux/of.h>
  14. #include <linux/of_platform.h>
  15. #include <linux/of_address.h>
  16. #include <linux/clk.h>
  17. #include <linux/phy/phy.h>
  18. #include <linux/delay.h>
  19. #include <linux/mfd/syscon.h>
  20. #include <linux/regmap.h>
  21. #include <linux/reset.h>
  22. #include <dt-bindings/phy/phy.h>
  23. /* MiPHY registers */
  24. #define MIPHY_CONF_RESET 0x00
  25. #define RST_APPLI_SW BIT(0)
  26. #define RST_CONF_SW BIT(1)
  27. #define RST_MACRO_SW BIT(2)
  28. #define MIPHY_RESET 0x01
  29. #define RST_PLL_SW BIT(0)
  30. #define RST_COMP_SW BIT(2)
  31. #define MIPHY_STATUS_1 0x02
  32. #define PHY_RDY BIT(0)
  33. #define HFC_RDY BIT(1)
  34. #define HFC_PLL BIT(2)
  35. #define MIPHY_CONTROL 0x04
  36. #define TERM_EN_SW BIT(2)
  37. #define DIS_LINK_RST BIT(3)
  38. #define AUTO_RST_RX BIT(4)
  39. #define PX_RX_POL BIT(5)
  40. #define MIPHY_BOUNDARY_SEL 0x0a
  41. #define TX_SEL BIT(6)
  42. #define SSC_SEL BIT(4)
  43. #define GENSEL_SEL BIT(0)
  44. #define MIPHY_BOUNDARY_1 0x0b
  45. #define MIPHY_BOUNDARY_2 0x0c
  46. #define SSC_EN_SW BIT(2)
  47. #define MIPHY_PLL_CLKREF_FREQ 0x0d
  48. #define MIPHY_SPEED 0x0e
  49. #define TX_SPDSEL_80DEC 0
  50. #define TX_SPDSEL_40DEC 1
  51. #define TX_SPDSEL_20DEC 2
  52. #define RX_SPDSEL_80DEC 0
  53. #define RX_SPDSEL_40DEC (1 << 2)
  54. #define RX_SPDSEL_20DEC (2 << 2)
  55. #define MIPHY_CONF 0x0f
  56. #define MIPHY_CTRL_TEST_SEL 0x20
  57. #define MIPHY_CTRL_TEST_1 0x21
  58. #define MIPHY_CTRL_TEST_2 0x22
  59. #define MIPHY_CTRL_TEST_3 0x23
  60. #define MIPHY_CTRL_TEST_4 0x24
  61. #define MIPHY_FEEDBACK_TEST 0x25
  62. #define MIPHY_DEBUG_BUS 0x26
  63. #define MIPHY_DEBUG_STATUS_MSB 0x27
  64. #define MIPHY_DEBUG_STATUS_LSB 0x28
  65. #define MIPHY_PWR_RAIL_1 0x29
  66. #define MIPHY_PWR_RAIL_2 0x2a
  67. #define MIPHY_SYNCHAR_CONTROL 0x30
  68. #define MIPHY_COMP_FSM_1 0x3a
  69. #define COMP_START BIT(6)
  70. #define MIPHY_COMP_FSM_6 0x3f
  71. #define COMP_DONE BIT(7)
  72. #define MIPHY_COMP_POSTP 0x42
  73. #define MIPHY_TX_CTRL_1 0x49
  74. #define TX_REG_STEP_0V 0
  75. #define TX_REG_STEP_P_25MV 1
  76. #define TX_REG_STEP_P_50MV 2
  77. #define TX_REG_STEP_N_25MV 7
  78. #define TX_REG_STEP_N_50MV 6
  79. #define TX_REG_STEP_N_75MV 5
  80. #define MIPHY_TX_CTRL_2 0x4a
  81. #define TX_SLEW_SW_40_PS 0
  82. #define TX_SLEW_SW_80_PS 1
  83. #define TX_SLEW_SW_120_PS 2
  84. #define MIPHY_TX_CTRL_3 0x4b
  85. #define MIPHY_TX_CAL_MAN 0x4e
  86. #define TX_SLEW_CAL_MAN_EN BIT(0)
  87. #define MIPHY_TST_BIAS_BOOST_2 0x62
  88. #define MIPHY_BIAS_BOOST_1 0x63
  89. #define MIPHY_BIAS_BOOST_2 0x64
  90. #define MIPHY_RX_DESBUFF_FDB_2 0x67
  91. #define MIPHY_RX_DESBUFF_FDB_3 0x68
  92. #define MIPHY_SIGDET_COMPENS1 0x69
  93. #define MIPHY_SIGDET_COMPENS2 0x6a
  94. #define MIPHY_JITTER_PERIOD 0x6b
  95. #define MIPHY_JITTER_AMPLITUDE_1 0x6c
  96. #define MIPHY_JITTER_AMPLITUDE_2 0x6d
  97. #define MIPHY_JITTER_AMPLITUDE_3 0x6e
  98. #define MIPHY_RX_K_GAIN 0x78
  99. #define MIPHY_RX_BUFFER_CTRL 0x7a
  100. #define VGA_GAIN BIT(0)
  101. #define EQ_DC_GAIN BIT(2)
  102. #define EQ_BOOST_GAIN BIT(3)
  103. #define MIPHY_RX_VGA_GAIN 0x7b
  104. #define MIPHY_RX_EQU_GAIN_1 0x7f
  105. #define MIPHY_RX_EQU_GAIN_2 0x80
  106. #define MIPHY_RX_EQU_GAIN_3 0x81
  107. #define MIPHY_RX_CAL_CTRL_1 0x97
  108. #define MIPHY_RX_CAL_CTRL_2 0x98
  109. #define MIPHY_RX_CAL_OFFSET_CTRL 0x99
  110. #define CAL_OFFSET_VGA_64 (0x03 << 0)
  111. #define CAL_OFFSET_THRESHOLD_64 (0x03 << 2)
  112. #define VGA_OFFSET_POLARITY BIT(4)
  113. #define OFFSET_COMPENSATION_EN BIT(6)
  114. #define MIPHY_RX_CAL_VGA_STEP 0x9a
  115. #define MIPHY_RX_CAL_EYE_MIN 0x9d
  116. #define MIPHY_RX_CAL_OPT_LENGTH 0x9f
  117. #define MIPHY_RX_LOCK_CTRL_1 0xc1
  118. #define MIPHY_RX_LOCK_SETTINGS_OPT 0xc2
  119. #define MIPHY_RX_LOCK_STEP 0xc4
  120. #define MIPHY_RX_SIGDET_SLEEP_OA 0xc9
  121. #define MIPHY_RX_SIGDET_SLEEP_SEL 0xca
  122. #define MIPHY_RX_SIGDET_WAIT_SEL 0xcb
  123. #define MIPHY_RX_SIGDET_DATA_SEL 0xcc
  124. #define EN_ULTRA_LOW_POWER BIT(0)
  125. #define EN_FIRST_HALF BIT(1)
  126. #define EN_SECOND_HALF BIT(2)
  127. #define EN_DIGIT_SIGNAL_CHECK BIT(3)
  128. #define MIPHY_RX_POWER_CTRL_1 0xcd
  129. #define MIPHY_RX_POWER_CTRL_2 0xce
  130. #define MIPHY_PLL_CALSET_CTRL 0xd3
  131. #define MIPHY_PLL_CALSET_1 0xd4
  132. #define MIPHY_PLL_CALSET_2 0xd5
  133. #define MIPHY_PLL_CALSET_3 0xd6
  134. #define MIPHY_PLL_CALSET_4 0xd7
  135. #define MIPHY_PLL_SBR_1 0xe3
  136. #define SET_NEW_CHANGE BIT(1)
  137. #define MIPHY_PLL_SBR_2 0xe4
  138. #define MIPHY_PLL_SBR_3 0xe5
  139. #define MIPHY_PLL_SBR_4 0xe6
  140. #define MIPHY_PLL_COMMON_MISC_2 0xe9
  141. #define START_ACT_FILT BIT(6)
  142. #define MIPHY_PLL_SPAREIN 0xeb
  143. /*
  144. * On STiH407 the glue logic can be different among MiPHY devices; for example:
  145. * MiPHY0: OSC_FORCE_EXT means:
  146. * 0: 30MHz crystal clk - 1: 100MHz ext clk routed through MiPHY1
  147. * MiPHY1: OSC_FORCE_EXT means:
  148. * 1: 30MHz crystal clk - 0: 100MHz ext clk routed through MiPHY1
  149. * Some devices have not the possibility to check if the osc is ready.
  150. */
  151. #define MIPHY_OSC_FORCE_EXT BIT(3)
  152. #define MIPHY_OSC_RDY BIT(5)
  153. #define MIPHY_CTRL_MASK 0x0f
  154. #define MIPHY_CTRL_DEFAULT 0
  155. #define MIPHY_CTRL_SYNC_D_EN BIT(2)
  156. /* SATA / PCIe defines */
  157. #define SATA_CTRL_MASK 0x07
  158. #define PCIE_CTRL_MASK 0xff
  159. #define SATA_CTRL_SELECT_SATA 1
  160. #define SATA_CTRL_SELECT_PCIE 0
  161. #define SYSCFG_PCIE_PCIE_VAL 0x80
  162. #define SATA_SPDMODE 1
  163. #define MIPHY_SATA_BANK_NB 3
  164. #define MIPHY_PCIE_BANK_NB 2
  165. enum {
  166. SYSCFG_CTRL,
  167. SYSCFG_STATUS,
  168. SYSCFG_PCI,
  169. SYSCFG_SATA,
  170. SYSCFG_REG_MAX,
  171. };
  172. struct miphy28lp_phy {
  173. struct phy *phy;
  174. struct miphy28lp_dev *phydev;
  175. void __iomem *base;
  176. void __iomem *pipebase;
  177. bool osc_force_ext;
  178. bool osc_rdy;
  179. bool px_rx_pol_inv;
  180. bool ssc;
  181. bool tx_impedance;
  182. struct reset_control *miphy_rst;
  183. u32 sata_gen;
  184. /* Sysconfig registers offsets needed to configure the device */
  185. u32 syscfg_reg[SYSCFG_REG_MAX];
  186. u8 type;
  187. };
  188. struct miphy28lp_dev {
  189. struct device *dev;
  190. struct regmap *regmap;
  191. struct mutex miphy_mutex;
  192. struct miphy28lp_phy **phys;
  193. int nphys;
  194. };
  195. struct miphy_initval {
  196. u16 reg;
  197. u16 val;
  198. };
  199. enum miphy_sata_gen { SATA_GEN1, SATA_GEN2, SATA_GEN3 };
  200. static char *PHY_TYPE_name[] = { "sata-up", "pcie-up", "", "usb3-up" };
  201. struct pll_ratio {
  202. int clk_ref;
  203. int calset_1;
  204. int calset_2;
  205. int calset_3;
  206. int calset_4;
  207. int cal_ctrl;
  208. };
  209. static struct pll_ratio sata_pll_ratio = {
  210. .clk_ref = 0x1e,
  211. .calset_1 = 0xc8,
  212. .calset_2 = 0x00,
  213. .calset_3 = 0x00,
  214. .calset_4 = 0x00,
  215. .cal_ctrl = 0x00,
  216. };
  217. static struct pll_ratio pcie_pll_ratio = {
  218. .clk_ref = 0x1e,
  219. .calset_1 = 0xa6,
  220. .calset_2 = 0xaa,
  221. .calset_3 = 0xaa,
  222. .calset_4 = 0x00,
  223. .cal_ctrl = 0x00,
  224. };
  225. static struct pll_ratio usb3_pll_ratio = {
  226. .clk_ref = 0x1e,
  227. .calset_1 = 0xa6,
  228. .calset_2 = 0xaa,
  229. .calset_3 = 0xaa,
  230. .calset_4 = 0x04,
  231. .cal_ctrl = 0x00,
  232. };
  233. struct miphy28lp_pll_gen {
  234. int bank;
  235. int speed;
  236. int bias_boost_1;
  237. int bias_boost_2;
  238. int tx_ctrl_1;
  239. int tx_ctrl_2;
  240. int tx_ctrl_3;
  241. int rx_k_gain;
  242. int rx_vga_gain;
  243. int rx_equ_gain_1;
  244. int rx_equ_gain_2;
  245. int rx_equ_gain_3;
  246. int rx_buff_ctrl;
  247. };
  248. static struct miphy28lp_pll_gen sata_pll_gen[] = {
  249. {
  250. .bank = 0x00,
  251. .speed = TX_SPDSEL_80DEC | RX_SPDSEL_80DEC,
  252. .bias_boost_1 = 0x00,
  253. .bias_boost_2 = 0xae,
  254. .tx_ctrl_2 = 0x53,
  255. .tx_ctrl_3 = 0x00,
  256. .rx_buff_ctrl = EQ_BOOST_GAIN | EQ_DC_GAIN | VGA_GAIN,
  257. .rx_vga_gain = 0x00,
  258. .rx_equ_gain_1 = 0x7d,
  259. .rx_equ_gain_2 = 0x56,
  260. .rx_equ_gain_3 = 0x00,
  261. },
  262. {
  263. .bank = 0x01,
  264. .speed = TX_SPDSEL_40DEC | RX_SPDSEL_40DEC,
  265. .bias_boost_1 = 0x00,
  266. .bias_boost_2 = 0xae,
  267. .tx_ctrl_2 = 0x72,
  268. .tx_ctrl_3 = 0x20,
  269. .rx_buff_ctrl = EQ_BOOST_GAIN | EQ_DC_GAIN | VGA_GAIN,
  270. .rx_vga_gain = 0x00,
  271. .rx_equ_gain_1 = 0x7d,
  272. .rx_equ_gain_2 = 0x56,
  273. .rx_equ_gain_3 = 0x00,
  274. },
  275. {
  276. .bank = 0x02,
  277. .speed = TX_SPDSEL_20DEC | RX_SPDSEL_20DEC,
  278. .bias_boost_1 = 0x00,
  279. .bias_boost_2 = 0xae,
  280. .tx_ctrl_2 = 0xc0,
  281. .tx_ctrl_3 = 0x20,
  282. .rx_buff_ctrl = EQ_BOOST_GAIN | EQ_DC_GAIN | VGA_GAIN,
  283. .rx_vga_gain = 0x00,
  284. .rx_equ_gain_1 = 0x7d,
  285. .rx_equ_gain_2 = 0x56,
  286. .rx_equ_gain_3 = 0x00,
  287. },
  288. };
  289. static struct miphy28lp_pll_gen pcie_pll_gen[] = {
  290. {
  291. .bank = 0x00,
  292. .speed = TX_SPDSEL_40DEC | RX_SPDSEL_40DEC,
  293. .bias_boost_1 = 0x00,
  294. .bias_boost_2 = 0xa5,
  295. .tx_ctrl_1 = TX_REG_STEP_N_25MV,
  296. .tx_ctrl_2 = 0x71,
  297. .tx_ctrl_3 = 0x60,
  298. .rx_k_gain = 0x98,
  299. .rx_buff_ctrl = EQ_BOOST_GAIN | EQ_DC_GAIN | VGA_GAIN,
  300. .rx_vga_gain = 0x00,
  301. .rx_equ_gain_1 = 0x79,
  302. .rx_equ_gain_2 = 0x56,
  303. },
  304. {
  305. .bank = 0x01,
  306. .speed = TX_SPDSEL_20DEC | RX_SPDSEL_20DEC,
  307. .bias_boost_1 = 0x00,
  308. .bias_boost_2 = 0xa5,
  309. .tx_ctrl_1 = TX_REG_STEP_N_25MV,
  310. .tx_ctrl_2 = 0x70,
  311. .tx_ctrl_3 = 0x60,
  312. .rx_k_gain = 0xcc,
  313. .rx_buff_ctrl = EQ_BOOST_GAIN | EQ_DC_GAIN | VGA_GAIN,
  314. .rx_vga_gain = 0x00,
  315. .rx_equ_gain_1 = 0x78,
  316. .rx_equ_gain_2 = 0x07,
  317. },
  318. };
  319. static inline void miphy28lp_set_reset(struct miphy28lp_phy *miphy_phy)
  320. {
  321. void __iomem *base = miphy_phy->base;
  322. u8 val;
  323. /* Putting Macro in reset */
  324. writeb_relaxed(RST_APPLI_SW, base + MIPHY_CONF_RESET);
  325. val = RST_APPLI_SW | RST_CONF_SW;
  326. writeb_relaxed(val, base + MIPHY_CONF_RESET);
  327. writeb_relaxed(RST_APPLI_SW, base + MIPHY_CONF_RESET);
  328. /* Bringing the MIPHY-CPU registers out of reset */
  329. if (miphy_phy->type == PHY_TYPE_PCIE) {
  330. val = AUTO_RST_RX | TERM_EN_SW;
  331. writeb_relaxed(val, base + MIPHY_CONTROL);
  332. } else {
  333. val = AUTO_RST_RX | TERM_EN_SW | DIS_LINK_RST;
  334. writeb_relaxed(val, base + MIPHY_CONTROL);
  335. }
  336. }
  337. static inline void miphy28lp_pll_calibration(struct miphy28lp_phy *miphy_phy,
  338. struct pll_ratio *pll_ratio)
  339. {
  340. void __iomem *base = miphy_phy->base;
  341. u8 val;
  342. /* Applying PLL Settings */
  343. writeb_relaxed(0x1d, base + MIPHY_PLL_SPAREIN);
  344. writeb_relaxed(pll_ratio->clk_ref, base + MIPHY_PLL_CLKREF_FREQ);
  345. /* PLL Ratio */
  346. writeb_relaxed(pll_ratio->calset_1, base + MIPHY_PLL_CALSET_1);
  347. writeb_relaxed(pll_ratio->calset_2, base + MIPHY_PLL_CALSET_2);
  348. writeb_relaxed(pll_ratio->calset_3, base + MIPHY_PLL_CALSET_3);
  349. writeb_relaxed(pll_ratio->calset_4, base + MIPHY_PLL_CALSET_4);
  350. writeb_relaxed(pll_ratio->cal_ctrl, base + MIPHY_PLL_CALSET_CTRL);
  351. writeb_relaxed(TX_SEL, base + MIPHY_BOUNDARY_SEL);
  352. val = (0x68 << 1) | TX_SLEW_CAL_MAN_EN;
  353. writeb_relaxed(val, base + MIPHY_TX_CAL_MAN);
  354. val = VGA_OFFSET_POLARITY | CAL_OFFSET_THRESHOLD_64 | CAL_OFFSET_VGA_64;
  355. if (miphy_phy->type != PHY_TYPE_SATA)
  356. val |= OFFSET_COMPENSATION_EN;
  357. writeb_relaxed(val, base + MIPHY_RX_CAL_OFFSET_CTRL);
  358. if (miphy_phy->type == PHY_TYPE_USB3) {
  359. writeb_relaxed(0x00, base + MIPHY_CONF);
  360. writeb_relaxed(0x70, base + MIPHY_RX_LOCK_STEP);
  361. writeb_relaxed(EN_FIRST_HALF, base + MIPHY_RX_SIGDET_SLEEP_OA);
  362. writeb_relaxed(EN_FIRST_HALF, base + MIPHY_RX_SIGDET_SLEEP_SEL);
  363. writeb_relaxed(EN_FIRST_HALF, base + MIPHY_RX_SIGDET_WAIT_SEL);
  364. val = EN_DIGIT_SIGNAL_CHECK | EN_FIRST_HALF;
  365. writeb_relaxed(val, base + MIPHY_RX_SIGDET_DATA_SEL);
  366. }
  367. }
  368. static inline void miphy28lp_sata_config_gen(struct miphy28lp_phy *miphy_phy)
  369. {
  370. void __iomem *base = miphy_phy->base;
  371. int i;
  372. for (i = 0; i < ARRAY_SIZE(sata_pll_gen); i++) {
  373. struct miphy28lp_pll_gen *gen = &sata_pll_gen[i];
  374. /* Banked settings */
  375. writeb_relaxed(gen->bank, base + MIPHY_CONF);
  376. writeb_relaxed(gen->speed, base + MIPHY_SPEED);
  377. writeb_relaxed(gen->bias_boost_1, base + MIPHY_BIAS_BOOST_1);
  378. writeb_relaxed(gen->bias_boost_2, base + MIPHY_BIAS_BOOST_2);
  379. /* TX buffer Settings */
  380. writeb_relaxed(gen->tx_ctrl_2, base + MIPHY_TX_CTRL_2);
  381. writeb_relaxed(gen->tx_ctrl_3, base + MIPHY_TX_CTRL_3);
  382. /* RX Buffer Settings */
  383. writeb_relaxed(gen->rx_buff_ctrl, base + MIPHY_RX_BUFFER_CTRL);
  384. writeb_relaxed(gen->rx_vga_gain, base + MIPHY_RX_VGA_GAIN);
  385. writeb_relaxed(gen->rx_equ_gain_1, base + MIPHY_RX_EQU_GAIN_1);
  386. writeb_relaxed(gen->rx_equ_gain_2, base + MIPHY_RX_EQU_GAIN_2);
  387. writeb_relaxed(gen->rx_equ_gain_3, base + MIPHY_RX_EQU_GAIN_3);
  388. }
  389. }
  390. static inline void miphy28lp_pcie_config_gen(struct miphy28lp_phy *miphy_phy)
  391. {
  392. void __iomem *base = miphy_phy->base;
  393. int i;
  394. for (i = 0; i < ARRAY_SIZE(pcie_pll_gen); i++) {
  395. struct miphy28lp_pll_gen *gen = &pcie_pll_gen[i];
  396. /* Banked settings */
  397. writeb_relaxed(gen->bank, base + MIPHY_CONF);
  398. writeb_relaxed(gen->speed, base + MIPHY_SPEED);
  399. writeb_relaxed(gen->bias_boost_1, base + MIPHY_BIAS_BOOST_1);
  400. writeb_relaxed(gen->bias_boost_2, base + MIPHY_BIAS_BOOST_2);
  401. /* TX buffer Settings */
  402. writeb_relaxed(gen->tx_ctrl_1, base + MIPHY_TX_CTRL_1);
  403. writeb_relaxed(gen->tx_ctrl_2, base + MIPHY_TX_CTRL_2);
  404. writeb_relaxed(gen->tx_ctrl_3, base + MIPHY_TX_CTRL_3);
  405. writeb_relaxed(gen->rx_k_gain, base + MIPHY_RX_K_GAIN);
  406. /* RX Buffer Settings */
  407. writeb_relaxed(gen->rx_buff_ctrl, base + MIPHY_RX_BUFFER_CTRL);
  408. writeb_relaxed(gen->rx_vga_gain, base + MIPHY_RX_VGA_GAIN);
  409. writeb_relaxed(gen->rx_equ_gain_1, base + MIPHY_RX_EQU_GAIN_1);
  410. writeb_relaxed(gen->rx_equ_gain_2, base + MIPHY_RX_EQU_GAIN_2);
  411. }
  412. }
  413. static inline int miphy28lp_wait_compensation(struct miphy28lp_phy *miphy_phy)
  414. {
  415. unsigned long finish = jiffies + 5 * HZ;
  416. u8 val;
  417. /* Waiting for Compensation to complete */
  418. do {
  419. val = readb_relaxed(miphy_phy->base + MIPHY_COMP_FSM_6);
  420. if (time_after_eq(jiffies, finish))
  421. return -EBUSY;
  422. cpu_relax();
  423. } while (!(val & COMP_DONE));
  424. return 0;
  425. }
  426. static inline int miphy28lp_compensation(struct miphy28lp_phy *miphy_phy,
  427. struct pll_ratio *pll_ratio)
  428. {
  429. void __iomem *base = miphy_phy->base;
  430. /* Poll for HFC ready after reset release */
  431. /* Compensation measurement */
  432. writeb_relaxed(RST_PLL_SW | RST_COMP_SW, base + MIPHY_RESET);
  433. writeb_relaxed(0x00, base + MIPHY_PLL_COMMON_MISC_2);
  434. writeb_relaxed(pll_ratio->clk_ref, base + MIPHY_PLL_CLKREF_FREQ);
  435. writeb_relaxed(COMP_START, base + MIPHY_COMP_FSM_1);
  436. if (miphy_phy->type == PHY_TYPE_PCIE)
  437. writeb_relaxed(RST_PLL_SW, base + MIPHY_RESET);
  438. writeb_relaxed(0x00, base + MIPHY_RESET);
  439. writeb_relaxed(START_ACT_FILT, base + MIPHY_PLL_COMMON_MISC_2);
  440. writeb_relaxed(SET_NEW_CHANGE, base + MIPHY_PLL_SBR_1);
  441. /* TX compensation offset to re-center TX impedance */
  442. writeb_relaxed(0x00, base + MIPHY_COMP_POSTP);
  443. if (miphy_phy->type == PHY_TYPE_PCIE)
  444. return miphy28lp_wait_compensation(miphy_phy);
  445. return 0;
  446. }
  447. static inline void miphy28_usb3_miphy_reset(struct miphy28lp_phy *miphy_phy)
  448. {
  449. void __iomem *base = miphy_phy->base;
  450. u8 val;
  451. /* MIPHY Reset */
  452. writeb_relaxed(RST_APPLI_SW, base + MIPHY_CONF_RESET);
  453. writeb_relaxed(0x00, base + MIPHY_CONF_RESET);
  454. writeb_relaxed(RST_COMP_SW, base + MIPHY_RESET);
  455. val = RST_COMP_SW | RST_PLL_SW;
  456. writeb_relaxed(val, base + MIPHY_RESET);
  457. writeb_relaxed(0x00, base + MIPHY_PLL_COMMON_MISC_2);
  458. writeb_relaxed(0x1e, base + MIPHY_PLL_CLKREF_FREQ);
  459. writeb_relaxed(COMP_START, base + MIPHY_COMP_FSM_1);
  460. writeb_relaxed(RST_PLL_SW, base + MIPHY_RESET);
  461. writeb_relaxed(0x00, base + MIPHY_RESET);
  462. writeb_relaxed(START_ACT_FILT, base + MIPHY_PLL_COMMON_MISC_2);
  463. writeb_relaxed(0x00, base + MIPHY_CONF);
  464. writeb_relaxed(0x00, base + MIPHY_BOUNDARY_1);
  465. writeb_relaxed(0x00, base + MIPHY_TST_BIAS_BOOST_2);
  466. writeb_relaxed(0x00, base + MIPHY_CONF);
  467. writeb_relaxed(SET_NEW_CHANGE, base + MIPHY_PLL_SBR_1);
  468. writeb_relaxed(0xa5, base + MIPHY_DEBUG_BUS);
  469. writeb_relaxed(0x00, base + MIPHY_CONF);
  470. }
  471. static void miphy_sata_tune_ssc(struct miphy28lp_phy *miphy_phy)
  472. {
  473. void __iomem *base = miphy_phy->base;
  474. u8 val;
  475. /* Compensate Tx impedance to avoid out of range values */
  476. /*
  477. * Enable the SSC on PLL for all banks
  478. * SSC Modulation @ 31 KHz and 4000 ppm modulation amp
  479. */
  480. val = readb_relaxed(base + MIPHY_BOUNDARY_2);
  481. val |= SSC_EN_SW;
  482. writeb_relaxed(val, base + MIPHY_BOUNDARY_2);
  483. val = readb_relaxed(base + MIPHY_BOUNDARY_SEL);
  484. val |= SSC_SEL;
  485. writeb_relaxed(val, base + MIPHY_BOUNDARY_SEL);
  486. for (val = 0; val < MIPHY_SATA_BANK_NB; val++) {
  487. writeb_relaxed(val, base + MIPHY_CONF);
  488. /* Add value to each reference clock cycle */
  489. /* and define the period length of the SSC */
  490. writeb_relaxed(0x3c, base + MIPHY_PLL_SBR_2);
  491. writeb_relaxed(0x6c, base + MIPHY_PLL_SBR_3);
  492. writeb_relaxed(0x81, base + MIPHY_PLL_SBR_4);
  493. /* Clear any previous request */
  494. writeb_relaxed(0x00, base + MIPHY_PLL_SBR_1);
  495. /* requests the PLL to take in account new parameters */
  496. writeb_relaxed(SET_NEW_CHANGE, base + MIPHY_PLL_SBR_1);
  497. /* To be sure there is no other pending requests */
  498. writeb_relaxed(0x00, base + MIPHY_PLL_SBR_1);
  499. }
  500. }
  501. static void miphy_pcie_tune_ssc(struct miphy28lp_phy *miphy_phy)
  502. {
  503. void __iomem *base = miphy_phy->base;
  504. u8 val;
  505. /* Compensate Tx impedance to avoid out of range values */
  506. /*
  507. * Enable the SSC on PLL for all banks
  508. * SSC Modulation @ 31 KHz and 4000 ppm modulation amp
  509. */
  510. val = readb_relaxed(base + MIPHY_BOUNDARY_2);
  511. val |= SSC_EN_SW;
  512. writeb_relaxed(val, base + MIPHY_BOUNDARY_2);
  513. val = readb_relaxed(base + MIPHY_BOUNDARY_SEL);
  514. val |= SSC_SEL;
  515. writeb_relaxed(val, base + MIPHY_BOUNDARY_SEL);
  516. for (val = 0; val < MIPHY_PCIE_BANK_NB; val++) {
  517. writeb_relaxed(val, base + MIPHY_CONF);
  518. /* Validate Step component */
  519. writeb_relaxed(0x69, base + MIPHY_PLL_SBR_3);
  520. writeb_relaxed(0x21, base + MIPHY_PLL_SBR_4);
  521. /* Validate Period component */
  522. writeb_relaxed(0x3c, base + MIPHY_PLL_SBR_2);
  523. writeb_relaxed(0x21, base + MIPHY_PLL_SBR_4);
  524. /* Clear any previous request */
  525. writeb_relaxed(0x00, base + MIPHY_PLL_SBR_1);
  526. /* requests the PLL to take in account new parameters */
  527. writeb_relaxed(SET_NEW_CHANGE, base + MIPHY_PLL_SBR_1);
  528. /* To be sure there is no other pending requests */
  529. writeb_relaxed(0x00, base + MIPHY_PLL_SBR_1);
  530. }
  531. }
  532. static inline void miphy_tune_tx_impedance(struct miphy28lp_phy *miphy_phy)
  533. {
  534. /* Compensate Tx impedance to avoid out of range values */
  535. writeb_relaxed(0x02, miphy_phy->base + MIPHY_COMP_POSTP);
  536. }
  537. static inline int miphy28lp_configure_sata(struct miphy28lp_phy *miphy_phy)
  538. {
  539. void __iomem *base = miphy_phy->base;
  540. int err;
  541. u8 val;
  542. /* Putting Macro in reset */
  543. miphy28lp_set_reset(miphy_phy);
  544. /* PLL calibration */
  545. miphy28lp_pll_calibration(miphy_phy, &sata_pll_ratio);
  546. /* Banked settings Gen1/Gen2/Gen3 */
  547. miphy28lp_sata_config_gen(miphy_phy);
  548. /* Power control */
  549. /* Input bridge enable, manual input bridge control */
  550. writeb_relaxed(0x21, base + MIPHY_RX_POWER_CTRL_1);
  551. /* Macro out of reset */
  552. writeb_relaxed(0x00, base + MIPHY_CONF_RESET);
  553. /* Poll for HFC ready after reset release */
  554. /* Compensation measurement */
  555. err = miphy28lp_compensation(miphy_phy, &sata_pll_ratio);
  556. if (err)
  557. return err;
  558. if (miphy_phy->px_rx_pol_inv) {
  559. /* Invert Rx polarity */
  560. val = readb_relaxed(miphy_phy->base + MIPHY_CONTROL);
  561. val |= PX_RX_POL;
  562. writeb_relaxed(val, miphy_phy->base + MIPHY_CONTROL);
  563. }
  564. if (miphy_phy->ssc)
  565. miphy_sata_tune_ssc(miphy_phy);
  566. if (miphy_phy->tx_impedance)
  567. miphy_tune_tx_impedance(miphy_phy);
  568. return 0;
  569. }
  570. static inline int miphy28lp_configure_pcie(struct miphy28lp_phy *miphy_phy)
  571. {
  572. void __iomem *base = miphy_phy->base;
  573. int err;
  574. /* Putting Macro in reset */
  575. miphy28lp_set_reset(miphy_phy);
  576. /* PLL calibration */
  577. miphy28lp_pll_calibration(miphy_phy, &pcie_pll_ratio);
  578. /* Banked settings Gen1/Gen2 */
  579. miphy28lp_pcie_config_gen(miphy_phy);
  580. /* Power control */
  581. /* Input bridge enable, manual input bridge control */
  582. writeb_relaxed(0x21, base + MIPHY_RX_POWER_CTRL_1);
  583. /* Macro out of reset */
  584. writeb_relaxed(0x00, base + MIPHY_CONF_RESET);
  585. /* Poll for HFC ready after reset release */
  586. /* Compensation measurement */
  587. err = miphy28lp_compensation(miphy_phy, &pcie_pll_ratio);
  588. if (err)
  589. return err;
  590. if (miphy_phy->ssc)
  591. miphy_pcie_tune_ssc(miphy_phy);
  592. if (miphy_phy->tx_impedance)
  593. miphy_tune_tx_impedance(miphy_phy);
  594. return 0;
  595. }
  596. static inline void miphy28lp_configure_usb3(struct miphy28lp_phy *miphy_phy)
  597. {
  598. void __iomem *base = miphy_phy->base;
  599. u8 val;
  600. /* Putting Macro in reset */
  601. miphy28lp_set_reset(miphy_phy);
  602. /* PLL calibration */
  603. miphy28lp_pll_calibration(miphy_phy, &usb3_pll_ratio);
  604. /* Writing The Speed Rate */
  605. writeb_relaxed(0x00, base + MIPHY_CONF);
  606. val = RX_SPDSEL_20DEC | TX_SPDSEL_20DEC;
  607. writeb_relaxed(val, base + MIPHY_SPEED);
  608. /* RX Channel compensation and calibration */
  609. writeb_relaxed(0x1c, base + MIPHY_RX_LOCK_SETTINGS_OPT);
  610. writeb_relaxed(0x51, base + MIPHY_RX_CAL_CTRL_1);
  611. writeb_relaxed(0x70, base + MIPHY_RX_CAL_CTRL_2);
  612. val = OFFSET_COMPENSATION_EN | VGA_OFFSET_POLARITY |
  613. CAL_OFFSET_THRESHOLD_64 | CAL_OFFSET_VGA_64;
  614. writeb_relaxed(val, base + MIPHY_RX_CAL_OFFSET_CTRL);
  615. writeb_relaxed(0x22, base + MIPHY_RX_CAL_VGA_STEP);
  616. writeb_relaxed(0x0e, base + MIPHY_RX_CAL_OPT_LENGTH);
  617. val = EQ_DC_GAIN | VGA_GAIN;
  618. writeb_relaxed(val, base + MIPHY_RX_BUFFER_CTRL);
  619. writeb_relaxed(0x78, base + MIPHY_RX_EQU_GAIN_1);
  620. writeb_relaxed(0x1b, base + MIPHY_SYNCHAR_CONTROL);
  621. /* TX compensation offset to re-center TX impedance */
  622. writeb_relaxed(0x02, base + MIPHY_COMP_POSTP);
  623. /* Enable GENSEL_SEL and SSC */
  624. /* TX_SEL=0 swing preemp forced by pipe registres */
  625. val = SSC_SEL | GENSEL_SEL;
  626. writeb_relaxed(val, base + MIPHY_BOUNDARY_SEL);
  627. /* MIPHY Bias boost */
  628. writeb_relaxed(0x00, base + MIPHY_BIAS_BOOST_1);
  629. writeb_relaxed(0xa7, base + MIPHY_BIAS_BOOST_2);
  630. /* SSC modulation */
  631. writeb_relaxed(SSC_EN_SW, base + MIPHY_BOUNDARY_2);
  632. /* MIPHY TX control */
  633. writeb_relaxed(0x00, base + MIPHY_CONF);
  634. /* Validate Step component */
  635. writeb_relaxed(0x5a, base + MIPHY_PLL_SBR_3);
  636. writeb_relaxed(0xa0, base + MIPHY_PLL_SBR_4);
  637. /* Validate Period component */
  638. writeb_relaxed(0x3c, base + MIPHY_PLL_SBR_2);
  639. writeb_relaxed(0xa1, base + MIPHY_PLL_SBR_4);
  640. /* Clear any previous request */
  641. writeb_relaxed(0x00, base + MIPHY_PLL_SBR_1);
  642. /* requests the PLL to take in account new parameters */
  643. writeb_relaxed(0x02, base + MIPHY_PLL_SBR_1);
  644. /* To be sure there is no other pending requests */
  645. writeb_relaxed(0x00, base + MIPHY_PLL_SBR_1);
  646. /* Rx PI controller settings */
  647. writeb_relaxed(0xca, base + MIPHY_RX_K_GAIN);
  648. /* MIPHY RX input bridge control */
  649. /* INPUT_BRIDGE_EN_SW=1, manual input bridge control[0]=1 */
  650. writeb_relaxed(0x21, base + MIPHY_RX_POWER_CTRL_1);
  651. writeb_relaxed(0x29, base + MIPHY_RX_POWER_CTRL_1);
  652. writeb_relaxed(0x1a, base + MIPHY_RX_POWER_CTRL_2);
  653. /* MIPHY Reset for usb3 */
  654. miphy28_usb3_miphy_reset(miphy_phy);
  655. }
  656. static inline int miphy_is_ready(struct miphy28lp_phy *miphy_phy)
  657. {
  658. unsigned long finish = jiffies + 5 * HZ;
  659. u8 mask = HFC_PLL | HFC_RDY;
  660. u8 val;
  661. /*
  662. * For PCIe and USB3 check only that PLL and HFC are ready
  663. * For SATA check also that phy is ready!
  664. */
  665. if (miphy_phy->type == PHY_TYPE_SATA)
  666. mask |= PHY_RDY;
  667. do {
  668. val = readb_relaxed(miphy_phy->base + MIPHY_STATUS_1);
  669. if ((val & mask) != mask)
  670. cpu_relax();
  671. else
  672. return 0;
  673. } while (!time_after_eq(jiffies, finish));
  674. return -EBUSY;
  675. }
  676. static int miphy_osc_is_ready(struct miphy28lp_phy *miphy_phy)
  677. {
  678. struct miphy28lp_dev *miphy_dev = miphy_phy->phydev;
  679. unsigned long finish = jiffies + 5 * HZ;
  680. u32 val;
  681. if (!miphy_phy->osc_rdy)
  682. return 0;
  683. if (!miphy_phy->syscfg_reg[SYSCFG_STATUS])
  684. return -EINVAL;
  685. do {
  686. regmap_read(miphy_dev->regmap,
  687. miphy_phy->syscfg_reg[SYSCFG_STATUS], &val);
  688. if ((val & MIPHY_OSC_RDY) != MIPHY_OSC_RDY)
  689. cpu_relax();
  690. else
  691. return 0;
  692. } while (!time_after_eq(jiffies, finish));
  693. return -EBUSY;
  694. }
  695. static int miphy28lp_get_resource_byname(struct device_node *child,
  696. char *rname, struct resource *res)
  697. {
  698. int index;
  699. index = of_property_match_string(child, "reg-names", rname);
  700. if (index < 0)
  701. return -ENODEV;
  702. return of_address_to_resource(child, index, res);
  703. }
  704. static int miphy28lp_get_one_addr(struct device *dev,
  705. struct device_node *child, char *rname,
  706. void __iomem **base)
  707. {
  708. struct resource res;
  709. int ret;
  710. ret = miphy28lp_get_resource_byname(child, rname, &res);
  711. if (!ret) {
  712. *base = devm_ioremap(dev, res.start, resource_size(&res));
  713. if (!*base) {
  714. dev_err(dev, "failed to ioremap %s address region\n"
  715. , rname);
  716. return -ENOENT;
  717. }
  718. }
  719. return 0;
  720. }
  721. /* MiPHY reset and sysconf setup */
  722. static int miphy28lp_setup(struct miphy28lp_phy *miphy_phy, u32 miphy_val)
  723. {
  724. int err;
  725. struct miphy28lp_dev *miphy_dev = miphy_phy->phydev;
  726. if (!miphy_phy->syscfg_reg[SYSCFG_CTRL])
  727. return -EINVAL;
  728. err = reset_control_assert(miphy_phy->miphy_rst);
  729. if (err) {
  730. dev_err(miphy_dev->dev, "unable to bring out of miphy reset\n");
  731. return err;
  732. }
  733. if (miphy_phy->osc_force_ext)
  734. miphy_val |= MIPHY_OSC_FORCE_EXT;
  735. regmap_update_bits(miphy_dev->regmap,
  736. miphy_phy->syscfg_reg[SYSCFG_CTRL],
  737. MIPHY_CTRL_MASK, miphy_val);
  738. err = reset_control_deassert(miphy_phy->miphy_rst);
  739. if (err) {
  740. dev_err(miphy_dev->dev, "unable to bring out of miphy reset\n");
  741. return err;
  742. }
  743. return miphy_osc_is_ready(miphy_phy);
  744. }
  745. static int miphy28lp_init_sata(struct miphy28lp_phy *miphy_phy)
  746. {
  747. struct miphy28lp_dev *miphy_dev = miphy_phy->phydev;
  748. int err, sata_conf = SATA_CTRL_SELECT_SATA;
  749. if ((!miphy_phy->syscfg_reg[SYSCFG_SATA]) ||
  750. (!miphy_phy->syscfg_reg[SYSCFG_PCI]) ||
  751. (!miphy_phy->base))
  752. return -EINVAL;
  753. dev_info(miphy_dev->dev, "sata-up mode, addr 0x%p\n", miphy_phy->base);
  754. /* Configure the glue-logic */
  755. sata_conf |= ((miphy_phy->sata_gen - SATA_GEN1) << SATA_SPDMODE);
  756. regmap_update_bits(miphy_dev->regmap,
  757. miphy_phy->syscfg_reg[SYSCFG_SATA],
  758. SATA_CTRL_MASK, sata_conf);
  759. regmap_update_bits(miphy_dev->regmap, miphy_phy->syscfg_reg[SYSCFG_PCI],
  760. PCIE_CTRL_MASK, SATA_CTRL_SELECT_PCIE);
  761. /* MiPHY path and clocking init */
  762. err = miphy28lp_setup(miphy_phy, MIPHY_CTRL_DEFAULT);
  763. if (err) {
  764. dev_err(miphy_dev->dev, "SATA phy setup failed\n");
  765. return err;
  766. }
  767. /* initialize miphy */
  768. miphy28lp_configure_sata(miphy_phy);
  769. return miphy_is_ready(miphy_phy);
  770. }
  771. static int miphy28lp_init_pcie(struct miphy28lp_phy *miphy_phy)
  772. {
  773. struct miphy28lp_dev *miphy_dev = miphy_phy->phydev;
  774. int err;
  775. if ((!miphy_phy->syscfg_reg[SYSCFG_SATA]) ||
  776. (!miphy_phy->syscfg_reg[SYSCFG_PCI])
  777. || (!miphy_phy->base) || (!miphy_phy->pipebase))
  778. return -EINVAL;
  779. dev_info(miphy_dev->dev, "pcie-up mode, addr 0x%p\n", miphy_phy->base);
  780. /* Configure the glue-logic */
  781. regmap_update_bits(miphy_dev->regmap,
  782. miphy_phy->syscfg_reg[SYSCFG_SATA],
  783. SATA_CTRL_MASK, SATA_CTRL_SELECT_PCIE);
  784. regmap_update_bits(miphy_dev->regmap, miphy_phy->syscfg_reg[SYSCFG_PCI],
  785. PCIE_CTRL_MASK, SYSCFG_PCIE_PCIE_VAL);
  786. /* MiPHY path and clocking init */
  787. err = miphy28lp_setup(miphy_phy, MIPHY_CTRL_DEFAULT);
  788. if (err) {
  789. dev_err(miphy_dev->dev, "PCIe phy setup failed\n");
  790. return err;
  791. }
  792. /* initialize miphy */
  793. err = miphy28lp_configure_pcie(miphy_phy);
  794. if (err)
  795. return err;
  796. /* PIPE Wrapper Configuration */
  797. writeb_relaxed(0x68, miphy_phy->pipebase + 0x104); /* Rise_0 */
  798. writeb_relaxed(0x61, miphy_phy->pipebase + 0x105); /* Rise_1 */
  799. writeb_relaxed(0x68, miphy_phy->pipebase + 0x108); /* Fall_0 */
  800. writeb_relaxed(0x61, miphy_phy->pipebase + 0x109); /* Fall-1 */
  801. writeb_relaxed(0x68, miphy_phy->pipebase + 0x10c); /* Threshold_0 */
  802. writeb_relaxed(0x60, miphy_phy->pipebase + 0x10d); /* Threshold_1 */
  803. /* Wait for phy_ready */
  804. return miphy_is_ready(miphy_phy);
  805. }
  806. static int miphy28lp_init_usb3(struct miphy28lp_phy *miphy_phy)
  807. {
  808. struct miphy28lp_dev *miphy_dev = miphy_phy->phydev;
  809. int err;
  810. if ((!miphy_phy->base) || (!miphy_phy->pipebase))
  811. return -EINVAL;
  812. dev_info(miphy_dev->dev, "usb3-up mode, addr 0x%p\n", miphy_phy->base);
  813. /* MiPHY path and clocking init */
  814. err = miphy28lp_setup(miphy_phy, MIPHY_CTRL_SYNC_D_EN);
  815. if (err) {
  816. dev_err(miphy_dev->dev, "USB3 phy setup failed\n");
  817. return err;
  818. }
  819. /* initialize miphy */
  820. miphy28lp_configure_usb3(miphy_phy);
  821. /* PIPE Wrapper Configuration */
  822. writeb_relaxed(0x68, miphy_phy->pipebase + 0x23);
  823. writeb_relaxed(0x61, miphy_phy->pipebase + 0x24);
  824. writeb_relaxed(0x68, miphy_phy->pipebase + 0x26);
  825. writeb_relaxed(0x61, miphy_phy->pipebase + 0x27);
  826. writeb_relaxed(0x18, miphy_phy->pipebase + 0x29);
  827. writeb_relaxed(0x61, miphy_phy->pipebase + 0x2a);
  828. /* pipe Wrapper usb3 TX swing de-emph margin PREEMPH[7:4], SWING[3:0] */
  829. writeb_relaxed(0X67, miphy_phy->pipebase + 0x68);
  830. writeb_relaxed(0x0d, miphy_phy->pipebase + 0x69);
  831. writeb_relaxed(0X67, miphy_phy->pipebase + 0x6a);
  832. writeb_relaxed(0X0d, miphy_phy->pipebase + 0x6b);
  833. writeb_relaxed(0X67, miphy_phy->pipebase + 0x6c);
  834. writeb_relaxed(0X0d, miphy_phy->pipebase + 0x6d);
  835. writeb_relaxed(0X67, miphy_phy->pipebase + 0x6e);
  836. writeb_relaxed(0X0d, miphy_phy->pipebase + 0x6f);
  837. return miphy_is_ready(miphy_phy);
  838. }
  839. static int miphy28lp_init(struct phy *phy)
  840. {
  841. struct miphy28lp_phy *miphy_phy = phy_get_drvdata(phy);
  842. struct miphy28lp_dev *miphy_dev = miphy_phy->phydev;
  843. int ret;
  844. mutex_lock(&miphy_dev->miphy_mutex);
  845. switch (miphy_phy->type) {
  846. case PHY_TYPE_SATA:
  847. ret = miphy28lp_init_sata(miphy_phy);
  848. break;
  849. case PHY_TYPE_PCIE:
  850. ret = miphy28lp_init_pcie(miphy_phy);
  851. break;
  852. case PHY_TYPE_USB3:
  853. ret = miphy28lp_init_usb3(miphy_phy);
  854. break;
  855. default:
  856. ret = -EINVAL;
  857. break;
  858. }
  859. mutex_unlock(&miphy_dev->miphy_mutex);
  860. return ret;
  861. }
  862. static int miphy28lp_get_addr(struct miphy28lp_phy *miphy_phy)
  863. {
  864. struct miphy28lp_dev *miphy_dev = miphy_phy->phydev;
  865. struct device_node *phynode = miphy_phy->phy->dev.of_node;
  866. int err;
  867. if ((miphy_phy->type != PHY_TYPE_SATA) &&
  868. (miphy_phy->type != PHY_TYPE_PCIE) &&
  869. (miphy_phy->type != PHY_TYPE_USB3)) {
  870. return -EINVAL;
  871. }
  872. err = miphy28lp_get_one_addr(miphy_dev->dev, phynode,
  873. PHY_TYPE_name[miphy_phy->type - PHY_TYPE_SATA],
  874. &miphy_phy->base);
  875. if (err)
  876. return err;
  877. if ((miphy_phy->type == PHY_TYPE_PCIE) ||
  878. (miphy_phy->type == PHY_TYPE_USB3)) {
  879. err = miphy28lp_get_one_addr(miphy_dev->dev, phynode, "pipew",
  880. &miphy_phy->pipebase);
  881. if (err)
  882. return err;
  883. }
  884. return 0;
  885. }
  886. static struct phy *miphy28lp_xlate(struct device *dev,
  887. struct of_phandle_args *args)
  888. {
  889. struct miphy28lp_dev *miphy_dev = dev_get_drvdata(dev);
  890. struct miphy28lp_phy *miphy_phy = NULL;
  891. struct device_node *phynode = args->np;
  892. int ret, index = 0;
  893. if (args->args_count != 1) {
  894. dev_err(dev, "Invalid number of cells in 'phy' property\n");
  895. return ERR_PTR(-EINVAL);
  896. }
  897. for (index = 0; index < miphy_dev->nphys; index++)
  898. if (phynode == miphy_dev->phys[index]->phy->dev.of_node) {
  899. miphy_phy = miphy_dev->phys[index];
  900. break;
  901. }
  902. if (!miphy_phy) {
  903. dev_err(dev, "Failed to find appropriate phy\n");
  904. return ERR_PTR(-EINVAL);
  905. }
  906. miphy_phy->type = args->args[0];
  907. ret = miphy28lp_get_addr(miphy_phy);
  908. if (ret < 0)
  909. return ERR_PTR(ret);
  910. return miphy_phy->phy;
  911. }
  912. static const struct phy_ops miphy28lp_ops = {
  913. .init = miphy28lp_init,
  914. .owner = THIS_MODULE,
  915. };
  916. static int miphy28lp_probe_resets(struct device_node *node,
  917. struct miphy28lp_phy *miphy_phy)
  918. {
  919. struct miphy28lp_dev *miphy_dev = miphy_phy->phydev;
  920. int err;
  921. miphy_phy->miphy_rst =
  922. of_reset_control_get_shared(node, "miphy-sw-rst");
  923. if (IS_ERR(miphy_phy->miphy_rst)) {
  924. dev_err(miphy_dev->dev,
  925. "miphy soft reset control not defined\n");
  926. return PTR_ERR(miphy_phy->miphy_rst);
  927. }
  928. err = reset_control_deassert(miphy_phy->miphy_rst);
  929. if (err) {
  930. dev_err(miphy_dev->dev, "unable to bring out of miphy reset\n");
  931. return err;
  932. }
  933. return 0;
  934. }
  935. static int miphy28lp_of_probe(struct device_node *np,
  936. struct miphy28lp_phy *miphy_phy)
  937. {
  938. int i;
  939. u32 ctrlreg;
  940. miphy_phy->osc_force_ext =
  941. of_property_read_bool(np, "st,osc-force-ext");
  942. miphy_phy->osc_rdy = of_property_read_bool(np, "st,osc-rdy");
  943. miphy_phy->px_rx_pol_inv =
  944. of_property_read_bool(np, "st,px_rx_pol_inv");
  945. miphy_phy->ssc = of_property_read_bool(np, "st,ssc-on");
  946. miphy_phy->tx_impedance =
  947. of_property_read_bool(np, "st,tx-impedance-comp");
  948. of_property_read_u32(np, "st,sata-gen", &miphy_phy->sata_gen);
  949. if (!miphy_phy->sata_gen)
  950. miphy_phy->sata_gen = SATA_GEN1;
  951. for (i = 0; i < SYSCFG_REG_MAX; i++) {
  952. if (!of_property_read_u32_index(np, "st,syscfg", i, &ctrlreg))
  953. miphy_phy->syscfg_reg[i] = ctrlreg;
  954. }
  955. return 0;
  956. }
  957. static int miphy28lp_probe(struct platform_device *pdev)
  958. {
  959. struct device_node *child, *np = pdev->dev.of_node;
  960. struct miphy28lp_dev *miphy_dev;
  961. struct phy_provider *provider;
  962. struct phy *phy;
  963. int ret, port = 0;
  964. miphy_dev = devm_kzalloc(&pdev->dev, sizeof(*miphy_dev), GFP_KERNEL);
  965. if (!miphy_dev)
  966. return -ENOMEM;
  967. miphy_dev->nphys = of_get_child_count(np);
  968. miphy_dev->phys = devm_kcalloc(&pdev->dev, miphy_dev->nphys,
  969. sizeof(*miphy_dev->phys), GFP_KERNEL);
  970. if (!miphy_dev->phys)
  971. return -ENOMEM;
  972. miphy_dev->regmap = syscon_regmap_lookup_by_phandle(np, "st,syscfg");
  973. if (IS_ERR(miphy_dev->regmap)) {
  974. dev_err(miphy_dev->dev, "No syscfg phandle specified\n");
  975. return PTR_ERR(miphy_dev->regmap);
  976. }
  977. miphy_dev->dev = &pdev->dev;
  978. dev_set_drvdata(&pdev->dev, miphy_dev);
  979. mutex_init(&miphy_dev->miphy_mutex);
  980. for_each_child_of_node(np, child) {
  981. struct miphy28lp_phy *miphy_phy;
  982. miphy_phy = devm_kzalloc(&pdev->dev, sizeof(*miphy_phy),
  983. GFP_KERNEL);
  984. if (!miphy_phy) {
  985. ret = -ENOMEM;
  986. goto put_child;
  987. }
  988. miphy_dev->phys[port] = miphy_phy;
  989. phy = devm_phy_create(&pdev->dev, child, &miphy28lp_ops);
  990. if (IS_ERR(phy)) {
  991. dev_err(&pdev->dev, "failed to create PHY\n");
  992. ret = PTR_ERR(phy);
  993. goto put_child;
  994. }
  995. miphy_dev->phys[port]->phy = phy;
  996. miphy_dev->phys[port]->phydev = miphy_dev;
  997. ret = miphy28lp_of_probe(child, miphy_phy);
  998. if (ret)
  999. goto put_child;
  1000. ret = miphy28lp_probe_resets(child, miphy_dev->phys[port]);
  1001. if (ret)
  1002. goto put_child;
  1003. phy_set_drvdata(phy, miphy_dev->phys[port]);
  1004. port++;
  1005. }
  1006. provider = devm_of_phy_provider_register(&pdev->dev, miphy28lp_xlate);
  1007. return PTR_ERR_OR_ZERO(provider);
  1008. put_child:
  1009. of_node_put(child);
  1010. return ret;
  1011. }
  1012. static const struct of_device_id miphy28lp_of_match[] = {
  1013. {.compatible = "st,miphy28lp-phy", },
  1014. {},
  1015. };
  1016. MODULE_DEVICE_TABLE(of, miphy28lp_of_match);
  1017. static struct platform_driver miphy28lp_driver = {
  1018. .probe = miphy28lp_probe,
  1019. .driver = {
  1020. .name = "miphy28lp-phy",
  1021. .of_match_table = miphy28lp_of_match,
  1022. }
  1023. };
  1024. module_platform_driver(miphy28lp_driver);
  1025. MODULE_AUTHOR("Alexandre Torgue <alexandre.torgue@st.com>");
  1026. MODULE_DESCRIPTION("STMicroelectronics miphy28lp driver");
  1027. MODULE_LICENSE("GPL v2");