phy-qcom-snps-femto-v2.c 9.6 KB

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  1. // SPDX-License-Identifier: GPL-2.0
  2. /*
  3. * Copyright (c) 2020, The Linux Foundation. All rights reserved.
  4. */
  5. #include <linux/clk.h>
  6. #include <linux/delay.h>
  7. #include <linux/err.h>
  8. #include <linux/io.h>
  9. #include <linux/kernel.h>
  10. #include <linux/module.h>
  11. #include <linux/of.h>
  12. #include <linux/of_device.h>
  13. #include <linux/phy/phy.h>
  14. #include <linux/platform_device.h>
  15. #include <linux/regmap.h>
  16. #include <linux/regulator/consumer.h>
  17. #include <linux/reset.h>
  18. #include <linux/slab.h>
  19. #define USB2_PHY_USB_PHY_UTMI_CTRL0 (0x3c)
  20. #define SLEEPM BIT(0)
  21. #define OPMODE_MASK GENMASK(4, 3)
  22. #define OPMODE_NORMAL (0x00)
  23. #define OPMODE_NONDRIVING BIT(3)
  24. #define TERMSEL BIT(5)
  25. #define USB2_PHY_USB_PHY_UTMI_CTRL1 (0x40)
  26. #define XCVRSEL BIT(0)
  27. #define USB2_PHY_USB_PHY_UTMI_CTRL5 (0x50)
  28. #define POR BIT(1)
  29. #define USB2_PHY_USB_PHY_HS_PHY_CTRL_COMMON0 (0x54)
  30. #define RETENABLEN BIT(3)
  31. #define FSEL_MASK GENMASK(6, 4)
  32. #define FSEL_DEFAULT (0x3 << 4)
  33. #define USB2_PHY_USB_PHY_HS_PHY_CTRL_COMMON1 (0x58)
  34. #define VBUSVLDEXTSEL0 BIT(4)
  35. #define PLLBTUNE BIT(5)
  36. #define USB2_PHY_USB_PHY_HS_PHY_CTRL_COMMON2 (0x5c)
  37. #define VREGBYPASS BIT(0)
  38. #define USB2_PHY_USB_PHY_HS_PHY_CTRL1 (0x60)
  39. #define VBUSVLDEXT0 BIT(0)
  40. #define USB2_PHY_USB_PHY_HS_PHY_CTRL2 (0x64)
  41. #define USB2_AUTO_RESUME BIT(0)
  42. #define USB2_SUSPEND_N BIT(2)
  43. #define USB2_SUSPEND_N_SEL BIT(3)
  44. #define USB2_PHY_USB_PHY_CFG0 (0x94)
  45. #define UTMI_PHY_DATAPATH_CTRL_OVERRIDE_EN BIT(0)
  46. #define UTMI_PHY_CMN_CTRL_OVERRIDE_EN BIT(1)
  47. #define USB2_PHY_USB_PHY_REFCLK_CTRL (0xa0)
  48. #define REFCLK_SEL_MASK GENMASK(1, 0)
  49. #define REFCLK_SEL_DEFAULT (0x2 << 0)
  50. static const char * const qcom_snps_hsphy_vreg_names[] = {
  51. "vdda-pll", "vdda33", "vdda18",
  52. };
  53. #define SNPS_HS_NUM_VREGS ARRAY_SIZE(qcom_snps_hsphy_vreg_names)
  54. /**
  55. * struct qcom_snps_hsphy - snps hs phy attributes
  56. *
  57. * @phy: generic phy
  58. * @base: iomapped memory space for snps hs phy
  59. *
  60. * @cfg_ahb_clk: AHB2PHY interface clock
  61. * @ref_clk: phy reference clock
  62. * @iface_clk: phy interface clock
  63. * @phy_reset: phy reset control
  64. * @vregs: regulator supplies bulk data
  65. * @phy_initialized: if PHY has been initialized correctly
  66. * @mode: contains the current mode the PHY is in
  67. */
  68. struct qcom_snps_hsphy {
  69. struct phy *phy;
  70. void __iomem *base;
  71. struct clk *cfg_ahb_clk;
  72. struct clk *ref_clk;
  73. struct reset_control *phy_reset;
  74. struct regulator_bulk_data vregs[SNPS_HS_NUM_VREGS];
  75. bool phy_initialized;
  76. enum phy_mode mode;
  77. };
  78. static inline void qcom_snps_hsphy_write_mask(void __iomem *base, u32 offset,
  79. u32 mask, u32 val)
  80. {
  81. u32 reg;
  82. reg = readl_relaxed(base + offset);
  83. reg &= ~mask;
  84. reg |= val & mask;
  85. writel_relaxed(reg, base + offset);
  86. /* Ensure above write is completed */
  87. readl_relaxed(base + offset);
  88. }
  89. static int qcom_snps_hsphy_suspend(struct qcom_snps_hsphy *hsphy)
  90. {
  91. dev_dbg(&hsphy->phy->dev, "Suspend QCOM SNPS PHY\n");
  92. if (hsphy->mode == PHY_MODE_USB_HOST) {
  93. /* Enable auto-resume to meet remote wakeup timing */
  94. qcom_snps_hsphy_write_mask(hsphy->base,
  95. USB2_PHY_USB_PHY_HS_PHY_CTRL2,
  96. USB2_AUTO_RESUME,
  97. USB2_AUTO_RESUME);
  98. usleep_range(500, 1000);
  99. qcom_snps_hsphy_write_mask(hsphy->base,
  100. USB2_PHY_USB_PHY_HS_PHY_CTRL2,
  101. 0, USB2_AUTO_RESUME);
  102. }
  103. clk_disable_unprepare(hsphy->cfg_ahb_clk);
  104. return 0;
  105. }
  106. static int qcom_snps_hsphy_resume(struct qcom_snps_hsphy *hsphy)
  107. {
  108. int ret;
  109. dev_dbg(&hsphy->phy->dev, "Resume QCOM SNPS PHY, mode\n");
  110. ret = clk_prepare_enable(hsphy->cfg_ahb_clk);
  111. if (ret) {
  112. dev_err(&hsphy->phy->dev, "failed to enable cfg ahb clock\n");
  113. return ret;
  114. }
  115. return 0;
  116. }
  117. static int __maybe_unused qcom_snps_hsphy_runtime_suspend(struct device *dev)
  118. {
  119. struct qcom_snps_hsphy *hsphy = dev_get_drvdata(dev);
  120. if (!hsphy->phy_initialized)
  121. return 0;
  122. qcom_snps_hsphy_suspend(hsphy);
  123. return 0;
  124. }
  125. static int __maybe_unused qcom_snps_hsphy_runtime_resume(struct device *dev)
  126. {
  127. struct qcom_snps_hsphy *hsphy = dev_get_drvdata(dev);
  128. if (!hsphy->phy_initialized)
  129. return 0;
  130. qcom_snps_hsphy_resume(hsphy);
  131. return 0;
  132. }
  133. static int qcom_snps_hsphy_set_mode(struct phy *phy, enum phy_mode mode,
  134. int submode)
  135. {
  136. struct qcom_snps_hsphy *hsphy = phy_get_drvdata(phy);
  137. hsphy->mode = mode;
  138. return 0;
  139. }
  140. static int qcom_snps_hsphy_init(struct phy *phy)
  141. {
  142. struct qcom_snps_hsphy *hsphy = phy_get_drvdata(phy);
  143. int ret;
  144. dev_vdbg(&phy->dev, "%s(): Initializing SNPS HS phy\n", __func__);
  145. ret = regulator_bulk_enable(ARRAY_SIZE(hsphy->vregs), hsphy->vregs);
  146. if (ret)
  147. return ret;
  148. ret = clk_prepare_enable(hsphy->cfg_ahb_clk);
  149. if (ret) {
  150. dev_err(&phy->dev, "failed to enable cfg ahb clock, %d\n", ret);
  151. goto poweroff_phy;
  152. }
  153. ret = reset_control_assert(hsphy->phy_reset);
  154. if (ret) {
  155. dev_err(&phy->dev, "failed to assert phy_reset, %d\n", ret);
  156. goto disable_ahb_clk;
  157. }
  158. usleep_range(100, 150);
  159. ret = reset_control_deassert(hsphy->phy_reset);
  160. if (ret) {
  161. dev_err(&phy->dev, "failed to de-assert phy_reset, %d\n", ret);
  162. goto disable_ahb_clk;
  163. }
  164. qcom_snps_hsphy_write_mask(hsphy->base, USB2_PHY_USB_PHY_CFG0,
  165. UTMI_PHY_CMN_CTRL_OVERRIDE_EN,
  166. UTMI_PHY_CMN_CTRL_OVERRIDE_EN);
  167. qcom_snps_hsphy_write_mask(hsphy->base, USB2_PHY_USB_PHY_UTMI_CTRL5,
  168. POR, POR);
  169. qcom_snps_hsphy_write_mask(hsphy->base,
  170. USB2_PHY_USB_PHY_HS_PHY_CTRL_COMMON0,
  171. FSEL_MASK, 0);
  172. qcom_snps_hsphy_write_mask(hsphy->base,
  173. USB2_PHY_USB_PHY_HS_PHY_CTRL_COMMON1,
  174. PLLBTUNE, PLLBTUNE);
  175. qcom_snps_hsphy_write_mask(hsphy->base, USB2_PHY_USB_PHY_REFCLK_CTRL,
  176. REFCLK_SEL_DEFAULT, REFCLK_SEL_MASK);
  177. qcom_snps_hsphy_write_mask(hsphy->base,
  178. USB2_PHY_USB_PHY_HS_PHY_CTRL_COMMON1,
  179. VBUSVLDEXTSEL0, VBUSVLDEXTSEL0);
  180. qcom_snps_hsphy_write_mask(hsphy->base, USB2_PHY_USB_PHY_HS_PHY_CTRL1,
  181. VBUSVLDEXT0, VBUSVLDEXT0);
  182. qcom_snps_hsphy_write_mask(hsphy->base,
  183. USB2_PHY_USB_PHY_HS_PHY_CTRL_COMMON2,
  184. VREGBYPASS, VREGBYPASS);
  185. qcom_snps_hsphy_write_mask(hsphy->base, USB2_PHY_USB_PHY_HS_PHY_CTRL2,
  186. USB2_SUSPEND_N_SEL | USB2_SUSPEND_N,
  187. USB2_SUSPEND_N_SEL | USB2_SUSPEND_N);
  188. qcom_snps_hsphy_write_mask(hsphy->base, USB2_PHY_USB_PHY_UTMI_CTRL0,
  189. SLEEPM, SLEEPM);
  190. qcom_snps_hsphy_write_mask(hsphy->base, USB2_PHY_USB_PHY_UTMI_CTRL5,
  191. POR, 0);
  192. qcom_snps_hsphy_write_mask(hsphy->base, USB2_PHY_USB_PHY_HS_PHY_CTRL2,
  193. USB2_SUSPEND_N_SEL, 0);
  194. qcom_snps_hsphy_write_mask(hsphy->base, USB2_PHY_USB_PHY_CFG0,
  195. UTMI_PHY_CMN_CTRL_OVERRIDE_EN, 0);
  196. hsphy->phy_initialized = true;
  197. return 0;
  198. disable_ahb_clk:
  199. clk_disable_unprepare(hsphy->cfg_ahb_clk);
  200. poweroff_phy:
  201. regulator_bulk_disable(ARRAY_SIZE(hsphy->vregs), hsphy->vregs);
  202. return ret;
  203. }
  204. static int qcom_snps_hsphy_exit(struct phy *phy)
  205. {
  206. struct qcom_snps_hsphy *hsphy = phy_get_drvdata(phy);
  207. reset_control_assert(hsphy->phy_reset);
  208. clk_disable_unprepare(hsphy->cfg_ahb_clk);
  209. regulator_bulk_disable(ARRAY_SIZE(hsphy->vregs), hsphy->vregs);
  210. hsphy->phy_initialized = false;
  211. return 0;
  212. }
  213. static const struct phy_ops qcom_snps_hsphy_gen_ops = {
  214. .init = qcom_snps_hsphy_init,
  215. .exit = qcom_snps_hsphy_exit,
  216. .set_mode = qcom_snps_hsphy_set_mode,
  217. .owner = THIS_MODULE,
  218. };
  219. static const struct of_device_id qcom_snps_hsphy_of_match_table[] = {
  220. { .compatible = "qcom,sm8150-usb-hs-phy", },
  221. { .compatible = "qcom,usb-snps-hs-7nm-phy", },
  222. { .compatible = "qcom,usb-snps-femto-v2-phy", },
  223. { }
  224. };
  225. MODULE_DEVICE_TABLE(of, qcom_snps_hsphy_of_match_table);
  226. static const struct dev_pm_ops qcom_snps_hsphy_pm_ops = {
  227. SET_RUNTIME_PM_OPS(qcom_snps_hsphy_runtime_suspend,
  228. qcom_snps_hsphy_runtime_resume, NULL)
  229. };
  230. static int qcom_snps_hsphy_probe(struct platform_device *pdev)
  231. {
  232. struct device *dev = &pdev->dev;
  233. struct qcom_snps_hsphy *hsphy;
  234. struct phy_provider *phy_provider;
  235. struct phy *generic_phy;
  236. int ret, i;
  237. int num;
  238. hsphy = devm_kzalloc(dev, sizeof(*hsphy), GFP_KERNEL);
  239. if (!hsphy)
  240. return -ENOMEM;
  241. hsphy->base = devm_platform_ioremap_resource(pdev, 0);
  242. if (IS_ERR(hsphy->base))
  243. return PTR_ERR(hsphy->base);
  244. hsphy->ref_clk = devm_clk_get(dev, "ref");
  245. if (IS_ERR(hsphy->ref_clk)) {
  246. ret = PTR_ERR(hsphy->ref_clk);
  247. if (ret != -EPROBE_DEFER)
  248. dev_err(dev, "failed to get ref clk, %d\n", ret);
  249. return ret;
  250. }
  251. hsphy->phy_reset = devm_reset_control_get_exclusive(&pdev->dev, NULL);
  252. if (IS_ERR(hsphy->phy_reset)) {
  253. dev_err(dev, "failed to get phy core reset\n");
  254. return PTR_ERR(hsphy->phy_reset);
  255. }
  256. num = ARRAY_SIZE(hsphy->vregs);
  257. for (i = 0; i < num; i++)
  258. hsphy->vregs[i].supply = qcom_snps_hsphy_vreg_names[i];
  259. ret = devm_regulator_bulk_get(dev, num, hsphy->vregs);
  260. if (ret) {
  261. if (ret != -EPROBE_DEFER)
  262. dev_err(dev, "failed to get regulator supplies: %d\n",
  263. ret);
  264. return ret;
  265. }
  266. pm_runtime_set_active(dev);
  267. pm_runtime_enable(dev);
  268. /*
  269. * Prevent runtime pm from being ON by default. Users can enable
  270. * it using power/control in sysfs.
  271. */
  272. pm_runtime_forbid(dev);
  273. generic_phy = devm_phy_create(dev, NULL, &qcom_snps_hsphy_gen_ops);
  274. if (IS_ERR(generic_phy)) {
  275. ret = PTR_ERR(generic_phy);
  276. dev_err(dev, "failed to create phy, %d\n", ret);
  277. return ret;
  278. }
  279. hsphy->phy = generic_phy;
  280. dev_set_drvdata(dev, hsphy);
  281. phy_set_drvdata(generic_phy, hsphy);
  282. phy_provider = devm_of_phy_provider_register(dev, of_phy_simple_xlate);
  283. if (!IS_ERR(phy_provider))
  284. dev_dbg(dev, "Registered Qcom-SNPS HS phy\n");
  285. else
  286. pm_runtime_disable(dev);
  287. return PTR_ERR_OR_ZERO(phy_provider);
  288. }
  289. static struct platform_driver qcom_snps_hsphy_driver = {
  290. .probe = qcom_snps_hsphy_probe,
  291. .driver = {
  292. .name = "qcom-snps-hs-femto-v2-phy",
  293. .pm = &qcom_snps_hsphy_pm_ops,
  294. .of_match_table = qcom_snps_hsphy_of_match_table,
  295. },
  296. };
  297. module_platform_driver(qcom_snps_hsphy_driver);
  298. MODULE_DESCRIPTION("Qualcomm SNPS FEMTO USB HS PHY V2 driver");
  299. MODULE_LICENSE("GPL v2");