phy-qcom-qusb2.c 27 KB

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  1. // SPDX-License-Identifier: GPL-2.0
  2. /*
  3. * Copyright (c) 2017, 2019, The Linux Foundation. All rights reserved.
  4. */
  5. #include <linux/clk.h>
  6. #include <linux/delay.h>
  7. #include <linux/err.h>
  8. #include <linux/io.h>
  9. #include <linux/kernel.h>
  10. #include <linux/mfd/syscon.h>
  11. #include <linux/module.h>
  12. #include <linux/nvmem-consumer.h>
  13. #include <linux/of.h>
  14. #include <linux/of_device.h>
  15. #include <linux/phy/phy.h>
  16. #include <linux/platform_device.h>
  17. #include <linux/regmap.h>
  18. #include <linux/regulator/consumer.h>
  19. #include <linux/reset.h>
  20. #include <linux/slab.h>
  21. #include <dt-bindings/phy/phy-qcom-qusb2.h>
  22. #define QUSB2PHY_PLL_TEST 0x04
  23. #define CLK_REF_SEL BIT(7)
  24. #define QUSB2PHY_PLL_TUNE 0x08
  25. #define QUSB2PHY_PLL_USER_CTL1 0x0c
  26. #define QUSB2PHY_PLL_USER_CTL2 0x10
  27. #define QUSB2PHY_PLL_AUTOPGM_CTL1 0x1c
  28. #define QUSB2PHY_PLL_PWR_CTRL 0x18
  29. /* QUSB2PHY_PLL_STATUS register bits */
  30. #define PLL_LOCKED BIT(5)
  31. /* QUSB2PHY_PLL_COMMON_STATUS_ONE register bits */
  32. #define CORE_READY_STATUS BIT(0)
  33. /* QUSB2PHY_PORT_POWERDOWN register bits */
  34. #define CLAMP_N_EN BIT(5)
  35. #define FREEZIO_N BIT(1)
  36. #define POWER_DOWN BIT(0)
  37. /* QUSB2PHY_PWR_CTRL1 register bits */
  38. #define PWR_CTRL1_VREF_SUPPLY_TRIM BIT(5)
  39. #define PWR_CTRL1_CLAMP_N_EN BIT(1)
  40. #define QUSB2PHY_REFCLK_ENABLE BIT(0)
  41. #define PHY_CLK_SCHEME_SEL BIT(0)
  42. /* QUSB2PHY_INTR_CTRL register bits */
  43. #define DMSE_INTR_HIGH_SEL BIT(4)
  44. #define DPSE_INTR_HIGH_SEL BIT(3)
  45. #define CHG_DET_INTR_EN BIT(2)
  46. #define DMSE_INTR_EN BIT(1)
  47. #define DPSE_INTR_EN BIT(0)
  48. /* QUSB2PHY_PLL_CORE_INPUT_OVERRIDE register bits */
  49. #define CORE_PLL_EN_FROM_RESET BIT(4)
  50. #define CORE_RESET BIT(5)
  51. #define CORE_RESET_MUX BIT(6)
  52. /* QUSB2PHY_IMP_CTRL1 register bits */
  53. #define IMP_RES_OFFSET_MASK GENMASK(5, 0)
  54. #define IMP_RES_OFFSET_SHIFT 0x0
  55. /* QUSB2PHY_PLL_BIAS_CONTROL_2 register bits */
  56. #define BIAS_CTRL2_RES_OFFSET_MASK GENMASK(5, 0)
  57. #define BIAS_CTRL2_RES_OFFSET_SHIFT 0x0
  58. /* QUSB2PHY_CHG_CONTROL_2 register bits */
  59. #define CHG_CTRL2_OFFSET_MASK GENMASK(5, 4)
  60. #define CHG_CTRL2_OFFSET_SHIFT 0x4
  61. /* QUSB2PHY_PORT_TUNE1 register bits */
  62. #define HSTX_TRIM_MASK GENMASK(7, 4)
  63. #define HSTX_TRIM_SHIFT 0x4
  64. #define PREEMPH_WIDTH_HALF_BIT BIT(2)
  65. #define PREEMPHASIS_EN_MASK GENMASK(1, 0)
  66. #define PREEMPHASIS_EN_SHIFT 0x0
  67. /* QUSB2PHY_PORT_TUNE2 register bits */
  68. #define HSDISC_TRIM_MASK GENMASK(1, 0)
  69. #define HSDISC_TRIM_SHIFT 0x0
  70. #define QUSB2PHY_PLL_ANALOG_CONTROLS_TWO 0x04
  71. #define QUSB2PHY_PLL_CLOCK_INVERTERS 0x18c
  72. #define QUSB2PHY_PLL_CMODE 0x2c
  73. #define QUSB2PHY_PLL_LOCK_DELAY 0x184
  74. #define QUSB2PHY_PLL_DIGITAL_TIMERS_TWO 0xb4
  75. #define QUSB2PHY_PLL_BIAS_CONTROL_1 0x194
  76. #define QUSB2PHY_PLL_BIAS_CONTROL_2 0x198
  77. #define QUSB2PHY_PWR_CTRL2 0x214
  78. #define QUSB2PHY_IMP_CTRL1 0x220
  79. #define QUSB2PHY_IMP_CTRL2 0x224
  80. #define QUSB2PHY_CHG_CTRL2 0x23c
  81. struct qusb2_phy_init_tbl {
  82. unsigned int offset;
  83. unsigned int val;
  84. /*
  85. * register part of layout ?
  86. * if yes, then offset gives index in the reg-layout
  87. */
  88. int in_layout;
  89. };
  90. #define QUSB2_PHY_INIT_CFG(o, v) \
  91. { \
  92. .offset = o, \
  93. .val = v, \
  94. }
  95. #define QUSB2_PHY_INIT_CFG_L(o, v) \
  96. { \
  97. .offset = o, \
  98. .val = v, \
  99. .in_layout = 1, \
  100. }
  101. /* set of registers with offsets different per-PHY */
  102. enum qusb2phy_reg_layout {
  103. QUSB2PHY_PLL_CORE_INPUT_OVERRIDE,
  104. QUSB2PHY_PLL_STATUS,
  105. QUSB2PHY_PORT_TUNE1,
  106. QUSB2PHY_PORT_TUNE2,
  107. QUSB2PHY_PORT_TUNE3,
  108. QUSB2PHY_PORT_TUNE4,
  109. QUSB2PHY_PORT_TUNE5,
  110. QUSB2PHY_PORT_TEST1,
  111. QUSB2PHY_PORT_TEST2,
  112. QUSB2PHY_PORT_POWERDOWN,
  113. QUSB2PHY_INTR_CTRL,
  114. };
  115. static const unsigned int msm8996_regs_layout[] = {
  116. [QUSB2PHY_PLL_STATUS] = 0x38,
  117. [QUSB2PHY_PORT_TUNE1] = 0x80,
  118. [QUSB2PHY_PORT_TUNE2] = 0x84,
  119. [QUSB2PHY_PORT_TUNE3] = 0x88,
  120. [QUSB2PHY_PORT_TUNE4] = 0x8c,
  121. [QUSB2PHY_PORT_TUNE5] = 0x90,
  122. [QUSB2PHY_PORT_TEST1] = 0xb8,
  123. [QUSB2PHY_PORT_TEST2] = 0x9c,
  124. [QUSB2PHY_PORT_POWERDOWN] = 0xb4,
  125. [QUSB2PHY_INTR_CTRL] = 0xbc,
  126. };
  127. static const struct qusb2_phy_init_tbl msm8996_init_tbl[] = {
  128. QUSB2_PHY_INIT_CFG_L(QUSB2PHY_PORT_TUNE1, 0xf8),
  129. QUSB2_PHY_INIT_CFG_L(QUSB2PHY_PORT_TUNE2, 0xb3),
  130. QUSB2_PHY_INIT_CFG_L(QUSB2PHY_PORT_TUNE3, 0x83),
  131. QUSB2_PHY_INIT_CFG_L(QUSB2PHY_PORT_TUNE4, 0xc0),
  132. QUSB2_PHY_INIT_CFG(QUSB2PHY_PLL_TUNE, 0x30),
  133. QUSB2_PHY_INIT_CFG(QUSB2PHY_PLL_USER_CTL1, 0x79),
  134. QUSB2_PHY_INIT_CFG(QUSB2PHY_PLL_USER_CTL2, 0x21),
  135. QUSB2_PHY_INIT_CFG_L(QUSB2PHY_PORT_TEST2, 0x14),
  136. QUSB2_PHY_INIT_CFG(QUSB2PHY_PLL_AUTOPGM_CTL1, 0x9f),
  137. QUSB2_PHY_INIT_CFG(QUSB2PHY_PLL_PWR_CTRL, 0x00),
  138. };
  139. static const unsigned int msm8998_regs_layout[] = {
  140. [QUSB2PHY_PLL_CORE_INPUT_OVERRIDE] = 0xa8,
  141. [QUSB2PHY_PLL_STATUS] = 0x1a0,
  142. [QUSB2PHY_PORT_TUNE1] = 0x23c,
  143. [QUSB2PHY_PORT_TUNE2] = 0x240,
  144. [QUSB2PHY_PORT_TUNE3] = 0x244,
  145. [QUSB2PHY_PORT_TUNE4] = 0x248,
  146. [QUSB2PHY_PORT_TEST1] = 0x24c,
  147. [QUSB2PHY_PORT_TEST2] = 0x250,
  148. [QUSB2PHY_PORT_POWERDOWN] = 0x210,
  149. [QUSB2PHY_INTR_CTRL] = 0x22c,
  150. };
  151. static const struct qusb2_phy_init_tbl msm8998_init_tbl[] = {
  152. QUSB2_PHY_INIT_CFG(QUSB2PHY_PLL_ANALOG_CONTROLS_TWO, 0x13),
  153. QUSB2_PHY_INIT_CFG(QUSB2PHY_PLL_CLOCK_INVERTERS, 0x7c),
  154. QUSB2_PHY_INIT_CFG(QUSB2PHY_PLL_CMODE, 0x80),
  155. QUSB2_PHY_INIT_CFG(QUSB2PHY_PLL_LOCK_DELAY, 0x0a),
  156. QUSB2_PHY_INIT_CFG_L(QUSB2PHY_PORT_TUNE1, 0xa5),
  157. QUSB2_PHY_INIT_CFG_L(QUSB2PHY_PORT_TUNE2, 0x09),
  158. QUSB2_PHY_INIT_CFG(QUSB2PHY_PLL_DIGITAL_TIMERS_TWO, 0x19),
  159. };
  160. static const unsigned int qusb2_v2_regs_layout[] = {
  161. [QUSB2PHY_PLL_CORE_INPUT_OVERRIDE] = 0xa8,
  162. [QUSB2PHY_PLL_STATUS] = 0x1a0,
  163. [QUSB2PHY_PORT_TUNE1] = 0x240,
  164. [QUSB2PHY_PORT_TUNE2] = 0x244,
  165. [QUSB2PHY_PORT_TUNE3] = 0x248,
  166. [QUSB2PHY_PORT_TUNE4] = 0x24c,
  167. [QUSB2PHY_PORT_TUNE5] = 0x250,
  168. [QUSB2PHY_PORT_TEST1] = 0x254,
  169. [QUSB2PHY_PORT_TEST2] = 0x258,
  170. [QUSB2PHY_PORT_POWERDOWN] = 0x210,
  171. [QUSB2PHY_INTR_CTRL] = 0x230,
  172. };
  173. static const struct qusb2_phy_init_tbl qusb2_v2_init_tbl[] = {
  174. QUSB2_PHY_INIT_CFG(QUSB2PHY_PLL_ANALOG_CONTROLS_TWO, 0x03),
  175. QUSB2_PHY_INIT_CFG(QUSB2PHY_PLL_CLOCK_INVERTERS, 0x7c),
  176. QUSB2_PHY_INIT_CFG(QUSB2PHY_PLL_CMODE, 0x80),
  177. QUSB2_PHY_INIT_CFG(QUSB2PHY_PLL_LOCK_DELAY, 0x0a),
  178. QUSB2_PHY_INIT_CFG(QUSB2PHY_PLL_DIGITAL_TIMERS_TWO, 0x19),
  179. QUSB2_PHY_INIT_CFG(QUSB2PHY_PLL_BIAS_CONTROL_1, 0x40),
  180. QUSB2_PHY_INIT_CFG(QUSB2PHY_PLL_BIAS_CONTROL_2, 0x20),
  181. QUSB2_PHY_INIT_CFG(QUSB2PHY_PWR_CTRL2, 0x21),
  182. QUSB2_PHY_INIT_CFG(QUSB2PHY_IMP_CTRL1, 0x0),
  183. QUSB2_PHY_INIT_CFG(QUSB2PHY_IMP_CTRL2, 0x58),
  184. QUSB2_PHY_INIT_CFG_L(QUSB2PHY_PORT_TUNE1, 0x30),
  185. QUSB2_PHY_INIT_CFG_L(QUSB2PHY_PORT_TUNE2, 0x29),
  186. QUSB2_PHY_INIT_CFG_L(QUSB2PHY_PORT_TUNE3, 0xca),
  187. QUSB2_PHY_INIT_CFG_L(QUSB2PHY_PORT_TUNE4, 0x04),
  188. QUSB2_PHY_INIT_CFG_L(QUSB2PHY_PORT_TUNE5, 0x03),
  189. QUSB2_PHY_INIT_CFG(QUSB2PHY_CHG_CTRL2, 0x0),
  190. };
  191. struct qusb2_phy_cfg {
  192. const struct qusb2_phy_init_tbl *tbl;
  193. /* number of entries in the table */
  194. unsigned int tbl_num;
  195. /* offset to PHY_CLK_SCHEME register in TCSR map */
  196. unsigned int clk_scheme_offset;
  197. /* array of registers with different offsets */
  198. const unsigned int *regs;
  199. unsigned int mask_core_ready;
  200. unsigned int disable_ctrl;
  201. unsigned int autoresume_en;
  202. /* true if PHY has PLL_TEST register to select clk_scheme */
  203. bool has_pll_test;
  204. /* true if TUNE1 register must be updated by fused value, else TUNE2 */
  205. bool update_tune1_with_efuse;
  206. /* true if PHY has PLL_CORE_INPUT_OVERRIDE register to reset PLL */
  207. bool has_pll_override;
  208. };
  209. static const struct qusb2_phy_cfg msm8996_phy_cfg = {
  210. .tbl = msm8996_init_tbl,
  211. .tbl_num = ARRAY_SIZE(msm8996_init_tbl),
  212. .regs = msm8996_regs_layout,
  213. .has_pll_test = true,
  214. .disable_ctrl = (CLAMP_N_EN | FREEZIO_N | POWER_DOWN),
  215. .mask_core_ready = PLL_LOCKED,
  216. .autoresume_en = BIT(3),
  217. };
  218. static const struct qusb2_phy_cfg msm8998_phy_cfg = {
  219. .tbl = msm8998_init_tbl,
  220. .tbl_num = ARRAY_SIZE(msm8998_init_tbl),
  221. .regs = msm8998_regs_layout,
  222. .disable_ctrl = POWER_DOWN,
  223. .mask_core_ready = CORE_READY_STATUS,
  224. .has_pll_override = true,
  225. .autoresume_en = BIT(0),
  226. .update_tune1_with_efuse = true,
  227. };
  228. static const struct qusb2_phy_cfg qusb2_v2_phy_cfg = {
  229. .tbl = qusb2_v2_init_tbl,
  230. .tbl_num = ARRAY_SIZE(qusb2_v2_init_tbl),
  231. .regs = qusb2_v2_regs_layout,
  232. .disable_ctrl = (PWR_CTRL1_VREF_SUPPLY_TRIM | PWR_CTRL1_CLAMP_N_EN |
  233. POWER_DOWN),
  234. .mask_core_ready = CORE_READY_STATUS,
  235. .has_pll_override = true,
  236. .autoresume_en = BIT(0),
  237. .update_tune1_with_efuse = true,
  238. };
  239. static const char * const qusb2_phy_vreg_names[] = {
  240. "vdda-pll", "vdda-phy-dpdm",
  241. };
  242. #define QUSB2_NUM_VREGS ARRAY_SIZE(qusb2_phy_vreg_names)
  243. /* struct override_param - structure holding qusb2 v2 phy overriding param
  244. * set override true if the device tree property exists and read and assign
  245. * to value
  246. */
  247. struct override_param {
  248. bool override;
  249. u8 value;
  250. };
  251. /*struct override_params - structure holding qusb2 v2 phy overriding params
  252. * @imp_res_offset: rescode offset to be updated in IMP_CTRL1 register
  253. * @hstx_trim: HSTX_TRIM to be updated in TUNE1 register
  254. * @preemphasis: Amplitude Pre-Emphasis to be updated in TUNE1 register
  255. * @preemphasis_width: half/full-width Pre-Emphasis updated via TUNE1
  256. * @bias_ctrl: bias ctrl to be updated in BIAS_CONTROL_2 register
  257. * @charge_ctrl: charge ctrl to be updated in CHG_CTRL2 register
  258. * @hsdisc_trim: disconnect threshold to be updated in TUNE2 register
  259. */
  260. struct override_params {
  261. struct override_param imp_res_offset;
  262. struct override_param hstx_trim;
  263. struct override_param preemphasis;
  264. struct override_param preemphasis_width;
  265. struct override_param bias_ctrl;
  266. struct override_param charge_ctrl;
  267. struct override_param hsdisc_trim;
  268. };
  269. /**
  270. * struct qusb2_phy - structure holding qusb2 phy attributes
  271. *
  272. * @phy: generic phy
  273. * @base: iomapped memory space for qubs2 phy
  274. *
  275. * @cfg_ahb_clk: AHB2PHY interface clock
  276. * @ref_clk: phy reference clock
  277. * @iface_clk: phy interface clock
  278. * @phy_reset: phy reset control
  279. * @vregs: regulator supplies bulk data
  280. *
  281. * @tcsr: TCSR syscon register map
  282. * @cell: nvmem cell containing phy tuning value
  283. *
  284. * @overrides: pointer to structure for all overriding tuning params
  285. *
  286. * @cfg: phy config data
  287. * @has_se_clk_scheme: indicate if PHY has single-ended ref clock scheme
  288. * @phy_initialized: indicate if PHY has been initialized
  289. * @mode: current PHY mode
  290. */
  291. struct qusb2_phy {
  292. struct phy *phy;
  293. void __iomem *base;
  294. struct clk *cfg_ahb_clk;
  295. struct clk *ref_clk;
  296. struct clk *iface_clk;
  297. struct reset_control *phy_reset;
  298. struct regulator_bulk_data vregs[QUSB2_NUM_VREGS];
  299. struct regmap *tcsr;
  300. struct nvmem_cell *cell;
  301. struct override_params overrides;
  302. const struct qusb2_phy_cfg *cfg;
  303. bool has_se_clk_scheme;
  304. bool phy_initialized;
  305. enum phy_mode mode;
  306. };
  307. static inline void qusb2_write_mask(void __iomem *base, u32 offset,
  308. u32 val, u32 mask)
  309. {
  310. u32 reg;
  311. reg = readl(base + offset);
  312. reg &= ~mask;
  313. reg |= val & mask;
  314. writel(reg, base + offset);
  315. /* Ensure above write is completed */
  316. readl(base + offset);
  317. }
  318. static inline void qusb2_setbits(void __iomem *base, u32 offset, u32 val)
  319. {
  320. u32 reg;
  321. reg = readl(base + offset);
  322. reg |= val;
  323. writel(reg, base + offset);
  324. /* Ensure above write is completed */
  325. readl(base + offset);
  326. }
  327. static inline void qusb2_clrbits(void __iomem *base, u32 offset, u32 val)
  328. {
  329. u32 reg;
  330. reg = readl(base + offset);
  331. reg &= ~val;
  332. writel(reg, base + offset);
  333. /* Ensure above write is completed */
  334. readl(base + offset);
  335. }
  336. static inline
  337. void qcom_qusb2_phy_configure(void __iomem *base,
  338. const unsigned int *regs,
  339. const struct qusb2_phy_init_tbl tbl[], int num)
  340. {
  341. int i;
  342. for (i = 0; i < num; i++) {
  343. if (tbl[i].in_layout)
  344. writel(tbl[i].val, base + regs[tbl[i].offset]);
  345. else
  346. writel(tbl[i].val, base + tbl[i].offset);
  347. }
  348. }
  349. /*
  350. * Update board specific PHY tuning override values if specified from
  351. * device tree.
  352. */
  353. static void qusb2_phy_override_phy_params(struct qusb2_phy *qphy)
  354. {
  355. const struct qusb2_phy_cfg *cfg = qphy->cfg;
  356. struct override_params *or = &qphy->overrides;
  357. if (or->imp_res_offset.override)
  358. qusb2_write_mask(qphy->base, QUSB2PHY_IMP_CTRL1,
  359. or->imp_res_offset.value << IMP_RES_OFFSET_SHIFT,
  360. IMP_RES_OFFSET_MASK);
  361. if (or->bias_ctrl.override)
  362. qusb2_write_mask(qphy->base, QUSB2PHY_PLL_BIAS_CONTROL_2,
  363. or->bias_ctrl.value << BIAS_CTRL2_RES_OFFSET_SHIFT,
  364. BIAS_CTRL2_RES_OFFSET_MASK);
  365. if (or->charge_ctrl.override)
  366. qusb2_write_mask(qphy->base, QUSB2PHY_CHG_CTRL2,
  367. or->charge_ctrl.value << CHG_CTRL2_OFFSET_SHIFT,
  368. CHG_CTRL2_OFFSET_MASK);
  369. if (or->hstx_trim.override)
  370. qusb2_write_mask(qphy->base, cfg->regs[QUSB2PHY_PORT_TUNE1],
  371. or->hstx_trim.value << HSTX_TRIM_SHIFT,
  372. HSTX_TRIM_MASK);
  373. if (or->preemphasis.override)
  374. qusb2_write_mask(qphy->base, cfg->regs[QUSB2PHY_PORT_TUNE1],
  375. or->preemphasis.value << PREEMPHASIS_EN_SHIFT,
  376. PREEMPHASIS_EN_MASK);
  377. if (or->preemphasis_width.override) {
  378. if (or->preemphasis_width.value ==
  379. QUSB2_V2_PREEMPHASIS_WIDTH_HALF_BIT)
  380. qusb2_setbits(qphy->base,
  381. cfg->regs[QUSB2PHY_PORT_TUNE1],
  382. PREEMPH_WIDTH_HALF_BIT);
  383. else
  384. qusb2_clrbits(qphy->base,
  385. cfg->regs[QUSB2PHY_PORT_TUNE1],
  386. PREEMPH_WIDTH_HALF_BIT);
  387. }
  388. if (or->hsdisc_trim.override)
  389. qusb2_write_mask(qphy->base, cfg->regs[QUSB2PHY_PORT_TUNE2],
  390. or->hsdisc_trim.value << HSDISC_TRIM_SHIFT,
  391. HSDISC_TRIM_MASK);
  392. }
  393. /*
  394. * Fetches HS Tx tuning value from nvmem and sets the
  395. * QUSB2PHY_PORT_TUNE1/2 register.
  396. * For error case, skip setting the value and use the default value.
  397. */
  398. static void qusb2_phy_set_tune2_param(struct qusb2_phy *qphy)
  399. {
  400. struct device *dev = &qphy->phy->dev;
  401. const struct qusb2_phy_cfg *cfg = qphy->cfg;
  402. u8 *val, hstx_trim;
  403. /* efuse register is optional */
  404. if (!qphy->cell)
  405. return;
  406. /*
  407. * Read efuse register having TUNE2/1 parameter's high nibble.
  408. * If efuse register shows value as 0x0 (indicating value is not
  409. * fused), or if we fail to find a valid efuse register setting,
  410. * then use default value for high nibble that we have already
  411. * set while configuring the phy.
  412. */
  413. val = nvmem_cell_read(qphy->cell, NULL);
  414. if (IS_ERR(val)) {
  415. dev_dbg(dev, "failed to read a valid hs-tx trim value\n");
  416. return;
  417. }
  418. hstx_trim = val[0];
  419. kfree(val);
  420. if (!hstx_trim) {
  421. dev_dbg(dev, "failed to read a valid hs-tx trim value\n");
  422. return;
  423. }
  424. /* Fused TUNE1/2 value is the higher nibble only */
  425. if (cfg->update_tune1_with_efuse)
  426. qusb2_write_mask(qphy->base, cfg->regs[QUSB2PHY_PORT_TUNE1],
  427. hstx_trim << HSTX_TRIM_SHIFT, HSTX_TRIM_MASK);
  428. else
  429. qusb2_write_mask(qphy->base, cfg->regs[QUSB2PHY_PORT_TUNE2],
  430. hstx_trim << HSTX_TRIM_SHIFT, HSTX_TRIM_MASK);
  431. }
  432. static int qusb2_phy_set_mode(struct phy *phy,
  433. enum phy_mode mode, int submode)
  434. {
  435. struct qusb2_phy *qphy = phy_get_drvdata(phy);
  436. qphy->mode = mode;
  437. return 0;
  438. }
  439. static int __maybe_unused qusb2_phy_runtime_suspend(struct device *dev)
  440. {
  441. struct qusb2_phy *qphy = dev_get_drvdata(dev);
  442. const struct qusb2_phy_cfg *cfg = qphy->cfg;
  443. u32 intr_mask;
  444. dev_vdbg(dev, "Suspending QUSB2 Phy, mode:%d\n", qphy->mode);
  445. if (!qphy->phy_initialized) {
  446. dev_vdbg(dev, "PHY not initialized, bailing out\n");
  447. return 0;
  448. }
  449. /*
  450. * Enable DP/DM interrupts to detect line state changes based on current
  451. * speed. In other words, enable the triggers _opposite_ of what the
  452. * current D+/D- levels are e.g. if currently D+ high, D- low
  453. * (HS 'J'/Suspend), configure the mask to trigger on D+ low OR D- high
  454. */
  455. intr_mask = DPSE_INTR_EN | DMSE_INTR_EN;
  456. switch (qphy->mode) {
  457. case PHY_MODE_USB_HOST_HS:
  458. case PHY_MODE_USB_HOST_FS:
  459. case PHY_MODE_USB_DEVICE_HS:
  460. case PHY_MODE_USB_DEVICE_FS:
  461. intr_mask |= DMSE_INTR_HIGH_SEL;
  462. break;
  463. case PHY_MODE_USB_HOST_LS:
  464. case PHY_MODE_USB_DEVICE_LS:
  465. intr_mask |= DPSE_INTR_HIGH_SEL;
  466. break;
  467. default:
  468. /* No device connected, enable both DP/DM high interrupt */
  469. intr_mask |= DMSE_INTR_HIGH_SEL;
  470. intr_mask |= DPSE_INTR_HIGH_SEL;
  471. break;
  472. }
  473. writel(intr_mask, qphy->base + cfg->regs[QUSB2PHY_INTR_CTRL]);
  474. /* hold core PLL into reset */
  475. if (cfg->has_pll_override) {
  476. qusb2_setbits(qphy->base,
  477. cfg->regs[QUSB2PHY_PLL_CORE_INPUT_OVERRIDE],
  478. CORE_PLL_EN_FROM_RESET | CORE_RESET |
  479. CORE_RESET_MUX);
  480. }
  481. /* enable phy auto-resume only if device is connected on bus */
  482. if (qphy->mode != PHY_MODE_INVALID) {
  483. qusb2_setbits(qphy->base, cfg->regs[QUSB2PHY_PORT_TEST1],
  484. cfg->autoresume_en);
  485. /* Autoresume bit has to be toggled in order to enable it */
  486. qusb2_clrbits(qphy->base, cfg->regs[QUSB2PHY_PORT_TEST1],
  487. cfg->autoresume_en);
  488. }
  489. if (!qphy->has_se_clk_scheme)
  490. clk_disable_unprepare(qphy->ref_clk);
  491. clk_disable_unprepare(qphy->cfg_ahb_clk);
  492. clk_disable_unprepare(qphy->iface_clk);
  493. return 0;
  494. }
  495. static int __maybe_unused qusb2_phy_runtime_resume(struct device *dev)
  496. {
  497. struct qusb2_phy *qphy = dev_get_drvdata(dev);
  498. const struct qusb2_phy_cfg *cfg = qphy->cfg;
  499. int ret;
  500. dev_vdbg(dev, "Resuming QUSB2 phy, mode:%d\n", qphy->mode);
  501. if (!qphy->phy_initialized) {
  502. dev_vdbg(dev, "PHY not initialized, bailing out\n");
  503. return 0;
  504. }
  505. ret = clk_prepare_enable(qphy->iface_clk);
  506. if (ret) {
  507. dev_err(dev, "failed to enable iface_clk, %d\n", ret);
  508. return ret;
  509. }
  510. ret = clk_prepare_enable(qphy->cfg_ahb_clk);
  511. if (ret) {
  512. dev_err(dev, "failed to enable cfg ahb clock, %d\n", ret);
  513. goto disable_iface_clk;
  514. }
  515. if (!qphy->has_se_clk_scheme) {
  516. ret = clk_prepare_enable(qphy->ref_clk);
  517. if (ret) {
  518. dev_err(dev, "failed to enable ref clk, %d\n", ret);
  519. goto disable_ahb_clk;
  520. }
  521. }
  522. writel(0x0, qphy->base + cfg->regs[QUSB2PHY_INTR_CTRL]);
  523. /* bring core PLL out of reset */
  524. if (cfg->has_pll_override) {
  525. qusb2_clrbits(qphy->base,
  526. cfg->regs[QUSB2PHY_PLL_CORE_INPUT_OVERRIDE],
  527. CORE_RESET | CORE_RESET_MUX);
  528. }
  529. return 0;
  530. disable_ahb_clk:
  531. clk_disable_unprepare(qphy->cfg_ahb_clk);
  532. disable_iface_clk:
  533. clk_disable_unprepare(qphy->iface_clk);
  534. return ret;
  535. }
  536. static int qusb2_phy_init(struct phy *phy)
  537. {
  538. struct qusb2_phy *qphy = phy_get_drvdata(phy);
  539. const struct qusb2_phy_cfg *cfg = qphy->cfg;
  540. unsigned int val = 0;
  541. unsigned int clk_scheme;
  542. int ret;
  543. dev_vdbg(&phy->dev, "%s(): Initializing QUSB2 phy\n", __func__);
  544. /* turn on regulator supplies */
  545. ret = regulator_bulk_enable(ARRAY_SIZE(qphy->vregs), qphy->vregs);
  546. if (ret)
  547. return ret;
  548. ret = clk_prepare_enable(qphy->iface_clk);
  549. if (ret) {
  550. dev_err(&phy->dev, "failed to enable iface_clk, %d\n", ret);
  551. goto poweroff_phy;
  552. }
  553. /* enable ahb interface clock to program phy */
  554. ret = clk_prepare_enable(qphy->cfg_ahb_clk);
  555. if (ret) {
  556. dev_err(&phy->dev, "failed to enable cfg ahb clock, %d\n", ret);
  557. goto disable_iface_clk;
  558. }
  559. /* Perform phy reset */
  560. ret = reset_control_assert(qphy->phy_reset);
  561. if (ret) {
  562. dev_err(&phy->dev, "failed to assert phy_reset, %d\n", ret);
  563. goto disable_ahb_clk;
  564. }
  565. /* 100 us delay to keep PHY in reset mode */
  566. usleep_range(100, 150);
  567. ret = reset_control_deassert(qphy->phy_reset);
  568. if (ret) {
  569. dev_err(&phy->dev, "failed to de-assert phy_reset, %d\n", ret);
  570. goto disable_ahb_clk;
  571. }
  572. /* Disable the PHY */
  573. qusb2_setbits(qphy->base, cfg->regs[QUSB2PHY_PORT_POWERDOWN],
  574. qphy->cfg->disable_ctrl);
  575. if (cfg->has_pll_test) {
  576. /* save reset value to override reference clock scheme later */
  577. val = readl(qphy->base + QUSB2PHY_PLL_TEST);
  578. }
  579. qcom_qusb2_phy_configure(qphy->base, cfg->regs, cfg->tbl,
  580. cfg->tbl_num);
  581. /* Override board specific PHY tuning values */
  582. qusb2_phy_override_phy_params(qphy);
  583. /* Set efuse value for tuning the PHY */
  584. qusb2_phy_set_tune2_param(qphy);
  585. /* Enable the PHY */
  586. qusb2_clrbits(qphy->base, cfg->regs[QUSB2PHY_PORT_POWERDOWN],
  587. POWER_DOWN);
  588. /* Required to get phy pll lock successfully */
  589. usleep_range(150, 160);
  590. /* Default is single-ended clock on msm8996 */
  591. qphy->has_se_clk_scheme = true;
  592. /*
  593. * read TCSR_PHY_CLK_SCHEME register to check if single-ended
  594. * clock scheme is selected. If yes, then disable differential
  595. * ref_clk and use single-ended clock, otherwise use differential
  596. * ref_clk only.
  597. */
  598. if (qphy->tcsr) {
  599. ret = regmap_read(qphy->tcsr, qphy->cfg->clk_scheme_offset,
  600. &clk_scheme);
  601. if (ret) {
  602. dev_err(&phy->dev, "failed to read clk scheme reg\n");
  603. goto assert_phy_reset;
  604. }
  605. /* is it a differential clock scheme ? */
  606. if (!(clk_scheme & PHY_CLK_SCHEME_SEL)) {
  607. dev_vdbg(&phy->dev, "%s(): select differential clk\n",
  608. __func__);
  609. qphy->has_se_clk_scheme = false;
  610. } else {
  611. dev_vdbg(&phy->dev, "%s(): select single-ended clk\n",
  612. __func__);
  613. }
  614. }
  615. if (!qphy->has_se_clk_scheme) {
  616. ret = clk_prepare_enable(qphy->ref_clk);
  617. if (ret) {
  618. dev_err(&phy->dev, "failed to enable ref clk, %d\n",
  619. ret);
  620. goto assert_phy_reset;
  621. }
  622. }
  623. if (cfg->has_pll_test) {
  624. if (!qphy->has_se_clk_scheme)
  625. val &= ~CLK_REF_SEL;
  626. else
  627. val |= CLK_REF_SEL;
  628. writel(val, qphy->base + QUSB2PHY_PLL_TEST);
  629. /* ensure above write is through */
  630. readl(qphy->base + QUSB2PHY_PLL_TEST);
  631. }
  632. /* Required to get phy pll lock successfully */
  633. usleep_range(100, 110);
  634. val = readb(qphy->base + cfg->regs[QUSB2PHY_PLL_STATUS]);
  635. if (!(val & cfg->mask_core_ready)) {
  636. dev_err(&phy->dev,
  637. "QUSB2PHY pll lock failed: status reg = %x\n", val);
  638. ret = -EBUSY;
  639. goto disable_ref_clk;
  640. }
  641. qphy->phy_initialized = true;
  642. return 0;
  643. disable_ref_clk:
  644. if (!qphy->has_se_clk_scheme)
  645. clk_disable_unprepare(qphy->ref_clk);
  646. assert_phy_reset:
  647. reset_control_assert(qphy->phy_reset);
  648. disable_ahb_clk:
  649. clk_disable_unprepare(qphy->cfg_ahb_clk);
  650. disable_iface_clk:
  651. clk_disable_unprepare(qphy->iface_clk);
  652. poweroff_phy:
  653. regulator_bulk_disable(ARRAY_SIZE(qphy->vregs), qphy->vregs);
  654. return ret;
  655. }
  656. static int qusb2_phy_exit(struct phy *phy)
  657. {
  658. struct qusb2_phy *qphy = phy_get_drvdata(phy);
  659. /* Disable the PHY */
  660. qusb2_setbits(qphy->base, qphy->cfg->regs[QUSB2PHY_PORT_POWERDOWN],
  661. qphy->cfg->disable_ctrl);
  662. if (!qphy->has_se_clk_scheme)
  663. clk_disable_unprepare(qphy->ref_clk);
  664. reset_control_assert(qphy->phy_reset);
  665. clk_disable_unprepare(qphy->cfg_ahb_clk);
  666. clk_disable_unprepare(qphy->iface_clk);
  667. regulator_bulk_disable(ARRAY_SIZE(qphy->vregs), qphy->vregs);
  668. qphy->phy_initialized = false;
  669. return 0;
  670. }
  671. static const struct phy_ops qusb2_phy_gen_ops = {
  672. .init = qusb2_phy_init,
  673. .exit = qusb2_phy_exit,
  674. .set_mode = qusb2_phy_set_mode,
  675. .owner = THIS_MODULE,
  676. };
  677. static const struct of_device_id qusb2_phy_of_match_table[] = {
  678. {
  679. .compatible = "qcom,ipq8074-qusb2-phy",
  680. .data = &msm8996_phy_cfg,
  681. }, {
  682. .compatible = "qcom,msm8996-qusb2-phy",
  683. .data = &msm8996_phy_cfg,
  684. }, {
  685. .compatible = "qcom,msm8998-qusb2-phy",
  686. .data = &msm8998_phy_cfg,
  687. }, {
  688. /*
  689. * Deprecated. Only here to support legacy device
  690. * trees that didn't include "qcom,qusb2-v2-phy"
  691. */
  692. .compatible = "qcom,sdm845-qusb2-phy",
  693. .data = &qusb2_v2_phy_cfg,
  694. }, {
  695. .compatible = "qcom,qusb2-v2-phy",
  696. .data = &qusb2_v2_phy_cfg,
  697. },
  698. { },
  699. };
  700. MODULE_DEVICE_TABLE(of, qusb2_phy_of_match_table);
  701. static const struct dev_pm_ops qusb2_phy_pm_ops = {
  702. SET_RUNTIME_PM_OPS(qusb2_phy_runtime_suspend,
  703. qusb2_phy_runtime_resume, NULL)
  704. };
  705. static int qusb2_phy_probe(struct platform_device *pdev)
  706. {
  707. struct device *dev = &pdev->dev;
  708. struct qusb2_phy *qphy;
  709. struct phy_provider *phy_provider;
  710. struct phy *generic_phy;
  711. struct resource *res;
  712. int ret, i;
  713. int num;
  714. u32 value;
  715. struct override_params *or;
  716. qphy = devm_kzalloc(dev, sizeof(*qphy), GFP_KERNEL);
  717. if (!qphy)
  718. return -ENOMEM;
  719. or = &qphy->overrides;
  720. res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
  721. qphy->base = devm_ioremap_resource(dev, res);
  722. if (IS_ERR(qphy->base))
  723. return PTR_ERR(qphy->base);
  724. qphy->cfg_ahb_clk = devm_clk_get(dev, "cfg_ahb");
  725. if (IS_ERR(qphy->cfg_ahb_clk)) {
  726. ret = PTR_ERR(qphy->cfg_ahb_clk);
  727. if (ret != -EPROBE_DEFER)
  728. dev_err(dev, "failed to get cfg ahb clk, %d\n", ret);
  729. return ret;
  730. }
  731. qphy->ref_clk = devm_clk_get(dev, "ref");
  732. if (IS_ERR(qphy->ref_clk)) {
  733. ret = PTR_ERR(qphy->ref_clk);
  734. if (ret != -EPROBE_DEFER)
  735. dev_err(dev, "failed to get ref clk, %d\n", ret);
  736. return ret;
  737. }
  738. qphy->iface_clk = devm_clk_get_optional(dev, "iface");
  739. if (IS_ERR(qphy->iface_clk))
  740. return PTR_ERR(qphy->iface_clk);
  741. qphy->phy_reset = devm_reset_control_get_by_index(&pdev->dev, 0);
  742. if (IS_ERR(qphy->phy_reset)) {
  743. dev_err(dev, "failed to get phy core reset\n");
  744. return PTR_ERR(qphy->phy_reset);
  745. }
  746. num = ARRAY_SIZE(qphy->vregs);
  747. for (i = 0; i < num; i++)
  748. qphy->vregs[i].supply = qusb2_phy_vreg_names[i];
  749. ret = devm_regulator_bulk_get(dev, num, qphy->vregs);
  750. if (ret) {
  751. if (ret != -EPROBE_DEFER)
  752. dev_err(dev, "failed to get regulator supplies: %d\n",
  753. ret);
  754. return ret;
  755. }
  756. /* Get the specific init parameters of QMP phy */
  757. qphy->cfg = of_device_get_match_data(dev);
  758. qphy->tcsr = syscon_regmap_lookup_by_phandle(dev->of_node,
  759. "qcom,tcsr-syscon");
  760. if (IS_ERR(qphy->tcsr)) {
  761. dev_dbg(dev, "failed to lookup TCSR regmap\n");
  762. qphy->tcsr = NULL;
  763. }
  764. qphy->cell = devm_nvmem_cell_get(dev, NULL);
  765. if (IS_ERR(qphy->cell)) {
  766. if (PTR_ERR(qphy->cell) == -EPROBE_DEFER)
  767. return -EPROBE_DEFER;
  768. qphy->cell = NULL;
  769. dev_dbg(dev, "failed to lookup tune2 hstx trim value\n");
  770. }
  771. if (!of_property_read_u32(dev->of_node, "qcom,imp-res-offset-value",
  772. &value)) {
  773. or->imp_res_offset.value = (u8)value;
  774. or->imp_res_offset.override = true;
  775. }
  776. if (!of_property_read_u32(dev->of_node, "qcom,bias-ctrl-value",
  777. &value)) {
  778. or->bias_ctrl.value = (u8)value;
  779. or->bias_ctrl.override = true;
  780. }
  781. if (!of_property_read_u32(dev->of_node, "qcom,charge-ctrl-value",
  782. &value)) {
  783. or->charge_ctrl.value = (u8)value;
  784. or->charge_ctrl.override = true;
  785. }
  786. if (!of_property_read_u32(dev->of_node, "qcom,hstx-trim-value",
  787. &value)) {
  788. or->hstx_trim.value = (u8)value;
  789. or->hstx_trim.override = true;
  790. }
  791. if (!of_property_read_u32(dev->of_node, "qcom,preemphasis-level",
  792. &value)) {
  793. or->preemphasis.value = (u8)value;
  794. or->preemphasis.override = true;
  795. }
  796. if (!of_property_read_u32(dev->of_node, "qcom,preemphasis-width",
  797. &value)) {
  798. or->preemphasis_width.value = (u8)value;
  799. or->preemphasis_width.override = true;
  800. }
  801. if (!of_property_read_u32(dev->of_node, "qcom,hsdisc-trim-value",
  802. &value)) {
  803. or->hsdisc_trim.value = (u8)value;
  804. or->hsdisc_trim.override = true;
  805. }
  806. pm_runtime_set_active(dev);
  807. pm_runtime_enable(dev);
  808. /*
  809. * Prevent runtime pm from being ON by default. Users can enable
  810. * it using power/control in sysfs.
  811. */
  812. pm_runtime_forbid(dev);
  813. generic_phy = devm_phy_create(dev, NULL, &qusb2_phy_gen_ops);
  814. if (IS_ERR(generic_phy)) {
  815. ret = PTR_ERR(generic_phy);
  816. dev_err(dev, "failed to create phy, %d\n", ret);
  817. pm_runtime_disable(dev);
  818. return ret;
  819. }
  820. qphy->phy = generic_phy;
  821. dev_set_drvdata(dev, qphy);
  822. phy_set_drvdata(generic_phy, qphy);
  823. phy_provider = devm_of_phy_provider_register(dev, of_phy_simple_xlate);
  824. if (!IS_ERR(phy_provider))
  825. dev_info(dev, "Registered Qcom-QUSB2 phy\n");
  826. else
  827. pm_runtime_disable(dev);
  828. return PTR_ERR_OR_ZERO(phy_provider);
  829. }
  830. static struct platform_driver qusb2_phy_driver = {
  831. .probe = qusb2_phy_probe,
  832. .driver = {
  833. .name = "qcom-qusb2-phy",
  834. .pm = &qusb2_phy_pm_ops,
  835. .of_match_table = qusb2_phy_of_match_table,
  836. },
  837. };
  838. module_platform_driver(qusb2_phy_driver);
  839. MODULE_AUTHOR("Vivek Gautam <vivek.gautam@codeaurora.org>");
  840. MODULE_DESCRIPTION("Qualcomm QUSB2 PHY driver");
  841. MODULE_LICENSE("GPL v2");