phy-qcom-ipq806x-sata.c 6.0 KB

123456789101112131415161718192021222324252627282930313233343536373839404142434445464748495051525354555657585960616263646566676869707172737475767778798081828384858687888990919293949596979899100101102103104105106107108109110111112113114115116117118119120121122123124125126127128129130131132133134135136137138139140141142143144145146147148149150151152153154155156157158159160161162163164165166167168169170171172173174175176177178179180181182183184185186187188189190191192193194195196197198199200201
  1. // SPDX-License-Identifier: GPL-2.0-only
  2. /*
  3. * Copyright (c) 2014, The Linux Foundation. All rights reserved.
  4. */
  5. #include <linux/io.h>
  6. #include <linux/kernel.h>
  7. #include <linux/module.h>
  8. #include <linux/of.h>
  9. #include <linux/of_address.h>
  10. #include <linux/time.h>
  11. #include <linux/delay.h>
  12. #include <linux/clk.h>
  13. #include <linux/slab.h>
  14. #include <linux/platform_device.h>
  15. #include <linux/phy/phy.h>
  16. struct qcom_ipq806x_sata_phy {
  17. void __iomem *mmio;
  18. struct clk *cfg_clk;
  19. struct device *dev;
  20. };
  21. #define __set(v, a, b) (((v) << (b)) & GENMASK(a, b))
  22. #define SATA_PHY_P0_PARAM0 0x200
  23. #define SATA_PHY_P0_PARAM0_P0_TX_PREEMPH_GEN3(x) __set(x, 17, 12)
  24. #define SATA_PHY_P0_PARAM0_P0_TX_PREEMPH_GEN3_MASK GENMASK(17, 12)
  25. #define SATA_PHY_P0_PARAM0_P0_TX_PREEMPH_GEN2(x) __set(x, 11, 6)
  26. #define SATA_PHY_P0_PARAM0_P0_TX_PREEMPH_GEN2_MASK GENMASK(11, 6)
  27. #define SATA_PHY_P0_PARAM0_P0_TX_PREEMPH_GEN1(x) __set(x, 5, 0)
  28. #define SATA_PHY_P0_PARAM0_P0_TX_PREEMPH_GEN1_MASK GENMASK(5, 0)
  29. #define SATA_PHY_P0_PARAM1 0x204
  30. #define SATA_PHY_P0_PARAM1_RESERVED_BITS31_21(x) __set(x, 31, 21)
  31. #define SATA_PHY_P0_PARAM1_P0_TX_AMPLITUDE_GEN3(x) __set(x, 20, 14)
  32. #define SATA_PHY_P0_PARAM1_P0_TX_AMPLITUDE_GEN3_MASK GENMASK(20, 14)
  33. #define SATA_PHY_P0_PARAM1_P0_TX_AMPLITUDE_GEN2(x) __set(x, 13, 7)
  34. #define SATA_PHY_P0_PARAM1_P0_TX_AMPLITUDE_GEN2_MASK GENMASK(13, 7)
  35. #define SATA_PHY_P0_PARAM1_P0_TX_AMPLITUDE_GEN1(x) __set(x, 6, 0)
  36. #define SATA_PHY_P0_PARAM1_P0_TX_AMPLITUDE_GEN1_MASK GENMASK(6, 0)
  37. #define SATA_PHY_P0_PARAM2 0x208
  38. #define SATA_PHY_P0_PARAM2_RX_EQ(x) __set(x, 20, 18)
  39. #define SATA_PHY_P0_PARAM2_RX_EQ_MASK GENMASK(20, 18)
  40. #define SATA_PHY_P0_PARAM3 0x20C
  41. #define SATA_PHY_SSC_EN 0x8
  42. #define SATA_PHY_P0_PARAM4 0x210
  43. #define SATA_PHY_REF_SSP_EN 0x2
  44. #define SATA_PHY_RESET 0x1
  45. static int qcom_ipq806x_sata_phy_init(struct phy *generic_phy)
  46. {
  47. struct qcom_ipq806x_sata_phy *phy = phy_get_drvdata(generic_phy);
  48. u32 reg;
  49. /* Setting SSC_EN to 1 */
  50. reg = readl_relaxed(phy->mmio + SATA_PHY_P0_PARAM3);
  51. reg = reg | SATA_PHY_SSC_EN;
  52. writel_relaxed(reg, phy->mmio + SATA_PHY_P0_PARAM3);
  53. reg = readl_relaxed(phy->mmio + SATA_PHY_P0_PARAM0) &
  54. ~(SATA_PHY_P0_PARAM0_P0_TX_PREEMPH_GEN3_MASK |
  55. SATA_PHY_P0_PARAM0_P0_TX_PREEMPH_GEN2_MASK |
  56. SATA_PHY_P0_PARAM0_P0_TX_PREEMPH_GEN1_MASK);
  57. reg |= SATA_PHY_P0_PARAM0_P0_TX_PREEMPH_GEN3(0xf);
  58. writel_relaxed(reg, phy->mmio + SATA_PHY_P0_PARAM0);
  59. reg = readl_relaxed(phy->mmio + SATA_PHY_P0_PARAM1) &
  60. ~(SATA_PHY_P0_PARAM1_P0_TX_AMPLITUDE_GEN3_MASK |
  61. SATA_PHY_P0_PARAM1_P0_TX_AMPLITUDE_GEN2_MASK |
  62. SATA_PHY_P0_PARAM1_P0_TX_AMPLITUDE_GEN1_MASK);
  63. reg |= SATA_PHY_P0_PARAM1_P0_TX_AMPLITUDE_GEN3(0x55) |
  64. SATA_PHY_P0_PARAM1_P0_TX_AMPLITUDE_GEN2(0x55) |
  65. SATA_PHY_P0_PARAM1_P0_TX_AMPLITUDE_GEN1(0x55);
  66. writel_relaxed(reg, phy->mmio + SATA_PHY_P0_PARAM1);
  67. reg = readl_relaxed(phy->mmio + SATA_PHY_P0_PARAM2) &
  68. ~SATA_PHY_P0_PARAM2_RX_EQ_MASK;
  69. reg |= SATA_PHY_P0_PARAM2_RX_EQ(0x3);
  70. writel_relaxed(reg, phy->mmio + SATA_PHY_P0_PARAM2);
  71. /* Setting PHY_RESET to 1 */
  72. reg = readl_relaxed(phy->mmio + SATA_PHY_P0_PARAM4);
  73. reg = reg | SATA_PHY_RESET;
  74. writel_relaxed(reg, phy->mmio + SATA_PHY_P0_PARAM4);
  75. /* Setting REF_SSP_EN to 1 */
  76. reg = readl_relaxed(phy->mmio + SATA_PHY_P0_PARAM4);
  77. reg = reg | SATA_PHY_REF_SSP_EN | SATA_PHY_RESET;
  78. writel_relaxed(reg, phy->mmio + SATA_PHY_P0_PARAM4);
  79. /* make sure all changes complete before we let the PHY out of reset */
  80. mb();
  81. /* sleep for max. 50us more to combine processor wakeups */
  82. usleep_range(20, 20 + 50);
  83. /* Clearing PHY_RESET to 0 */
  84. reg = readl_relaxed(phy->mmio + SATA_PHY_P0_PARAM4);
  85. reg = reg & ~SATA_PHY_RESET;
  86. writel_relaxed(reg, phy->mmio + SATA_PHY_P0_PARAM4);
  87. return 0;
  88. }
  89. static int qcom_ipq806x_sata_phy_exit(struct phy *generic_phy)
  90. {
  91. struct qcom_ipq806x_sata_phy *phy = phy_get_drvdata(generic_phy);
  92. u32 reg;
  93. /* Setting PHY_RESET to 1 */
  94. reg = readl_relaxed(phy->mmio + SATA_PHY_P0_PARAM4);
  95. reg = reg | SATA_PHY_RESET;
  96. writel_relaxed(reg, phy->mmio + SATA_PHY_P0_PARAM4);
  97. return 0;
  98. }
  99. static const struct phy_ops qcom_ipq806x_sata_phy_ops = {
  100. .init = qcom_ipq806x_sata_phy_init,
  101. .exit = qcom_ipq806x_sata_phy_exit,
  102. .owner = THIS_MODULE,
  103. };
  104. static int qcom_ipq806x_sata_phy_probe(struct platform_device *pdev)
  105. {
  106. struct qcom_ipq806x_sata_phy *phy;
  107. struct device *dev = &pdev->dev;
  108. struct resource *res;
  109. struct phy_provider *phy_provider;
  110. struct phy *generic_phy;
  111. int ret;
  112. phy = devm_kzalloc(dev, sizeof(*phy), GFP_KERNEL);
  113. if (!phy)
  114. return -ENOMEM;
  115. res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
  116. phy->mmio = devm_ioremap_resource(dev, res);
  117. if (IS_ERR(phy->mmio))
  118. return PTR_ERR(phy->mmio);
  119. generic_phy = devm_phy_create(dev, NULL, &qcom_ipq806x_sata_phy_ops);
  120. if (IS_ERR(generic_phy)) {
  121. dev_err(dev, "%s: failed to create phy\n", __func__);
  122. return PTR_ERR(generic_phy);
  123. }
  124. phy->dev = dev;
  125. phy_set_drvdata(generic_phy, phy);
  126. platform_set_drvdata(pdev, phy);
  127. phy->cfg_clk = devm_clk_get(dev, "cfg");
  128. if (IS_ERR(phy->cfg_clk)) {
  129. dev_err(dev, "Failed to get sata cfg clock\n");
  130. return PTR_ERR(phy->cfg_clk);
  131. }
  132. ret = clk_prepare_enable(phy->cfg_clk);
  133. if (ret)
  134. return ret;
  135. phy_provider = devm_of_phy_provider_register(dev, of_phy_simple_xlate);
  136. if (IS_ERR(phy_provider)) {
  137. clk_disable_unprepare(phy->cfg_clk);
  138. dev_err(dev, "%s: failed to register phy\n", __func__);
  139. return PTR_ERR(phy_provider);
  140. }
  141. return 0;
  142. }
  143. static int qcom_ipq806x_sata_phy_remove(struct platform_device *pdev)
  144. {
  145. struct qcom_ipq806x_sata_phy *phy = platform_get_drvdata(pdev);
  146. clk_disable_unprepare(phy->cfg_clk);
  147. return 0;
  148. }
  149. static const struct of_device_id qcom_ipq806x_sata_phy_of_match[] = {
  150. { .compatible = "qcom,ipq806x-sata-phy" },
  151. { },
  152. };
  153. MODULE_DEVICE_TABLE(of, qcom_ipq806x_sata_phy_of_match);
  154. static struct platform_driver qcom_ipq806x_sata_phy_driver = {
  155. .probe = qcom_ipq806x_sata_phy_probe,
  156. .remove = qcom_ipq806x_sata_phy_remove,
  157. .driver = {
  158. .name = "qcom-ipq806x-sata-phy",
  159. .of_match_table = qcom_ipq806x_sata_phy_of_match,
  160. }
  161. };
  162. module_platform_driver(qcom_ipq806x_sata_phy_driver);
  163. MODULE_DESCRIPTION("QCOM IPQ806x SATA PHY driver");
  164. MODULE_LICENSE("GPL v2");