phy-mtk-xsphy.c 15 KB

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  1. // SPDX-License-Identifier: GPL-2.0
  2. /*
  3. * MediaTek USB3.1 gen2 xsphy Driver
  4. *
  5. * Copyright (c) 2018 MediaTek Inc.
  6. * Author: Chunfeng Yun <chunfeng.yun@mediatek.com>
  7. *
  8. */
  9. #include <dt-bindings/phy/phy.h>
  10. #include <linux/clk.h>
  11. #include <linux/delay.h>
  12. #include <linux/io.h>
  13. #include <linux/iopoll.h>
  14. #include <linux/module.h>
  15. #include <linux/of_address.h>
  16. #include <linux/phy/phy.h>
  17. #include <linux/platform_device.h>
  18. /* u2 phy banks */
  19. #define SSUSB_SIFSLV_MISC 0x000
  20. #define SSUSB_SIFSLV_U2FREQ 0x100
  21. #define SSUSB_SIFSLV_U2PHY_COM 0x300
  22. /* u3 phy shared banks */
  23. #define SSPXTP_SIFSLV_DIG_GLB 0x000
  24. #define SSPXTP_SIFSLV_PHYA_GLB 0x100
  25. /* u3 phy banks */
  26. #define SSPXTP_SIFSLV_DIG_LN_TOP 0x000
  27. #define SSPXTP_SIFSLV_DIG_LN_TX0 0x100
  28. #define SSPXTP_SIFSLV_DIG_LN_RX0 0x200
  29. #define SSPXTP_SIFSLV_DIG_LN_DAIF 0x300
  30. #define SSPXTP_SIFSLV_PHYA_LN 0x400
  31. #define XSP_U2FREQ_FMCR0 ((SSUSB_SIFSLV_U2FREQ) + 0x00)
  32. #define P2F_RG_FREQDET_EN BIT(24)
  33. #define P2F_RG_CYCLECNT GENMASK(23, 0)
  34. #define P2F_RG_CYCLECNT_VAL(x) ((P2F_RG_CYCLECNT) & (x))
  35. #define XSP_U2FREQ_MMONR0 ((SSUSB_SIFSLV_U2FREQ) + 0x0c)
  36. #define XSP_U2FREQ_FMMONR1 ((SSUSB_SIFSLV_U2FREQ) + 0x10)
  37. #define P2F_RG_FRCK_EN BIT(8)
  38. #define P2F_USB_FM_VALID BIT(0)
  39. #define XSP_USBPHYACR0 ((SSUSB_SIFSLV_U2PHY_COM) + 0x00)
  40. #define P2A0_RG_INTR_EN BIT(5)
  41. #define XSP_USBPHYACR1 ((SSUSB_SIFSLV_U2PHY_COM) + 0x04)
  42. #define P2A1_RG_INTR_CAL GENMASK(23, 19)
  43. #define P2A1_RG_INTR_CAL_VAL(x) ((0x1f & (x)) << 19)
  44. #define P2A1_RG_VRT_SEL GENMASK(14, 12)
  45. #define P2A1_RG_VRT_SEL_VAL(x) ((0x7 & (x)) << 12)
  46. #define P2A1_RG_TERM_SEL GENMASK(10, 8)
  47. #define P2A1_RG_TERM_SEL_VAL(x) ((0x7 & (x)) << 8)
  48. #define XSP_USBPHYACR5 ((SSUSB_SIFSLV_U2PHY_COM) + 0x014)
  49. #define P2A5_RG_HSTX_SRCAL_EN BIT(15)
  50. #define P2A5_RG_HSTX_SRCTRL GENMASK(14, 12)
  51. #define P2A5_RG_HSTX_SRCTRL_VAL(x) ((0x7 & (x)) << 12)
  52. #define XSP_USBPHYACR6 ((SSUSB_SIFSLV_U2PHY_COM) + 0x018)
  53. #define P2A6_RG_BC11_SW_EN BIT(23)
  54. #define P2A6_RG_OTG_VBUSCMP_EN BIT(20)
  55. #define XSP_U2PHYDTM1 ((SSUSB_SIFSLV_U2PHY_COM) + 0x06C)
  56. #define P2D_FORCE_IDDIG BIT(9)
  57. #define P2D_RG_VBUSVALID BIT(5)
  58. #define P2D_RG_SESSEND BIT(4)
  59. #define P2D_RG_AVALID BIT(2)
  60. #define P2D_RG_IDDIG BIT(1)
  61. #define SSPXTP_PHYA_GLB_00 ((SSPXTP_SIFSLV_PHYA_GLB) + 0x00)
  62. #define RG_XTP_GLB_BIAS_INTR_CTRL GENMASK(21, 16)
  63. #define RG_XTP_GLB_BIAS_INTR_CTRL_VAL(x) ((0x3f & (x)) << 16)
  64. #define SSPXTP_PHYA_LN_04 ((SSPXTP_SIFSLV_PHYA_LN) + 0x04)
  65. #define RG_XTP_LN0_TX_IMPSEL GENMASK(4, 0)
  66. #define RG_XTP_LN0_TX_IMPSEL_VAL(x) (0x1f & (x))
  67. #define SSPXTP_PHYA_LN_14 ((SSPXTP_SIFSLV_PHYA_LN) + 0x014)
  68. #define RG_XTP_LN0_RX_IMPSEL GENMASK(4, 0)
  69. #define RG_XTP_LN0_RX_IMPSEL_VAL(x) (0x1f & (x))
  70. #define XSP_REF_CLK 26 /* MHZ */
  71. #define XSP_SLEW_RATE_COEF 17
  72. #define XSP_SR_COEF_DIVISOR 1000
  73. #define XSP_FM_DET_CYCLE_CNT 1024
  74. struct xsphy_instance {
  75. struct phy *phy;
  76. void __iomem *port_base;
  77. struct clk *ref_clk; /* reference clock of anolog phy */
  78. u32 index;
  79. u32 type;
  80. /* only for HQA test */
  81. int efuse_intr;
  82. int efuse_tx_imp;
  83. int efuse_rx_imp;
  84. /* u2 eye diagram */
  85. int eye_src;
  86. int eye_vrt;
  87. int eye_term;
  88. };
  89. struct mtk_xsphy {
  90. struct device *dev;
  91. void __iomem *glb_base; /* only shared u3 sif */
  92. struct xsphy_instance **phys;
  93. int nphys;
  94. int src_ref_clk; /* MHZ, reference clock for slew rate calibrate */
  95. int src_coef; /* coefficient for slew rate calibrate */
  96. };
  97. static void u2_phy_slew_rate_calibrate(struct mtk_xsphy *xsphy,
  98. struct xsphy_instance *inst)
  99. {
  100. void __iomem *pbase = inst->port_base;
  101. int calib_val;
  102. int fm_out;
  103. u32 tmp;
  104. /* use force value */
  105. if (inst->eye_src)
  106. return;
  107. /* enable USB ring oscillator */
  108. tmp = readl(pbase + XSP_USBPHYACR5);
  109. tmp |= P2A5_RG_HSTX_SRCAL_EN;
  110. writel(tmp, pbase + XSP_USBPHYACR5);
  111. udelay(1); /* wait clock stable */
  112. /* enable free run clock */
  113. tmp = readl(pbase + XSP_U2FREQ_FMMONR1);
  114. tmp |= P2F_RG_FRCK_EN;
  115. writel(tmp, pbase + XSP_U2FREQ_FMMONR1);
  116. /* set cycle count as 1024 */
  117. tmp = readl(pbase + XSP_U2FREQ_FMCR0);
  118. tmp &= ~(P2F_RG_CYCLECNT);
  119. tmp |= P2F_RG_CYCLECNT_VAL(XSP_FM_DET_CYCLE_CNT);
  120. writel(tmp, pbase + XSP_U2FREQ_FMCR0);
  121. /* enable frequency meter */
  122. tmp = readl(pbase + XSP_U2FREQ_FMCR0);
  123. tmp |= P2F_RG_FREQDET_EN;
  124. writel(tmp, pbase + XSP_U2FREQ_FMCR0);
  125. /* ignore return value */
  126. readl_poll_timeout(pbase + XSP_U2FREQ_FMMONR1, tmp,
  127. (tmp & P2F_USB_FM_VALID), 10, 200);
  128. fm_out = readl(pbase + XSP_U2FREQ_MMONR0);
  129. /* disable frequency meter */
  130. tmp = readl(pbase + XSP_U2FREQ_FMCR0);
  131. tmp &= ~P2F_RG_FREQDET_EN;
  132. writel(tmp, pbase + XSP_U2FREQ_FMCR0);
  133. /* disable free run clock */
  134. tmp = readl(pbase + XSP_U2FREQ_FMMONR1);
  135. tmp &= ~P2F_RG_FRCK_EN;
  136. writel(tmp, pbase + XSP_U2FREQ_FMMONR1);
  137. if (fm_out) {
  138. /* (1024 / FM_OUT) x reference clock frequency x coefficient */
  139. tmp = xsphy->src_ref_clk * xsphy->src_coef;
  140. tmp = (tmp * XSP_FM_DET_CYCLE_CNT) / fm_out;
  141. calib_val = DIV_ROUND_CLOSEST(tmp, XSP_SR_COEF_DIVISOR);
  142. } else {
  143. /* if FM detection fail, set default value */
  144. calib_val = 3;
  145. }
  146. dev_dbg(xsphy->dev, "phy.%d, fm_out:%d, calib:%d (clk:%d, coef:%d)\n",
  147. inst->index, fm_out, calib_val,
  148. xsphy->src_ref_clk, xsphy->src_coef);
  149. /* set HS slew rate */
  150. tmp = readl(pbase + XSP_USBPHYACR5);
  151. tmp &= ~P2A5_RG_HSTX_SRCTRL;
  152. tmp |= P2A5_RG_HSTX_SRCTRL_VAL(calib_val);
  153. writel(tmp, pbase + XSP_USBPHYACR5);
  154. /* disable USB ring oscillator */
  155. tmp = readl(pbase + XSP_USBPHYACR5);
  156. tmp &= ~P2A5_RG_HSTX_SRCAL_EN;
  157. writel(tmp, pbase + XSP_USBPHYACR5);
  158. }
  159. static void u2_phy_instance_init(struct mtk_xsphy *xsphy,
  160. struct xsphy_instance *inst)
  161. {
  162. void __iomem *pbase = inst->port_base;
  163. u32 tmp;
  164. /* DP/DM BC1.1 path Disable */
  165. tmp = readl(pbase + XSP_USBPHYACR6);
  166. tmp &= ~P2A6_RG_BC11_SW_EN;
  167. writel(tmp, pbase + XSP_USBPHYACR6);
  168. tmp = readl(pbase + XSP_USBPHYACR0);
  169. tmp |= P2A0_RG_INTR_EN;
  170. writel(tmp, pbase + XSP_USBPHYACR0);
  171. }
  172. static void u2_phy_instance_power_on(struct mtk_xsphy *xsphy,
  173. struct xsphy_instance *inst)
  174. {
  175. void __iomem *pbase = inst->port_base;
  176. u32 index = inst->index;
  177. u32 tmp;
  178. tmp = readl(pbase + XSP_USBPHYACR6);
  179. tmp |= P2A6_RG_OTG_VBUSCMP_EN;
  180. writel(tmp, pbase + XSP_USBPHYACR6);
  181. tmp = readl(pbase + XSP_U2PHYDTM1);
  182. tmp |= P2D_RG_VBUSVALID | P2D_RG_AVALID;
  183. tmp &= ~P2D_RG_SESSEND;
  184. writel(tmp, pbase + XSP_U2PHYDTM1);
  185. dev_dbg(xsphy->dev, "%s(%d)\n", __func__, index);
  186. }
  187. static void u2_phy_instance_power_off(struct mtk_xsphy *xsphy,
  188. struct xsphy_instance *inst)
  189. {
  190. void __iomem *pbase = inst->port_base;
  191. u32 index = inst->index;
  192. u32 tmp;
  193. tmp = readl(pbase + XSP_USBPHYACR6);
  194. tmp &= ~P2A6_RG_OTG_VBUSCMP_EN;
  195. writel(tmp, pbase + XSP_USBPHYACR6);
  196. tmp = readl(pbase + XSP_U2PHYDTM1);
  197. tmp &= ~(P2D_RG_VBUSVALID | P2D_RG_AVALID);
  198. tmp |= P2D_RG_SESSEND;
  199. writel(tmp, pbase + XSP_U2PHYDTM1);
  200. dev_dbg(xsphy->dev, "%s(%d)\n", __func__, index);
  201. }
  202. static void u2_phy_instance_set_mode(struct mtk_xsphy *xsphy,
  203. struct xsphy_instance *inst,
  204. enum phy_mode mode)
  205. {
  206. u32 tmp;
  207. tmp = readl(inst->port_base + XSP_U2PHYDTM1);
  208. switch (mode) {
  209. case PHY_MODE_USB_DEVICE:
  210. tmp |= P2D_FORCE_IDDIG | P2D_RG_IDDIG;
  211. break;
  212. case PHY_MODE_USB_HOST:
  213. tmp |= P2D_FORCE_IDDIG;
  214. tmp &= ~P2D_RG_IDDIG;
  215. break;
  216. case PHY_MODE_USB_OTG:
  217. tmp &= ~(P2D_FORCE_IDDIG | P2D_RG_IDDIG);
  218. break;
  219. default:
  220. return;
  221. }
  222. writel(tmp, inst->port_base + XSP_U2PHYDTM1);
  223. }
  224. static void phy_parse_property(struct mtk_xsphy *xsphy,
  225. struct xsphy_instance *inst)
  226. {
  227. struct device *dev = &inst->phy->dev;
  228. switch (inst->type) {
  229. case PHY_TYPE_USB2:
  230. device_property_read_u32(dev, "mediatek,efuse-intr",
  231. &inst->efuse_intr);
  232. device_property_read_u32(dev, "mediatek,eye-src",
  233. &inst->eye_src);
  234. device_property_read_u32(dev, "mediatek,eye-vrt",
  235. &inst->eye_vrt);
  236. device_property_read_u32(dev, "mediatek,eye-term",
  237. &inst->eye_term);
  238. dev_dbg(dev, "intr:%d, src:%d, vrt:%d, term:%d\n",
  239. inst->efuse_intr, inst->eye_src,
  240. inst->eye_vrt, inst->eye_term);
  241. break;
  242. case PHY_TYPE_USB3:
  243. device_property_read_u32(dev, "mediatek,efuse-intr",
  244. &inst->efuse_intr);
  245. device_property_read_u32(dev, "mediatek,efuse-tx-imp",
  246. &inst->efuse_tx_imp);
  247. device_property_read_u32(dev, "mediatek,efuse-rx-imp",
  248. &inst->efuse_rx_imp);
  249. dev_dbg(dev, "intr:%d, tx-imp:%d, rx-imp:%d\n",
  250. inst->efuse_intr, inst->efuse_tx_imp,
  251. inst->efuse_rx_imp);
  252. break;
  253. default:
  254. dev_err(xsphy->dev, "incompatible phy type\n");
  255. return;
  256. }
  257. }
  258. static void u2_phy_props_set(struct mtk_xsphy *xsphy,
  259. struct xsphy_instance *inst)
  260. {
  261. void __iomem *pbase = inst->port_base;
  262. u32 tmp;
  263. if (inst->efuse_intr) {
  264. tmp = readl(pbase + XSP_USBPHYACR1);
  265. tmp &= ~P2A1_RG_INTR_CAL;
  266. tmp |= P2A1_RG_INTR_CAL_VAL(inst->efuse_intr);
  267. writel(tmp, pbase + XSP_USBPHYACR1);
  268. }
  269. if (inst->eye_src) {
  270. tmp = readl(pbase + XSP_USBPHYACR5);
  271. tmp &= ~P2A5_RG_HSTX_SRCTRL;
  272. tmp |= P2A5_RG_HSTX_SRCTRL_VAL(inst->eye_src);
  273. writel(tmp, pbase + XSP_USBPHYACR5);
  274. }
  275. if (inst->eye_vrt) {
  276. tmp = readl(pbase + XSP_USBPHYACR1);
  277. tmp &= ~P2A1_RG_VRT_SEL;
  278. tmp |= P2A1_RG_VRT_SEL_VAL(inst->eye_vrt);
  279. writel(tmp, pbase + XSP_USBPHYACR1);
  280. }
  281. if (inst->eye_term) {
  282. tmp = readl(pbase + XSP_USBPHYACR1);
  283. tmp &= ~P2A1_RG_TERM_SEL;
  284. tmp |= P2A1_RG_TERM_SEL_VAL(inst->eye_term);
  285. writel(tmp, pbase + XSP_USBPHYACR1);
  286. }
  287. }
  288. static void u3_phy_props_set(struct mtk_xsphy *xsphy,
  289. struct xsphy_instance *inst)
  290. {
  291. void __iomem *pbase = inst->port_base;
  292. u32 tmp;
  293. if (inst->efuse_intr) {
  294. tmp = readl(xsphy->glb_base + SSPXTP_PHYA_GLB_00);
  295. tmp &= ~RG_XTP_GLB_BIAS_INTR_CTRL;
  296. tmp |= RG_XTP_GLB_BIAS_INTR_CTRL_VAL(inst->efuse_intr);
  297. writel(tmp, xsphy->glb_base + SSPXTP_PHYA_GLB_00);
  298. }
  299. if (inst->efuse_tx_imp) {
  300. tmp = readl(pbase + SSPXTP_PHYA_LN_04);
  301. tmp &= ~RG_XTP_LN0_TX_IMPSEL;
  302. tmp |= RG_XTP_LN0_TX_IMPSEL_VAL(inst->efuse_tx_imp);
  303. writel(tmp, pbase + SSPXTP_PHYA_LN_04);
  304. }
  305. if (inst->efuse_rx_imp) {
  306. tmp = readl(pbase + SSPXTP_PHYA_LN_14);
  307. tmp &= ~RG_XTP_LN0_RX_IMPSEL;
  308. tmp |= RG_XTP_LN0_RX_IMPSEL_VAL(inst->efuse_rx_imp);
  309. writel(tmp, pbase + SSPXTP_PHYA_LN_14);
  310. }
  311. }
  312. static int mtk_phy_init(struct phy *phy)
  313. {
  314. struct xsphy_instance *inst = phy_get_drvdata(phy);
  315. struct mtk_xsphy *xsphy = dev_get_drvdata(phy->dev.parent);
  316. int ret;
  317. ret = clk_prepare_enable(inst->ref_clk);
  318. if (ret) {
  319. dev_err(xsphy->dev, "failed to enable ref_clk\n");
  320. return ret;
  321. }
  322. switch (inst->type) {
  323. case PHY_TYPE_USB2:
  324. u2_phy_instance_init(xsphy, inst);
  325. u2_phy_props_set(xsphy, inst);
  326. break;
  327. case PHY_TYPE_USB3:
  328. u3_phy_props_set(xsphy, inst);
  329. break;
  330. default:
  331. dev_err(xsphy->dev, "incompatible phy type\n");
  332. clk_disable_unprepare(inst->ref_clk);
  333. return -EINVAL;
  334. }
  335. return 0;
  336. }
  337. static int mtk_phy_power_on(struct phy *phy)
  338. {
  339. struct xsphy_instance *inst = phy_get_drvdata(phy);
  340. struct mtk_xsphy *xsphy = dev_get_drvdata(phy->dev.parent);
  341. if (inst->type == PHY_TYPE_USB2) {
  342. u2_phy_instance_power_on(xsphy, inst);
  343. u2_phy_slew_rate_calibrate(xsphy, inst);
  344. }
  345. return 0;
  346. }
  347. static int mtk_phy_power_off(struct phy *phy)
  348. {
  349. struct xsphy_instance *inst = phy_get_drvdata(phy);
  350. struct mtk_xsphy *xsphy = dev_get_drvdata(phy->dev.parent);
  351. if (inst->type == PHY_TYPE_USB2)
  352. u2_phy_instance_power_off(xsphy, inst);
  353. return 0;
  354. }
  355. static int mtk_phy_exit(struct phy *phy)
  356. {
  357. struct xsphy_instance *inst = phy_get_drvdata(phy);
  358. clk_disable_unprepare(inst->ref_clk);
  359. return 0;
  360. }
  361. static int mtk_phy_set_mode(struct phy *phy, enum phy_mode mode, int submode)
  362. {
  363. struct xsphy_instance *inst = phy_get_drvdata(phy);
  364. struct mtk_xsphy *xsphy = dev_get_drvdata(phy->dev.parent);
  365. if (inst->type == PHY_TYPE_USB2)
  366. u2_phy_instance_set_mode(xsphy, inst, mode);
  367. return 0;
  368. }
  369. static struct phy *mtk_phy_xlate(struct device *dev,
  370. struct of_phandle_args *args)
  371. {
  372. struct mtk_xsphy *xsphy = dev_get_drvdata(dev);
  373. struct xsphy_instance *inst = NULL;
  374. struct device_node *phy_np = args->np;
  375. int index;
  376. if (args->args_count != 1) {
  377. dev_err(dev, "invalid number of cells in 'phy' property\n");
  378. return ERR_PTR(-EINVAL);
  379. }
  380. for (index = 0; index < xsphy->nphys; index++)
  381. if (phy_np == xsphy->phys[index]->phy->dev.of_node) {
  382. inst = xsphy->phys[index];
  383. break;
  384. }
  385. if (!inst) {
  386. dev_err(dev, "failed to find appropriate phy\n");
  387. return ERR_PTR(-EINVAL);
  388. }
  389. inst->type = args->args[0];
  390. if (!(inst->type == PHY_TYPE_USB2 ||
  391. inst->type == PHY_TYPE_USB3)) {
  392. dev_err(dev, "unsupported phy type: %d\n", inst->type);
  393. return ERR_PTR(-EINVAL);
  394. }
  395. phy_parse_property(xsphy, inst);
  396. return inst->phy;
  397. }
  398. static const struct phy_ops mtk_xsphy_ops = {
  399. .init = mtk_phy_init,
  400. .exit = mtk_phy_exit,
  401. .power_on = mtk_phy_power_on,
  402. .power_off = mtk_phy_power_off,
  403. .set_mode = mtk_phy_set_mode,
  404. .owner = THIS_MODULE,
  405. };
  406. static const struct of_device_id mtk_xsphy_id_table[] = {
  407. { .compatible = "mediatek,xsphy", },
  408. { },
  409. };
  410. MODULE_DEVICE_TABLE(of, mtk_xsphy_id_table);
  411. static int mtk_xsphy_probe(struct platform_device *pdev)
  412. {
  413. struct device *dev = &pdev->dev;
  414. struct device_node *np = dev->of_node;
  415. struct device_node *child_np;
  416. struct phy_provider *provider;
  417. struct resource *glb_res;
  418. struct mtk_xsphy *xsphy;
  419. struct resource res;
  420. int port, retval;
  421. xsphy = devm_kzalloc(dev, sizeof(*xsphy), GFP_KERNEL);
  422. if (!xsphy)
  423. return -ENOMEM;
  424. xsphy->nphys = of_get_child_count(np);
  425. xsphy->phys = devm_kcalloc(dev, xsphy->nphys,
  426. sizeof(*xsphy->phys), GFP_KERNEL);
  427. if (!xsphy->phys)
  428. return -ENOMEM;
  429. xsphy->dev = dev;
  430. platform_set_drvdata(pdev, xsphy);
  431. glb_res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
  432. /* optional, may not exist if no u3 phys */
  433. if (glb_res) {
  434. /* get banks shared by multiple u3 phys */
  435. xsphy->glb_base = devm_ioremap_resource(dev, glb_res);
  436. if (IS_ERR(xsphy->glb_base)) {
  437. dev_err(dev, "failed to remap glb regs\n");
  438. return PTR_ERR(xsphy->glb_base);
  439. }
  440. }
  441. xsphy->src_ref_clk = XSP_REF_CLK;
  442. xsphy->src_coef = XSP_SLEW_RATE_COEF;
  443. /* update parameters of slew rate calibrate if exist */
  444. device_property_read_u32(dev, "mediatek,src-ref-clk-mhz",
  445. &xsphy->src_ref_clk);
  446. device_property_read_u32(dev, "mediatek,src-coef", &xsphy->src_coef);
  447. port = 0;
  448. for_each_child_of_node(np, child_np) {
  449. struct xsphy_instance *inst;
  450. struct phy *phy;
  451. inst = devm_kzalloc(dev, sizeof(*inst), GFP_KERNEL);
  452. if (!inst) {
  453. retval = -ENOMEM;
  454. goto put_child;
  455. }
  456. xsphy->phys[port] = inst;
  457. phy = devm_phy_create(dev, child_np, &mtk_xsphy_ops);
  458. if (IS_ERR(phy)) {
  459. dev_err(dev, "failed to create phy\n");
  460. retval = PTR_ERR(phy);
  461. goto put_child;
  462. }
  463. retval = of_address_to_resource(child_np, 0, &res);
  464. if (retval) {
  465. dev_err(dev, "failed to get address resource(id-%d)\n",
  466. port);
  467. goto put_child;
  468. }
  469. inst->port_base = devm_ioremap_resource(&phy->dev, &res);
  470. if (IS_ERR(inst->port_base)) {
  471. dev_err(dev, "failed to remap phy regs\n");
  472. retval = PTR_ERR(inst->port_base);
  473. goto put_child;
  474. }
  475. inst->phy = phy;
  476. inst->index = port;
  477. phy_set_drvdata(phy, inst);
  478. port++;
  479. inst->ref_clk = devm_clk_get(&phy->dev, "ref");
  480. if (IS_ERR(inst->ref_clk)) {
  481. dev_err(dev, "failed to get ref_clk(id-%d)\n", port);
  482. retval = PTR_ERR(inst->ref_clk);
  483. goto put_child;
  484. }
  485. }
  486. provider = devm_of_phy_provider_register(dev, mtk_phy_xlate);
  487. return PTR_ERR_OR_ZERO(provider);
  488. put_child:
  489. of_node_put(child_np);
  490. return retval;
  491. }
  492. static struct platform_driver mtk_xsphy_driver = {
  493. .probe = mtk_xsphy_probe,
  494. .driver = {
  495. .name = "mtk-xsphy",
  496. .of_match_table = mtk_xsphy_id_table,
  497. },
  498. };
  499. module_platform_driver(mtk_xsphy_driver);
  500. MODULE_AUTHOR("Chunfeng Yun <chunfeng.yun@mediatek.com>");
  501. MODULE_DESCRIPTION("MediaTek USB XS-PHY driver");
  502. MODULE_LICENSE("GPL v2");