phy-mtk-tphy.c 35 KB

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  1. // SPDX-License-Identifier: GPL-2.0
  2. /*
  3. * Copyright (c) 2015 MediaTek Inc.
  4. * Author: Chunfeng Yun <chunfeng.yun@mediatek.com>
  5. *
  6. */
  7. #include <dt-bindings/phy/phy.h>
  8. #include <linux/clk.h>
  9. #include <linux/delay.h>
  10. #include <linux/io.h>
  11. #include <linux/iopoll.h>
  12. #include <linux/module.h>
  13. #include <linux/of_address.h>
  14. #include <linux/of_device.h>
  15. #include <linux/phy/phy.h>
  16. #include <linux/platform_device.h>
  17. /* version V1 sub-banks offset base address */
  18. /* banks shared by multiple phys */
  19. #define SSUSB_SIFSLV_V1_SPLLC 0x000 /* shared by u3 phys */
  20. #define SSUSB_SIFSLV_V1_U2FREQ 0x100 /* shared by u2 phys */
  21. #define SSUSB_SIFSLV_V1_CHIP 0x300 /* shared by u3 phys */
  22. /* u2 phy bank */
  23. #define SSUSB_SIFSLV_V1_U2PHY_COM 0x000
  24. /* u3/pcie/sata phy banks */
  25. #define SSUSB_SIFSLV_V1_U3PHYD 0x000
  26. #define SSUSB_SIFSLV_V1_U3PHYA 0x200
  27. /* version V2 sub-banks offset base address */
  28. /* u2 phy banks */
  29. #define SSUSB_SIFSLV_V2_MISC 0x000
  30. #define SSUSB_SIFSLV_V2_U2FREQ 0x100
  31. #define SSUSB_SIFSLV_V2_U2PHY_COM 0x300
  32. /* u3/pcie/sata phy banks */
  33. #define SSUSB_SIFSLV_V2_SPLLC 0x000
  34. #define SSUSB_SIFSLV_V2_CHIP 0x100
  35. #define SSUSB_SIFSLV_V2_U3PHYD 0x200
  36. #define SSUSB_SIFSLV_V2_U3PHYA 0x400
  37. #define U3P_USBPHYACR0 0x000
  38. #define PA0_RG_U2PLL_FORCE_ON BIT(15)
  39. #define PA0_RG_USB20_INTR_EN BIT(5)
  40. #define U3P_USBPHYACR1 0x004
  41. #define PA1_RG_INTR_CAL GENMASK(23, 19)
  42. #define PA1_RG_INTR_CAL_VAL(x) ((0x1f & (x)) << 19)
  43. #define PA1_RG_VRT_SEL GENMASK(14, 12)
  44. #define PA1_RG_VRT_SEL_VAL(x) ((0x7 & (x)) << 12)
  45. #define PA1_RG_TERM_SEL GENMASK(10, 8)
  46. #define PA1_RG_TERM_SEL_VAL(x) ((0x7 & (x)) << 8)
  47. #define U3P_USBPHYACR2 0x008
  48. #define PA2_RG_SIF_U2PLL_FORCE_EN BIT(18)
  49. #define U3P_USBPHYACR5 0x014
  50. #define PA5_RG_U2_HSTX_SRCAL_EN BIT(15)
  51. #define PA5_RG_U2_HSTX_SRCTRL GENMASK(14, 12)
  52. #define PA5_RG_U2_HSTX_SRCTRL_VAL(x) ((0x7 & (x)) << 12)
  53. #define PA5_RG_U2_HS_100U_U3_EN BIT(11)
  54. #define U3P_USBPHYACR6 0x018
  55. #define PA6_RG_U2_BC11_SW_EN BIT(23)
  56. #define PA6_RG_U2_OTG_VBUSCMP_EN BIT(20)
  57. #define PA6_RG_U2_DISCTH GENMASK(7, 4)
  58. #define PA6_RG_U2_DISCTH_VAL(x) ((0xf & (x)) << 4)
  59. #define PA6_RG_U2_SQTH GENMASK(3, 0)
  60. #define PA6_RG_U2_SQTH_VAL(x) (0xf & (x))
  61. #define U3P_U2PHYACR4 0x020
  62. #define P2C_RG_USB20_GPIO_CTL BIT(9)
  63. #define P2C_USB20_GPIO_MODE BIT(8)
  64. #define P2C_U2_GPIO_CTR_MSK (P2C_RG_USB20_GPIO_CTL | P2C_USB20_GPIO_MODE)
  65. #define U3D_U2PHYDCR0 0x060
  66. #define P2C_RG_SIF_U2PLL_FORCE_ON BIT(24)
  67. #define U3P_U2PHYDTM0 0x068
  68. #define P2C_FORCE_UART_EN BIT(26)
  69. #define P2C_FORCE_DATAIN BIT(23)
  70. #define P2C_FORCE_DM_PULLDOWN BIT(21)
  71. #define P2C_FORCE_DP_PULLDOWN BIT(20)
  72. #define P2C_FORCE_XCVRSEL BIT(19)
  73. #define P2C_FORCE_SUSPENDM BIT(18)
  74. #define P2C_FORCE_TERMSEL BIT(17)
  75. #define P2C_RG_DATAIN GENMASK(13, 10)
  76. #define P2C_RG_DATAIN_VAL(x) ((0xf & (x)) << 10)
  77. #define P2C_RG_DMPULLDOWN BIT(7)
  78. #define P2C_RG_DPPULLDOWN BIT(6)
  79. #define P2C_RG_XCVRSEL GENMASK(5, 4)
  80. #define P2C_RG_XCVRSEL_VAL(x) ((0x3 & (x)) << 4)
  81. #define P2C_RG_SUSPENDM BIT(3)
  82. #define P2C_RG_TERMSEL BIT(2)
  83. #define P2C_DTM0_PART_MASK \
  84. (P2C_FORCE_DATAIN | P2C_FORCE_DM_PULLDOWN | \
  85. P2C_FORCE_DP_PULLDOWN | P2C_FORCE_XCVRSEL | \
  86. P2C_FORCE_TERMSEL | P2C_RG_DMPULLDOWN | \
  87. P2C_RG_DPPULLDOWN | P2C_RG_TERMSEL)
  88. #define U3P_U2PHYDTM1 0x06C
  89. #define P2C_RG_UART_EN BIT(16)
  90. #define P2C_FORCE_IDDIG BIT(9)
  91. #define P2C_RG_VBUSVALID BIT(5)
  92. #define P2C_RG_SESSEND BIT(4)
  93. #define P2C_RG_AVALID BIT(2)
  94. #define P2C_RG_IDDIG BIT(1)
  95. #define U3P_U2PHYBC12C 0x080
  96. #define P2C_RG_CHGDT_EN BIT(0)
  97. #define U3P_U3_CHIP_GPIO_CTLD 0x0c
  98. #define P3C_REG_IP_SW_RST BIT(31)
  99. #define P3C_MCU_BUS_CK_GATE_EN BIT(30)
  100. #define P3C_FORCE_IP_SW_RST BIT(29)
  101. #define U3P_U3_CHIP_GPIO_CTLE 0x10
  102. #define P3C_RG_SWRST_U3_PHYD BIT(25)
  103. #define P3C_RG_SWRST_U3_PHYD_FORCE_EN BIT(24)
  104. #define U3P_U3_PHYA_REG0 0x000
  105. #define P3A_RG_CLKDRV_OFF GENMASK(3, 2)
  106. #define P3A_RG_CLKDRV_OFF_VAL(x) ((0x3 & (x)) << 2)
  107. #define U3P_U3_PHYA_REG1 0x004
  108. #define P3A_RG_CLKDRV_AMP GENMASK(31, 29)
  109. #define P3A_RG_CLKDRV_AMP_VAL(x) ((0x7 & (x)) << 29)
  110. #define U3P_U3_PHYA_REG6 0x018
  111. #define P3A_RG_TX_EIDLE_CM GENMASK(31, 28)
  112. #define P3A_RG_TX_EIDLE_CM_VAL(x) ((0xf & (x)) << 28)
  113. #define U3P_U3_PHYA_REG9 0x024
  114. #define P3A_RG_RX_DAC_MUX GENMASK(5, 1)
  115. #define P3A_RG_RX_DAC_MUX_VAL(x) ((0x1f & (x)) << 1)
  116. #define U3P_U3_PHYA_DA_REG0 0x100
  117. #define P3A_RG_XTAL_EXT_PE2H GENMASK(17, 16)
  118. #define P3A_RG_XTAL_EXT_PE2H_VAL(x) ((0x3 & (x)) << 16)
  119. #define P3A_RG_XTAL_EXT_PE1H GENMASK(13, 12)
  120. #define P3A_RG_XTAL_EXT_PE1H_VAL(x) ((0x3 & (x)) << 12)
  121. #define P3A_RG_XTAL_EXT_EN_U3 GENMASK(11, 10)
  122. #define P3A_RG_XTAL_EXT_EN_U3_VAL(x) ((0x3 & (x)) << 10)
  123. #define U3P_U3_PHYA_DA_REG4 0x108
  124. #define P3A_RG_PLL_DIVEN_PE2H GENMASK(21, 19)
  125. #define P3A_RG_PLL_BC_PE2H GENMASK(7, 6)
  126. #define P3A_RG_PLL_BC_PE2H_VAL(x) ((0x3 & (x)) << 6)
  127. #define U3P_U3_PHYA_DA_REG5 0x10c
  128. #define P3A_RG_PLL_BR_PE2H GENMASK(29, 28)
  129. #define P3A_RG_PLL_BR_PE2H_VAL(x) ((0x3 & (x)) << 28)
  130. #define P3A_RG_PLL_IC_PE2H GENMASK(15, 12)
  131. #define P3A_RG_PLL_IC_PE2H_VAL(x) ((0xf & (x)) << 12)
  132. #define U3P_U3_PHYA_DA_REG6 0x110
  133. #define P3A_RG_PLL_IR_PE2H GENMASK(19, 16)
  134. #define P3A_RG_PLL_IR_PE2H_VAL(x) ((0xf & (x)) << 16)
  135. #define U3P_U3_PHYA_DA_REG7 0x114
  136. #define P3A_RG_PLL_BP_PE2H GENMASK(19, 16)
  137. #define P3A_RG_PLL_BP_PE2H_VAL(x) ((0xf & (x)) << 16)
  138. #define U3P_U3_PHYA_DA_REG20 0x13c
  139. #define P3A_RG_PLL_DELTA1_PE2H GENMASK(31, 16)
  140. #define P3A_RG_PLL_DELTA1_PE2H_VAL(x) ((0xffff & (x)) << 16)
  141. #define U3P_U3_PHYA_DA_REG25 0x148
  142. #define P3A_RG_PLL_DELTA_PE2H GENMASK(15, 0)
  143. #define P3A_RG_PLL_DELTA_PE2H_VAL(x) (0xffff & (x))
  144. #define U3P_U3_PHYD_LFPS1 0x00c
  145. #define P3D_RG_FWAKE_TH GENMASK(21, 16)
  146. #define P3D_RG_FWAKE_TH_VAL(x) ((0x3f & (x)) << 16)
  147. #define U3P_U3_PHYD_CDR1 0x05c
  148. #define P3D_RG_CDR_BIR_LTD1 GENMASK(28, 24)
  149. #define P3D_RG_CDR_BIR_LTD1_VAL(x) ((0x1f & (x)) << 24)
  150. #define P3D_RG_CDR_BIR_LTD0 GENMASK(12, 8)
  151. #define P3D_RG_CDR_BIR_LTD0_VAL(x) ((0x1f & (x)) << 8)
  152. #define U3P_U3_PHYD_RXDET1 0x128
  153. #define P3D_RG_RXDET_STB2_SET GENMASK(17, 9)
  154. #define P3D_RG_RXDET_STB2_SET_VAL(x) ((0x1ff & (x)) << 9)
  155. #define U3P_U3_PHYD_RXDET2 0x12c
  156. #define P3D_RG_RXDET_STB2_SET_P3 GENMASK(8, 0)
  157. #define P3D_RG_RXDET_STB2_SET_P3_VAL(x) (0x1ff & (x))
  158. #define U3P_SPLLC_XTALCTL3 0x018
  159. #define XC3_RG_U3_XTAL_RX_PWD BIT(9)
  160. #define XC3_RG_U3_FRC_XTAL_RX_PWD BIT(8)
  161. #define U3P_U2FREQ_FMCR0 0x00
  162. #define P2F_RG_MONCLK_SEL GENMASK(27, 26)
  163. #define P2F_RG_MONCLK_SEL_VAL(x) ((0x3 & (x)) << 26)
  164. #define P2F_RG_FREQDET_EN BIT(24)
  165. #define P2F_RG_CYCLECNT GENMASK(23, 0)
  166. #define P2F_RG_CYCLECNT_VAL(x) ((P2F_RG_CYCLECNT) & (x))
  167. #define U3P_U2FREQ_VALUE 0x0c
  168. #define U3P_U2FREQ_FMMONR1 0x10
  169. #define P2F_USB_FM_VALID BIT(0)
  170. #define P2F_RG_FRCK_EN BIT(8)
  171. #define U3P_REF_CLK 26 /* MHZ */
  172. #define U3P_SLEW_RATE_COEF 28
  173. #define U3P_SR_COEF_DIVISOR 1000
  174. #define U3P_FM_DET_CYCLE_CNT 1024
  175. /* SATA register setting */
  176. #define PHYD_CTRL_SIGNAL_MODE4 0x1c
  177. /* CDR Charge Pump P-path current adjustment */
  178. #define RG_CDR_BICLTD1_GEN1_MSK GENMASK(23, 20)
  179. #define RG_CDR_BICLTD1_GEN1_VAL(x) ((0xf & (x)) << 20)
  180. #define RG_CDR_BICLTD0_GEN1_MSK GENMASK(11, 8)
  181. #define RG_CDR_BICLTD0_GEN1_VAL(x) ((0xf & (x)) << 8)
  182. #define PHYD_DESIGN_OPTION2 0x24
  183. /* Symbol lock count selection */
  184. #define RG_LOCK_CNT_SEL_MSK GENMASK(5, 4)
  185. #define RG_LOCK_CNT_SEL_VAL(x) ((0x3 & (x)) << 4)
  186. #define PHYD_DESIGN_OPTION9 0x40
  187. /* COMWAK GAP width window */
  188. #define RG_TG_MAX_MSK GENMASK(20, 16)
  189. #define RG_TG_MAX_VAL(x) ((0x1f & (x)) << 16)
  190. /* COMINIT GAP width window */
  191. #define RG_T2_MAX_MSK GENMASK(13, 8)
  192. #define RG_T2_MAX_VAL(x) ((0x3f & (x)) << 8)
  193. /* COMWAK GAP width window */
  194. #define RG_TG_MIN_MSK GENMASK(7, 5)
  195. #define RG_TG_MIN_VAL(x) ((0x7 & (x)) << 5)
  196. /* COMINIT GAP width window */
  197. #define RG_T2_MIN_MSK GENMASK(4, 0)
  198. #define RG_T2_MIN_VAL(x) (0x1f & (x))
  199. #define ANA_RG_CTRL_SIGNAL1 0x4c
  200. /* TX driver tail current control for 0dB de-empahsis mdoe for Gen1 speed */
  201. #define RG_IDRV_0DB_GEN1_MSK GENMASK(13, 8)
  202. #define RG_IDRV_0DB_GEN1_VAL(x) ((0x3f & (x)) << 8)
  203. #define ANA_RG_CTRL_SIGNAL4 0x58
  204. #define RG_CDR_BICLTR_GEN1_MSK GENMASK(23, 20)
  205. #define RG_CDR_BICLTR_GEN1_VAL(x) ((0xf & (x)) << 20)
  206. /* Loop filter R1 resistance adjustment for Gen1 speed */
  207. #define RG_CDR_BR_GEN2_MSK GENMASK(10, 8)
  208. #define RG_CDR_BR_GEN2_VAL(x) ((0x7 & (x)) << 8)
  209. #define ANA_RG_CTRL_SIGNAL6 0x60
  210. /* I-path capacitance adjustment for Gen1 */
  211. #define RG_CDR_BC_GEN1_MSK GENMASK(28, 24)
  212. #define RG_CDR_BC_GEN1_VAL(x) ((0x1f & (x)) << 24)
  213. #define RG_CDR_BIRLTR_GEN1_MSK GENMASK(4, 0)
  214. #define RG_CDR_BIRLTR_GEN1_VAL(x) (0x1f & (x))
  215. #define ANA_EQ_EYE_CTRL_SIGNAL1 0x6c
  216. /* RX Gen1 LEQ tuning step */
  217. #define RG_EQ_DLEQ_LFI_GEN1_MSK GENMASK(11, 8)
  218. #define RG_EQ_DLEQ_LFI_GEN1_VAL(x) ((0xf & (x)) << 8)
  219. #define ANA_EQ_EYE_CTRL_SIGNAL4 0xd8
  220. #define RG_CDR_BIRLTD0_GEN1_MSK GENMASK(20, 16)
  221. #define RG_CDR_BIRLTD0_GEN1_VAL(x) ((0x1f & (x)) << 16)
  222. #define ANA_EQ_EYE_CTRL_SIGNAL5 0xdc
  223. #define RG_CDR_BIRLTD0_GEN3_MSK GENMASK(4, 0)
  224. #define RG_CDR_BIRLTD0_GEN3_VAL(x) (0x1f & (x))
  225. enum mtk_phy_version {
  226. MTK_PHY_V1 = 1,
  227. MTK_PHY_V2,
  228. };
  229. struct mtk_phy_pdata {
  230. /* avoid RX sensitivity level degradation only for mt8173 */
  231. bool avoid_rx_sen_degradation;
  232. enum mtk_phy_version version;
  233. };
  234. struct u2phy_banks {
  235. void __iomem *misc;
  236. void __iomem *fmreg;
  237. void __iomem *com;
  238. };
  239. struct u3phy_banks {
  240. void __iomem *spllc;
  241. void __iomem *chip;
  242. void __iomem *phyd; /* include u3phyd_bank2 */
  243. void __iomem *phya; /* include u3phya_da */
  244. };
  245. struct mtk_phy_instance {
  246. struct phy *phy;
  247. void __iomem *port_base;
  248. union {
  249. struct u2phy_banks u2_banks;
  250. struct u3phy_banks u3_banks;
  251. };
  252. struct clk *ref_clk; /* reference clock of (digital) phy */
  253. struct clk *da_ref_clk; /* reference clock of analog phy */
  254. u32 index;
  255. u8 type;
  256. int eye_src;
  257. int eye_vrt;
  258. int eye_term;
  259. int intr;
  260. int discth;
  261. bool bc12_en;
  262. };
  263. struct mtk_tphy {
  264. struct device *dev;
  265. void __iomem *sif_base; /* only shared sif */
  266. const struct mtk_phy_pdata *pdata;
  267. struct mtk_phy_instance **phys;
  268. int nphys;
  269. int src_ref_clk; /* MHZ, reference clock for slew rate calibrate */
  270. int src_coef; /* coefficient for slew rate calibrate */
  271. };
  272. static void hs_slew_rate_calibrate(struct mtk_tphy *tphy,
  273. struct mtk_phy_instance *instance)
  274. {
  275. struct u2phy_banks *u2_banks = &instance->u2_banks;
  276. void __iomem *fmreg = u2_banks->fmreg;
  277. void __iomem *com = u2_banks->com;
  278. int calibration_val;
  279. int fm_out;
  280. u32 tmp;
  281. /* use force value */
  282. if (instance->eye_src)
  283. return;
  284. /* enable USB ring oscillator */
  285. tmp = readl(com + U3P_USBPHYACR5);
  286. tmp |= PA5_RG_U2_HSTX_SRCAL_EN;
  287. writel(tmp, com + U3P_USBPHYACR5);
  288. udelay(1);
  289. /*enable free run clock */
  290. tmp = readl(fmreg + U3P_U2FREQ_FMMONR1);
  291. tmp |= P2F_RG_FRCK_EN;
  292. writel(tmp, fmreg + U3P_U2FREQ_FMMONR1);
  293. /* set cycle count as 1024, and select u2 channel */
  294. tmp = readl(fmreg + U3P_U2FREQ_FMCR0);
  295. tmp &= ~(P2F_RG_CYCLECNT | P2F_RG_MONCLK_SEL);
  296. tmp |= P2F_RG_CYCLECNT_VAL(U3P_FM_DET_CYCLE_CNT);
  297. if (tphy->pdata->version == MTK_PHY_V1)
  298. tmp |= P2F_RG_MONCLK_SEL_VAL(instance->index >> 1);
  299. writel(tmp, fmreg + U3P_U2FREQ_FMCR0);
  300. /* enable frequency meter */
  301. tmp = readl(fmreg + U3P_U2FREQ_FMCR0);
  302. tmp |= P2F_RG_FREQDET_EN;
  303. writel(tmp, fmreg + U3P_U2FREQ_FMCR0);
  304. /* ignore return value */
  305. readl_poll_timeout(fmreg + U3P_U2FREQ_FMMONR1, tmp,
  306. (tmp & P2F_USB_FM_VALID), 10, 200);
  307. fm_out = readl(fmreg + U3P_U2FREQ_VALUE);
  308. /* disable frequency meter */
  309. tmp = readl(fmreg + U3P_U2FREQ_FMCR0);
  310. tmp &= ~P2F_RG_FREQDET_EN;
  311. writel(tmp, fmreg + U3P_U2FREQ_FMCR0);
  312. /*disable free run clock */
  313. tmp = readl(fmreg + U3P_U2FREQ_FMMONR1);
  314. tmp &= ~P2F_RG_FRCK_EN;
  315. writel(tmp, fmreg + U3P_U2FREQ_FMMONR1);
  316. if (fm_out) {
  317. /* ( 1024 / FM_OUT ) x reference clock frequency x coef */
  318. tmp = tphy->src_ref_clk * tphy->src_coef;
  319. tmp = (tmp * U3P_FM_DET_CYCLE_CNT) / fm_out;
  320. calibration_val = DIV_ROUND_CLOSEST(tmp, U3P_SR_COEF_DIVISOR);
  321. } else {
  322. /* if FM detection fail, set default value */
  323. calibration_val = 4;
  324. }
  325. dev_dbg(tphy->dev, "phy:%d, fm_out:%d, calib:%d (clk:%d, coef:%d)\n",
  326. instance->index, fm_out, calibration_val,
  327. tphy->src_ref_clk, tphy->src_coef);
  328. /* set HS slew rate */
  329. tmp = readl(com + U3P_USBPHYACR5);
  330. tmp &= ~PA5_RG_U2_HSTX_SRCTRL;
  331. tmp |= PA5_RG_U2_HSTX_SRCTRL_VAL(calibration_val);
  332. writel(tmp, com + U3P_USBPHYACR5);
  333. /* disable USB ring oscillator */
  334. tmp = readl(com + U3P_USBPHYACR5);
  335. tmp &= ~PA5_RG_U2_HSTX_SRCAL_EN;
  336. writel(tmp, com + U3P_USBPHYACR5);
  337. }
  338. static void u3_phy_instance_init(struct mtk_tphy *tphy,
  339. struct mtk_phy_instance *instance)
  340. {
  341. struct u3phy_banks *u3_banks = &instance->u3_banks;
  342. u32 tmp;
  343. /* gating PCIe Analog XTAL clock */
  344. tmp = readl(u3_banks->spllc + U3P_SPLLC_XTALCTL3);
  345. tmp |= XC3_RG_U3_XTAL_RX_PWD | XC3_RG_U3_FRC_XTAL_RX_PWD;
  346. writel(tmp, u3_banks->spllc + U3P_SPLLC_XTALCTL3);
  347. /* gating XSQ */
  348. tmp = readl(u3_banks->phya + U3P_U3_PHYA_DA_REG0);
  349. tmp &= ~P3A_RG_XTAL_EXT_EN_U3;
  350. tmp |= P3A_RG_XTAL_EXT_EN_U3_VAL(2);
  351. writel(tmp, u3_banks->phya + U3P_U3_PHYA_DA_REG0);
  352. tmp = readl(u3_banks->phya + U3P_U3_PHYA_REG9);
  353. tmp &= ~P3A_RG_RX_DAC_MUX;
  354. tmp |= P3A_RG_RX_DAC_MUX_VAL(4);
  355. writel(tmp, u3_banks->phya + U3P_U3_PHYA_REG9);
  356. tmp = readl(u3_banks->phya + U3P_U3_PHYA_REG6);
  357. tmp &= ~P3A_RG_TX_EIDLE_CM;
  358. tmp |= P3A_RG_TX_EIDLE_CM_VAL(0xe);
  359. writel(tmp, u3_banks->phya + U3P_U3_PHYA_REG6);
  360. tmp = readl(u3_banks->phyd + U3P_U3_PHYD_CDR1);
  361. tmp &= ~(P3D_RG_CDR_BIR_LTD0 | P3D_RG_CDR_BIR_LTD1);
  362. tmp |= P3D_RG_CDR_BIR_LTD0_VAL(0xc) | P3D_RG_CDR_BIR_LTD1_VAL(0x3);
  363. writel(tmp, u3_banks->phyd + U3P_U3_PHYD_CDR1);
  364. tmp = readl(u3_banks->phyd + U3P_U3_PHYD_LFPS1);
  365. tmp &= ~P3D_RG_FWAKE_TH;
  366. tmp |= P3D_RG_FWAKE_TH_VAL(0x34);
  367. writel(tmp, u3_banks->phyd + U3P_U3_PHYD_LFPS1);
  368. tmp = readl(u3_banks->phyd + U3P_U3_PHYD_RXDET1);
  369. tmp &= ~P3D_RG_RXDET_STB2_SET;
  370. tmp |= P3D_RG_RXDET_STB2_SET_VAL(0x10);
  371. writel(tmp, u3_banks->phyd + U3P_U3_PHYD_RXDET1);
  372. tmp = readl(u3_banks->phyd + U3P_U3_PHYD_RXDET2);
  373. tmp &= ~P3D_RG_RXDET_STB2_SET_P3;
  374. tmp |= P3D_RG_RXDET_STB2_SET_P3_VAL(0x10);
  375. writel(tmp, u3_banks->phyd + U3P_U3_PHYD_RXDET2);
  376. dev_dbg(tphy->dev, "%s(%d)\n", __func__, instance->index);
  377. }
  378. static void u2_phy_instance_init(struct mtk_tphy *tphy,
  379. struct mtk_phy_instance *instance)
  380. {
  381. struct u2phy_banks *u2_banks = &instance->u2_banks;
  382. void __iomem *com = u2_banks->com;
  383. u32 index = instance->index;
  384. u32 tmp;
  385. /* switch to USB function, and enable usb pll */
  386. tmp = readl(com + U3P_U2PHYDTM0);
  387. tmp &= ~(P2C_FORCE_UART_EN | P2C_FORCE_SUSPENDM);
  388. tmp |= P2C_RG_XCVRSEL_VAL(1) | P2C_RG_DATAIN_VAL(0);
  389. writel(tmp, com + U3P_U2PHYDTM0);
  390. tmp = readl(com + U3P_U2PHYDTM1);
  391. tmp &= ~P2C_RG_UART_EN;
  392. writel(tmp, com + U3P_U2PHYDTM1);
  393. tmp = readl(com + U3P_USBPHYACR0);
  394. tmp |= PA0_RG_USB20_INTR_EN;
  395. writel(tmp, com + U3P_USBPHYACR0);
  396. /* disable switch 100uA current to SSUSB */
  397. tmp = readl(com + U3P_USBPHYACR5);
  398. tmp &= ~PA5_RG_U2_HS_100U_U3_EN;
  399. writel(tmp, com + U3P_USBPHYACR5);
  400. if (!index) {
  401. tmp = readl(com + U3P_U2PHYACR4);
  402. tmp &= ~P2C_U2_GPIO_CTR_MSK;
  403. writel(tmp, com + U3P_U2PHYACR4);
  404. }
  405. if (tphy->pdata->avoid_rx_sen_degradation) {
  406. if (!index) {
  407. tmp = readl(com + U3P_USBPHYACR2);
  408. tmp |= PA2_RG_SIF_U2PLL_FORCE_EN;
  409. writel(tmp, com + U3P_USBPHYACR2);
  410. tmp = readl(com + U3D_U2PHYDCR0);
  411. tmp &= ~P2C_RG_SIF_U2PLL_FORCE_ON;
  412. writel(tmp, com + U3D_U2PHYDCR0);
  413. } else {
  414. tmp = readl(com + U3D_U2PHYDCR0);
  415. tmp |= P2C_RG_SIF_U2PLL_FORCE_ON;
  416. writel(tmp, com + U3D_U2PHYDCR0);
  417. tmp = readl(com + U3P_U2PHYDTM0);
  418. tmp |= P2C_RG_SUSPENDM | P2C_FORCE_SUSPENDM;
  419. writel(tmp, com + U3P_U2PHYDTM0);
  420. }
  421. }
  422. tmp = readl(com + U3P_USBPHYACR6);
  423. tmp &= ~PA6_RG_U2_BC11_SW_EN; /* DP/DM BC1.1 path Disable */
  424. tmp &= ~PA6_RG_U2_SQTH;
  425. tmp |= PA6_RG_U2_SQTH_VAL(2);
  426. writel(tmp, com + U3P_USBPHYACR6);
  427. dev_dbg(tphy->dev, "%s(%d)\n", __func__, index);
  428. }
  429. static void u2_phy_instance_power_on(struct mtk_tphy *tphy,
  430. struct mtk_phy_instance *instance)
  431. {
  432. struct u2phy_banks *u2_banks = &instance->u2_banks;
  433. void __iomem *com = u2_banks->com;
  434. u32 index = instance->index;
  435. u32 tmp;
  436. tmp = readl(com + U3P_U2PHYDTM0);
  437. tmp &= ~(P2C_RG_XCVRSEL | P2C_RG_DATAIN | P2C_DTM0_PART_MASK);
  438. writel(tmp, com + U3P_U2PHYDTM0);
  439. /* OTG Enable */
  440. tmp = readl(com + U3P_USBPHYACR6);
  441. tmp |= PA6_RG_U2_OTG_VBUSCMP_EN;
  442. writel(tmp, com + U3P_USBPHYACR6);
  443. tmp = readl(com + U3P_U2PHYDTM1);
  444. tmp |= P2C_RG_VBUSVALID | P2C_RG_AVALID;
  445. tmp &= ~P2C_RG_SESSEND;
  446. writel(tmp, com + U3P_U2PHYDTM1);
  447. if (tphy->pdata->avoid_rx_sen_degradation && index) {
  448. tmp = readl(com + U3D_U2PHYDCR0);
  449. tmp |= P2C_RG_SIF_U2PLL_FORCE_ON;
  450. writel(tmp, com + U3D_U2PHYDCR0);
  451. tmp = readl(com + U3P_U2PHYDTM0);
  452. tmp |= P2C_RG_SUSPENDM | P2C_FORCE_SUSPENDM;
  453. writel(tmp, com + U3P_U2PHYDTM0);
  454. }
  455. dev_dbg(tphy->dev, "%s(%d)\n", __func__, index);
  456. }
  457. static void u2_phy_instance_power_off(struct mtk_tphy *tphy,
  458. struct mtk_phy_instance *instance)
  459. {
  460. struct u2phy_banks *u2_banks = &instance->u2_banks;
  461. void __iomem *com = u2_banks->com;
  462. u32 index = instance->index;
  463. u32 tmp;
  464. tmp = readl(com + U3P_U2PHYDTM0);
  465. tmp &= ~(P2C_RG_XCVRSEL | P2C_RG_DATAIN);
  466. writel(tmp, com + U3P_U2PHYDTM0);
  467. /* OTG Disable */
  468. tmp = readl(com + U3P_USBPHYACR6);
  469. tmp &= ~PA6_RG_U2_OTG_VBUSCMP_EN;
  470. writel(tmp, com + U3P_USBPHYACR6);
  471. tmp = readl(com + U3P_U2PHYDTM1);
  472. tmp &= ~(P2C_RG_VBUSVALID | P2C_RG_AVALID);
  473. tmp |= P2C_RG_SESSEND;
  474. writel(tmp, com + U3P_U2PHYDTM1);
  475. if (tphy->pdata->avoid_rx_sen_degradation && index) {
  476. tmp = readl(com + U3P_U2PHYDTM0);
  477. tmp &= ~(P2C_RG_SUSPENDM | P2C_FORCE_SUSPENDM);
  478. writel(tmp, com + U3P_U2PHYDTM0);
  479. tmp = readl(com + U3D_U2PHYDCR0);
  480. tmp &= ~P2C_RG_SIF_U2PLL_FORCE_ON;
  481. writel(tmp, com + U3D_U2PHYDCR0);
  482. }
  483. dev_dbg(tphy->dev, "%s(%d)\n", __func__, index);
  484. }
  485. static void u2_phy_instance_exit(struct mtk_tphy *tphy,
  486. struct mtk_phy_instance *instance)
  487. {
  488. struct u2phy_banks *u2_banks = &instance->u2_banks;
  489. void __iomem *com = u2_banks->com;
  490. u32 index = instance->index;
  491. u32 tmp;
  492. if (tphy->pdata->avoid_rx_sen_degradation && index) {
  493. tmp = readl(com + U3D_U2PHYDCR0);
  494. tmp &= ~P2C_RG_SIF_U2PLL_FORCE_ON;
  495. writel(tmp, com + U3D_U2PHYDCR0);
  496. tmp = readl(com + U3P_U2PHYDTM0);
  497. tmp &= ~P2C_FORCE_SUSPENDM;
  498. writel(tmp, com + U3P_U2PHYDTM0);
  499. }
  500. }
  501. static void u2_phy_instance_set_mode(struct mtk_tphy *tphy,
  502. struct mtk_phy_instance *instance,
  503. enum phy_mode mode)
  504. {
  505. struct u2phy_banks *u2_banks = &instance->u2_banks;
  506. u32 tmp;
  507. tmp = readl(u2_banks->com + U3P_U2PHYDTM1);
  508. switch (mode) {
  509. case PHY_MODE_USB_DEVICE:
  510. tmp |= P2C_FORCE_IDDIG | P2C_RG_IDDIG;
  511. break;
  512. case PHY_MODE_USB_HOST:
  513. tmp |= P2C_FORCE_IDDIG;
  514. tmp &= ~P2C_RG_IDDIG;
  515. break;
  516. case PHY_MODE_USB_OTG:
  517. tmp &= ~(P2C_FORCE_IDDIG | P2C_RG_IDDIG);
  518. break;
  519. default:
  520. return;
  521. }
  522. writel(tmp, u2_banks->com + U3P_U2PHYDTM1);
  523. }
  524. static void pcie_phy_instance_init(struct mtk_tphy *tphy,
  525. struct mtk_phy_instance *instance)
  526. {
  527. struct u3phy_banks *u3_banks = &instance->u3_banks;
  528. u32 tmp;
  529. if (tphy->pdata->version != MTK_PHY_V1)
  530. return;
  531. tmp = readl(u3_banks->phya + U3P_U3_PHYA_DA_REG0);
  532. tmp &= ~(P3A_RG_XTAL_EXT_PE1H | P3A_RG_XTAL_EXT_PE2H);
  533. tmp |= P3A_RG_XTAL_EXT_PE1H_VAL(0x2) | P3A_RG_XTAL_EXT_PE2H_VAL(0x2);
  534. writel(tmp, u3_banks->phya + U3P_U3_PHYA_DA_REG0);
  535. /* ref clk drive */
  536. tmp = readl(u3_banks->phya + U3P_U3_PHYA_REG1);
  537. tmp &= ~P3A_RG_CLKDRV_AMP;
  538. tmp |= P3A_RG_CLKDRV_AMP_VAL(0x4);
  539. writel(tmp, u3_banks->phya + U3P_U3_PHYA_REG1);
  540. tmp = readl(u3_banks->phya + U3P_U3_PHYA_REG0);
  541. tmp &= ~P3A_RG_CLKDRV_OFF;
  542. tmp |= P3A_RG_CLKDRV_OFF_VAL(0x1);
  543. writel(tmp, u3_banks->phya + U3P_U3_PHYA_REG0);
  544. /* SSC delta -5000ppm */
  545. tmp = readl(u3_banks->phya + U3P_U3_PHYA_DA_REG20);
  546. tmp &= ~P3A_RG_PLL_DELTA1_PE2H;
  547. tmp |= P3A_RG_PLL_DELTA1_PE2H_VAL(0x3c);
  548. writel(tmp, u3_banks->phya + U3P_U3_PHYA_DA_REG20);
  549. tmp = readl(u3_banks->phya + U3P_U3_PHYA_DA_REG25);
  550. tmp &= ~P3A_RG_PLL_DELTA_PE2H;
  551. tmp |= P3A_RG_PLL_DELTA_PE2H_VAL(0x36);
  552. writel(tmp, u3_banks->phya + U3P_U3_PHYA_DA_REG25);
  553. /* change pll BW 0.6M */
  554. tmp = readl(u3_banks->phya + U3P_U3_PHYA_DA_REG5);
  555. tmp &= ~(P3A_RG_PLL_BR_PE2H | P3A_RG_PLL_IC_PE2H);
  556. tmp |= P3A_RG_PLL_BR_PE2H_VAL(0x1) | P3A_RG_PLL_IC_PE2H_VAL(0x1);
  557. writel(tmp, u3_banks->phya + U3P_U3_PHYA_DA_REG5);
  558. tmp = readl(u3_banks->phya + U3P_U3_PHYA_DA_REG4);
  559. tmp &= ~(P3A_RG_PLL_DIVEN_PE2H | P3A_RG_PLL_BC_PE2H);
  560. tmp |= P3A_RG_PLL_BC_PE2H_VAL(0x3);
  561. writel(tmp, u3_banks->phya + U3P_U3_PHYA_DA_REG4);
  562. tmp = readl(u3_banks->phya + U3P_U3_PHYA_DA_REG6);
  563. tmp &= ~P3A_RG_PLL_IR_PE2H;
  564. tmp |= P3A_RG_PLL_IR_PE2H_VAL(0x2);
  565. writel(tmp, u3_banks->phya + U3P_U3_PHYA_DA_REG6);
  566. tmp = readl(u3_banks->phya + U3P_U3_PHYA_DA_REG7);
  567. tmp &= ~P3A_RG_PLL_BP_PE2H;
  568. tmp |= P3A_RG_PLL_BP_PE2H_VAL(0xa);
  569. writel(tmp, u3_banks->phya + U3P_U3_PHYA_DA_REG7);
  570. /* Tx Detect Rx Timing: 10us -> 5us */
  571. tmp = readl(u3_banks->phyd + U3P_U3_PHYD_RXDET1);
  572. tmp &= ~P3D_RG_RXDET_STB2_SET;
  573. tmp |= P3D_RG_RXDET_STB2_SET_VAL(0x10);
  574. writel(tmp, u3_banks->phyd + U3P_U3_PHYD_RXDET1);
  575. tmp = readl(u3_banks->phyd + U3P_U3_PHYD_RXDET2);
  576. tmp &= ~P3D_RG_RXDET_STB2_SET_P3;
  577. tmp |= P3D_RG_RXDET_STB2_SET_P3_VAL(0x10);
  578. writel(tmp, u3_banks->phyd + U3P_U3_PHYD_RXDET2);
  579. /* wait for PCIe subsys register to active */
  580. usleep_range(2500, 3000);
  581. dev_dbg(tphy->dev, "%s(%d)\n", __func__, instance->index);
  582. }
  583. static void pcie_phy_instance_power_on(struct mtk_tphy *tphy,
  584. struct mtk_phy_instance *instance)
  585. {
  586. struct u3phy_banks *bank = &instance->u3_banks;
  587. u32 tmp;
  588. tmp = readl(bank->chip + U3P_U3_CHIP_GPIO_CTLD);
  589. tmp &= ~(P3C_FORCE_IP_SW_RST | P3C_REG_IP_SW_RST);
  590. writel(tmp, bank->chip + U3P_U3_CHIP_GPIO_CTLD);
  591. tmp = readl(bank->chip + U3P_U3_CHIP_GPIO_CTLE);
  592. tmp &= ~(P3C_RG_SWRST_U3_PHYD_FORCE_EN | P3C_RG_SWRST_U3_PHYD);
  593. writel(tmp, bank->chip + U3P_U3_CHIP_GPIO_CTLE);
  594. }
  595. static void pcie_phy_instance_power_off(struct mtk_tphy *tphy,
  596. struct mtk_phy_instance *instance)
  597. {
  598. struct u3phy_banks *bank = &instance->u3_banks;
  599. u32 tmp;
  600. tmp = readl(bank->chip + U3P_U3_CHIP_GPIO_CTLD);
  601. tmp |= P3C_FORCE_IP_SW_RST | P3C_REG_IP_SW_RST;
  602. writel(tmp, bank->chip + U3P_U3_CHIP_GPIO_CTLD);
  603. tmp = readl(bank->chip + U3P_U3_CHIP_GPIO_CTLE);
  604. tmp |= P3C_RG_SWRST_U3_PHYD_FORCE_EN | P3C_RG_SWRST_U3_PHYD;
  605. writel(tmp, bank->chip + U3P_U3_CHIP_GPIO_CTLE);
  606. }
  607. static void sata_phy_instance_init(struct mtk_tphy *tphy,
  608. struct mtk_phy_instance *instance)
  609. {
  610. struct u3phy_banks *u3_banks = &instance->u3_banks;
  611. void __iomem *phyd = u3_banks->phyd;
  612. u32 tmp;
  613. /* charge current adjustment */
  614. tmp = readl(phyd + ANA_RG_CTRL_SIGNAL6);
  615. tmp &= ~(RG_CDR_BIRLTR_GEN1_MSK | RG_CDR_BC_GEN1_MSK);
  616. tmp |= RG_CDR_BIRLTR_GEN1_VAL(0x6) | RG_CDR_BC_GEN1_VAL(0x1a);
  617. writel(tmp, phyd + ANA_RG_CTRL_SIGNAL6);
  618. tmp = readl(phyd + ANA_EQ_EYE_CTRL_SIGNAL4);
  619. tmp &= ~RG_CDR_BIRLTD0_GEN1_MSK;
  620. tmp |= RG_CDR_BIRLTD0_GEN1_VAL(0x18);
  621. writel(tmp, phyd + ANA_EQ_EYE_CTRL_SIGNAL4);
  622. tmp = readl(phyd + ANA_EQ_EYE_CTRL_SIGNAL5);
  623. tmp &= ~RG_CDR_BIRLTD0_GEN3_MSK;
  624. tmp |= RG_CDR_BIRLTD0_GEN3_VAL(0x06);
  625. writel(tmp, phyd + ANA_EQ_EYE_CTRL_SIGNAL5);
  626. tmp = readl(phyd + ANA_RG_CTRL_SIGNAL4);
  627. tmp &= ~(RG_CDR_BICLTR_GEN1_MSK | RG_CDR_BR_GEN2_MSK);
  628. tmp |= RG_CDR_BICLTR_GEN1_VAL(0x0c) | RG_CDR_BR_GEN2_VAL(0x07);
  629. writel(tmp, phyd + ANA_RG_CTRL_SIGNAL4);
  630. tmp = readl(phyd + PHYD_CTRL_SIGNAL_MODE4);
  631. tmp &= ~(RG_CDR_BICLTD0_GEN1_MSK | RG_CDR_BICLTD1_GEN1_MSK);
  632. tmp |= RG_CDR_BICLTD0_GEN1_VAL(0x08) | RG_CDR_BICLTD1_GEN1_VAL(0x02);
  633. writel(tmp, phyd + PHYD_CTRL_SIGNAL_MODE4);
  634. tmp = readl(phyd + PHYD_DESIGN_OPTION2);
  635. tmp &= ~RG_LOCK_CNT_SEL_MSK;
  636. tmp |= RG_LOCK_CNT_SEL_VAL(0x02);
  637. writel(tmp, phyd + PHYD_DESIGN_OPTION2);
  638. tmp = readl(phyd + PHYD_DESIGN_OPTION9);
  639. tmp &= ~(RG_T2_MIN_MSK | RG_TG_MIN_MSK |
  640. RG_T2_MAX_MSK | RG_TG_MAX_MSK);
  641. tmp |= RG_T2_MIN_VAL(0x12) | RG_TG_MIN_VAL(0x04) |
  642. RG_T2_MAX_VAL(0x31) | RG_TG_MAX_VAL(0x0e);
  643. writel(tmp, phyd + PHYD_DESIGN_OPTION9);
  644. tmp = readl(phyd + ANA_RG_CTRL_SIGNAL1);
  645. tmp &= ~RG_IDRV_0DB_GEN1_MSK;
  646. tmp |= RG_IDRV_0DB_GEN1_VAL(0x20);
  647. writel(tmp, phyd + ANA_RG_CTRL_SIGNAL1);
  648. tmp = readl(phyd + ANA_EQ_EYE_CTRL_SIGNAL1);
  649. tmp &= ~RG_EQ_DLEQ_LFI_GEN1_MSK;
  650. tmp |= RG_EQ_DLEQ_LFI_GEN1_VAL(0x03);
  651. writel(tmp, phyd + ANA_EQ_EYE_CTRL_SIGNAL1);
  652. dev_dbg(tphy->dev, "%s(%d)\n", __func__, instance->index);
  653. }
  654. static void phy_v1_banks_init(struct mtk_tphy *tphy,
  655. struct mtk_phy_instance *instance)
  656. {
  657. struct u2phy_banks *u2_banks = &instance->u2_banks;
  658. struct u3phy_banks *u3_banks = &instance->u3_banks;
  659. switch (instance->type) {
  660. case PHY_TYPE_USB2:
  661. u2_banks->misc = NULL;
  662. u2_banks->fmreg = tphy->sif_base + SSUSB_SIFSLV_V1_U2FREQ;
  663. u2_banks->com = instance->port_base + SSUSB_SIFSLV_V1_U2PHY_COM;
  664. break;
  665. case PHY_TYPE_USB3:
  666. case PHY_TYPE_PCIE:
  667. u3_banks->spllc = tphy->sif_base + SSUSB_SIFSLV_V1_SPLLC;
  668. u3_banks->chip = tphy->sif_base + SSUSB_SIFSLV_V1_CHIP;
  669. u3_banks->phyd = instance->port_base + SSUSB_SIFSLV_V1_U3PHYD;
  670. u3_banks->phya = instance->port_base + SSUSB_SIFSLV_V1_U3PHYA;
  671. break;
  672. case PHY_TYPE_SATA:
  673. u3_banks->phyd = instance->port_base + SSUSB_SIFSLV_V1_U3PHYD;
  674. break;
  675. default:
  676. dev_err(tphy->dev, "incompatible PHY type\n");
  677. return;
  678. }
  679. }
  680. static void phy_v2_banks_init(struct mtk_tphy *tphy,
  681. struct mtk_phy_instance *instance)
  682. {
  683. struct u2phy_banks *u2_banks = &instance->u2_banks;
  684. struct u3phy_banks *u3_banks = &instance->u3_banks;
  685. switch (instance->type) {
  686. case PHY_TYPE_USB2:
  687. u2_banks->misc = instance->port_base + SSUSB_SIFSLV_V2_MISC;
  688. u2_banks->fmreg = instance->port_base + SSUSB_SIFSLV_V2_U2FREQ;
  689. u2_banks->com = instance->port_base + SSUSB_SIFSLV_V2_U2PHY_COM;
  690. break;
  691. case PHY_TYPE_USB3:
  692. case PHY_TYPE_PCIE:
  693. u3_banks->spllc = instance->port_base + SSUSB_SIFSLV_V2_SPLLC;
  694. u3_banks->chip = instance->port_base + SSUSB_SIFSLV_V2_CHIP;
  695. u3_banks->phyd = instance->port_base + SSUSB_SIFSLV_V2_U3PHYD;
  696. u3_banks->phya = instance->port_base + SSUSB_SIFSLV_V2_U3PHYA;
  697. break;
  698. default:
  699. dev_err(tphy->dev, "incompatible PHY type\n");
  700. return;
  701. }
  702. }
  703. static void phy_parse_property(struct mtk_tphy *tphy,
  704. struct mtk_phy_instance *instance)
  705. {
  706. struct device *dev = &instance->phy->dev;
  707. if (instance->type != PHY_TYPE_USB2)
  708. return;
  709. instance->bc12_en = device_property_read_bool(dev, "mediatek,bc12");
  710. device_property_read_u32(dev, "mediatek,eye-src",
  711. &instance->eye_src);
  712. device_property_read_u32(dev, "mediatek,eye-vrt",
  713. &instance->eye_vrt);
  714. device_property_read_u32(dev, "mediatek,eye-term",
  715. &instance->eye_term);
  716. device_property_read_u32(dev, "mediatek,intr",
  717. &instance->intr);
  718. device_property_read_u32(dev, "mediatek,discth",
  719. &instance->discth);
  720. dev_dbg(dev, "bc12:%d, src:%d, vrt:%d, term:%d, intr:%d, disc:%d\n",
  721. instance->bc12_en, instance->eye_src,
  722. instance->eye_vrt, instance->eye_term,
  723. instance->intr, instance->discth);
  724. }
  725. static void u2_phy_props_set(struct mtk_tphy *tphy,
  726. struct mtk_phy_instance *instance)
  727. {
  728. struct u2phy_banks *u2_banks = &instance->u2_banks;
  729. void __iomem *com = u2_banks->com;
  730. u32 tmp;
  731. if (instance->bc12_en) {
  732. tmp = readl(com + U3P_U2PHYBC12C);
  733. tmp |= P2C_RG_CHGDT_EN; /* BC1.2 path Enable */
  734. writel(tmp, com + U3P_U2PHYBC12C);
  735. }
  736. if (instance->eye_src) {
  737. tmp = readl(com + U3P_USBPHYACR5);
  738. tmp &= ~PA5_RG_U2_HSTX_SRCTRL;
  739. tmp |= PA5_RG_U2_HSTX_SRCTRL_VAL(instance->eye_src);
  740. writel(tmp, com + U3P_USBPHYACR5);
  741. }
  742. if (instance->eye_vrt) {
  743. tmp = readl(com + U3P_USBPHYACR1);
  744. tmp &= ~PA1_RG_VRT_SEL;
  745. tmp |= PA1_RG_VRT_SEL_VAL(instance->eye_vrt);
  746. writel(tmp, com + U3P_USBPHYACR1);
  747. }
  748. if (instance->eye_term) {
  749. tmp = readl(com + U3P_USBPHYACR1);
  750. tmp &= ~PA1_RG_TERM_SEL;
  751. tmp |= PA1_RG_TERM_SEL_VAL(instance->eye_term);
  752. writel(tmp, com + U3P_USBPHYACR1);
  753. }
  754. if (instance->intr) {
  755. tmp = readl(com + U3P_USBPHYACR1);
  756. tmp &= ~PA1_RG_INTR_CAL;
  757. tmp |= PA1_RG_INTR_CAL_VAL(instance->intr);
  758. writel(tmp, com + U3P_USBPHYACR1);
  759. }
  760. if (instance->discth) {
  761. tmp = readl(com + U3P_USBPHYACR6);
  762. tmp &= ~PA6_RG_U2_DISCTH;
  763. tmp |= PA6_RG_U2_DISCTH_VAL(instance->discth);
  764. writel(tmp, com + U3P_USBPHYACR6);
  765. }
  766. }
  767. static int mtk_phy_init(struct phy *phy)
  768. {
  769. struct mtk_phy_instance *instance = phy_get_drvdata(phy);
  770. struct mtk_tphy *tphy = dev_get_drvdata(phy->dev.parent);
  771. int ret;
  772. ret = clk_prepare_enable(instance->ref_clk);
  773. if (ret) {
  774. dev_err(tphy->dev, "failed to enable ref_clk\n");
  775. return ret;
  776. }
  777. ret = clk_prepare_enable(instance->da_ref_clk);
  778. if (ret) {
  779. dev_err(tphy->dev, "failed to enable da_ref\n");
  780. clk_disable_unprepare(instance->ref_clk);
  781. return ret;
  782. }
  783. switch (instance->type) {
  784. case PHY_TYPE_USB2:
  785. u2_phy_instance_init(tphy, instance);
  786. u2_phy_props_set(tphy, instance);
  787. break;
  788. case PHY_TYPE_USB3:
  789. u3_phy_instance_init(tphy, instance);
  790. break;
  791. case PHY_TYPE_PCIE:
  792. pcie_phy_instance_init(tphy, instance);
  793. break;
  794. case PHY_TYPE_SATA:
  795. sata_phy_instance_init(tphy, instance);
  796. break;
  797. default:
  798. dev_err(tphy->dev, "incompatible PHY type\n");
  799. clk_disable_unprepare(instance->ref_clk);
  800. clk_disable_unprepare(instance->da_ref_clk);
  801. return -EINVAL;
  802. }
  803. return 0;
  804. }
  805. static int mtk_phy_power_on(struct phy *phy)
  806. {
  807. struct mtk_phy_instance *instance = phy_get_drvdata(phy);
  808. struct mtk_tphy *tphy = dev_get_drvdata(phy->dev.parent);
  809. if (instance->type == PHY_TYPE_USB2) {
  810. u2_phy_instance_power_on(tphy, instance);
  811. hs_slew_rate_calibrate(tphy, instance);
  812. } else if (instance->type == PHY_TYPE_PCIE) {
  813. pcie_phy_instance_power_on(tphy, instance);
  814. }
  815. return 0;
  816. }
  817. static int mtk_phy_power_off(struct phy *phy)
  818. {
  819. struct mtk_phy_instance *instance = phy_get_drvdata(phy);
  820. struct mtk_tphy *tphy = dev_get_drvdata(phy->dev.parent);
  821. if (instance->type == PHY_TYPE_USB2)
  822. u2_phy_instance_power_off(tphy, instance);
  823. else if (instance->type == PHY_TYPE_PCIE)
  824. pcie_phy_instance_power_off(tphy, instance);
  825. return 0;
  826. }
  827. static int mtk_phy_exit(struct phy *phy)
  828. {
  829. struct mtk_phy_instance *instance = phy_get_drvdata(phy);
  830. struct mtk_tphy *tphy = dev_get_drvdata(phy->dev.parent);
  831. if (instance->type == PHY_TYPE_USB2)
  832. u2_phy_instance_exit(tphy, instance);
  833. clk_disable_unprepare(instance->ref_clk);
  834. clk_disable_unprepare(instance->da_ref_clk);
  835. return 0;
  836. }
  837. static int mtk_phy_set_mode(struct phy *phy, enum phy_mode mode, int submode)
  838. {
  839. struct mtk_phy_instance *instance = phy_get_drvdata(phy);
  840. struct mtk_tphy *tphy = dev_get_drvdata(phy->dev.parent);
  841. if (instance->type == PHY_TYPE_USB2)
  842. u2_phy_instance_set_mode(tphy, instance, mode);
  843. return 0;
  844. }
  845. static struct phy *mtk_phy_xlate(struct device *dev,
  846. struct of_phandle_args *args)
  847. {
  848. struct mtk_tphy *tphy = dev_get_drvdata(dev);
  849. struct mtk_phy_instance *instance = NULL;
  850. struct device_node *phy_np = args->np;
  851. int index;
  852. if (args->args_count != 1) {
  853. dev_err(dev, "invalid number of cells in 'phy' property\n");
  854. return ERR_PTR(-EINVAL);
  855. }
  856. for (index = 0; index < tphy->nphys; index++)
  857. if (phy_np == tphy->phys[index]->phy->dev.of_node) {
  858. instance = tphy->phys[index];
  859. break;
  860. }
  861. if (!instance) {
  862. dev_err(dev, "failed to find appropriate phy\n");
  863. return ERR_PTR(-EINVAL);
  864. }
  865. instance->type = args->args[0];
  866. if (!(instance->type == PHY_TYPE_USB2 ||
  867. instance->type == PHY_TYPE_USB3 ||
  868. instance->type == PHY_TYPE_PCIE ||
  869. instance->type == PHY_TYPE_SATA)) {
  870. dev_err(dev, "unsupported device type: %d\n", instance->type);
  871. return ERR_PTR(-EINVAL);
  872. }
  873. if (tphy->pdata->version == MTK_PHY_V1) {
  874. phy_v1_banks_init(tphy, instance);
  875. } else if (tphy->pdata->version == MTK_PHY_V2) {
  876. phy_v2_banks_init(tphy, instance);
  877. } else {
  878. dev_err(dev, "phy version is not supported\n");
  879. return ERR_PTR(-EINVAL);
  880. }
  881. phy_parse_property(tphy, instance);
  882. return instance->phy;
  883. }
  884. static const struct phy_ops mtk_tphy_ops = {
  885. .init = mtk_phy_init,
  886. .exit = mtk_phy_exit,
  887. .power_on = mtk_phy_power_on,
  888. .power_off = mtk_phy_power_off,
  889. .set_mode = mtk_phy_set_mode,
  890. .owner = THIS_MODULE,
  891. };
  892. static const struct mtk_phy_pdata tphy_v1_pdata = {
  893. .avoid_rx_sen_degradation = false,
  894. .version = MTK_PHY_V1,
  895. };
  896. static const struct mtk_phy_pdata tphy_v2_pdata = {
  897. .avoid_rx_sen_degradation = false,
  898. .version = MTK_PHY_V2,
  899. };
  900. static const struct mtk_phy_pdata mt8173_pdata = {
  901. .avoid_rx_sen_degradation = true,
  902. .version = MTK_PHY_V1,
  903. };
  904. static const struct of_device_id mtk_tphy_id_table[] = {
  905. { .compatible = "mediatek,mt2701-u3phy", .data = &tphy_v1_pdata },
  906. { .compatible = "mediatek,mt2712-u3phy", .data = &tphy_v2_pdata },
  907. { .compatible = "mediatek,mt8173-u3phy", .data = &mt8173_pdata },
  908. { .compatible = "mediatek,generic-tphy-v1", .data = &tphy_v1_pdata },
  909. { .compatible = "mediatek,generic-tphy-v2", .data = &tphy_v2_pdata },
  910. { },
  911. };
  912. MODULE_DEVICE_TABLE(of, mtk_tphy_id_table);
  913. static int mtk_tphy_probe(struct platform_device *pdev)
  914. {
  915. struct device *dev = &pdev->dev;
  916. struct device_node *np = dev->of_node;
  917. struct device_node *child_np;
  918. struct phy_provider *provider;
  919. struct resource *sif_res;
  920. struct mtk_tphy *tphy;
  921. struct resource res;
  922. int port, retval;
  923. tphy = devm_kzalloc(dev, sizeof(*tphy), GFP_KERNEL);
  924. if (!tphy)
  925. return -ENOMEM;
  926. tphy->pdata = of_device_get_match_data(dev);
  927. if (!tphy->pdata)
  928. return -EINVAL;
  929. tphy->nphys = of_get_child_count(np);
  930. tphy->phys = devm_kcalloc(dev, tphy->nphys,
  931. sizeof(*tphy->phys), GFP_KERNEL);
  932. if (!tphy->phys)
  933. return -ENOMEM;
  934. tphy->dev = dev;
  935. platform_set_drvdata(pdev, tphy);
  936. sif_res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
  937. /* SATA phy of V1 needn't it if not shared with PCIe or USB */
  938. if (sif_res && tphy->pdata->version == MTK_PHY_V1) {
  939. /* get banks shared by multiple phys */
  940. tphy->sif_base = devm_ioremap_resource(dev, sif_res);
  941. if (IS_ERR(tphy->sif_base)) {
  942. dev_err(dev, "failed to remap sif regs\n");
  943. return PTR_ERR(tphy->sif_base);
  944. }
  945. }
  946. tphy->src_ref_clk = U3P_REF_CLK;
  947. tphy->src_coef = U3P_SLEW_RATE_COEF;
  948. /* update parameters of slew rate calibrate if exist */
  949. device_property_read_u32(dev, "mediatek,src-ref-clk-mhz",
  950. &tphy->src_ref_clk);
  951. device_property_read_u32(dev, "mediatek,src-coef", &tphy->src_coef);
  952. port = 0;
  953. for_each_child_of_node(np, child_np) {
  954. struct mtk_phy_instance *instance;
  955. struct phy *phy;
  956. instance = devm_kzalloc(dev, sizeof(*instance), GFP_KERNEL);
  957. if (!instance) {
  958. retval = -ENOMEM;
  959. goto put_child;
  960. }
  961. tphy->phys[port] = instance;
  962. phy = devm_phy_create(dev, child_np, &mtk_tphy_ops);
  963. if (IS_ERR(phy)) {
  964. dev_err(dev, "failed to create phy\n");
  965. retval = PTR_ERR(phy);
  966. goto put_child;
  967. }
  968. retval = of_address_to_resource(child_np, 0, &res);
  969. if (retval) {
  970. dev_err(dev, "failed to get address resource(id-%d)\n",
  971. port);
  972. goto put_child;
  973. }
  974. instance->port_base = devm_ioremap_resource(&phy->dev, &res);
  975. if (IS_ERR(instance->port_base)) {
  976. dev_err(dev, "failed to remap phy regs\n");
  977. retval = PTR_ERR(instance->port_base);
  978. goto put_child;
  979. }
  980. instance->phy = phy;
  981. instance->index = port;
  982. phy_set_drvdata(phy, instance);
  983. port++;
  984. instance->ref_clk = devm_clk_get_optional(&phy->dev, "ref");
  985. if (IS_ERR(instance->ref_clk)) {
  986. dev_err(dev, "failed to get ref_clk(id-%d)\n", port);
  987. retval = PTR_ERR(instance->ref_clk);
  988. goto put_child;
  989. }
  990. instance->da_ref_clk =
  991. devm_clk_get_optional(&phy->dev, "da_ref");
  992. if (IS_ERR(instance->da_ref_clk)) {
  993. dev_err(dev, "failed to get da_ref_clk(id-%d)\n", port);
  994. retval = PTR_ERR(instance->da_ref_clk);
  995. goto put_child;
  996. }
  997. }
  998. provider = devm_of_phy_provider_register(dev, mtk_phy_xlate);
  999. return PTR_ERR_OR_ZERO(provider);
  1000. put_child:
  1001. of_node_put(child_np);
  1002. return retval;
  1003. }
  1004. static struct platform_driver mtk_tphy_driver = {
  1005. .probe = mtk_tphy_probe,
  1006. .driver = {
  1007. .name = "mtk-tphy",
  1008. .of_match_table = mtk_tphy_id_table,
  1009. },
  1010. };
  1011. module_platform_driver(mtk_tphy_driver);
  1012. MODULE_AUTHOR("Chunfeng Yun <chunfeng.yun@mediatek.com>");
  1013. MODULE_DESCRIPTION("MediaTek T-PHY driver");
  1014. MODULE_LICENSE("GPL v2");