phy-cadence-torrent.c 114 KB

1234567891011121314151617181920212223242526272829303132333435363738394041424344454647484950515253545556575859606162636465666768697071727374757677787980818283848586878889909192939495969798991001011021031041051061071081091101111121131141151161171181191201211221231241251261271281291301311321331341351361371381391401411421431441451461471481491501511521531541551561571581591601611621631641651661671681691701711721731741751761771781791801811821831841851861871881891901911921931941951961971981992002012022032042052062072082092102112122132142152162172182192202212222232242252262272282292302312322332342352362372382392402412422432442452462472482492502512522532542552562572582592602612622632642652662672682692702712722732742752762772782792802812822832842852862872882892902912922932942952962972982993003013023033043053063073083093103113123133143153163173183193203213223233243253263273283293303313323333343353363373383393403413423433443453463473483493503513523533543553563573583593603613623633643653663673683693703713723733743753763773783793803813823833843853863873883893903913923933943953963973983994004014024034044054064074084094104114124134144154164174184194204214224234244254264274284294304314324334344354364374384394404414424434444454464474484494504514524534544554564574584594604614624634644654664674684694704714724734744754764774784794804814824834844854864874884894904914924934944954964974984995005015025035045055065075085095105115125135145155165175185195205215225235245255265275285295305315325335345355365375385395405415425435445455465475485495505515525535545555565575585595605615625635645655665675685695705715725735745755765775785795805815825835845855865875885895905915925935945955965975985996006016026036046056066076086096106116126136146156166176186196206216226236246256266276286296306316326336346356366376386396406416426436446456466476486496506516526536546556566576586596606616626636646656666676686696706716726736746756766776786796806816826836846856866876886896906916926936946956966976986997007017027037047057067077087097107117127137147157167177187197207217227237247257267277287297307317327337347357367377387397407417427437447457467477487497507517527537547557567577587597607617627637647657667677687697707717727737747757767777787797807817827837847857867877887897907917927937947957967977987998008018028038048058068078088098108118128138148158168178188198208218228238248258268278288298308318328338348358368378388398408418428438448458468478488498508518528538548558568578588598608618628638648658668678688698708718728738748758768778788798808818828838848858868878888898908918928938948958968978988999009019029039049059069079089099109119129139149159169179189199209219229239249259269279289299309319329339349359369379389399409419429439449459469479489499509519529539549559569579589599609619629639649659669679689699709719729739749759769779789799809819829839849859869879889899909919929939949959969979989991000100110021003100410051006100710081009101010111012101310141015101610171018101910201021102210231024102510261027102810291030103110321033103410351036103710381039104010411042104310441045104610471048104910501051105210531054105510561057105810591060106110621063106410651066106710681069107010711072107310741075107610771078107910801081108210831084108510861087108810891090109110921093109410951096109710981099110011011102110311041105110611071108110911101111111211131114111511161117111811191120112111221123112411251126112711281129113011311132113311341135113611371138113911401141114211431144114511461147114811491150115111521153115411551156115711581159116011611162116311641165116611671168116911701171117211731174117511761177117811791180118111821183118411851186118711881189119011911192119311941195119611971198119912001201120212031204120512061207120812091210121112121213121412151216121712181219122012211222122312241225122612271228122912301231123212331234123512361237123812391240124112421243124412451246124712481249125012511252125312541255125612571258125912601261126212631264126512661267126812691270127112721273127412751276127712781279128012811282128312841285128612871288128912901291129212931294129512961297129812991300130113021303130413051306130713081309131013111312131313141315131613171318131913201321132213231324132513261327132813291330133113321333133413351336133713381339134013411342134313441345134613471348134913501351135213531354135513561357135813591360136113621363136413651366136713681369137013711372137313741375137613771378137913801381138213831384138513861387138813891390139113921393139413951396139713981399140014011402140314041405140614071408140914101411141214131414141514161417141814191420142114221423142414251426142714281429143014311432143314341435143614371438143914401441144214431444144514461447144814491450145114521453145414551456145714581459146014611462146314641465146614671468146914701471147214731474147514761477147814791480148114821483148414851486148714881489149014911492149314941495149614971498149915001501150215031504150515061507150815091510151115121513151415151516151715181519152015211522152315241525152615271528152915301531153215331534153515361537153815391540154115421543154415451546154715481549155015511552155315541555155615571558155915601561156215631564156515661567156815691570157115721573157415751576157715781579158015811582158315841585158615871588158915901591159215931594159515961597159815991600160116021603160416051606160716081609161016111612161316141615161616171618161916201621162216231624162516261627162816291630163116321633163416351636163716381639164016411642164316441645164616471648164916501651165216531654165516561657165816591660166116621663166416651666166716681669167016711672167316741675167616771678167916801681168216831684168516861687168816891690169116921693169416951696169716981699170017011702170317041705170617071708170917101711171217131714171517161717171817191720172117221723172417251726172717281729173017311732173317341735173617371738173917401741174217431744174517461747174817491750175117521753175417551756175717581759176017611762176317641765176617671768176917701771177217731774177517761777177817791780178117821783178417851786178717881789179017911792179317941795179617971798179918001801180218031804180518061807180818091810181118121813181418151816181718181819182018211822182318241825182618271828182918301831183218331834183518361837183818391840184118421843184418451846184718481849185018511852185318541855185618571858185918601861186218631864186518661867186818691870187118721873187418751876187718781879188018811882188318841885188618871888188918901891189218931894189518961897189818991900190119021903190419051906190719081909191019111912191319141915191619171918191919201921192219231924192519261927192819291930193119321933193419351936193719381939194019411942194319441945194619471948194919501951195219531954195519561957195819591960196119621963196419651966196719681969197019711972197319741975197619771978197919801981198219831984198519861987198819891990199119921993199419951996199719981999200020012002200320042005200620072008200920102011201220132014201520162017201820192020202120222023202420252026202720282029203020312032203320342035203620372038203920402041204220432044204520462047204820492050205120522053205420552056205720582059206020612062206320642065206620672068206920702071207220732074207520762077207820792080208120822083208420852086208720882089209020912092209320942095209620972098209921002101210221032104210521062107210821092110211121122113211421152116211721182119212021212122212321242125212621272128212921302131213221332134213521362137213821392140214121422143214421452146214721482149215021512152215321542155215621572158215921602161216221632164216521662167216821692170217121722173217421752176217721782179218021812182218321842185218621872188218921902191219221932194219521962197219821992200220122022203220422052206220722082209221022112212221322142215221622172218221922202221222222232224222522262227222822292230223122322233223422352236223722382239224022412242224322442245224622472248224922502251225222532254225522562257225822592260226122622263226422652266226722682269227022712272227322742275227622772278227922802281228222832284228522862287228822892290229122922293229422952296229722982299230023012302230323042305230623072308230923102311231223132314231523162317231823192320232123222323232423252326232723282329233023312332233323342335233623372338233923402341234223432344234523462347234823492350235123522353235423552356235723582359236023612362236323642365236623672368236923702371237223732374237523762377237823792380238123822383238423852386238723882389239023912392239323942395239623972398239924002401240224032404240524062407240824092410241124122413241424152416241724182419242024212422242324242425242624272428242924302431243224332434243524362437243824392440244124422443244424452446244724482449245024512452245324542455245624572458245924602461246224632464246524662467246824692470247124722473247424752476247724782479248024812482248324842485248624872488248924902491249224932494249524962497249824992500250125022503250425052506250725082509251025112512251325142515251625172518251925202521252225232524252525262527252825292530253125322533253425352536253725382539254025412542254325442545254625472548254925502551255225532554255525562557255825592560256125622563256425652566256725682569257025712572257325742575257625772578257925802581258225832584258525862587258825892590259125922593259425952596259725982599260026012602260326042605260626072608260926102611261226132614261526162617261826192620262126222623262426252626262726282629263026312632263326342635263626372638263926402641264226432644264526462647264826492650265126522653265426552656265726582659266026612662266326642665266626672668266926702671267226732674267526762677267826792680268126822683268426852686268726882689269026912692269326942695269626972698269927002701270227032704270527062707270827092710271127122713271427152716271727182719272027212722272327242725272627272728272927302731273227332734273527362737273827392740274127422743274427452746274727482749275027512752275327542755275627572758275927602761276227632764276527662767276827692770277127722773277427752776277727782779278027812782278327842785278627872788278927902791279227932794279527962797279827992800280128022803280428052806280728082809281028112812281328142815281628172818281928202821282228232824282528262827282828292830283128322833283428352836283728382839284028412842284328442845284628472848284928502851285228532854285528562857285828592860286128622863286428652866286728682869287028712872287328742875287628772878287928802881288228832884288528862887288828892890289128922893289428952896289728982899290029012902290329042905290629072908290929102911291229132914291529162917291829192920292129222923292429252926292729282929293029312932293329342935293629372938293929402941294229432944294529462947294829492950295129522953295429552956295729582959296029612962296329642965296629672968296929702971297229732974297529762977297829792980298129822983298429852986298729882989299029912992299329942995299629972998299930003001300230033004300530063007300830093010301130123013301430153016301730183019302030213022302330243025302630273028302930303031303230333034303530363037303830393040304130423043304430453046304730483049305030513052305330543055305630573058305930603061306230633064306530663067306830693070307130723073307430753076307730783079308030813082308330843085308630873088308930903091309230933094309530963097309830993100310131023103310431053106310731083109311031113112311331143115311631173118311931203121312231233124312531263127312831293130313131323133313431353136313731383139314031413142314331443145314631473148314931503151315231533154315531563157315831593160316131623163316431653166316731683169317031713172317331743175317631773178317931803181318231833184318531863187318831893190319131923193319431953196319731983199320032013202320332043205320632073208320932103211321232133214321532163217321832193220322132223223322432253226322732283229323032313232323332343235323632373238323932403241324232433244324532463247324832493250325132523253325432553256325732583259326032613262326332643265326632673268326932703271327232733274327532763277327832793280328132823283328432853286328732883289329032913292329332943295329632973298329933003301330233033304330533063307330833093310331133123313331433153316331733183319332033213322332333243325332633273328332933303331333233333334333533363337333833393340334133423343334433453346334733483349335033513352335333543355335633573358335933603361336233633364336533663367336833693370337133723373337433753376337733783379338033813382338333843385338633873388338933903391339233933394339533963397339833993400340134023403340434053406340734083409341034113412341334143415341634173418341934203421342234233424342534263427342834293430343134323433343434353436343734383439344034413442344334443445344634473448344934503451345234533454345534563457345834593460346134623463346434653466346734683469347034713472347334743475347634773478347934803481348234833484348534863487348834893490349134923493349434953496349734983499350035013502350335043505350635073508350935103511351235133514351535163517351835193520352135223523352435253526352735283529353035313532353335343535353635373538353935403541354235433544354535463547354835493550355135523553355435553556355735583559356035613562356335643565356635673568356935703571357235733574357535763577357835793580358135823583358435853586358735883589359035913592359335943595359635973598359936003601360236033604360536063607360836093610361136123613361436153616361736183619362036213622362336243625362636273628362936303631363236333634363536363637363836393640364136423643364436453646364736483649365036513652365336543655365636573658365936603661366236633664366536663667366836693670367136723673367436753676367736783679368036813682368336843685368636873688368936903691369236933694369536963697369836993700370137023703370437053706370737083709371037113712371337143715371637173718371937203721372237233724372537263727372837293730373137323733373437353736373737383739374037413742374337443745374637473748374937503751375237533754375537563757375837593760376137623763376437653766376737683769377037713772377337743775377637773778377937803781378237833784378537863787378837893790379137923793379437953796379737983799380038013802380338043805380638073808380938103811381238133814381538163817381838193820382138223823382438253826382738283829383038313832383338343835383638373838383938403841384238433844384538463847384838493850385138523853385438553856385738583859386038613862
  1. // SPDX-License-Identifier: GPL-2.0-only
  2. /*
  3. * Cadence Torrent SD0801 PHY driver.
  4. *
  5. * Copyright 2018 Cadence Design Systems, Inc.
  6. *
  7. */
  8. #include <dt-bindings/phy/phy.h>
  9. #include <linux/clk.h>
  10. #include <linux/delay.h>
  11. #include <linux/err.h>
  12. #include <linux/io.h>
  13. #include <linux/iopoll.h>
  14. #include <linux/kernel.h>
  15. #include <linux/module.h>
  16. #include <linux/of.h>
  17. #include <linux/of_address.h>
  18. #include <linux/of_device.h>
  19. #include <linux/phy/phy.h>
  20. #include <linux/platform_device.h>
  21. #include <linux/reset.h>
  22. #include <linux/regmap.h>
  23. #define REF_CLK_19_2MHz 19200000
  24. #define REF_CLK_25MHz 25000000
  25. #define MAX_NUM_LANES 4
  26. #define DEFAULT_MAX_BIT_RATE 8100 /* in Mbps */
  27. #define NUM_SSC_MODE 3
  28. #define NUM_PHY_TYPE 6
  29. #define POLL_TIMEOUT_US 5000
  30. #define PLL_LOCK_TIMEOUT 100000
  31. #define TORRENT_COMMON_CDB_OFFSET 0x0
  32. #define TORRENT_TX_LANE_CDB_OFFSET(ln, block_offset, reg_offset) \
  33. ((0x4000 << (block_offset)) + \
  34. (((ln) << 9) << (reg_offset)))
  35. #define TORRENT_RX_LANE_CDB_OFFSET(ln, block_offset, reg_offset) \
  36. ((0x8000 << (block_offset)) + \
  37. (((ln) << 9) << (reg_offset)))
  38. #define TORRENT_PHY_PCS_COMMON_OFFSET(block_offset) \
  39. (0xC000 << (block_offset))
  40. #define TORRENT_PHY_PMA_COMMON_OFFSET(block_offset) \
  41. (0xE000 << (block_offset))
  42. #define TORRENT_DPTX_PHY_OFFSET 0x0
  43. /*
  44. * register offsets from DPTX PHY register block base (i.e MHDP
  45. * register base + 0x30a00)
  46. */
  47. #define PHY_AUX_CTRL 0x04
  48. #define PHY_RESET 0x20
  49. #define PMA_TX_ELEC_IDLE_MASK 0xF0U
  50. #define PMA_TX_ELEC_IDLE_SHIFT 4
  51. #define PHY_L00_RESET_N_MASK 0x01U
  52. #define PHY_PMA_XCVR_PLLCLK_EN 0x24
  53. #define PHY_PMA_XCVR_PLLCLK_EN_ACK 0x28
  54. #define PHY_PMA_XCVR_POWER_STATE_REQ 0x2c
  55. #define PHY_POWER_STATE_LN_0 0x0000
  56. #define PHY_POWER_STATE_LN_1 0x0008
  57. #define PHY_POWER_STATE_LN_2 0x0010
  58. #define PHY_POWER_STATE_LN_3 0x0018
  59. #define PMA_XCVR_POWER_STATE_REQ_LN_MASK 0x3FU
  60. #define PHY_PMA_XCVR_POWER_STATE_ACK 0x30
  61. #define PHY_PMA_CMN_READY 0x34
  62. /*
  63. * register offsets from SD0801 PHY register block base (i.e MHDP
  64. * register base + 0x500000)
  65. */
  66. #define CMN_SSM_BANDGAP_TMR 0x0021U
  67. #define CMN_SSM_BIAS_TMR 0x0022U
  68. #define CMN_PLLSM0_PLLPRE_TMR 0x002AU
  69. #define CMN_PLLSM0_PLLLOCK_TMR 0x002CU
  70. #define CMN_PLLSM1_PLLPRE_TMR 0x0032U
  71. #define CMN_PLLSM1_PLLLOCK_TMR 0x0034U
  72. #define CMN_CDIAG_CDB_PWRI_OVRD 0x0041U
  73. #define CMN_CDIAG_XCVRC_PWRI_OVRD 0x0047U
  74. #define CMN_BGCAL_INIT_TMR 0x0064U
  75. #define CMN_BGCAL_ITER_TMR 0x0065U
  76. #define CMN_IBCAL_INIT_TMR 0x0074U
  77. #define CMN_PLL0_VCOCAL_TCTRL 0x0082U
  78. #define CMN_PLL0_VCOCAL_INIT_TMR 0x0084U
  79. #define CMN_PLL0_VCOCAL_ITER_TMR 0x0085U
  80. #define CMN_PLL0_VCOCAL_REFTIM_START 0x0086U
  81. #define CMN_PLL0_VCOCAL_PLLCNT_START 0x0088U
  82. #define CMN_PLL0_INTDIV_M0 0x0090U
  83. #define CMN_PLL0_FRACDIVL_M0 0x0091U
  84. #define CMN_PLL0_FRACDIVH_M0 0x0092U
  85. #define CMN_PLL0_HIGH_THR_M0 0x0093U
  86. #define CMN_PLL0_DSM_DIAG_M0 0x0094U
  87. #define CMN_PLL0_SS_CTRL1_M0 0x0098U
  88. #define CMN_PLL0_SS_CTRL2_M0 0x0099U
  89. #define CMN_PLL0_SS_CTRL3_M0 0x009AU
  90. #define CMN_PLL0_SS_CTRL4_M0 0x009BU
  91. #define CMN_PLL0_LOCK_REFCNT_START 0x009CU
  92. #define CMN_PLL0_LOCK_PLLCNT_START 0x009EU
  93. #define CMN_PLL0_LOCK_PLLCNT_THR 0x009FU
  94. #define CMN_PLL0_INTDIV_M1 0x00A0U
  95. #define CMN_PLL0_FRACDIVH_M1 0x00A2U
  96. #define CMN_PLL0_HIGH_THR_M1 0x00A3U
  97. #define CMN_PLL0_DSM_DIAG_M1 0x00A4U
  98. #define CMN_PLL0_SS_CTRL1_M1 0x00A8U
  99. #define CMN_PLL0_SS_CTRL2_M1 0x00A9U
  100. #define CMN_PLL0_SS_CTRL3_M1 0x00AAU
  101. #define CMN_PLL0_SS_CTRL4_M1 0x00ABU
  102. #define CMN_PLL1_VCOCAL_TCTRL 0x00C2U
  103. #define CMN_PLL1_VCOCAL_INIT_TMR 0x00C4U
  104. #define CMN_PLL1_VCOCAL_ITER_TMR 0x00C5U
  105. #define CMN_PLL1_VCOCAL_REFTIM_START 0x00C6U
  106. #define CMN_PLL1_VCOCAL_PLLCNT_START 0x00C8U
  107. #define CMN_PLL1_INTDIV_M0 0x00D0U
  108. #define CMN_PLL1_FRACDIVL_M0 0x00D1U
  109. #define CMN_PLL1_FRACDIVH_M0 0x00D2U
  110. #define CMN_PLL1_HIGH_THR_M0 0x00D3U
  111. #define CMN_PLL1_DSM_DIAG_M0 0x00D4U
  112. #define CMN_PLL1_SS_CTRL1_M0 0x00D8U
  113. #define CMN_PLL1_SS_CTRL2_M0 0x00D9U
  114. #define CMN_PLL1_SS_CTRL3_M0 0x00DAU
  115. #define CMN_PLL1_SS_CTRL4_M0 0x00DBU
  116. #define CMN_PLL1_LOCK_REFCNT_START 0x00DCU
  117. #define CMN_PLL1_LOCK_PLLCNT_START 0x00DEU
  118. #define CMN_PLL1_LOCK_PLLCNT_THR 0x00DFU
  119. #define CMN_TXPUCAL_TUNE 0x0103U
  120. #define CMN_TXPUCAL_INIT_TMR 0x0104U
  121. #define CMN_TXPUCAL_ITER_TMR 0x0105U
  122. #define CMN_TXPDCAL_TUNE 0x010BU
  123. #define CMN_TXPDCAL_INIT_TMR 0x010CU
  124. #define CMN_TXPDCAL_ITER_TMR 0x010DU
  125. #define CMN_RXCAL_INIT_TMR 0x0114U
  126. #define CMN_RXCAL_ITER_TMR 0x0115U
  127. #define CMN_SD_CAL_INIT_TMR 0x0124U
  128. #define CMN_SD_CAL_ITER_TMR 0x0125U
  129. #define CMN_SD_CAL_REFTIM_START 0x0126U
  130. #define CMN_SD_CAL_PLLCNT_START 0x0128U
  131. #define CMN_PDIAG_PLL0_CTRL_M0 0x01A0U
  132. #define CMN_PDIAG_PLL0_CLK_SEL_M0 0x01A1U
  133. #define CMN_PDIAG_PLL0_CP_PADJ_M0 0x01A4U
  134. #define CMN_PDIAG_PLL0_CP_IADJ_M0 0x01A5U
  135. #define CMN_PDIAG_PLL0_FILT_PADJ_M0 0x01A6U
  136. #define CMN_PDIAG_PLL0_CTRL_M1 0x01B0U
  137. #define CMN_PDIAG_PLL0_CLK_SEL_M1 0x01B1U
  138. #define CMN_PDIAG_PLL0_CP_PADJ_M1 0x01B4U
  139. #define CMN_PDIAG_PLL0_CP_IADJ_M1 0x01B5U
  140. #define CMN_PDIAG_PLL0_FILT_PADJ_M1 0x01B6U
  141. #define CMN_PDIAG_PLL1_CTRL_M0 0x01C0U
  142. #define CMN_PDIAG_PLL1_CLK_SEL_M0 0x01C1U
  143. #define CMN_PDIAG_PLL1_CP_PADJ_M0 0x01C4U
  144. #define CMN_PDIAG_PLL1_CP_IADJ_M0 0x01C5U
  145. #define CMN_PDIAG_PLL1_FILT_PADJ_M0 0x01C6U
  146. #define CMN_DIAG_BIAS_OVRD1 0x01E1U
  147. /* PMA TX Lane registers */
  148. #define TX_TXCC_CTRL 0x0040U
  149. #define TX_TXCC_CPOST_MULT_00 0x004CU
  150. #define TX_TXCC_CPOST_MULT_01 0x004DU
  151. #define TX_TXCC_MGNFS_MULT_000 0x0050U
  152. #define DRV_DIAG_TX_DRV 0x00C6U
  153. #define XCVR_DIAG_PLLDRC_CTRL 0x00E5U
  154. #define XCVR_DIAG_HSCLK_SEL 0x00E6U
  155. #define XCVR_DIAG_HSCLK_DIV 0x00E7U
  156. #define XCVR_DIAG_BIDI_CTRL 0x00EAU
  157. #define XCVR_DIAG_PSC_OVRD 0x00EBU
  158. #define TX_PSC_A0 0x0100U
  159. #define TX_PSC_A1 0x0101U
  160. #define TX_PSC_A2 0x0102U
  161. #define TX_PSC_A3 0x0103U
  162. #define TX_RCVDET_ST_TMR 0x0123U
  163. #define TX_DIAG_ACYA 0x01E7U
  164. #define TX_DIAG_ACYA_HBDC_MASK 0x0001U
  165. /* PMA RX Lane registers */
  166. #define RX_PSC_A0 0x0000U
  167. #define RX_PSC_A1 0x0001U
  168. #define RX_PSC_A2 0x0002U
  169. #define RX_PSC_A3 0x0003U
  170. #define RX_PSC_CAL 0x0006U
  171. #define RX_CDRLF_CNFG 0x0080U
  172. #define RX_CDRLF_CNFG3 0x0082U
  173. #define RX_SIGDET_HL_FILT_TMR 0x0090U
  174. #define RX_REE_GCSM1_CTRL 0x0108U
  175. #define RX_REE_GCSM1_EQENM_PH1 0x0109U
  176. #define RX_REE_GCSM1_EQENM_PH2 0x010AU
  177. #define RX_REE_GCSM2_CTRL 0x0110U
  178. #define RX_REE_PERGCSM_CTRL 0x0118U
  179. #define RX_REE_ATTEN_THR 0x0149U
  180. #define RX_REE_TAP1_CLIP 0x0171U
  181. #define RX_REE_TAP2TON_CLIP 0x0172U
  182. #define RX_REE_SMGM_CTRL1 0x0177U
  183. #define RX_REE_SMGM_CTRL2 0x0178U
  184. #define RX_DIAG_DFE_CTRL 0x01E0U
  185. #define RX_DIAG_DFE_AMP_TUNE_2 0x01E2U
  186. #define RX_DIAG_DFE_AMP_TUNE_3 0x01E3U
  187. #define RX_DIAG_NQST_CTRL 0x01E5U
  188. #define RX_DIAG_SIGDET_TUNE 0x01E8U
  189. #define RX_DIAG_PI_RATE 0x01F4U
  190. #define RX_DIAG_PI_CAP 0x01F5U
  191. #define RX_DIAG_ACYA 0x01FFU
  192. /* PHY PCS common registers */
  193. #define PHY_PLL_CFG 0x000EU
  194. #define PHY_PIPE_USB3_GEN2_PRE_CFG0 0x0020U
  195. #define PHY_PIPE_USB3_GEN2_POST_CFG0 0x0022U
  196. #define PHY_PIPE_USB3_GEN2_POST_CFG1 0x0023U
  197. /* PHY PMA common registers */
  198. #define PHY_PMA_CMN_CTRL1 0x0000U
  199. #define PHY_PMA_CMN_CTRL2 0x0001U
  200. #define PHY_PMA_PLL_RAW_CTRL 0x0003U
  201. static const struct reg_field phy_pll_cfg =
  202. REG_FIELD(PHY_PLL_CFG, 0, 1);
  203. static const struct reg_field phy_pma_cmn_ctrl_1 =
  204. REG_FIELD(PHY_PMA_CMN_CTRL1, 0, 0);
  205. static const struct reg_field phy_pma_cmn_ctrl_2 =
  206. REG_FIELD(PHY_PMA_CMN_CTRL2, 0, 7);
  207. static const struct reg_field phy_pma_pll_raw_ctrl =
  208. REG_FIELD(PHY_PMA_PLL_RAW_CTRL, 0, 1);
  209. static const struct reg_field phy_reset_ctrl =
  210. REG_FIELD(PHY_RESET, 8, 8);
  211. enum cdns_torrent_phy_type {
  212. TYPE_NONE,
  213. TYPE_DP,
  214. TYPE_PCIE,
  215. TYPE_SGMII,
  216. TYPE_QSGMII,
  217. TYPE_USB,
  218. };
  219. enum cdns_torrent_ssc_mode {
  220. NO_SSC,
  221. EXTERNAL_SSC,
  222. INTERNAL_SSC
  223. };
  224. struct cdns_torrent_inst {
  225. struct phy *phy;
  226. u32 mlane;
  227. enum cdns_torrent_phy_type phy_type;
  228. u32 num_lanes;
  229. struct reset_control *lnk_rst;
  230. enum cdns_torrent_ssc_mode ssc_mode;
  231. };
  232. struct cdns_torrent_phy {
  233. void __iomem *base; /* DPTX registers base */
  234. void __iomem *sd_base; /* SD0801 registers base */
  235. u32 max_bit_rate; /* Maximum link bit rate to use (in Mbps) */
  236. struct reset_control *phy_rst;
  237. struct reset_control *apb_rst;
  238. struct device *dev;
  239. struct clk *clk;
  240. unsigned long ref_clk_rate;
  241. struct cdns_torrent_inst phys[MAX_NUM_LANES];
  242. int nsubnodes;
  243. const struct cdns_torrent_data *init_data;
  244. struct regmap *regmap;
  245. struct regmap *regmap_common_cdb;
  246. struct regmap *regmap_phy_pcs_common_cdb;
  247. struct regmap *regmap_phy_pma_common_cdb;
  248. struct regmap *regmap_tx_lane_cdb[MAX_NUM_LANES];
  249. struct regmap *regmap_rx_lane_cdb[MAX_NUM_LANES];
  250. struct regmap *regmap_dptx_phy_reg;
  251. struct regmap_field *phy_pll_cfg;
  252. struct regmap_field *phy_pma_cmn_ctrl_1;
  253. struct regmap_field *phy_pma_cmn_ctrl_2;
  254. struct regmap_field *phy_pma_pll_raw_ctrl;
  255. struct regmap_field *phy_reset_ctrl;
  256. };
  257. enum phy_powerstate {
  258. POWERSTATE_A0 = 0,
  259. /* Powerstate A1 is unused */
  260. POWERSTATE_A2 = 2,
  261. POWERSTATE_A3 = 3,
  262. };
  263. static int cdns_torrent_phy_init(struct phy *phy);
  264. static int cdns_torrent_dp_init(struct phy *phy);
  265. static int cdns_torrent_dp_run(struct cdns_torrent_phy *cdns_phy,
  266. u32 num_lanes);
  267. static
  268. int cdns_torrent_dp_wait_pma_cmn_ready(struct cdns_torrent_phy *cdns_phy);
  269. static void cdns_torrent_dp_pma_cfg(struct cdns_torrent_phy *cdns_phy,
  270. struct cdns_torrent_inst *inst);
  271. static
  272. void cdns_torrent_dp_pma_cmn_cfg_19_2mhz(struct cdns_torrent_phy *cdns_phy);
  273. static
  274. void cdns_torrent_dp_pma_cmn_vco_cfg_19_2mhz(struct cdns_torrent_phy *cdns_phy,
  275. u32 rate, bool ssc);
  276. static
  277. void cdns_torrent_dp_pma_cmn_cfg_25mhz(struct cdns_torrent_phy *cdns_phy);
  278. static
  279. void cdns_torrent_dp_pma_cmn_vco_cfg_25mhz(struct cdns_torrent_phy *cdns_phy,
  280. u32 rate, bool ssc);
  281. static void cdns_torrent_dp_pma_lane_cfg(struct cdns_torrent_phy *cdns_phy,
  282. unsigned int lane);
  283. static void cdns_torrent_dp_pma_cmn_rate(struct cdns_torrent_phy *cdns_phy,
  284. u32 rate, u32 num_lanes);
  285. static int cdns_torrent_dp_configure(struct phy *phy,
  286. union phy_configure_opts *opts);
  287. static int cdns_torrent_dp_set_power_state(struct cdns_torrent_phy *cdns_phy,
  288. u32 num_lanes,
  289. enum phy_powerstate powerstate);
  290. static int cdns_torrent_phy_on(struct phy *phy);
  291. static int cdns_torrent_phy_off(struct phy *phy);
  292. static const struct phy_ops cdns_torrent_phy_ops = {
  293. .init = cdns_torrent_phy_init,
  294. .configure = cdns_torrent_dp_configure,
  295. .power_on = cdns_torrent_phy_on,
  296. .power_off = cdns_torrent_phy_off,
  297. .owner = THIS_MODULE,
  298. };
  299. struct cdns_reg_pairs {
  300. u32 val;
  301. u32 off;
  302. };
  303. struct cdns_torrent_vals {
  304. struct cdns_reg_pairs *reg_pairs;
  305. u32 num_regs;
  306. };
  307. struct cdns_torrent_data {
  308. u8 block_offset_shift;
  309. u8 reg_offset_shift;
  310. struct cdns_torrent_vals *link_cmn_vals[NUM_PHY_TYPE][NUM_PHY_TYPE]
  311. [NUM_SSC_MODE];
  312. struct cdns_torrent_vals *xcvr_diag_vals[NUM_PHY_TYPE][NUM_PHY_TYPE]
  313. [NUM_SSC_MODE];
  314. struct cdns_torrent_vals *pcs_cmn_vals[NUM_PHY_TYPE][NUM_PHY_TYPE]
  315. [NUM_SSC_MODE];
  316. struct cdns_torrent_vals *cmn_vals[NUM_PHY_TYPE][NUM_PHY_TYPE]
  317. [NUM_SSC_MODE];
  318. struct cdns_torrent_vals *tx_ln_vals[NUM_PHY_TYPE][NUM_PHY_TYPE]
  319. [NUM_SSC_MODE];
  320. struct cdns_torrent_vals *rx_ln_vals[NUM_PHY_TYPE][NUM_PHY_TYPE]
  321. [NUM_SSC_MODE];
  322. };
  323. struct cdns_regmap_cdb_context {
  324. struct device *dev;
  325. void __iomem *base;
  326. u8 reg_offset_shift;
  327. };
  328. static int cdns_regmap_write(void *context, unsigned int reg, unsigned int val)
  329. {
  330. struct cdns_regmap_cdb_context *ctx = context;
  331. u32 offset = reg << ctx->reg_offset_shift;
  332. writew(val, ctx->base + offset);
  333. return 0;
  334. }
  335. static int cdns_regmap_read(void *context, unsigned int reg, unsigned int *val)
  336. {
  337. struct cdns_regmap_cdb_context *ctx = context;
  338. u32 offset = reg << ctx->reg_offset_shift;
  339. *val = readw(ctx->base + offset);
  340. return 0;
  341. }
  342. static int cdns_regmap_dptx_write(void *context, unsigned int reg,
  343. unsigned int val)
  344. {
  345. struct cdns_regmap_cdb_context *ctx = context;
  346. u32 offset = reg;
  347. writel(val, ctx->base + offset);
  348. return 0;
  349. }
  350. static int cdns_regmap_dptx_read(void *context, unsigned int reg,
  351. unsigned int *val)
  352. {
  353. struct cdns_regmap_cdb_context *ctx = context;
  354. u32 offset = reg;
  355. *val = readl(ctx->base + offset);
  356. return 0;
  357. }
  358. #define TORRENT_TX_LANE_CDB_REGMAP_CONF(n) \
  359. { \
  360. .name = "torrent_tx_lane" n "_cdb", \
  361. .reg_stride = 1, \
  362. .fast_io = true, \
  363. .reg_write = cdns_regmap_write, \
  364. .reg_read = cdns_regmap_read, \
  365. }
  366. #define TORRENT_RX_LANE_CDB_REGMAP_CONF(n) \
  367. { \
  368. .name = "torrent_rx_lane" n "_cdb", \
  369. .reg_stride = 1, \
  370. .fast_io = true, \
  371. .reg_write = cdns_regmap_write, \
  372. .reg_read = cdns_regmap_read, \
  373. }
  374. static const struct regmap_config cdns_torrent_tx_lane_cdb_config[] = {
  375. TORRENT_TX_LANE_CDB_REGMAP_CONF("0"),
  376. TORRENT_TX_LANE_CDB_REGMAP_CONF("1"),
  377. TORRENT_TX_LANE_CDB_REGMAP_CONF("2"),
  378. TORRENT_TX_LANE_CDB_REGMAP_CONF("3"),
  379. };
  380. static const struct regmap_config cdns_torrent_rx_lane_cdb_config[] = {
  381. TORRENT_RX_LANE_CDB_REGMAP_CONF("0"),
  382. TORRENT_RX_LANE_CDB_REGMAP_CONF("1"),
  383. TORRENT_RX_LANE_CDB_REGMAP_CONF("2"),
  384. TORRENT_RX_LANE_CDB_REGMAP_CONF("3"),
  385. };
  386. static const struct regmap_config cdns_torrent_common_cdb_config = {
  387. .name = "torrent_common_cdb",
  388. .reg_stride = 1,
  389. .fast_io = true,
  390. .reg_write = cdns_regmap_write,
  391. .reg_read = cdns_regmap_read,
  392. };
  393. static const struct regmap_config cdns_torrent_phy_pcs_cmn_cdb_config = {
  394. .name = "torrent_phy_pcs_cmn_cdb",
  395. .reg_stride = 1,
  396. .fast_io = true,
  397. .reg_write = cdns_regmap_write,
  398. .reg_read = cdns_regmap_read,
  399. };
  400. static const struct regmap_config cdns_torrent_phy_pma_cmn_cdb_config = {
  401. .name = "torrent_phy_pma_cmn_cdb",
  402. .reg_stride = 1,
  403. .fast_io = true,
  404. .reg_write = cdns_regmap_write,
  405. .reg_read = cdns_regmap_read,
  406. };
  407. static const struct regmap_config cdns_torrent_dptx_phy_config = {
  408. .name = "torrent_dptx_phy",
  409. .reg_stride = 1,
  410. .fast_io = true,
  411. .reg_write = cdns_regmap_dptx_write,
  412. .reg_read = cdns_regmap_dptx_read,
  413. };
  414. /* PHY mmr access functions */
  415. static void cdns_torrent_phy_write(struct regmap *regmap, u32 offset, u32 val)
  416. {
  417. regmap_write(regmap, offset, val);
  418. }
  419. static u32 cdns_torrent_phy_read(struct regmap *regmap, u32 offset)
  420. {
  421. unsigned int val;
  422. regmap_read(regmap, offset, &val);
  423. return val;
  424. }
  425. /* DPTX mmr access functions */
  426. static void cdns_torrent_dp_write(struct regmap *regmap, u32 offset, u32 val)
  427. {
  428. regmap_write(regmap, offset, val);
  429. }
  430. static u32 cdns_torrent_dp_read(struct regmap *regmap, u32 offset)
  431. {
  432. u32 val;
  433. regmap_read(regmap, offset, &val);
  434. return val;
  435. }
  436. /*
  437. * Structure used to store values of PHY registers for voltage-related
  438. * coefficients, for particular voltage swing and pre-emphasis level. Values
  439. * are shared across all physical lanes.
  440. */
  441. struct coefficients {
  442. /* Value of DRV_DIAG_TX_DRV register to use */
  443. u16 diag_tx_drv;
  444. /* Value of TX_TXCC_MGNFS_MULT_000 register to use */
  445. u16 mgnfs_mult;
  446. /* Value of TX_TXCC_CPOST_MULT_00 register to use */
  447. u16 cpost_mult;
  448. };
  449. /*
  450. * Array consists of values of voltage-related registers for sd0801 PHY. A value
  451. * of 0xFFFF is a placeholder for invalid combination, and will never be used.
  452. */
  453. static const struct coefficients vltg_coeff[4][4] = {
  454. /* voltage swing 0, pre-emphasis 0->3 */
  455. { {.diag_tx_drv = 0x0003, .mgnfs_mult = 0x002A,
  456. .cpost_mult = 0x0000},
  457. {.diag_tx_drv = 0x0003, .mgnfs_mult = 0x001F,
  458. .cpost_mult = 0x0014},
  459. {.diag_tx_drv = 0x0003, .mgnfs_mult = 0x0012,
  460. .cpost_mult = 0x0020},
  461. {.diag_tx_drv = 0x0003, .mgnfs_mult = 0x0000,
  462. .cpost_mult = 0x002A}
  463. },
  464. /* voltage swing 1, pre-emphasis 0->3 */
  465. { {.diag_tx_drv = 0x0003, .mgnfs_mult = 0x001F,
  466. .cpost_mult = 0x0000},
  467. {.diag_tx_drv = 0x0003, .mgnfs_mult = 0x0013,
  468. .cpost_mult = 0x0012},
  469. {.diag_tx_drv = 0x0003, .mgnfs_mult = 0x0000,
  470. .cpost_mult = 0x001F},
  471. {.diag_tx_drv = 0xFFFF, .mgnfs_mult = 0xFFFF,
  472. .cpost_mult = 0xFFFF}
  473. },
  474. /* voltage swing 2, pre-emphasis 0->3 */
  475. { {.diag_tx_drv = 0x0003, .mgnfs_mult = 0x0013,
  476. .cpost_mult = 0x0000},
  477. {.diag_tx_drv = 0x0003, .mgnfs_mult = 0x0000,
  478. .cpost_mult = 0x0013},
  479. {.diag_tx_drv = 0xFFFF, .mgnfs_mult = 0xFFFF,
  480. .cpost_mult = 0xFFFF},
  481. {.diag_tx_drv = 0xFFFF, .mgnfs_mult = 0xFFFF,
  482. .cpost_mult = 0xFFFF}
  483. },
  484. /* voltage swing 3, pre-emphasis 0->3 */
  485. { {.diag_tx_drv = 0x0003, .mgnfs_mult = 0x0000,
  486. .cpost_mult = 0x0000},
  487. {.diag_tx_drv = 0xFFFF, .mgnfs_mult = 0xFFFF,
  488. .cpost_mult = 0xFFFF},
  489. {.diag_tx_drv = 0xFFFF, .mgnfs_mult = 0xFFFF,
  490. .cpost_mult = 0xFFFF},
  491. {.diag_tx_drv = 0xFFFF, .mgnfs_mult = 0xFFFF,
  492. .cpost_mult = 0xFFFF}
  493. }
  494. };
  495. /*
  496. * Enable or disable PLL for selected lanes.
  497. */
  498. static int cdns_torrent_dp_set_pll_en(struct cdns_torrent_phy *cdns_phy,
  499. struct phy_configure_opts_dp *dp,
  500. bool enable)
  501. {
  502. u32 rd_val;
  503. u32 ret;
  504. struct regmap *regmap = cdns_phy->regmap_dptx_phy_reg;
  505. /*
  506. * Used to determine, which bits to check for or enable in
  507. * PHY_PMA_XCVR_PLLCLK_EN register.
  508. */
  509. u32 pll_bits;
  510. /* Used to enable or disable lanes. */
  511. u32 pll_val;
  512. /* Select values of registers and mask, depending on enabled lane
  513. * count.
  514. */
  515. switch (dp->lanes) {
  516. /* lane 0 */
  517. case (1):
  518. pll_bits = 0x00000001;
  519. break;
  520. /* lanes 0-1 */
  521. case (2):
  522. pll_bits = 0x00000003;
  523. break;
  524. /* lanes 0-3, all */
  525. default:
  526. pll_bits = 0x0000000F;
  527. break;
  528. }
  529. if (enable)
  530. pll_val = pll_bits;
  531. else
  532. pll_val = 0x00000000;
  533. cdns_torrent_dp_write(regmap, PHY_PMA_XCVR_PLLCLK_EN, pll_val);
  534. /* Wait for acknowledgment from PHY. */
  535. ret = regmap_read_poll_timeout(regmap,
  536. PHY_PMA_XCVR_PLLCLK_EN_ACK,
  537. rd_val,
  538. (rd_val & pll_bits) == pll_val,
  539. 0, POLL_TIMEOUT_US);
  540. ndelay(100);
  541. return ret;
  542. }
  543. /*
  544. * Perform register operations related to setting link rate, once powerstate is
  545. * set and PLL disable request was processed.
  546. */
  547. static int cdns_torrent_dp_configure_rate(struct cdns_torrent_phy *cdns_phy,
  548. struct phy_configure_opts_dp *dp)
  549. {
  550. u32 ret;
  551. u32 read_val;
  552. /* Disable the cmn_pll0_en before re-programming the new data rate. */
  553. regmap_field_write(cdns_phy->phy_pma_pll_raw_ctrl, 0x0);
  554. /*
  555. * Wait for PLL ready de-assertion.
  556. * For PLL0 - PHY_PMA_CMN_CTRL2[2] == 1
  557. */
  558. ret = regmap_field_read_poll_timeout(cdns_phy->phy_pma_cmn_ctrl_2,
  559. read_val,
  560. ((read_val >> 2) & 0x01) != 0,
  561. 0, POLL_TIMEOUT_US);
  562. if (ret)
  563. return ret;
  564. ndelay(200);
  565. /* DP Rate Change - VCO Output settings. */
  566. if (cdns_phy->ref_clk_rate == REF_CLK_19_2MHz) {
  567. /* PMA common configuration 19.2MHz */
  568. cdns_torrent_dp_pma_cmn_vco_cfg_19_2mhz(cdns_phy, dp->link_rate,
  569. dp->ssc);
  570. cdns_torrent_dp_pma_cmn_cfg_19_2mhz(cdns_phy);
  571. } else if (cdns_phy->ref_clk_rate == REF_CLK_25MHz) {
  572. /* PMA common configuration 25MHz */
  573. cdns_torrent_dp_pma_cmn_vco_cfg_25mhz(cdns_phy, dp->link_rate,
  574. dp->ssc);
  575. cdns_torrent_dp_pma_cmn_cfg_25mhz(cdns_phy);
  576. }
  577. cdns_torrent_dp_pma_cmn_rate(cdns_phy, dp->link_rate, dp->lanes);
  578. /* Enable the cmn_pll0_en. */
  579. regmap_field_write(cdns_phy->phy_pma_pll_raw_ctrl, 0x3);
  580. /*
  581. * Wait for PLL ready assertion.
  582. * For PLL0 - PHY_PMA_CMN_CTRL2[0] == 1
  583. */
  584. ret = regmap_field_read_poll_timeout(cdns_phy->phy_pma_cmn_ctrl_2,
  585. read_val,
  586. (read_val & 0x01) != 0,
  587. 0, POLL_TIMEOUT_US);
  588. return ret;
  589. }
  590. /*
  591. * Verify, that parameters to configure PHY with are correct.
  592. */
  593. static int cdns_torrent_dp_verify_config(struct cdns_torrent_inst *inst,
  594. struct phy_configure_opts_dp *dp)
  595. {
  596. u8 i;
  597. /* If changing link rate was required, verify it's supported. */
  598. if (dp->set_rate) {
  599. switch (dp->link_rate) {
  600. case 1620:
  601. case 2160:
  602. case 2430:
  603. case 2700:
  604. case 3240:
  605. case 4320:
  606. case 5400:
  607. case 8100:
  608. /* valid bit rate */
  609. break;
  610. default:
  611. return -EINVAL;
  612. }
  613. }
  614. /* Verify lane count. */
  615. switch (dp->lanes) {
  616. case 1:
  617. case 2:
  618. case 4:
  619. /* valid lane count. */
  620. break;
  621. default:
  622. return -EINVAL;
  623. }
  624. /* Check against actual number of PHY's lanes. */
  625. if (dp->lanes > inst->num_lanes)
  626. return -EINVAL;
  627. /*
  628. * If changing voltages is required, check swing and pre-emphasis
  629. * levels, per-lane.
  630. */
  631. if (dp->set_voltages) {
  632. /* Lane count verified previously. */
  633. for (i = 0; i < dp->lanes; i++) {
  634. if (dp->voltage[i] > 3 || dp->pre[i] > 3)
  635. return -EINVAL;
  636. /* Sum of voltage swing and pre-emphasis levels cannot
  637. * exceed 3.
  638. */
  639. if (dp->voltage[i] + dp->pre[i] > 3)
  640. return -EINVAL;
  641. }
  642. }
  643. return 0;
  644. }
  645. /* Set power state A0 and PLL clock enable to 0 on enabled lanes. */
  646. static void cdns_torrent_dp_set_a0_pll(struct cdns_torrent_phy *cdns_phy,
  647. u32 num_lanes)
  648. {
  649. struct regmap *regmap = cdns_phy->regmap_dptx_phy_reg;
  650. u32 pwr_state = cdns_torrent_dp_read(regmap,
  651. PHY_PMA_XCVR_POWER_STATE_REQ);
  652. u32 pll_clk_en = cdns_torrent_dp_read(regmap,
  653. PHY_PMA_XCVR_PLLCLK_EN);
  654. /* Lane 0 is always enabled. */
  655. pwr_state &= ~(PMA_XCVR_POWER_STATE_REQ_LN_MASK <<
  656. PHY_POWER_STATE_LN_0);
  657. pll_clk_en &= ~0x01U;
  658. if (num_lanes > 1) {
  659. /* lane 1 */
  660. pwr_state &= ~(PMA_XCVR_POWER_STATE_REQ_LN_MASK <<
  661. PHY_POWER_STATE_LN_1);
  662. pll_clk_en &= ~(0x01U << 1);
  663. }
  664. if (num_lanes > 2) {
  665. /* lanes 2 and 3 */
  666. pwr_state &= ~(PMA_XCVR_POWER_STATE_REQ_LN_MASK <<
  667. PHY_POWER_STATE_LN_2);
  668. pwr_state &= ~(PMA_XCVR_POWER_STATE_REQ_LN_MASK <<
  669. PHY_POWER_STATE_LN_3);
  670. pll_clk_en &= ~(0x01U << 2);
  671. pll_clk_en &= ~(0x01U << 3);
  672. }
  673. cdns_torrent_dp_write(regmap, PHY_PMA_XCVR_POWER_STATE_REQ, pwr_state);
  674. cdns_torrent_dp_write(regmap, PHY_PMA_XCVR_PLLCLK_EN, pll_clk_en);
  675. }
  676. /* Configure lane count as required. */
  677. static int cdns_torrent_dp_set_lanes(struct cdns_torrent_phy *cdns_phy,
  678. struct phy_configure_opts_dp *dp)
  679. {
  680. u32 value;
  681. u32 ret;
  682. struct regmap *regmap = cdns_phy->regmap_dptx_phy_reg;
  683. u8 lane_mask = (1 << dp->lanes) - 1;
  684. value = cdns_torrent_dp_read(regmap, PHY_RESET);
  685. /* clear pma_tx_elec_idle_ln_* bits. */
  686. value &= ~PMA_TX_ELEC_IDLE_MASK;
  687. /* Assert pma_tx_elec_idle_ln_* for disabled lanes. */
  688. value |= ((~lane_mask) << PMA_TX_ELEC_IDLE_SHIFT) &
  689. PMA_TX_ELEC_IDLE_MASK;
  690. cdns_torrent_dp_write(regmap, PHY_RESET, value);
  691. /* reset the link by asserting phy_l00_reset_n low */
  692. cdns_torrent_dp_write(regmap, PHY_RESET,
  693. value & (~PHY_L00_RESET_N_MASK));
  694. /*
  695. * Assert lane reset on unused lanes and lane 0 so they remain in reset
  696. * and powered down when re-enabling the link
  697. */
  698. value = (value & 0x0000FFF0) | (0x0000000E & lane_mask);
  699. cdns_torrent_dp_write(regmap, PHY_RESET, value);
  700. cdns_torrent_dp_set_a0_pll(cdns_phy, dp->lanes);
  701. /* release phy_l0*_reset_n based on used laneCount */
  702. value = (value & 0x0000FFF0) | (0x0000000F & lane_mask);
  703. cdns_torrent_dp_write(regmap, PHY_RESET, value);
  704. /* Wait, until PHY gets ready after releasing PHY reset signal. */
  705. ret = cdns_torrent_dp_wait_pma_cmn_ready(cdns_phy);
  706. if (ret)
  707. return ret;
  708. ndelay(100);
  709. /* release pma_xcvr_pllclk_en_ln_*, only for the master lane */
  710. cdns_torrent_dp_write(regmap, PHY_PMA_XCVR_PLLCLK_EN, 0x0001);
  711. ret = cdns_torrent_dp_run(cdns_phy, dp->lanes);
  712. return ret;
  713. }
  714. /* Configure link rate as required. */
  715. static int cdns_torrent_dp_set_rate(struct cdns_torrent_phy *cdns_phy,
  716. struct phy_configure_opts_dp *dp)
  717. {
  718. u32 ret;
  719. ret = cdns_torrent_dp_set_power_state(cdns_phy, dp->lanes,
  720. POWERSTATE_A3);
  721. if (ret)
  722. return ret;
  723. ret = cdns_torrent_dp_set_pll_en(cdns_phy, dp, false);
  724. if (ret)
  725. return ret;
  726. ndelay(200);
  727. ret = cdns_torrent_dp_configure_rate(cdns_phy, dp);
  728. if (ret)
  729. return ret;
  730. ndelay(200);
  731. ret = cdns_torrent_dp_set_pll_en(cdns_phy, dp, true);
  732. if (ret)
  733. return ret;
  734. ret = cdns_torrent_dp_set_power_state(cdns_phy, dp->lanes,
  735. POWERSTATE_A2);
  736. if (ret)
  737. return ret;
  738. ret = cdns_torrent_dp_set_power_state(cdns_phy, dp->lanes,
  739. POWERSTATE_A0);
  740. if (ret)
  741. return ret;
  742. ndelay(900);
  743. return ret;
  744. }
  745. /* Configure voltage swing and pre-emphasis for all enabled lanes. */
  746. static void cdns_torrent_dp_set_voltages(struct cdns_torrent_phy *cdns_phy,
  747. struct phy_configure_opts_dp *dp)
  748. {
  749. u8 lane;
  750. u16 val;
  751. for (lane = 0; lane < dp->lanes; lane++) {
  752. val = cdns_torrent_phy_read(cdns_phy->regmap_tx_lane_cdb[lane],
  753. TX_DIAG_ACYA);
  754. /*
  755. * Write 1 to register bit TX_DIAG_ACYA[0] to freeze the
  756. * current state of the analog TX driver.
  757. */
  758. val |= TX_DIAG_ACYA_HBDC_MASK;
  759. cdns_torrent_phy_write(cdns_phy->regmap_tx_lane_cdb[lane],
  760. TX_DIAG_ACYA, val);
  761. cdns_torrent_phy_write(cdns_phy->regmap_tx_lane_cdb[lane],
  762. TX_TXCC_CTRL, 0x08A4);
  763. val = vltg_coeff[dp->voltage[lane]][dp->pre[lane]].diag_tx_drv;
  764. cdns_torrent_phy_write(cdns_phy->regmap_tx_lane_cdb[lane],
  765. DRV_DIAG_TX_DRV, val);
  766. val = vltg_coeff[dp->voltage[lane]][dp->pre[lane]].mgnfs_mult;
  767. cdns_torrent_phy_write(cdns_phy->regmap_tx_lane_cdb[lane],
  768. TX_TXCC_MGNFS_MULT_000,
  769. val);
  770. val = vltg_coeff[dp->voltage[lane]][dp->pre[lane]].cpost_mult;
  771. cdns_torrent_phy_write(cdns_phy->regmap_tx_lane_cdb[lane],
  772. TX_TXCC_CPOST_MULT_00,
  773. val);
  774. val = cdns_torrent_phy_read(cdns_phy->regmap_tx_lane_cdb[lane],
  775. TX_DIAG_ACYA);
  776. /*
  777. * Write 0 to register bit TX_DIAG_ACYA[0] to allow the state of
  778. * analog TX driver to reflect the new programmed one.
  779. */
  780. val &= ~TX_DIAG_ACYA_HBDC_MASK;
  781. cdns_torrent_phy_write(cdns_phy->regmap_tx_lane_cdb[lane],
  782. TX_DIAG_ACYA, val);
  783. }
  784. };
  785. static int cdns_torrent_dp_configure(struct phy *phy,
  786. union phy_configure_opts *opts)
  787. {
  788. struct cdns_torrent_inst *inst = phy_get_drvdata(phy);
  789. struct cdns_torrent_phy *cdns_phy = dev_get_drvdata(phy->dev.parent);
  790. int ret;
  791. ret = cdns_torrent_dp_verify_config(inst, &opts->dp);
  792. if (ret) {
  793. dev_err(&phy->dev, "invalid params for phy configure\n");
  794. return ret;
  795. }
  796. if (opts->dp.set_lanes) {
  797. ret = cdns_torrent_dp_set_lanes(cdns_phy, &opts->dp);
  798. if (ret) {
  799. dev_err(&phy->dev, "cdns_torrent_dp_set_lanes failed\n");
  800. return ret;
  801. }
  802. }
  803. if (opts->dp.set_rate) {
  804. ret = cdns_torrent_dp_set_rate(cdns_phy, &opts->dp);
  805. if (ret) {
  806. dev_err(&phy->dev, "cdns_torrent_dp_set_rate failed\n");
  807. return ret;
  808. }
  809. }
  810. if (opts->dp.set_voltages)
  811. cdns_torrent_dp_set_voltages(cdns_phy, &opts->dp);
  812. return ret;
  813. }
  814. static int cdns_torrent_dp_init(struct phy *phy)
  815. {
  816. unsigned char lane_bits;
  817. int ret;
  818. struct cdns_torrent_inst *inst = phy_get_drvdata(phy);
  819. struct cdns_torrent_phy *cdns_phy = dev_get_drvdata(phy->dev.parent);
  820. struct regmap *regmap = cdns_phy->regmap_dptx_phy_reg;
  821. switch (cdns_phy->ref_clk_rate) {
  822. case REF_CLK_19_2MHz:
  823. case REF_CLK_25MHz:
  824. /* Valid Ref Clock Rate */
  825. break;
  826. default:
  827. dev_err(cdns_phy->dev, "Unsupported Ref Clock Rate\n");
  828. return -EINVAL;
  829. }
  830. cdns_torrent_dp_write(regmap, PHY_AUX_CTRL, 0x0003); /* enable AUX */
  831. /* PHY PMA registers configuration function */
  832. cdns_torrent_dp_pma_cfg(cdns_phy, inst);
  833. /*
  834. * Set lines power state to A0
  835. * Set lines pll clk enable to 0
  836. */
  837. cdns_torrent_dp_set_a0_pll(cdns_phy, inst->num_lanes);
  838. /*
  839. * release phy_l0*_reset_n and pma_tx_elec_idle_ln_* based on
  840. * used lanes
  841. */
  842. lane_bits = (1 << inst->num_lanes) - 1;
  843. cdns_torrent_dp_write(regmap, PHY_RESET,
  844. ((0xF & ~lane_bits) << 4) | (0xF & lane_bits));
  845. /* release pma_xcvr_pllclk_en_ln_*, only for the master lane */
  846. cdns_torrent_dp_write(regmap, PHY_PMA_XCVR_PLLCLK_EN, 0x0001);
  847. /* PHY PMA registers configuration functions */
  848. /* Initialize PHY with max supported link rate, without SSC. */
  849. if (cdns_phy->ref_clk_rate == REF_CLK_19_2MHz)
  850. cdns_torrent_dp_pma_cmn_vco_cfg_19_2mhz(cdns_phy,
  851. cdns_phy->max_bit_rate,
  852. false);
  853. else if (cdns_phy->ref_clk_rate == REF_CLK_25MHz)
  854. cdns_torrent_dp_pma_cmn_vco_cfg_25mhz(cdns_phy,
  855. cdns_phy->max_bit_rate,
  856. false);
  857. cdns_torrent_dp_pma_cmn_rate(cdns_phy, cdns_phy->max_bit_rate,
  858. inst->num_lanes);
  859. /* take out of reset */
  860. regmap_field_write(cdns_phy->phy_reset_ctrl, 0x1);
  861. cdns_torrent_phy_on(phy);
  862. ret = cdns_torrent_dp_wait_pma_cmn_ready(cdns_phy);
  863. if (ret)
  864. return ret;
  865. ret = cdns_torrent_dp_run(cdns_phy, inst->num_lanes);
  866. return ret;
  867. }
  868. static
  869. int cdns_torrent_dp_wait_pma_cmn_ready(struct cdns_torrent_phy *cdns_phy)
  870. {
  871. unsigned int reg;
  872. int ret;
  873. struct regmap *regmap = cdns_phy->regmap_dptx_phy_reg;
  874. ret = regmap_read_poll_timeout(regmap, PHY_PMA_CMN_READY, reg,
  875. reg & 1, 0, POLL_TIMEOUT_US);
  876. if (ret == -ETIMEDOUT) {
  877. dev_err(cdns_phy->dev,
  878. "timeout waiting for PMA common ready\n");
  879. return -ETIMEDOUT;
  880. }
  881. return 0;
  882. }
  883. static void cdns_torrent_dp_pma_cfg(struct cdns_torrent_phy *cdns_phy,
  884. struct cdns_torrent_inst *inst)
  885. {
  886. unsigned int i;
  887. if (cdns_phy->ref_clk_rate == REF_CLK_19_2MHz)
  888. /* PMA common configuration 19.2MHz */
  889. cdns_torrent_dp_pma_cmn_cfg_19_2mhz(cdns_phy);
  890. else if (cdns_phy->ref_clk_rate == REF_CLK_25MHz)
  891. /* PMA common configuration 25MHz */
  892. cdns_torrent_dp_pma_cmn_cfg_25mhz(cdns_phy);
  893. /* PMA lane configuration to deal with multi-link operation */
  894. for (i = 0; i < inst->num_lanes; i++)
  895. cdns_torrent_dp_pma_lane_cfg(cdns_phy, i);
  896. }
  897. static
  898. void cdns_torrent_dp_pma_cmn_cfg_19_2mhz(struct cdns_torrent_phy *cdns_phy)
  899. {
  900. struct regmap *regmap = cdns_phy->regmap_common_cdb;
  901. /* refclock registers - assumes 19.2 MHz refclock */
  902. cdns_torrent_phy_write(regmap, CMN_SSM_BIAS_TMR, 0x0014);
  903. cdns_torrent_phy_write(regmap, CMN_PLLSM0_PLLPRE_TMR, 0x0027);
  904. cdns_torrent_phy_write(regmap, CMN_PLLSM0_PLLLOCK_TMR, 0x00A1);
  905. cdns_torrent_phy_write(regmap, CMN_PLLSM1_PLLPRE_TMR, 0x0027);
  906. cdns_torrent_phy_write(regmap, CMN_PLLSM1_PLLLOCK_TMR, 0x00A1);
  907. cdns_torrent_phy_write(regmap, CMN_BGCAL_INIT_TMR, 0x0060);
  908. cdns_torrent_phy_write(regmap, CMN_BGCAL_ITER_TMR, 0x0060);
  909. cdns_torrent_phy_write(regmap, CMN_IBCAL_INIT_TMR, 0x0014);
  910. cdns_torrent_phy_write(regmap, CMN_TXPUCAL_INIT_TMR, 0x0018);
  911. cdns_torrent_phy_write(regmap, CMN_TXPUCAL_ITER_TMR, 0x0005);
  912. cdns_torrent_phy_write(regmap, CMN_TXPDCAL_INIT_TMR, 0x0018);
  913. cdns_torrent_phy_write(regmap, CMN_TXPDCAL_ITER_TMR, 0x0005);
  914. cdns_torrent_phy_write(regmap, CMN_RXCAL_INIT_TMR, 0x0240);
  915. cdns_torrent_phy_write(regmap, CMN_RXCAL_ITER_TMR, 0x0005);
  916. cdns_torrent_phy_write(regmap, CMN_SD_CAL_INIT_TMR, 0x0002);
  917. cdns_torrent_phy_write(regmap, CMN_SD_CAL_ITER_TMR, 0x0002);
  918. cdns_torrent_phy_write(regmap, CMN_SD_CAL_REFTIM_START, 0x000B);
  919. cdns_torrent_phy_write(regmap, CMN_SD_CAL_PLLCNT_START, 0x0137);
  920. /* PLL registers */
  921. cdns_torrent_phy_write(regmap, CMN_PDIAG_PLL0_CP_PADJ_M0, 0x0509);
  922. cdns_torrent_phy_write(regmap, CMN_PDIAG_PLL0_CP_IADJ_M0, 0x0F00);
  923. cdns_torrent_phy_write(regmap, CMN_PDIAG_PLL0_FILT_PADJ_M0, 0x0F08);
  924. cdns_torrent_phy_write(regmap, CMN_PLL0_DSM_DIAG_M0, 0x0004);
  925. cdns_torrent_phy_write(regmap, CMN_PDIAG_PLL1_CP_PADJ_M0, 0x0509);
  926. cdns_torrent_phy_write(regmap, CMN_PDIAG_PLL1_CP_IADJ_M0, 0x0F00);
  927. cdns_torrent_phy_write(regmap, CMN_PDIAG_PLL1_FILT_PADJ_M0, 0x0F08);
  928. cdns_torrent_phy_write(regmap, CMN_PLL1_DSM_DIAG_M0, 0x0004);
  929. cdns_torrent_phy_write(regmap, CMN_PLL0_VCOCAL_INIT_TMR, 0x00C0);
  930. cdns_torrent_phy_write(regmap, CMN_PLL0_VCOCAL_ITER_TMR, 0x0004);
  931. cdns_torrent_phy_write(regmap, CMN_PLL1_VCOCAL_INIT_TMR, 0x00C0);
  932. cdns_torrent_phy_write(regmap, CMN_PLL1_VCOCAL_ITER_TMR, 0x0004);
  933. cdns_torrent_phy_write(regmap, CMN_PLL0_VCOCAL_REFTIM_START, 0x0260);
  934. cdns_torrent_phy_write(regmap, CMN_PLL0_VCOCAL_TCTRL, 0x0003);
  935. cdns_torrent_phy_write(regmap, CMN_PLL1_VCOCAL_REFTIM_START, 0x0260);
  936. cdns_torrent_phy_write(regmap, CMN_PLL1_VCOCAL_TCTRL, 0x0003);
  937. }
  938. /*
  939. * Set registers responsible for enabling and configuring SSC, with second and
  940. * third register values provided by parameters.
  941. */
  942. static
  943. void cdns_torrent_dp_enable_ssc_19_2mhz(struct cdns_torrent_phy *cdns_phy,
  944. u32 ctrl2_val, u32 ctrl3_val)
  945. {
  946. struct regmap *regmap = cdns_phy->regmap_common_cdb;
  947. cdns_torrent_phy_write(regmap, CMN_PLL0_SS_CTRL1_M0, 0x0001);
  948. cdns_torrent_phy_write(regmap, CMN_PLL0_SS_CTRL1_M0, ctrl2_val);
  949. cdns_torrent_phy_write(regmap, CMN_PLL0_SS_CTRL1_M0, ctrl3_val);
  950. cdns_torrent_phy_write(regmap, CMN_PLL0_SS_CTRL4_M0, 0x0003);
  951. cdns_torrent_phy_write(regmap, CMN_PLL1_SS_CTRL1_M0, 0x0001);
  952. cdns_torrent_phy_write(regmap, CMN_PLL1_SS_CTRL1_M0, ctrl2_val);
  953. cdns_torrent_phy_write(regmap, CMN_PLL1_SS_CTRL1_M0, ctrl3_val);
  954. cdns_torrent_phy_write(regmap, CMN_PLL1_SS_CTRL4_M0, 0x0003);
  955. }
  956. static
  957. void cdns_torrent_dp_pma_cmn_vco_cfg_19_2mhz(struct cdns_torrent_phy *cdns_phy,
  958. u32 rate, bool ssc)
  959. {
  960. struct regmap *regmap = cdns_phy->regmap_common_cdb;
  961. /* Assumes 19.2 MHz refclock */
  962. switch (rate) {
  963. /* Setting VCO for 10.8GHz */
  964. case 2700:
  965. case 5400:
  966. cdns_torrent_phy_write(regmap,
  967. CMN_PLL0_INTDIV_M0, 0x0119);
  968. cdns_torrent_phy_write(regmap,
  969. CMN_PLL0_FRACDIVL_M0, 0x4000);
  970. cdns_torrent_phy_write(regmap,
  971. CMN_PLL0_FRACDIVH_M0, 0x0002);
  972. cdns_torrent_phy_write(regmap,
  973. CMN_PLL0_HIGH_THR_M0, 0x00BC);
  974. cdns_torrent_phy_write(regmap,
  975. CMN_PDIAG_PLL0_CTRL_M0, 0x0012);
  976. cdns_torrent_phy_write(regmap,
  977. CMN_PLL1_INTDIV_M0, 0x0119);
  978. cdns_torrent_phy_write(regmap,
  979. CMN_PLL1_FRACDIVL_M0, 0x4000);
  980. cdns_torrent_phy_write(regmap,
  981. CMN_PLL1_FRACDIVH_M0, 0x0002);
  982. cdns_torrent_phy_write(regmap,
  983. CMN_PLL1_HIGH_THR_M0, 0x00BC);
  984. cdns_torrent_phy_write(regmap,
  985. CMN_PDIAG_PLL1_CTRL_M0, 0x0012);
  986. if (ssc)
  987. cdns_torrent_dp_enable_ssc_19_2mhz(cdns_phy, 0x033A,
  988. 0x006A);
  989. break;
  990. /* Setting VCO for 9.72GHz */
  991. case 1620:
  992. case 2430:
  993. case 3240:
  994. cdns_torrent_phy_write(regmap,
  995. CMN_PLL0_INTDIV_M0, 0x01FA);
  996. cdns_torrent_phy_write(regmap,
  997. CMN_PLL0_FRACDIVL_M0, 0x4000);
  998. cdns_torrent_phy_write(regmap,
  999. CMN_PLL0_FRACDIVH_M0, 0x0002);
  1000. cdns_torrent_phy_write(regmap,
  1001. CMN_PLL0_HIGH_THR_M0, 0x0152);
  1002. cdns_torrent_phy_write(regmap,
  1003. CMN_PDIAG_PLL0_CTRL_M0, 0x0002);
  1004. cdns_torrent_phy_write(regmap,
  1005. CMN_PLL1_INTDIV_M0, 0x01FA);
  1006. cdns_torrent_phy_write(regmap,
  1007. CMN_PLL1_FRACDIVL_M0, 0x4000);
  1008. cdns_torrent_phy_write(regmap,
  1009. CMN_PLL1_FRACDIVH_M0, 0x0002);
  1010. cdns_torrent_phy_write(regmap,
  1011. CMN_PLL1_HIGH_THR_M0, 0x0152);
  1012. cdns_torrent_phy_write(regmap,
  1013. CMN_PDIAG_PLL1_CTRL_M0, 0x0002);
  1014. if (ssc)
  1015. cdns_torrent_dp_enable_ssc_19_2mhz(cdns_phy, 0x05DD,
  1016. 0x0069);
  1017. break;
  1018. /* Setting VCO for 8.64GHz */
  1019. case 2160:
  1020. case 4320:
  1021. cdns_torrent_phy_write(regmap,
  1022. CMN_PLL0_INTDIV_M0, 0x01C2);
  1023. cdns_torrent_phy_write(regmap,
  1024. CMN_PLL0_FRACDIVL_M0, 0x0000);
  1025. cdns_torrent_phy_write(regmap,
  1026. CMN_PLL0_FRACDIVH_M0, 0x0002);
  1027. cdns_torrent_phy_write(regmap,
  1028. CMN_PLL0_HIGH_THR_M0, 0x012C);
  1029. cdns_torrent_phy_write(regmap,
  1030. CMN_PDIAG_PLL0_CTRL_M0, 0x0002);
  1031. cdns_torrent_phy_write(regmap,
  1032. CMN_PLL1_INTDIV_M0, 0x01C2);
  1033. cdns_torrent_phy_write(regmap,
  1034. CMN_PLL1_FRACDIVL_M0, 0x0000);
  1035. cdns_torrent_phy_write(regmap,
  1036. CMN_PLL1_FRACDIVH_M0, 0x0002);
  1037. cdns_torrent_phy_write(regmap,
  1038. CMN_PLL1_HIGH_THR_M0, 0x012C);
  1039. cdns_torrent_phy_write(regmap,
  1040. CMN_PDIAG_PLL1_CTRL_M0, 0x0002);
  1041. if (ssc)
  1042. cdns_torrent_dp_enable_ssc_19_2mhz(cdns_phy, 0x0536,
  1043. 0x0069);
  1044. break;
  1045. /* Setting VCO for 8.1GHz */
  1046. case 8100:
  1047. cdns_torrent_phy_write(regmap,
  1048. CMN_PLL0_INTDIV_M0, 0x01A5);
  1049. cdns_torrent_phy_write(regmap,
  1050. CMN_PLL0_FRACDIVL_M0, 0xE000);
  1051. cdns_torrent_phy_write(regmap,
  1052. CMN_PLL0_FRACDIVH_M0, 0x0002);
  1053. cdns_torrent_phy_write(regmap,
  1054. CMN_PLL0_HIGH_THR_M0, 0x011A);
  1055. cdns_torrent_phy_write(regmap,
  1056. CMN_PDIAG_PLL0_CTRL_M0, 0x0002);
  1057. cdns_torrent_phy_write(regmap,
  1058. CMN_PLL1_INTDIV_M0, 0x01A5);
  1059. cdns_torrent_phy_write(regmap,
  1060. CMN_PLL1_FRACDIVL_M0, 0xE000);
  1061. cdns_torrent_phy_write(regmap,
  1062. CMN_PLL1_FRACDIVH_M0, 0x0002);
  1063. cdns_torrent_phy_write(regmap,
  1064. CMN_PLL1_HIGH_THR_M0, 0x011A);
  1065. cdns_torrent_phy_write(regmap,
  1066. CMN_PDIAG_PLL1_CTRL_M0, 0x0002);
  1067. if (ssc)
  1068. cdns_torrent_dp_enable_ssc_19_2mhz(cdns_phy, 0x04D7,
  1069. 0x006A);
  1070. break;
  1071. }
  1072. if (ssc) {
  1073. cdns_torrent_phy_write(regmap,
  1074. CMN_PLL0_VCOCAL_PLLCNT_START, 0x025E);
  1075. cdns_torrent_phy_write(regmap,
  1076. CMN_PLL0_LOCK_PLLCNT_THR, 0x0005);
  1077. cdns_torrent_phy_write(regmap,
  1078. CMN_PLL1_VCOCAL_PLLCNT_START, 0x025E);
  1079. cdns_torrent_phy_write(regmap,
  1080. CMN_PLL1_LOCK_PLLCNT_THR, 0x0005);
  1081. } else {
  1082. cdns_torrent_phy_write(regmap,
  1083. CMN_PLL0_VCOCAL_PLLCNT_START, 0x0260);
  1084. cdns_torrent_phy_write(regmap,
  1085. CMN_PLL1_VCOCAL_PLLCNT_START, 0x0260);
  1086. /* Set reset register values to disable SSC */
  1087. cdns_torrent_phy_write(regmap,
  1088. CMN_PLL0_SS_CTRL1_M0, 0x0002);
  1089. cdns_torrent_phy_write(regmap,
  1090. CMN_PLL0_SS_CTRL2_M0, 0x0000);
  1091. cdns_torrent_phy_write(regmap,
  1092. CMN_PLL0_SS_CTRL3_M0, 0x0000);
  1093. cdns_torrent_phy_write(regmap,
  1094. CMN_PLL0_SS_CTRL4_M0, 0x0000);
  1095. cdns_torrent_phy_write(regmap,
  1096. CMN_PLL0_LOCK_PLLCNT_THR, 0x0003);
  1097. cdns_torrent_phy_write(regmap,
  1098. CMN_PLL1_SS_CTRL1_M0, 0x0002);
  1099. cdns_torrent_phy_write(regmap,
  1100. CMN_PLL1_SS_CTRL2_M0, 0x0000);
  1101. cdns_torrent_phy_write(regmap,
  1102. CMN_PLL1_SS_CTRL3_M0, 0x0000);
  1103. cdns_torrent_phy_write(regmap,
  1104. CMN_PLL1_SS_CTRL4_M0, 0x0000);
  1105. cdns_torrent_phy_write(regmap,
  1106. CMN_PLL1_LOCK_PLLCNT_THR, 0x0003);
  1107. }
  1108. cdns_torrent_phy_write(regmap, CMN_PLL0_LOCK_REFCNT_START, 0x0099);
  1109. cdns_torrent_phy_write(regmap, CMN_PLL0_LOCK_PLLCNT_START, 0x0099);
  1110. cdns_torrent_phy_write(regmap, CMN_PLL1_LOCK_REFCNT_START, 0x0099);
  1111. cdns_torrent_phy_write(regmap, CMN_PLL1_LOCK_PLLCNT_START, 0x0099);
  1112. }
  1113. static
  1114. void cdns_torrent_dp_pma_cmn_cfg_25mhz(struct cdns_torrent_phy *cdns_phy)
  1115. {
  1116. struct regmap *regmap = cdns_phy->regmap_common_cdb;
  1117. /* refclock registers - assumes 25 MHz refclock */
  1118. cdns_torrent_phy_write(regmap, CMN_SSM_BIAS_TMR, 0x0019);
  1119. cdns_torrent_phy_write(regmap, CMN_PLLSM0_PLLPRE_TMR, 0x0032);
  1120. cdns_torrent_phy_write(regmap, CMN_PLLSM0_PLLLOCK_TMR, 0x00D1);
  1121. cdns_torrent_phy_write(regmap, CMN_PLLSM1_PLLPRE_TMR, 0x0032);
  1122. cdns_torrent_phy_write(regmap, CMN_PLLSM1_PLLLOCK_TMR, 0x00D1);
  1123. cdns_torrent_phy_write(regmap, CMN_BGCAL_INIT_TMR, 0x007D);
  1124. cdns_torrent_phy_write(regmap, CMN_BGCAL_ITER_TMR, 0x007D);
  1125. cdns_torrent_phy_write(regmap, CMN_IBCAL_INIT_TMR, 0x0019);
  1126. cdns_torrent_phy_write(regmap, CMN_TXPUCAL_INIT_TMR, 0x001E);
  1127. cdns_torrent_phy_write(regmap, CMN_TXPUCAL_ITER_TMR, 0x0006);
  1128. cdns_torrent_phy_write(regmap, CMN_TXPDCAL_INIT_TMR, 0x001E);
  1129. cdns_torrent_phy_write(regmap, CMN_TXPDCAL_ITER_TMR, 0x0006);
  1130. cdns_torrent_phy_write(regmap, CMN_RXCAL_INIT_TMR, 0x02EE);
  1131. cdns_torrent_phy_write(regmap, CMN_RXCAL_ITER_TMR, 0x0006);
  1132. cdns_torrent_phy_write(regmap, CMN_SD_CAL_INIT_TMR, 0x0002);
  1133. cdns_torrent_phy_write(regmap, CMN_SD_CAL_ITER_TMR, 0x0002);
  1134. cdns_torrent_phy_write(regmap, CMN_SD_CAL_REFTIM_START, 0x000E);
  1135. cdns_torrent_phy_write(regmap, CMN_SD_CAL_PLLCNT_START, 0x012B);
  1136. /* PLL registers */
  1137. cdns_torrent_phy_write(regmap, CMN_PDIAG_PLL0_CP_PADJ_M0, 0x0509);
  1138. cdns_torrent_phy_write(regmap, CMN_PDIAG_PLL0_CP_IADJ_M0, 0x0F00);
  1139. cdns_torrent_phy_write(regmap, CMN_PDIAG_PLL0_FILT_PADJ_M0, 0x0F08);
  1140. cdns_torrent_phy_write(regmap, CMN_PLL0_DSM_DIAG_M0, 0x0004);
  1141. cdns_torrent_phy_write(regmap, CMN_PDIAG_PLL1_CP_PADJ_M0, 0x0509);
  1142. cdns_torrent_phy_write(regmap, CMN_PDIAG_PLL1_CP_IADJ_M0, 0x0F00);
  1143. cdns_torrent_phy_write(regmap, CMN_PDIAG_PLL1_FILT_PADJ_M0, 0x0F08);
  1144. cdns_torrent_phy_write(regmap, CMN_PLL1_DSM_DIAG_M0, 0x0004);
  1145. cdns_torrent_phy_write(regmap, CMN_PLL0_VCOCAL_INIT_TMR, 0x00FA);
  1146. cdns_torrent_phy_write(regmap, CMN_PLL0_VCOCAL_ITER_TMR, 0x0004);
  1147. cdns_torrent_phy_write(regmap, CMN_PLL1_VCOCAL_INIT_TMR, 0x00FA);
  1148. cdns_torrent_phy_write(regmap, CMN_PLL1_VCOCAL_ITER_TMR, 0x0004);
  1149. cdns_torrent_phy_write(regmap, CMN_PLL0_VCOCAL_REFTIM_START, 0x0317);
  1150. cdns_torrent_phy_write(regmap, CMN_PLL0_VCOCAL_TCTRL, 0x0003);
  1151. cdns_torrent_phy_write(regmap, CMN_PLL1_VCOCAL_REFTIM_START, 0x0317);
  1152. cdns_torrent_phy_write(regmap, CMN_PLL1_VCOCAL_TCTRL, 0x0003);
  1153. }
  1154. /*
  1155. * Set registers responsible for enabling and configuring SSC, with second
  1156. * register value provided by a parameter.
  1157. */
  1158. static void cdns_torrent_dp_enable_ssc_25mhz(struct cdns_torrent_phy *cdns_phy,
  1159. u32 ctrl2_val)
  1160. {
  1161. struct regmap *regmap = cdns_phy->regmap_common_cdb;
  1162. cdns_torrent_phy_write(regmap, CMN_PLL0_SS_CTRL1_M0, 0x0001);
  1163. cdns_torrent_phy_write(regmap, CMN_PLL0_SS_CTRL1_M0, ctrl2_val);
  1164. cdns_torrent_phy_write(regmap, CMN_PLL0_SS_CTRL1_M0, 0x007F);
  1165. cdns_torrent_phy_write(regmap, CMN_PLL0_SS_CTRL4_M0, 0x0003);
  1166. cdns_torrent_phy_write(regmap, CMN_PLL1_SS_CTRL1_M0, 0x0001);
  1167. cdns_torrent_phy_write(regmap, CMN_PLL1_SS_CTRL1_M0, ctrl2_val);
  1168. cdns_torrent_phy_write(regmap, CMN_PLL1_SS_CTRL1_M0, 0x007F);
  1169. cdns_torrent_phy_write(regmap, CMN_PLL1_SS_CTRL4_M0, 0x0003);
  1170. }
  1171. static
  1172. void cdns_torrent_dp_pma_cmn_vco_cfg_25mhz(struct cdns_torrent_phy *cdns_phy,
  1173. u32 rate, bool ssc)
  1174. {
  1175. struct regmap *regmap = cdns_phy->regmap_common_cdb;
  1176. /* Assumes 25 MHz refclock */
  1177. switch (rate) {
  1178. /* Setting VCO for 10.8GHz */
  1179. case 2700:
  1180. case 5400:
  1181. cdns_torrent_phy_write(regmap, CMN_PLL0_INTDIV_M0, 0x01B0);
  1182. cdns_torrent_phy_write(regmap, CMN_PLL0_FRACDIVL_M0, 0x0000);
  1183. cdns_torrent_phy_write(regmap, CMN_PLL0_FRACDIVH_M0, 0x0002);
  1184. cdns_torrent_phy_write(regmap, CMN_PLL0_HIGH_THR_M0, 0x0120);
  1185. cdns_torrent_phy_write(regmap, CMN_PLL1_INTDIV_M0, 0x01B0);
  1186. cdns_torrent_phy_write(regmap, CMN_PLL1_FRACDIVL_M0, 0x0000);
  1187. cdns_torrent_phy_write(regmap, CMN_PLL1_FRACDIVH_M0, 0x0002);
  1188. cdns_torrent_phy_write(regmap, CMN_PLL1_HIGH_THR_M0, 0x0120);
  1189. if (ssc)
  1190. cdns_torrent_dp_enable_ssc_25mhz(cdns_phy, 0x0423);
  1191. break;
  1192. /* Setting VCO for 9.72GHz */
  1193. case 1620:
  1194. case 2430:
  1195. case 3240:
  1196. cdns_torrent_phy_write(regmap, CMN_PLL0_INTDIV_M0, 0x0184);
  1197. cdns_torrent_phy_write(regmap, CMN_PLL0_FRACDIVL_M0, 0xCCCD);
  1198. cdns_torrent_phy_write(regmap, CMN_PLL0_FRACDIVH_M0, 0x0002);
  1199. cdns_torrent_phy_write(regmap, CMN_PLL0_HIGH_THR_M0, 0x0104);
  1200. cdns_torrent_phy_write(regmap, CMN_PLL1_INTDIV_M0, 0x0184);
  1201. cdns_torrent_phy_write(regmap, CMN_PLL1_FRACDIVL_M0, 0xCCCD);
  1202. cdns_torrent_phy_write(regmap, CMN_PLL1_FRACDIVH_M0, 0x0002);
  1203. cdns_torrent_phy_write(regmap, CMN_PLL1_HIGH_THR_M0, 0x0104);
  1204. if (ssc)
  1205. cdns_torrent_dp_enable_ssc_25mhz(cdns_phy, 0x03B9);
  1206. break;
  1207. /* Setting VCO for 8.64GHz */
  1208. case 2160:
  1209. case 4320:
  1210. cdns_torrent_phy_write(regmap, CMN_PLL0_INTDIV_M0, 0x0159);
  1211. cdns_torrent_phy_write(regmap, CMN_PLL0_FRACDIVL_M0, 0x999A);
  1212. cdns_torrent_phy_write(regmap, CMN_PLL0_FRACDIVH_M0, 0x0002);
  1213. cdns_torrent_phy_write(regmap, CMN_PLL0_HIGH_THR_M0, 0x00E7);
  1214. cdns_torrent_phy_write(regmap, CMN_PLL1_INTDIV_M0, 0x0159);
  1215. cdns_torrent_phy_write(regmap, CMN_PLL1_FRACDIVL_M0, 0x999A);
  1216. cdns_torrent_phy_write(regmap, CMN_PLL1_FRACDIVH_M0, 0x0002);
  1217. cdns_torrent_phy_write(regmap, CMN_PLL1_HIGH_THR_M0, 0x00E7);
  1218. if (ssc)
  1219. cdns_torrent_dp_enable_ssc_25mhz(cdns_phy, 0x034F);
  1220. break;
  1221. /* Setting VCO for 8.1GHz */
  1222. case 8100:
  1223. cdns_torrent_phy_write(regmap, CMN_PLL0_INTDIV_M0, 0x0144);
  1224. cdns_torrent_phy_write(regmap, CMN_PLL0_FRACDIVL_M0, 0x0000);
  1225. cdns_torrent_phy_write(regmap, CMN_PLL0_FRACDIVH_M0, 0x0002);
  1226. cdns_torrent_phy_write(regmap, CMN_PLL0_HIGH_THR_M0, 0x00D8);
  1227. cdns_torrent_phy_write(regmap, CMN_PLL1_INTDIV_M0, 0x0144);
  1228. cdns_torrent_phy_write(regmap, CMN_PLL1_FRACDIVL_M0, 0x0000);
  1229. cdns_torrent_phy_write(regmap, CMN_PLL1_FRACDIVH_M0, 0x0002);
  1230. cdns_torrent_phy_write(regmap, CMN_PLL1_HIGH_THR_M0, 0x00D8);
  1231. if (ssc)
  1232. cdns_torrent_dp_enable_ssc_25mhz(cdns_phy, 0x031A);
  1233. break;
  1234. }
  1235. cdns_torrent_phy_write(regmap, CMN_PDIAG_PLL0_CTRL_M0, 0x0002);
  1236. cdns_torrent_phy_write(regmap, CMN_PDIAG_PLL1_CTRL_M0, 0x0002);
  1237. if (ssc) {
  1238. cdns_torrent_phy_write(regmap,
  1239. CMN_PLL0_VCOCAL_PLLCNT_START, 0x0315);
  1240. cdns_torrent_phy_write(regmap,
  1241. CMN_PLL0_LOCK_PLLCNT_THR, 0x0005);
  1242. cdns_torrent_phy_write(regmap,
  1243. CMN_PLL1_VCOCAL_PLLCNT_START, 0x0315);
  1244. cdns_torrent_phy_write(regmap,
  1245. CMN_PLL1_LOCK_PLLCNT_THR, 0x0005);
  1246. } else {
  1247. cdns_torrent_phy_write(regmap,
  1248. CMN_PLL0_VCOCAL_PLLCNT_START, 0x0317);
  1249. cdns_torrent_phy_write(regmap,
  1250. CMN_PLL1_VCOCAL_PLLCNT_START, 0x0317);
  1251. /* Set reset register values to disable SSC */
  1252. cdns_torrent_phy_write(regmap, CMN_PLL0_SS_CTRL1_M0, 0x0002);
  1253. cdns_torrent_phy_write(regmap, CMN_PLL0_SS_CTRL2_M0, 0x0000);
  1254. cdns_torrent_phy_write(regmap, CMN_PLL0_SS_CTRL3_M0, 0x0000);
  1255. cdns_torrent_phy_write(regmap, CMN_PLL0_SS_CTRL4_M0, 0x0000);
  1256. cdns_torrent_phy_write(regmap,
  1257. CMN_PLL0_LOCK_PLLCNT_THR, 0x0003);
  1258. cdns_torrent_phy_write(regmap, CMN_PLL1_SS_CTRL1_M0, 0x0002);
  1259. cdns_torrent_phy_write(regmap, CMN_PLL1_SS_CTRL2_M0, 0x0000);
  1260. cdns_torrent_phy_write(regmap, CMN_PLL1_SS_CTRL3_M0, 0x0000);
  1261. cdns_torrent_phy_write(regmap, CMN_PLL1_SS_CTRL4_M0, 0x0000);
  1262. cdns_torrent_phy_write(regmap,
  1263. CMN_PLL1_LOCK_PLLCNT_THR, 0x0003);
  1264. }
  1265. cdns_torrent_phy_write(regmap, CMN_PLL0_LOCK_REFCNT_START, 0x00C7);
  1266. cdns_torrent_phy_write(regmap, CMN_PLL0_LOCK_PLLCNT_START, 0x00C7);
  1267. cdns_torrent_phy_write(regmap, CMN_PLL1_LOCK_REFCNT_START, 0x00C7);
  1268. cdns_torrent_phy_write(regmap, CMN_PLL1_LOCK_PLLCNT_START, 0x00C7);
  1269. }
  1270. static void cdns_torrent_dp_pma_cmn_rate(struct cdns_torrent_phy *cdns_phy,
  1271. u32 rate, u32 num_lanes)
  1272. {
  1273. unsigned int clk_sel_val = 0;
  1274. unsigned int hsclk_div_val = 0;
  1275. unsigned int i;
  1276. /* 16'h0000 for single DP link configuration */
  1277. regmap_field_write(cdns_phy->phy_pll_cfg, 0x0);
  1278. switch (rate) {
  1279. case 1620:
  1280. clk_sel_val = 0x0f01;
  1281. hsclk_div_val = 2;
  1282. break;
  1283. case 2160:
  1284. case 2430:
  1285. case 2700:
  1286. clk_sel_val = 0x0701;
  1287. hsclk_div_val = 1;
  1288. break;
  1289. case 3240:
  1290. clk_sel_val = 0x0b00;
  1291. hsclk_div_val = 2;
  1292. break;
  1293. case 4320:
  1294. case 5400:
  1295. clk_sel_val = 0x0301;
  1296. hsclk_div_val = 0;
  1297. break;
  1298. case 8100:
  1299. clk_sel_val = 0x0200;
  1300. hsclk_div_val = 0;
  1301. break;
  1302. }
  1303. cdns_torrent_phy_write(cdns_phy->regmap_common_cdb,
  1304. CMN_PDIAG_PLL0_CLK_SEL_M0, clk_sel_val);
  1305. cdns_torrent_phy_write(cdns_phy->regmap_common_cdb,
  1306. CMN_PDIAG_PLL1_CLK_SEL_M0, clk_sel_val);
  1307. /* PMA lane configuration to deal with multi-link operation */
  1308. for (i = 0; i < num_lanes; i++)
  1309. cdns_torrent_phy_write(cdns_phy->regmap_tx_lane_cdb[i],
  1310. XCVR_DIAG_HSCLK_DIV, hsclk_div_val);
  1311. }
  1312. static void cdns_torrent_dp_pma_lane_cfg(struct cdns_torrent_phy *cdns_phy,
  1313. unsigned int lane)
  1314. {
  1315. /* Per lane, refclock-dependent receiver detection setting */
  1316. if (cdns_phy->ref_clk_rate == REF_CLK_19_2MHz)
  1317. cdns_torrent_phy_write(cdns_phy->regmap_tx_lane_cdb[lane],
  1318. TX_RCVDET_ST_TMR, 0x0780);
  1319. else if (cdns_phy->ref_clk_rate == REF_CLK_25MHz)
  1320. cdns_torrent_phy_write(cdns_phy->regmap_tx_lane_cdb[lane],
  1321. TX_RCVDET_ST_TMR, 0x09C4);
  1322. /* Writing Tx/Rx Power State Controllers registers */
  1323. cdns_torrent_phy_write(cdns_phy->regmap_tx_lane_cdb[lane],
  1324. TX_PSC_A0, 0x00FB);
  1325. cdns_torrent_phy_write(cdns_phy->regmap_tx_lane_cdb[lane],
  1326. TX_PSC_A2, 0x04AA);
  1327. cdns_torrent_phy_write(cdns_phy->regmap_tx_lane_cdb[lane],
  1328. TX_PSC_A3, 0x04AA);
  1329. cdns_torrent_phy_write(cdns_phy->regmap_rx_lane_cdb[lane],
  1330. RX_PSC_A0, 0x0000);
  1331. cdns_torrent_phy_write(cdns_phy->regmap_rx_lane_cdb[lane],
  1332. RX_PSC_A2, 0x0000);
  1333. cdns_torrent_phy_write(cdns_phy->regmap_rx_lane_cdb[lane],
  1334. RX_PSC_A3, 0x0000);
  1335. cdns_torrent_phy_write(cdns_phy->regmap_rx_lane_cdb[lane],
  1336. RX_PSC_CAL, 0x0000);
  1337. cdns_torrent_phy_write(cdns_phy->regmap_rx_lane_cdb[lane],
  1338. RX_REE_GCSM1_CTRL, 0x0000);
  1339. cdns_torrent_phy_write(cdns_phy->regmap_rx_lane_cdb[lane],
  1340. RX_REE_GCSM2_CTRL, 0x0000);
  1341. cdns_torrent_phy_write(cdns_phy->regmap_rx_lane_cdb[lane],
  1342. RX_REE_PERGCSM_CTRL, 0x0000);
  1343. cdns_torrent_phy_write(cdns_phy->regmap_tx_lane_cdb[lane],
  1344. XCVR_DIAG_BIDI_CTRL, 0x000F);
  1345. cdns_torrent_phy_write(cdns_phy->regmap_tx_lane_cdb[lane],
  1346. XCVR_DIAG_PLLDRC_CTRL, 0x0001);
  1347. cdns_torrent_phy_write(cdns_phy->regmap_tx_lane_cdb[lane],
  1348. XCVR_DIAG_HSCLK_SEL, 0x0000);
  1349. }
  1350. static int cdns_torrent_dp_set_power_state(struct cdns_torrent_phy *cdns_phy,
  1351. u32 num_lanes,
  1352. enum phy_powerstate powerstate)
  1353. {
  1354. /* Register value for power state for a single byte. */
  1355. u32 value_part;
  1356. u32 value;
  1357. u32 mask;
  1358. u32 read_val;
  1359. u32 ret;
  1360. struct regmap *regmap = cdns_phy->regmap_dptx_phy_reg;
  1361. switch (powerstate) {
  1362. case (POWERSTATE_A0):
  1363. value_part = 0x01U;
  1364. break;
  1365. case (POWERSTATE_A2):
  1366. value_part = 0x04U;
  1367. break;
  1368. default:
  1369. /* Powerstate A3 */
  1370. value_part = 0x08U;
  1371. break;
  1372. }
  1373. /* Select values of registers and mask, depending on enabled
  1374. * lane count.
  1375. */
  1376. switch (num_lanes) {
  1377. /* lane 0 */
  1378. case (1):
  1379. value = value_part;
  1380. mask = 0x0000003FU;
  1381. break;
  1382. /* lanes 0-1 */
  1383. case (2):
  1384. value = (value_part
  1385. | (value_part << 8));
  1386. mask = 0x00003F3FU;
  1387. break;
  1388. /* lanes 0-3, all */
  1389. default:
  1390. value = (value_part
  1391. | (value_part << 8)
  1392. | (value_part << 16)
  1393. | (value_part << 24));
  1394. mask = 0x3F3F3F3FU;
  1395. break;
  1396. }
  1397. /* Set power state A<n>. */
  1398. cdns_torrent_dp_write(regmap, PHY_PMA_XCVR_POWER_STATE_REQ, value);
  1399. /* Wait, until PHY acknowledges power state completion. */
  1400. ret = regmap_read_poll_timeout(regmap, PHY_PMA_XCVR_POWER_STATE_ACK,
  1401. read_val, (read_val & mask) == value, 0,
  1402. POLL_TIMEOUT_US);
  1403. cdns_torrent_dp_write(regmap, PHY_PMA_XCVR_POWER_STATE_REQ, 0x00000000);
  1404. ndelay(100);
  1405. return ret;
  1406. }
  1407. static int cdns_torrent_dp_run(struct cdns_torrent_phy *cdns_phy, u32 num_lanes)
  1408. {
  1409. unsigned int read_val;
  1410. int ret;
  1411. struct regmap *regmap = cdns_phy->regmap_dptx_phy_reg;
  1412. /*
  1413. * waiting for ACK of pma_xcvr_pllclk_en_ln_*, only for the
  1414. * master lane
  1415. */
  1416. ret = regmap_read_poll_timeout(regmap, PHY_PMA_XCVR_PLLCLK_EN_ACK,
  1417. read_val, read_val & 1,
  1418. 0, POLL_TIMEOUT_US);
  1419. if (ret == -ETIMEDOUT) {
  1420. dev_err(cdns_phy->dev,
  1421. "timeout waiting for link PLL clock enable ack\n");
  1422. return ret;
  1423. }
  1424. ndelay(100);
  1425. ret = cdns_torrent_dp_set_power_state(cdns_phy, num_lanes,
  1426. POWERSTATE_A2);
  1427. if (ret)
  1428. return ret;
  1429. ret = cdns_torrent_dp_set_power_state(cdns_phy, num_lanes,
  1430. POWERSTATE_A0);
  1431. return ret;
  1432. }
  1433. static int cdns_torrent_phy_on(struct phy *phy)
  1434. {
  1435. struct cdns_torrent_inst *inst = phy_get_drvdata(phy);
  1436. struct cdns_torrent_phy *cdns_phy = dev_get_drvdata(phy->dev.parent);
  1437. u32 read_val;
  1438. int ret;
  1439. if (cdns_phy->nsubnodes == 1) {
  1440. /* Take the PHY lane group out of reset */
  1441. reset_control_deassert(inst->lnk_rst);
  1442. /* Take the PHY out of reset */
  1443. ret = reset_control_deassert(cdns_phy->phy_rst);
  1444. if (ret)
  1445. return ret;
  1446. }
  1447. /*
  1448. * Wait for cmn_ready assertion
  1449. * PHY_PMA_CMN_CTRL1[0] == 1
  1450. */
  1451. ret = regmap_field_read_poll_timeout(cdns_phy->phy_pma_cmn_ctrl_1,
  1452. read_val, read_val, 1000,
  1453. PLL_LOCK_TIMEOUT);
  1454. if (ret) {
  1455. dev_err(cdns_phy->dev, "Timeout waiting for CMN ready\n");
  1456. return ret;
  1457. }
  1458. mdelay(10);
  1459. return 0;
  1460. }
  1461. static int cdns_torrent_phy_off(struct phy *phy)
  1462. {
  1463. struct cdns_torrent_inst *inst = phy_get_drvdata(phy);
  1464. struct cdns_torrent_phy *cdns_phy = dev_get_drvdata(phy->dev.parent);
  1465. int ret;
  1466. if (cdns_phy->nsubnodes != 1)
  1467. return 0;
  1468. ret = reset_control_assert(cdns_phy->phy_rst);
  1469. if (ret)
  1470. return ret;
  1471. return reset_control_assert(inst->lnk_rst);
  1472. }
  1473. static struct regmap *cdns_regmap_init(struct device *dev, void __iomem *base,
  1474. u32 block_offset,
  1475. u8 reg_offset_shift,
  1476. const struct regmap_config *config)
  1477. {
  1478. struct cdns_regmap_cdb_context *ctx;
  1479. ctx = devm_kzalloc(dev, sizeof(*ctx), GFP_KERNEL);
  1480. if (!ctx)
  1481. return ERR_PTR(-ENOMEM);
  1482. ctx->dev = dev;
  1483. ctx->base = base + block_offset;
  1484. ctx->reg_offset_shift = reg_offset_shift;
  1485. return devm_regmap_init(dev, NULL, ctx, config);
  1486. }
  1487. static int cdns_torrent_dp_regfield_init(struct cdns_torrent_phy *cdns_phy)
  1488. {
  1489. struct device *dev = cdns_phy->dev;
  1490. struct regmap_field *field;
  1491. struct regmap *regmap;
  1492. regmap = cdns_phy->regmap_dptx_phy_reg;
  1493. field = devm_regmap_field_alloc(dev, regmap, phy_reset_ctrl);
  1494. if (IS_ERR(field)) {
  1495. dev_err(dev, "PHY_RESET reg field init failed\n");
  1496. return PTR_ERR(field);
  1497. }
  1498. cdns_phy->phy_reset_ctrl = field;
  1499. return 0;
  1500. }
  1501. static int cdns_torrent_regfield_init(struct cdns_torrent_phy *cdns_phy)
  1502. {
  1503. struct device *dev = cdns_phy->dev;
  1504. struct regmap_field *field;
  1505. struct regmap *regmap;
  1506. regmap = cdns_phy->regmap_phy_pcs_common_cdb;
  1507. field = devm_regmap_field_alloc(dev, regmap, phy_pll_cfg);
  1508. if (IS_ERR(field)) {
  1509. dev_err(dev, "PHY_PLL_CFG reg field init failed\n");
  1510. return PTR_ERR(field);
  1511. }
  1512. cdns_phy->phy_pll_cfg = field;
  1513. regmap = cdns_phy->regmap_phy_pma_common_cdb;
  1514. field = devm_regmap_field_alloc(dev, regmap, phy_pma_cmn_ctrl_1);
  1515. if (IS_ERR(field)) {
  1516. dev_err(dev, "PHY_PMA_CMN_CTRL1 reg field init failed\n");
  1517. return PTR_ERR(field);
  1518. }
  1519. cdns_phy->phy_pma_cmn_ctrl_1 = field;
  1520. regmap = cdns_phy->regmap_phy_pma_common_cdb;
  1521. field = devm_regmap_field_alloc(dev, regmap, phy_pma_cmn_ctrl_2);
  1522. if (IS_ERR(field)) {
  1523. dev_err(dev, "PHY_PMA_CMN_CTRL2 reg field init failed\n");
  1524. return PTR_ERR(field);
  1525. }
  1526. cdns_phy->phy_pma_cmn_ctrl_2 = field;
  1527. regmap = cdns_phy->regmap_phy_pma_common_cdb;
  1528. field = devm_regmap_field_alloc(dev, regmap, phy_pma_pll_raw_ctrl);
  1529. if (IS_ERR(field)) {
  1530. dev_err(dev, "PHY_PMA_PLL_RAW_CTRL reg field init failed\n");
  1531. return PTR_ERR(field);
  1532. }
  1533. cdns_phy->phy_pma_pll_raw_ctrl = field;
  1534. return 0;
  1535. }
  1536. static int cdns_torrent_dp_regmap_init(struct cdns_torrent_phy *cdns_phy)
  1537. {
  1538. void __iomem *base = cdns_phy->base;
  1539. struct device *dev = cdns_phy->dev;
  1540. struct regmap *regmap;
  1541. u8 reg_offset_shift;
  1542. u32 block_offset;
  1543. reg_offset_shift = cdns_phy->init_data->reg_offset_shift;
  1544. block_offset = TORRENT_DPTX_PHY_OFFSET;
  1545. regmap = cdns_regmap_init(dev, base, block_offset,
  1546. reg_offset_shift,
  1547. &cdns_torrent_dptx_phy_config);
  1548. if (IS_ERR(regmap)) {
  1549. dev_err(dev, "Failed to init DPTX PHY regmap\n");
  1550. return PTR_ERR(regmap);
  1551. }
  1552. cdns_phy->regmap_dptx_phy_reg = regmap;
  1553. return 0;
  1554. }
  1555. static int cdns_torrent_regmap_init(struct cdns_torrent_phy *cdns_phy)
  1556. {
  1557. void __iomem *sd_base = cdns_phy->sd_base;
  1558. u8 block_offset_shift, reg_offset_shift;
  1559. struct device *dev = cdns_phy->dev;
  1560. struct regmap *regmap;
  1561. u32 block_offset;
  1562. int i;
  1563. block_offset_shift = cdns_phy->init_data->block_offset_shift;
  1564. reg_offset_shift = cdns_phy->init_data->reg_offset_shift;
  1565. for (i = 0; i < MAX_NUM_LANES; i++) {
  1566. block_offset = TORRENT_TX_LANE_CDB_OFFSET(i, block_offset_shift,
  1567. reg_offset_shift);
  1568. regmap = cdns_regmap_init(dev, sd_base, block_offset,
  1569. reg_offset_shift,
  1570. &cdns_torrent_tx_lane_cdb_config[i]);
  1571. if (IS_ERR(regmap)) {
  1572. dev_err(dev, "Failed to init tx lane CDB regmap\n");
  1573. return PTR_ERR(regmap);
  1574. }
  1575. cdns_phy->regmap_tx_lane_cdb[i] = regmap;
  1576. block_offset = TORRENT_RX_LANE_CDB_OFFSET(i, block_offset_shift,
  1577. reg_offset_shift);
  1578. regmap = cdns_regmap_init(dev, sd_base, block_offset,
  1579. reg_offset_shift,
  1580. &cdns_torrent_rx_lane_cdb_config[i]);
  1581. if (IS_ERR(regmap)) {
  1582. dev_err(dev, "Failed to init rx lane CDB regmap\n");
  1583. return PTR_ERR(regmap);
  1584. }
  1585. cdns_phy->regmap_rx_lane_cdb[i] = regmap;
  1586. }
  1587. block_offset = TORRENT_COMMON_CDB_OFFSET;
  1588. regmap = cdns_regmap_init(dev, sd_base, block_offset,
  1589. reg_offset_shift,
  1590. &cdns_torrent_common_cdb_config);
  1591. if (IS_ERR(regmap)) {
  1592. dev_err(dev, "Failed to init common CDB regmap\n");
  1593. return PTR_ERR(regmap);
  1594. }
  1595. cdns_phy->regmap_common_cdb = regmap;
  1596. block_offset = TORRENT_PHY_PCS_COMMON_OFFSET(block_offset_shift);
  1597. regmap = cdns_regmap_init(dev, sd_base, block_offset,
  1598. reg_offset_shift,
  1599. &cdns_torrent_phy_pcs_cmn_cdb_config);
  1600. if (IS_ERR(regmap)) {
  1601. dev_err(dev, "Failed to init PHY PCS common CDB regmap\n");
  1602. return PTR_ERR(regmap);
  1603. }
  1604. cdns_phy->regmap_phy_pcs_common_cdb = regmap;
  1605. block_offset = TORRENT_PHY_PMA_COMMON_OFFSET(block_offset_shift);
  1606. regmap = cdns_regmap_init(dev, sd_base, block_offset,
  1607. reg_offset_shift,
  1608. &cdns_torrent_phy_pma_cmn_cdb_config);
  1609. if (IS_ERR(regmap)) {
  1610. dev_err(dev, "Failed to init PHY PMA common CDB regmap\n");
  1611. return PTR_ERR(regmap);
  1612. }
  1613. cdns_phy->regmap_phy_pma_common_cdb = regmap;
  1614. return 0;
  1615. }
  1616. static int cdns_torrent_phy_init(struct phy *phy)
  1617. {
  1618. struct cdns_torrent_phy *cdns_phy = dev_get_drvdata(phy->dev.parent);
  1619. const struct cdns_torrent_data *init_data = cdns_phy->init_data;
  1620. struct cdns_torrent_vals *cmn_vals, *tx_ln_vals, *rx_ln_vals;
  1621. struct cdns_torrent_vals *link_cmn_vals, *xcvr_diag_vals;
  1622. struct cdns_torrent_inst *inst = phy_get_drvdata(phy);
  1623. enum cdns_torrent_phy_type phy_type = inst->phy_type;
  1624. enum cdns_torrent_ssc_mode ssc = inst->ssc_mode;
  1625. struct cdns_torrent_vals *pcs_cmn_vals;
  1626. struct cdns_reg_pairs *reg_pairs;
  1627. struct regmap *regmap;
  1628. u32 num_regs;
  1629. int i, j;
  1630. if (cdns_phy->nsubnodes > 1)
  1631. return 0;
  1632. if (phy_type == TYPE_DP)
  1633. return cdns_torrent_dp_init(phy);
  1634. /**
  1635. * Spread spectrum generation is not required or supported
  1636. * for SGMII/QSGMII
  1637. */
  1638. if (phy_type == TYPE_SGMII || phy_type == TYPE_QSGMII)
  1639. ssc = NO_SSC;
  1640. /* PHY configuration specific registers for single link */
  1641. link_cmn_vals = init_data->link_cmn_vals[phy_type][TYPE_NONE][ssc];
  1642. if (link_cmn_vals) {
  1643. reg_pairs = link_cmn_vals->reg_pairs;
  1644. num_regs = link_cmn_vals->num_regs;
  1645. regmap = cdns_phy->regmap_common_cdb;
  1646. /**
  1647. * First array value in link_cmn_vals must be of
  1648. * PHY_PLL_CFG register
  1649. */
  1650. regmap_field_write(cdns_phy->phy_pll_cfg, reg_pairs[0].val);
  1651. for (i = 1; i < num_regs; i++)
  1652. regmap_write(regmap, reg_pairs[i].off,
  1653. reg_pairs[i].val);
  1654. }
  1655. xcvr_diag_vals = init_data->xcvr_diag_vals[phy_type][TYPE_NONE][ssc];
  1656. if (xcvr_diag_vals) {
  1657. reg_pairs = xcvr_diag_vals->reg_pairs;
  1658. num_regs = xcvr_diag_vals->num_regs;
  1659. for (i = 0; i < inst->num_lanes; i++) {
  1660. regmap = cdns_phy->regmap_tx_lane_cdb[i + inst->mlane];
  1661. for (j = 0; j < num_regs; j++)
  1662. regmap_write(regmap, reg_pairs[j].off,
  1663. reg_pairs[j].val);
  1664. }
  1665. }
  1666. /* PHY PCS common registers configurations */
  1667. pcs_cmn_vals = init_data->pcs_cmn_vals[phy_type][TYPE_NONE][ssc];
  1668. if (pcs_cmn_vals) {
  1669. reg_pairs = pcs_cmn_vals->reg_pairs;
  1670. num_regs = pcs_cmn_vals->num_regs;
  1671. regmap = cdns_phy->regmap_phy_pcs_common_cdb;
  1672. for (i = 0; i < num_regs; i++)
  1673. regmap_write(regmap, reg_pairs[i].off,
  1674. reg_pairs[i].val);
  1675. }
  1676. /* PMA common registers configurations */
  1677. cmn_vals = init_data->cmn_vals[phy_type][TYPE_NONE][ssc];
  1678. if (cmn_vals) {
  1679. reg_pairs = cmn_vals->reg_pairs;
  1680. num_regs = cmn_vals->num_regs;
  1681. regmap = cdns_phy->regmap_common_cdb;
  1682. for (i = 0; i < num_regs; i++)
  1683. regmap_write(regmap, reg_pairs[i].off,
  1684. reg_pairs[i].val);
  1685. }
  1686. /* PMA TX lane registers configurations */
  1687. tx_ln_vals = init_data->tx_ln_vals[phy_type][TYPE_NONE][ssc];
  1688. if (tx_ln_vals) {
  1689. reg_pairs = tx_ln_vals->reg_pairs;
  1690. num_regs = tx_ln_vals->num_regs;
  1691. for (i = 0; i < inst->num_lanes; i++) {
  1692. regmap = cdns_phy->regmap_tx_lane_cdb[i + inst->mlane];
  1693. for (j = 0; j < num_regs; j++)
  1694. regmap_write(regmap, reg_pairs[j].off,
  1695. reg_pairs[j].val);
  1696. }
  1697. }
  1698. /* PMA RX lane registers configurations */
  1699. rx_ln_vals = init_data->rx_ln_vals[phy_type][TYPE_NONE][ssc];
  1700. if (rx_ln_vals) {
  1701. reg_pairs = rx_ln_vals->reg_pairs;
  1702. num_regs = rx_ln_vals->num_regs;
  1703. for (i = 0; i < inst->num_lanes; i++) {
  1704. regmap = cdns_phy->regmap_rx_lane_cdb[i + inst->mlane];
  1705. for (j = 0; j < num_regs; j++)
  1706. regmap_write(regmap, reg_pairs[j].off,
  1707. reg_pairs[j].val);
  1708. }
  1709. }
  1710. return 0;
  1711. }
  1712. static
  1713. int cdns_torrent_phy_configure_multilink(struct cdns_torrent_phy *cdns_phy)
  1714. {
  1715. const struct cdns_torrent_data *init_data = cdns_phy->init_data;
  1716. struct cdns_torrent_vals *cmn_vals, *tx_ln_vals, *rx_ln_vals;
  1717. struct cdns_torrent_vals *link_cmn_vals, *xcvr_diag_vals;
  1718. enum cdns_torrent_phy_type phy_t1, phy_t2, tmp_phy_type;
  1719. struct cdns_torrent_vals *pcs_cmn_vals;
  1720. int i, j, node, mlane, num_lanes, ret;
  1721. struct cdns_reg_pairs *reg_pairs;
  1722. enum cdns_torrent_ssc_mode ssc;
  1723. struct regmap *regmap;
  1724. u32 num_regs;
  1725. /* Maximum 2 links (subnodes) are supported */
  1726. if (cdns_phy->nsubnodes != 2)
  1727. return -EINVAL;
  1728. phy_t1 = cdns_phy->phys[0].phy_type;
  1729. phy_t2 = cdns_phy->phys[1].phy_type;
  1730. /**
  1731. * First configure the PHY for first link with phy_t1. Get the array
  1732. * values as [phy_t1][phy_t2][ssc].
  1733. */
  1734. for (node = 0; node < cdns_phy->nsubnodes; node++) {
  1735. if (node == 1) {
  1736. /**
  1737. * If first link with phy_t1 is configured, then
  1738. * configure the PHY for second link with phy_t2.
  1739. * Get the array values as [phy_t2][phy_t1][ssc].
  1740. */
  1741. tmp_phy_type = phy_t1;
  1742. phy_t1 = phy_t2;
  1743. phy_t2 = tmp_phy_type;
  1744. }
  1745. mlane = cdns_phy->phys[node].mlane;
  1746. ssc = cdns_phy->phys[node].ssc_mode;
  1747. num_lanes = cdns_phy->phys[node].num_lanes;
  1748. /**
  1749. * PHY configuration specific registers:
  1750. * link_cmn_vals depend on combination of PHY types being
  1751. * configured and are common for both PHY types, so array
  1752. * values should be same for [phy_t1][phy_t2][ssc] and
  1753. * [phy_t2][phy_t1][ssc].
  1754. * xcvr_diag_vals also depend on combination of PHY types
  1755. * being configured, but these can be different for particular
  1756. * PHY type and are per lane.
  1757. */
  1758. link_cmn_vals = init_data->link_cmn_vals[phy_t1][phy_t2][ssc];
  1759. if (link_cmn_vals) {
  1760. reg_pairs = link_cmn_vals->reg_pairs;
  1761. num_regs = link_cmn_vals->num_regs;
  1762. regmap = cdns_phy->regmap_common_cdb;
  1763. /**
  1764. * First array value in link_cmn_vals must be of
  1765. * PHY_PLL_CFG register
  1766. */
  1767. regmap_field_write(cdns_phy->phy_pll_cfg,
  1768. reg_pairs[0].val);
  1769. for (i = 1; i < num_regs; i++)
  1770. regmap_write(regmap, reg_pairs[i].off,
  1771. reg_pairs[i].val);
  1772. }
  1773. xcvr_diag_vals = init_data->xcvr_diag_vals[phy_t1][phy_t2][ssc];
  1774. if (xcvr_diag_vals) {
  1775. reg_pairs = xcvr_diag_vals->reg_pairs;
  1776. num_regs = xcvr_diag_vals->num_regs;
  1777. for (i = 0; i < num_lanes; i++) {
  1778. regmap = cdns_phy->regmap_tx_lane_cdb[i + mlane];
  1779. for (j = 0; j < num_regs; j++)
  1780. regmap_write(regmap, reg_pairs[j].off,
  1781. reg_pairs[j].val);
  1782. }
  1783. }
  1784. /* PHY PCS common registers configurations */
  1785. pcs_cmn_vals = init_data->pcs_cmn_vals[phy_t1][phy_t2][ssc];
  1786. if (pcs_cmn_vals) {
  1787. reg_pairs = pcs_cmn_vals->reg_pairs;
  1788. num_regs = pcs_cmn_vals->num_regs;
  1789. regmap = cdns_phy->regmap_phy_pcs_common_cdb;
  1790. for (i = 0; i < num_regs; i++)
  1791. regmap_write(regmap, reg_pairs[i].off,
  1792. reg_pairs[i].val);
  1793. }
  1794. /* PMA common registers configurations */
  1795. cmn_vals = init_data->cmn_vals[phy_t1][phy_t2][ssc];
  1796. if (cmn_vals) {
  1797. reg_pairs = cmn_vals->reg_pairs;
  1798. num_regs = cmn_vals->num_regs;
  1799. regmap = cdns_phy->regmap_common_cdb;
  1800. for (i = 0; i < num_regs; i++)
  1801. regmap_write(regmap, reg_pairs[i].off,
  1802. reg_pairs[i].val);
  1803. }
  1804. /* PMA TX lane registers configurations */
  1805. tx_ln_vals = init_data->tx_ln_vals[phy_t1][phy_t2][ssc];
  1806. if (tx_ln_vals) {
  1807. reg_pairs = tx_ln_vals->reg_pairs;
  1808. num_regs = tx_ln_vals->num_regs;
  1809. for (i = 0; i < num_lanes; i++) {
  1810. regmap = cdns_phy->regmap_tx_lane_cdb[i + mlane];
  1811. for (j = 0; j < num_regs; j++)
  1812. regmap_write(regmap, reg_pairs[j].off,
  1813. reg_pairs[j].val);
  1814. }
  1815. }
  1816. /* PMA RX lane registers configurations */
  1817. rx_ln_vals = init_data->rx_ln_vals[phy_t1][phy_t2][ssc];
  1818. if (rx_ln_vals) {
  1819. reg_pairs = rx_ln_vals->reg_pairs;
  1820. num_regs = rx_ln_vals->num_regs;
  1821. for (i = 0; i < num_lanes; i++) {
  1822. regmap = cdns_phy->regmap_rx_lane_cdb[i + mlane];
  1823. for (j = 0; j < num_regs; j++)
  1824. regmap_write(regmap, reg_pairs[j].off,
  1825. reg_pairs[j].val);
  1826. }
  1827. }
  1828. reset_control_deassert(cdns_phy->phys[node].lnk_rst);
  1829. }
  1830. /* Take the PHY out of reset */
  1831. ret = reset_control_deassert(cdns_phy->phy_rst);
  1832. if (ret)
  1833. return ret;
  1834. return 0;
  1835. }
  1836. static int cdns_torrent_phy_probe(struct platform_device *pdev)
  1837. {
  1838. struct cdns_torrent_phy *cdns_phy;
  1839. struct device *dev = &pdev->dev;
  1840. struct phy_provider *phy_provider;
  1841. const struct cdns_torrent_data *data;
  1842. struct device_node *child;
  1843. int ret, subnodes, node = 0, i;
  1844. u32 total_num_lanes = 0;
  1845. u8 init_dp_regmap = 0;
  1846. u32 phy_type;
  1847. /* Get init data for this PHY */
  1848. data = of_device_get_match_data(dev);
  1849. if (!data)
  1850. return -EINVAL;
  1851. cdns_phy = devm_kzalloc(dev, sizeof(*cdns_phy), GFP_KERNEL);
  1852. if (!cdns_phy)
  1853. return -ENOMEM;
  1854. dev_set_drvdata(dev, cdns_phy);
  1855. cdns_phy->dev = dev;
  1856. cdns_phy->init_data = data;
  1857. cdns_phy->phy_rst = devm_reset_control_get_exclusive_by_index(dev, 0);
  1858. if (IS_ERR(cdns_phy->phy_rst)) {
  1859. dev_err(dev, "%s: failed to get reset\n",
  1860. dev->of_node->full_name);
  1861. return PTR_ERR(cdns_phy->phy_rst);
  1862. }
  1863. cdns_phy->apb_rst = devm_reset_control_get_optional(dev, "torrent_apb");
  1864. if (IS_ERR(cdns_phy->apb_rst)) {
  1865. dev_err(dev, "%s: failed to get apb reset\n",
  1866. dev->of_node->full_name);
  1867. return PTR_ERR(cdns_phy->apb_rst);
  1868. }
  1869. cdns_phy->clk = devm_clk_get(dev, "refclk");
  1870. if (IS_ERR(cdns_phy->clk)) {
  1871. dev_err(dev, "phy ref clock not found\n");
  1872. return PTR_ERR(cdns_phy->clk);
  1873. }
  1874. cdns_phy->sd_base = devm_platform_ioremap_resource(pdev, 0);
  1875. if (IS_ERR(cdns_phy->sd_base))
  1876. return PTR_ERR(cdns_phy->sd_base);
  1877. subnodes = of_get_available_child_count(dev->of_node);
  1878. if (subnodes == 0) {
  1879. dev_err(dev, "No available link subnodes found\n");
  1880. return -EINVAL;
  1881. }
  1882. ret = cdns_torrent_regmap_init(cdns_phy);
  1883. if (ret)
  1884. return ret;
  1885. ret = cdns_torrent_regfield_init(cdns_phy);
  1886. if (ret)
  1887. return ret;
  1888. ret = clk_prepare_enable(cdns_phy->clk);
  1889. if (ret) {
  1890. dev_err(cdns_phy->dev, "Failed to prepare ref clock\n");
  1891. return ret;
  1892. }
  1893. cdns_phy->ref_clk_rate = clk_get_rate(cdns_phy->clk);
  1894. if (!(cdns_phy->ref_clk_rate)) {
  1895. dev_err(cdns_phy->dev, "Failed to get ref clock rate\n");
  1896. clk_disable_unprepare(cdns_phy->clk);
  1897. return -EINVAL;
  1898. }
  1899. /* Enable APB */
  1900. reset_control_deassert(cdns_phy->apb_rst);
  1901. for_each_available_child_of_node(dev->of_node, child) {
  1902. struct phy *gphy;
  1903. /* PHY subnode name must be 'phy'. */
  1904. if (!(of_node_name_eq(child, "phy")))
  1905. continue;
  1906. cdns_phy->phys[node].lnk_rst =
  1907. of_reset_control_array_get_exclusive(child);
  1908. if (IS_ERR(cdns_phy->phys[node].lnk_rst)) {
  1909. dev_err(dev, "%s: failed to get reset\n",
  1910. child->full_name);
  1911. ret = PTR_ERR(cdns_phy->phys[node].lnk_rst);
  1912. goto put_lnk_rst;
  1913. }
  1914. if (of_property_read_u32(child, "reg",
  1915. &cdns_phy->phys[node].mlane)) {
  1916. dev_err(dev, "%s: No \"reg\"-property.\n",
  1917. child->full_name);
  1918. ret = -EINVAL;
  1919. goto put_child;
  1920. }
  1921. if (of_property_read_u32(child, "cdns,phy-type", &phy_type)) {
  1922. dev_err(dev, "%s: No \"cdns,phy-type\"-property.\n",
  1923. child->full_name);
  1924. ret = -EINVAL;
  1925. goto put_child;
  1926. }
  1927. switch (phy_type) {
  1928. case PHY_TYPE_PCIE:
  1929. cdns_phy->phys[node].phy_type = TYPE_PCIE;
  1930. break;
  1931. case PHY_TYPE_DP:
  1932. cdns_phy->phys[node].phy_type = TYPE_DP;
  1933. break;
  1934. case PHY_TYPE_SGMII:
  1935. cdns_phy->phys[node].phy_type = TYPE_SGMII;
  1936. break;
  1937. case PHY_TYPE_QSGMII:
  1938. cdns_phy->phys[node].phy_type = TYPE_QSGMII;
  1939. break;
  1940. case PHY_TYPE_USB3:
  1941. cdns_phy->phys[node].phy_type = TYPE_USB;
  1942. break;
  1943. default:
  1944. dev_err(dev, "Unsupported protocol\n");
  1945. ret = -EINVAL;
  1946. goto put_child;
  1947. }
  1948. if (of_property_read_u32(child, "cdns,num-lanes",
  1949. &cdns_phy->phys[node].num_lanes)) {
  1950. dev_err(dev, "%s: No \"cdns,num-lanes\"-property.\n",
  1951. child->full_name);
  1952. ret = -EINVAL;
  1953. goto put_child;
  1954. }
  1955. total_num_lanes += cdns_phy->phys[node].num_lanes;
  1956. /* Get SSC mode */
  1957. cdns_phy->phys[node].ssc_mode = NO_SSC;
  1958. of_property_read_u32(child, "cdns,ssc-mode",
  1959. &cdns_phy->phys[node].ssc_mode);
  1960. gphy = devm_phy_create(dev, child, &cdns_torrent_phy_ops);
  1961. if (IS_ERR(gphy)) {
  1962. ret = PTR_ERR(gphy);
  1963. goto put_child;
  1964. }
  1965. if (cdns_phy->phys[node].phy_type == TYPE_DP) {
  1966. switch (cdns_phy->phys[node].num_lanes) {
  1967. case 1:
  1968. case 2:
  1969. case 4:
  1970. /* valid number of lanes */
  1971. break;
  1972. default:
  1973. dev_err(dev, "unsupported number of lanes: %d\n",
  1974. cdns_phy->phys[node].num_lanes);
  1975. ret = -EINVAL;
  1976. goto put_child;
  1977. }
  1978. cdns_phy->max_bit_rate = DEFAULT_MAX_BIT_RATE;
  1979. of_property_read_u32(child, "cdns,max-bit-rate",
  1980. &cdns_phy->max_bit_rate);
  1981. switch (cdns_phy->max_bit_rate) {
  1982. case 1620:
  1983. case 2160:
  1984. case 2430:
  1985. case 2700:
  1986. case 3240:
  1987. case 4320:
  1988. case 5400:
  1989. case 8100:
  1990. /* valid bit rate */
  1991. break;
  1992. default:
  1993. dev_err(dev, "unsupported max bit rate: %dMbps\n",
  1994. cdns_phy->max_bit_rate);
  1995. ret = -EINVAL;
  1996. goto put_child;
  1997. }
  1998. /* DPTX registers */
  1999. cdns_phy->base = devm_platform_ioremap_resource(pdev, 1);
  2000. if (IS_ERR(cdns_phy->base)) {
  2001. ret = PTR_ERR(cdns_phy->base);
  2002. goto put_child;
  2003. }
  2004. if (!init_dp_regmap) {
  2005. ret = cdns_torrent_dp_regmap_init(cdns_phy);
  2006. if (ret)
  2007. goto put_child;
  2008. ret = cdns_torrent_dp_regfield_init(cdns_phy);
  2009. if (ret)
  2010. goto put_child;
  2011. init_dp_regmap++;
  2012. }
  2013. dev_info(dev, "%d lanes, max bit rate %d.%03d Gbps\n",
  2014. cdns_phy->phys[node].num_lanes,
  2015. cdns_phy->max_bit_rate / 1000,
  2016. cdns_phy->max_bit_rate % 1000);
  2017. gphy->attrs.bus_width = cdns_phy->phys[node].num_lanes;
  2018. gphy->attrs.max_link_rate = cdns_phy->max_bit_rate;
  2019. gphy->attrs.mode = PHY_MODE_DP;
  2020. }
  2021. cdns_phy->phys[node].phy = gphy;
  2022. phy_set_drvdata(gphy, &cdns_phy->phys[node]);
  2023. node++;
  2024. }
  2025. cdns_phy->nsubnodes = node;
  2026. if (total_num_lanes > MAX_NUM_LANES) {
  2027. dev_err(dev, "Invalid lane configuration\n");
  2028. ret = -EINVAL;
  2029. goto put_lnk_rst;
  2030. }
  2031. if (cdns_phy->nsubnodes > 1) {
  2032. ret = cdns_torrent_phy_configure_multilink(cdns_phy);
  2033. if (ret)
  2034. goto put_lnk_rst;
  2035. }
  2036. phy_provider = devm_of_phy_provider_register(dev, of_phy_simple_xlate);
  2037. if (IS_ERR(phy_provider)) {
  2038. ret = PTR_ERR(phy_provider);
  2039. goto put_lnk_rst;
  2040. }
  2041. return 0;
  2042. put_child:
  2043. node++;
  2044. put_lnk_rst:
  2045. for (i = 0; i < node; i++)
  2046. reset_control_put(cdns_phy->phys[i].lnk_rst);
  2047. of_node_put(child);
  2048. reset_control_assert(cdns_phy->apb_rst);
  2049. clk_disable_unprepare(cdns_phy->clk);
  2050. return ret;
  2051. }
  2052. static int cdns_torrent_phy_remove(struct platform_device *pdev)
  2053. {
  2054. struct cdns_torrent_phy *cdns_phy = platform_get_drvdata(pdev);
  2055. int i;
  2056. reset_control_assert(cdns_phy->phy_rst);
  2057. reset_control_assert(cdns_phy->apb_rst);
  2058. for (i = 0; i < cdns_phy->nsubnodes; i++) {
  2059. reset_control_assert(cdns_phy->phys[i].lnk_rst);
  2060. reset_control_put(cdns_phy->phys[i].lnk_rst);
  2061. }
  2062. clk_disable_unprepare(cdns_phy->clk);
  2063. return 0;
  2064. }
  2065. /* USB and SGMII/QSGMII link configuration */
  2066. static struct cdns_reg_pairs usb_sgmii_link_cmn_regs[] = {
  2067. {0x0002, PHY_PLL_CFG},
  2068. {0x8600, CMN_PDIAG_PLL0_CLK_SEL_M0},
  2069. {0x0601, CMN_PDIAG_PLL1_CLK_SEL_M0}
  2070. };
  2071. static struct cdns_reg_pairs usb_sgmii_xcvr_diag_ln_regs[] = {
  2072. {0x0000, XCVR_DIAG_HSCLK_SEL},
  2073. {0x0001, XCVR_DIAG_HSCLK_DIV},
  2074. {0x0041, XCVR_DIAG_PLLDRC_CTRL}
  2075. };
  2076. static struct cdns_reg_pairs sgmii_usb_xcvr_diag_ln_regs[] = {
  2077. {0x0011, XCVR_DIAG_HSCLK_SEL},
  2078. {0x0003, XCVR_DIAG_HSCLK_DIV},
  2079. {0x009B, XCVR_DIAG_PLLDRC_CTRL}
  2080. };
  2081. static struct cdns_torrent_vals usb_sgmii_link_cmn_vals = {
  2082. .reg_pairs = usb_sgmii_link_cmn_regs,
  2083. .num_regs = ARRAY_SIZE(usb_sgmii_link_cmn_regs),
  2084. };
  2085. static struct cdns_torrent_vals usb_sgmii_xcvr_diag_ln_vals = {
  2086. .reg_pairs = usb_sgmii_xcvr_diag_ln_regs,
  2087. .num_regs = ARRAY_SIZE(usb_sgmii_xcvr_diag_ln_regs),
  2088. };
  2089. static struct cdns_torrent_vals sgmii_usb_xcvr_diag_ln_vals = {
  2090. .reg_pairs = sgmii_usb_xcvr_diag_ln_regs,
  2091. .num_regs = ARRAY_SIZE(sgmii_usb_xcvr_diag_ln_regs),
  2092. };
  2093. /* PCIe and USB Unique SSC link configuration */
  2094. static struct cdns_reg_pairs pcie_usb_link_cmn_regs[] = {
  2095. {0x0003, PHY_PLL_CFG},
  2096. {0x0601, CMN_PDIAG_PLL0_CLK_SEL_M0},
  2097. {0x0400, CMN_PDIAG_PLL0_CLK_SEL_M1},
  2098. {0x8600, CMN_PDIAG_PLL1_CLK_SEL_M0}
  2099. };
  2100. static struct cdns_reg_pairs pcie_usb_xcvr_diag_ln_regs[] = {
  2101. {0x0000, XCVR_DIAG_HSCLK_SEL},
  2102. {0x0001, XCVR_DIAG_HSCLK_DIV},
  2103. {0x0012, XCVR_DIAG_PLLDRC_CTRL}
  2104. };
  2105. static struct cdns_reg_pairs usb_pcie_xcvr_diag_ln_regs[] = {
  2106. {0x0011, XCVR_DIAG_HSCLK_SEL},
  2107. {0x0001, XCVR_DIAG_HSCLK_DIV},
  2108. {0x00C9, XCVR_DIAG_PLLDRC_CTRL}
  2109. };
  2110. static struct cdns_torrent_vals pcie_usb_link_cmn_vals = {
  2111. .reg_pairs = pcie_usb_link_cmn_regs,
  2112. .num_regs = ARRAY_SIZE(pcie_usb_link_cmn_regs),
  2113. };
  2114. static struct cdns_torrent_vals pcie_usb_xcvr_diag_ln_vals = {
  2115. .reg_pairs = pcie_usb_xcvr_diag_ln_regs,
  2116. .num_regs = ARRAY_SIZE(pcie_usb_xcvr_diag_ln_regs),
  2117. };
  2118. static struct cdns_torrent_vals usb_pcie_xcvr_diag_ln_vals = {
  2119. .reg_pairs = usb_pcie_xcvr_diag_ln_regs,
  2120. .num_regs = ARRAY_SIZE(usb_pcie_xcvr_diag_ln_regs),
  2121. };
  2122. /* USB 100 MHz Ref clk, internal SSC */
  2123. static struct cdns_reg_pairs usb_100_int_ssc_cmn_regs[] = {
  2124. {0x0004, CMN_PLL0_DSM_DIAG_M0},
  2125. {0x0004, CMN_PLL0_DSM_DIAG_M1},
  2126. {0x0004, CMN_PLL1_DSM_DIAG_M0},
  2127. {0x0509, CMN_PDIAG_PLL0_CP_PADJ_M0},
  2128. {0x0509, CMN_PDIAG_PLL0_CP_PADJ_M1},
  2129. {0x0509, CMN_PDIAG_PLL1_CP_PADJ_M0},
  2130. {0x0F00, CMN_PDIAG_PLL0_CP_IADJ_M0},
  2131. {0x0F00, CMN_PDIAG_PLL0_CP_IADJ_M1},
  2132. {0x0F00, CMN_PDIAG_PLL1_CP_IADJ_M0},
  2133. {0x0F08, CMN_PDIAG_PLL0_FILT_PADJ_M0},
  2134. {0x0F08, CMN_PDIAG_PLL0_FILT_PADJ_M1},
  2135. {0x0F08, CMN_PDIAG_PLL1_FILT_PADJ_M0},
  2136. {0x0064, CMN_PLL0_INTDIV_M0},
  2137. {0x0050, CMN_PLL0_INTDIV_M1},
  2138. {0x0064, CMN_PLL1_INTDIV_M0},
  2139. {0x0002, CMN_PLL0_FRACDIVH_M0},
  2140. {0x0002, CMN_PLL0_FRACDIVH_M1},
  2141. {0x0002, CMN_PLL1_FRACDIVH_M0},
  2142. {0x0044, CMN_PLL0_HIGH_THR_M0},
  2143. {0x0036, CMN_PLL0_HIGH_THR_M1},
  2144. {0x0044, CMN_PLL1_HIGH_THR_M0},
  2145. {0x0002, CMN_PDIAG_PLL0_CTRL_M0},
  2146. {0x0002, CMN_PDIAG_PLL0_CTRL_M1},
  2147. {0x0002, CMN_PDIAG_PLL1_CTRL_M0},
  2148. {0x0001, CMN_PLL0_SS_CTRL1_M0},
  2149. {0x0001, CMN_PLL0_SS_CTRL1_M1},
  2150. {0x0001, CMN_PLL1_SS_CTRL1_M0},
  2151. {0x011B, CMN_PLL0_SS_CTRL2_M0},
  2152. {0x011B, CMN_PLL0_SS_CTRL2_M1},
  2153. {0x011B, CMN_PLL1_SS_CTRL2_M0},
  2154. {0x006E, CMN_PLL0_SS_CTRL3_M0},
  2155. {0x0058, CMN_PLL0_SS_CTRL3_M1},
  2156. {0x006E, CMN_PLL1_SS_CTRL3_M0},
  2157. {0x000E, CMN_PLL0_SS_CTRL4_M0},
  2158. {0x0012, CMN_PLL0_SS_CTRL4_M1},
  2159. {0x000E, CMN_PLL1_SS_CTRL4_M0},
  2160. {0x0C5E, CMN_PLL0_VCOCAL_REFTIM_START},
  2161. {0x0C5E, CMN_PLL1_VCOCAL_REFTIM_START},
  2162. {0x0C56, CMN_PLL0_VCOCAL_PLLCNT_START},
  2163. {0x0C56, CMN_PLL1_VCOCAL_PLLCNT_START},
  2164. {0x0003, CMN_PLL0_VCOCAL_TCTRL},
  2165. {0x0003, CMN_PLL1_VCOCAL_TCTRL},
  2166. {0x00C7, CMN_PLL0_LOCK_REFCNT_START},
  2167. {0x00C7, CMN_PLL1_LOCK_REFCNT_START},
  2168. {0x00C7, CMN_PLL0_LOCK_PLLCNT_START},
  2169. {0x00C7, CMN_PLL1_LOCK_PLLCNT_START},
  2170. {0x0005, CMN_PLL0_LOCK_PLLCNT_THR},
  2171. {0x0005, CMN_PLL1_LOCK_PLLCNT_THR},
  2172. {0x8200, CMN_CDIAG_CDB_PWRI_OVRD},
  2173. {0x8200, CMN_CDIAG_XCVRC_PWRI_OVRD}
  2174. };
  2175. static struct cdns_torrent_vals usb_100_int_ssc_cmn_vals = {
  2176. .reg_pairs = usb_100_int_ssc_cmn_regs,
  2177. .num_regs = ARRAY_SIZE(usb_100_int_ssc_cmn_regs),
  2178. };
  2179. /* Single USB link configuration */
  2180. static struct cdns_reg_pairs sl_usb_link_cmn_regs[] = {
  2181. {0x0000, PHY_PLL_CFG},
  2182. {0x8600, CMN_PDIAG_PLL0_CLK_SEL_M0}
  2183. };
  2184. static struct cdns_reg_pairs sl_usb_xcvr_diag_ln_regs[] = {
  2185. {0x0000, XCVR_DIAG_HSCLK_SEL},
  2186. {0x0001, XCVR_DIAG_HSCLK_DIV},
  2187. {0x0041, XCVR_DIAG_PLLDRC_CTRL}
  2188. };
  2189. static struct cdns_torrent_vals sl_usb_link_cmn_vals = {
  2190. .reg_pairs = sl_usb_link_cmn_regs,
  2191. .num_regs = ARRAY_SIZE(sl_usb_link_cmn_regs),
  2192. };
  2193. static struct cdns_torrent_vals sl_usb_xcvr_diag_ln_vals = {
  2194. .reg_pairs = sl_usb_xcvr_diag_ln_regs,
  2195. .num_regs = ARRAY_SIZE(sl_usb_xcvr_diag_ln_regs),
  2196. };
  2197. /* USB PHY PCS common configuration */
  2198. static struct cdns_reg_pairs usb_phy_pcs_cmn_regs[] = {
  2199. {0x0A0A, PHY_PIPE_USB3_GEN2_PRE_CFG0},
  2200. {0x1000, PHY_PIPE_USB3_GEN2_POST_CFG0},
  2201. {0x0010, PHY_PIPE_USB3_GEN2_POST_CFG1}
  2202. };
  2203. static struct cdns_torrent_vals usb_phy_pcs_cmn_vals = {
  2204. .reg_pairs = usb_phy_pcs_cmn_regs,
  2205. .num_regs = ARRAY_SIZE(usb_phy_pcs_cmn_regs),
  2206. };
  2207. /* USB 100 MHz Ref clk, no SSC */
  2208. static struct cdns_reg_pairs usb_100_no_ssc_cmn_regs[] = {
  2209. {0x0003, CMN_PLL0_VCOCAL_TCTRL},
  2210. {0x0003, CMN_PLL1_VCOCAL_TCTRL},
  2211. {0x8200, CMN_CDIAG_CDB_PWRI_OVRD},
  2212. {0x8200, CMN_CDIAG_XCVRC_PWRI_OVRD}
  2213. };
  2214. static struct cdns_reg_pairs usb_100_no_ssc_tx_ln_regs[] = {
  2215. {0x02FF, TX_PSC_A0},
  2216. {0x06AF, TX_PSC_A1},
  2217. {0x06AE, TX_PSC_A2},
  2218. {0x06AE, TX_PSC_A3},
  2219. {0x2A82, TX_TXCC_CTRL},
  2220. {0x0014, TX_TXCC_CPOST_MULT_01},
  2221. {0x0003, XCVR_DIAG_PSC_OVRD}
  2222. };
  2223. static struct cdns_reg_pairs usb_100_no_ssc_rx_ln_regs[] = {
  2224. {0x0D1D, RX_PSC_A0},
  2225. {0x0D1D, RX_PSC_A1},
  2226. {0x0D00, RX_PSC_A2},
  2227. {0x0500, RX_PSC_A3},
  2228. {0x0013, RX_SIGDET_HL_FILT_TMR},
  2229. {0x0000, RX_REE_GCSM1_CTRL},
  2230. {0x0C02, RX_REE_ATTEN_THR},
  2231. {0x0330, RX_REE_SMGM_CTRL1},
  2232. {0x0300, RX_REE_SMGM_CTRL2},
  2233. {0x0019, RX_REE_TAP1_CLIP},
  2234. {0x0019, RX_REE_TAP2TON_CLIP},
  2235. {0x1004, RX_DIAG_SIGDET_TUNE},
  2236. {0x00F9, RX_DIAG_NQST_CTRL},
  2237. {0x0C01, RX_DIAG_DFE_AMP_TUNE_2},
  2238. {0x0002, RX_DIAG_DFE_AMP_TUNE_3},
  2239. {0x0000, RX_DIAG_PI_CAP},
  2240. {0x0031, RX_DIAG_PI_RATE},
  2241. {0x0001, RX_DIAG_ACYA},
  2242. {0x018C, RX_CDRLF_CNFG},
  2243. {0x0003, RX_CDRLF_CNFG3}
  2244. };
  2245. static struct cdns_torrent_vals usb_100_no_ssc_cmn_vals = {
  2246. .reg_pairs = usb_100_no_ssc_cmn_regs,
  2247. .num_regs = ARRAY_SIZE(usb_100_no_ssc_cmn_regs),
  2248. };
  2249. static struct cdns_torrent_vals usb_100_no_ssc_tx_ln_vals = {
  2250. .reg_pairs = usb_100_no_ssc_tx_ln_regs,
  2251. .num_regs = ARRAY_SIZE(usb_100_no_ssc_tx_ln_regs),
  2252. };
  2253. static struct cdns_torrent_vals usb_100_no_ssc_rx_ln_vals = {
  2254. .reg_pairs = usb_100_no_ssc_rx_ln_regs,
  2255. .num_regs = ARRAY_SIZE(usb_100_no_ssc_rx_ln_regs),
  2256. };
  2257. /* Single link USB, 100 MHz Ref clk, internal SSC */
  2258. static struct cdns_reg_pairs sl_usb_100_int_ssc_cmn_regs[] = {
  2259. {0x0004, CMN_PLL0_DSM_DIAG_M0},
  2260. {0x0004, CMN_PLL1_DSM_DIAG_M0},
  2261. {0x0509, CMN_PDIAG_PLL0_CP_PADJ_M0},
  2262. {0x0509, CMN_PDIAG_PLL1_CP_PADJ_M0},
  2263. {0x0F00, CMN_PDIAG_PLL0_CP_IADJ_M0},
  2264. {0x0F00, CMN_PDIAG_PLL1_CP_IADJ_M0},
  2265. {0x0F08, CMN_PDIAG_PLL0_FILT_PADJ_M0},
  2266. {0x0F08, CMN_PDIAG_PLL1_FILT_PADJ_M0},
  2267. {0x0064, CMN_PLL0_INTDIV_M0},
  2268. {0x0064, CMN_PLL1_INTDIV_M0},
  2269. {0x0002, CMN_PLL0_FRACDIVH_M0},
  2270. {0x0002, CMN_PLL1_FRACDIVH_M0},
  2271. {0x0044, CMN_PLL0_HIGH_THR_M0},
  2272. {0x0044, CMN_PLL1_HIGH_THR_M0},
  2273. {0x0002, CMN_PDIAG_PLL0_CTRL_M0},
  2274. {0x0002, CMN_PDIAG_PLL1_CTRL_M0},
  2275. {0x0001, CMN_PLL0_SS_CTRL1_M0},
  2276. {0x0001, CMN_PLL1_SS_CTRL1_M0},
  2277. {0x011B, CMN_PLL0_SS_CTRL2_M0},
  2278. {0x011B, CMN_PLL1_SS_CTRL2_M0},
  2279. {0x006E, CMN_PLL0_SS_CTRL3_M0},
  2280. {0x006E, CMN_PLL1_SS_CTRL3_M0},
  2281. {0x000E, CMN_PLL0_SS_CTRL4_M0},
  2282. {0x000E, CMN_PLL1_SS_CTRL4_M0},
  2283. {0x0C5E, CMN_PLL0_VCOCAL_REFTIM_START},
  2284. {0x0C5E, CMN_PLL1_VCOCAL_REFTIM_START},
  2285. {0x0C56, CMN_PLL0_VCOCAL_PLLCNT_START},
  2286. {0x0C56, CMN_PLL1_VCOCAL_PLLCNT_START},
  2287. {0x0003, CMN_PLL0_VCOCAL_TCTRL},
  2288. {0x0003, CMN_PLL1_VCOCAL_TCTRL},
  2289. {0x00C7, CMN_PLL0_LOCK_REFCNT_START},
  2290. {0x00C7, CMN_PLL1_LOCK_REFCNT_START},
  2291. {0x00C7, CMN_PLL0_LOCK_PLLCNT_START},
  2292. {0x00C7, CMN_PLL1_LOCK_PLLCNT_START},
  2293. {0x0005, CMN_PLL0_LOCK_PLLCNT_THR},
  2294. {0x0005, CMN_PLL1_LOCK_PLLCNT_THR},
  2295. {0x8200, CMN_CDIAG_CDB_PWRI_OVRD},
  2296. {0x8200, CMN_CDIAG_XCVRC_PWRI_OVRD}
  2297. };
  2298. static struct cdns_torrent_vals sl_usb_100_int_ssc_cmn_vals = {
  2299. .reg_pairs = sl_usb_100_int_ssc_cmn_regs,
  2300. .num_regs = ARRAY_SIZE(sl_usb_100_int_ssc_cmn_regs),
  2301. };
  2302. /* PCIe and SGMII/QSGMII Unique SSC link configuration */
  2303. static struct cdns_reg_pairs pcie_sgmii_link_cmn_regs[] = {
  2304. {0x0003, PHY_PLL_CFG},
  2305. {0x0601, CMN_PDIAG_PLL0_CLK_SEL_M0},
  2306. {0x0400, CMN_PDIAG_PLL0_CLK_SEL_M1},
  2307. {0x0601, CMN_PDIAG_PLL1_CLK_SEL_M0}
  2308. };
  2309. static struct cdns_reg_pairs pcie_sgmii_xcvr_diag_ln_regs[] = {
  2310. {0x0000, XCVR_DIAG_HSCLK_SEL},
  2311. {0x0001, XCVR_DIAG_HSCLK_DIV},
  2312. {0x0012, XCVR_DIAG_PLLDRC_CTRL}
  2313. };
  2314. static struct cdns_reg_pairs sgmii_pcie_xcvr_diag_ln_regs[] = {
  2315. {0x0011, XCVR_DIAG_HSCLK_SEL},
  2316. {0x0003, XCVR_DIAG_HSCLK_DIV},
  2317. {0x009B, XCVR_DIAG_PLLDRC_CTRL}
  2318. };
  2319. static struct cdns_torrent_vals pcie_sgmii_link_cmn_vals = {
  2320. .reg_pairs = pcie_sgmii_link_cmn_regs,
  2321. .num_regs = ARRAY_SIZE(pcie_sgmii_link_cmn_regs),
  2322. };
  2323. static struct cdns_torrent_vals pcie_sgmii_xcvr_diag_ln_vals = {
  2324. .reg_pairs = pcie_sgmii_xcvr_diag_ln_regs,
  2325. .num_regs = ARRAY_SIZE(pcie_sgmii_xcvr_diag_ln_regs),
  2326. };
  2327. static struct cdns_torrent_vals sgmii_pcie_xcvr_diag_ln_vals = {
  2328. .reg_pairs = sgmii_pcie_xcvr_diag_ln_regs,
  2329. .num_regs = ARRAY_SIZE(sgmii_pcie_xcvr_diag_ln_regs),
  2330. };
  2331. /* SGMII 100 MHz Ref clk, no SSC */
  2332. static struct cdns_reg_pairs sgmii_100_no_ssc_cmn_regs[] = {
  2333. {0x0003, CMN_PLL0_VCOCAL_TCTRL},
  2334. {0x0003, CMN_PLL1_VCOCAL_TCTRL},
  2335. {0x3700, CMN_DIAG_BIAS_OVRD1},
  2336. {0x0008, CMN_TXPUCAL_TUNE},
  2337. {0x0008, CMN_TXPDCAL_TUNE}
  2338. };
  2339. static struct cdns_reg_pairs sgmii_100_no_ssc_tx_ln_regs[] = {
  2340. {0x00F3, TX_PSC_A0},
  2341. {0x04A2, TX_PSC_A2},
  2342. {0x04A2, TX_PSC_A3},
  2343. {0x0000, TX_TXCC_CPOST_MULT_00},
  2344. {0x00B3, DRV_DIAG_TX_DRV}
  2345. };
  2346. static struct cdns_reg_pairs sgmii_100_no_ssc_rx_ln_regs[] = {
  2347. {0x091D, RX_PSC_A0},
  2348. {0x0900, RX_PSC_A2},
  2349. {0x0100, RX_PSC_A3},
  2350. {0x03C7, RX_REE_GCSM1_EQENM_PH1},
  2351. {0x01C7, RX_REE_GCSM1_EQENM_PH2},
  2352. {0x0000, RX_DIAG_DFE_CTRL},
  2353. {0x0019, RX_REE_TAP1_CLIP},
  2354. {0x0019, RX_REE_TAP2TON_CLIP},
  2355. {0x0098, RX_DIAG_NQST_CTRL},
  2356. {0x0C01, RX_DIAG_DFE_AMP_TUNE_2},
  2357. {0x0000, RX_DIAG_DFE_AMP_TUNE_3},
  2358. {0x0000, RX_DIAG_PI_CAP},
  2359. {0x0010, RX_DIAG_PI_RATE},
  2360. {0x0001, RX_DIAG_ACYA},
  2361. {0x018C, RX_CDRLF_CNFG},
  2362. };
  2363. static struct cdns_torrent_vals sgmii_100_no_ssc_cmn_vals = {
  2364. .reg_pairs = sgmii_100_no_ssc_cmn_regs,
  2365. .num_regs = ARRAY_SIZE(sgmii_100_no_ssc_cmn_regs),
  2366. };
  2367. static struct cdns_torrent_vals sgmii_100_no_ssc_tx_ln_vals = {
  2368. .reg_pairs = sgmii_100_no_ssc_tx_ln_regs,
  2369. .num_regs = ARRAY_SIZE(sgmii_100_no_ssc_tx_ln_regs),
  2370. };
  2371. static struct cdns_torrent_vals sgmii_100_no_ssc_rx_ln_vals = {
  2372. .reg_pairs = sgmii_100_no_ssc_rx_ln_regs,
  2373. .num_regs = ARRAY_SIZE(sgmii_100_no_ssc_rx_ln_regs),
  2374. };
  2375. /* SGMII 100 MHz Ref clk, internal SSC */
  2376. static struct cdns_reg_pairs sgmii_100_int_ssc_cmn_regs[] = {
  2377. {0x0004, CMN_PLL0_DSM_DIAG_M0},
  2378. {0x0004, CMN_PLL0_DSM_DIAG_M1},
  2379. {0x0004, CMN_PLL1_DSM_DIAG_M0},
  2380. {0x0509, CMN_PDIAG_PLL0_CP_PADJ_M0},
  2381. {0x0509, CMN_PDIAG_PLL0_CP_PADJ_M1},
  2382. {0x0509, CMN_PDIAG_PLL1_CP_PADJ_M0},
  2383. {0x0F00, CMN_PDIAG_PLL0_CP_IADJ_M0},
  2384. {0x0F00, CMN_PDIAG_PLL0_CP_IADJ_M1},
  2385. {0x0F00, CMN_PDIAG_PLL1_CP_IADJ_M0},
  2386. {0x0F08, CMN_PDIAG_PLL0_FILT_PADJ_M0},
  2387. {0x0F08, CMN_PDIAG_PLL0_FILT_PADJ_M1},
  2388. {0x0F08, CMN_PDIAG_PLL1_FILT_PADJ_M0},
  2389. {0x0064, CMN_PLL0_INTDIV_M0},
  2390. {0x0050, CMN_PLL0_INTDIV_M1},
  2391. {0x0064, CMN_PLL1_INTDIV_M0},
  2392. {0x0002, CMN_PLL0_FRACDIVH_M0},
  2393. {0x0002, CMN_PLL0_FRACDIVH_M1},
  2394. {0x0002, CMN_PLL1_FRACDIVH_M0},
  2395. {0x0044, CMN_PLL0_HIGH_THR_M0},
  2396. {0x0036, CMN_PLL0_HIGH_THR_M1},
  2397. {0x0044, CMN_PLL1_HIGH_THR_M0},
  2398. {0x0002, CMN_PDIAG_PLL0_CTRL_M0},
  2399. {0x0002, CMN_PDIAG_PLL0_CTRL_M1},
  2400. {0x0002, CMN_PDIAG_PLL1_CTRL_M0},
  2401. {0x0001, CMN_PLL0_SS_CTRL1_M0},
  2402. {0x0001, CMN_PLL0_SS_CTRL1_M1},
  2403. {0x0001, CMN_PLL1_SS_CTRL1_M0},
  2404. {0x011B, CMN_PLL0_SS_CTRL2_M0},
  2405. {0x011B, CMN_PLL0_SS_CTRL2_M1},
  2406. {0x011B, CMN_PLL1_SS_CTRL2_M0},
  2407. {0x006E, CMN_PLL0_SS_CTRL3_M0},
  2408. {0x0058, CMN_PLL0_SS_CTRL3_M1},
  2409. {0x006E, CMN_PLL1_SS_CTRL3_M0},
  2410. {0x000E, CMN_PLL0_SS_CTRL4_M0},
  2411. {0x0012, CMN_PLL0_SS_CTRL4_M1},
  2412. {0x000E, CMN_PLL1_SS_CTRL4_M0},
  2413. {0x0C5E, CMN_PLL0_VCOCAL_REFTIM_START},
  2414. {0x0C5E, CMN_PLL1_VCOCAL_REFTIM_START},
  2415. {0x0C56, CMN_PLL0_VCOCAL_PLLCNT_START},
  2416. {0x0C56, CMN_PLL1_VCOCAL_PLLCNT_START},
  2417. {0x0003, CMN_PLL0_VCOCAL_TCTRL},
  2418. {0x0003, CMN_PLL1_VCOCAL_TCTRL},
  2419. {0x00C7, CMN_PLL0_LOCK_REFCNT_START},
  2420. {0x00C7, CMN_PLL1_LOCK_REFCNT_START},
  2421. {0x00C7, CMN_PLL0_LOCK_PLLCNT_START},
  2422. {0x00C7, CMN_PLL1_LOCK_PLLCNT_START},
  2423. {0x0005, CMN_PLL0_LOCK_PLLCNT_THR},
  2424. {0x0005, CMN_PLL1_LOCK_PLLCNT_THR},
  2425. {0x3700, CMN_DIAG_BIAS_OVRD1},
  2426. {0x0008, CMN_TXPUCAL_TUNE},
  2427. {0x0008, CMN_TXPDCAL_TUNE}
  2428. };
  2429. static struct cdns_torrent_vals sgmii_100_int_ssc_cmn_vals = {
  2430. .reg_pairs = sgmii_100_int_ssc_cmn_regs,
  2431. .num_regs = ARRAY_SIZE(sgmii_100_int_ssc_cmn_regs),
  2432. };
  2433. /* QSGMII 100 MHz Ref clk, no SSC */
  2434. static struct cdns_reg_pairs qsgmii_100_no_ssc_cmn_regs[] = {
  2435. {0x0003, CMN_PLL0_VCOCAL_TCTRL},
  2436. {0x0003, CMN_PLL1_VCOCAL_TCTRL}
  2437. };
  2438. static struct cdns_reg_pairs qsgmii_100_no_ssc_tx_ln_regs[] = {
  2439. {0x00F3, TX_PSC_A0},
  2440. {0x04A2, TX_PSC_A2},
  2441. {0x04A2, TX_PSC_A3},
  2442. {0x0000, TX_TXCC_CPOST_MULT_00},
  2443. {0x0003, DRV_DIAG_TX_DRV}
  2444. };
  2445. static struct cdns_reg_pairs qsgmii_100_no_ssc_rx_ln_regs[] = {
  2446. {0x091D, RX_PSC_A0},
  2447. {0x0900, RX_PSC_A2},
  2448. {0x0100, RX_PSC_A3},
  2449. {0x03C7, RX_REE_GCSM1_EQENM_PH1},
  2450. {0x01C7, RX_REE_GCSM1_EQENM_PH2},
  2451. {0x0000, RX_DIAG_DFE_CTRL},
  2452. {0x0019, RX_REE_TAP1_CLIP},
  2453. {0x0019, RX_REE_TAP2TON_CLIP},
  2454. {0x0098, RX_DIAG_NQST_CTRL},
  2455. {0x0C01, RX_DIAG_DFE_AMP_TUNE_2},
  2456. {0x0000, RX_DIAG_DFE_AMP_TUNE_3},
  2457. {0x0000, RX_DIAG_PI_CAP},
  2458. {0x0010, RX_DIAG_PI_RATE},
  2459. {0x0001, RX_DIAG_ACYA},
  2460. {0x018C, RX_CDRLF_CNFG},
  2461. };
  2462. static struct cdns_torrent_vals qsgmii_100_no_ssc_cmn_vals = {
  2463. .reg_pairs = qsgmii_100_no_ssc_cmn_regs,
  2464. .num_regs = ARRAY_SIZE(qsgmii_100_no_ssc_cmn_regs),
  2465. };
  2466. static struct cdns_torrent_vals qsgmii_100_no_ssc_tx_ln_vals = {
  2467. .reg_pairs = qsgmii_100_no_ssc_tx_ln_regs,
  2468. .num_regs = ARRAY_SIZE(qsgmii_100_no_ssc_tx_ln_regs),
  2469. };
  2470. static struct cdns_torrent_vals qsgmii_100_no_ssc_rx_ln_vals = {
  2471. .reg_pairs = qsgmii_100_no_ssc_rx_ln_regs,
  2472. .num_regs = ARRAY_SIZE(qsgmii_100_no_ssc_rx_ln_regs),
  2473. };
  2474. /* QSGMII 100 MHz Ref clk, internal SSC */
  2475. static struct cdns_reg_pairs qsgmii_100_int_ssc_cmn_regs[] = {
  2476. {0x0004, CMN_PLL0_DSM_DIAG_M0},
  2477. {0x0004, CMN_PLL0_DSM_DIAG_M1},
  2478. {0x0004, CMN_PLL1_DSM_DIAG_M0},
  2479. {0x0509, CMN_PDIAG_PLL0_CP_PADJ_M0},
  2480. {0x0509, CMN_PDIAG_PLL0_CP_PADJ_M1},
  2481. {0x0509, CMN_PDIAG_PLL1_CP_PADJ_M0},
  2482. {0x0F00, CMN_PDIAG_PLL0_CP_IADJ_M0},
  2483. {0x0F00, CMN_PDIAG_PLL0_CP_IADJ_M1},
  2484. {0x0F00, CMN_PDIAG_PLL1_CP_IADJ_M0},
  2485. {0x0F08, CMN_PDIAG_PLL0_FILT_PADJ_M0},
  2486. {0x0F08, CMN_PDIAG_PLL0_FILT_PADJ_M1},
  2487. {0x0F08, CMN_PDIAG_PLL1_FILT_PADJ_M0},
  2488. {0x0064, CMN_PLL0_INTDIV_M0},
  2489. {0x0050, CMN_PLL0_INTDIV_M1},
  2490. {0x0064, CMN_PLL1_INTDIV_M0},
  2491. {0x0002, CMN_PLL0_FRACDIVH_M0},
  2492. {0x0002, CMN_PLL0_FRACDIVH_M1},
  2493. {0x0002, CMN_PLL1_FRACDIVH_M0},
  2494. {0x0044, CMN_PLL0_HIGH_THR_M0},
  2495. {0x0036, CMN_PLL0_HIGH_THR_M1},
  2496. {0x0044, CMN_PLL1_HIGH_THR_M0},
  2497. {0x0002, CMN_PDIAG_PLL0_CTRL_M0},
  2498. {0x0002, CMN_PDIAG_PLL0_CTRL_M1},
  2499. {0x0002, CMN_PDIAG_PLL1_CTRL_M0},
  2500. {0x0001, CMN_PLL0_SS_CTRL1_M0},
  2501. {0x0001, CMN_PLL0_SS_CTRL1_M1},
  2502. {0x0001, CMN_PLL1_SS_CTRL1_M0},
  2503. {0x011B, CMN_PLL0_SS_CTRL2_M0},
  2504. {0x011B, CMN_PLL0_SS_CTRL2_M1},
  2505. {0x011B, CMN_PLL1_SS_CTRL2_M0},
  2506. {0x006E, CMN_PLL0_SS_CTRL3_M0},
  2507. {0x0058, CMN_PLL0_SS_CTRL3_M1},
  2508. {0x006E, CMN_PLL1_SS_CTRL3_M0},
  2509. {0x000E, CMN_PLL0_SS_CTRL4_M0},
  2510. {0x0012, CMN_PLL0_SS_CTRL4_M1},
  2511. {0x000E, CMN_PLL1_SS_CTRL4_M0},
  2512. {0x0C5E, CMN_PLL0_VCOCAL_REFTIM_START},
  2513. {0x0C5E, CMN_PLL1_VCOCAL_REFTIM_START},
  2514. {0x0C56, CMN_PLL0_VCOCAL_PLLCNT_START},
  2515. {0x0C56, CMN_PLL1_VCOCAL_PLLCNT_START},
  2516. {0x0003, CMN_PLL0_VCOCAL_TCTRL},
  2517. {0x0003, CMN_PLL1_VCOCAL_TCTRL},
  2518. {0x00C7, CMN_PLL0_LOCK_REFCNT_START},
  2519. {0x00C7, CMN_PLL1_LOCK_REFCNT_START},
  2520. {0x00C7, CMN_PLL0_LOCK_PLLCNT_START},
  2521. {0x00C7, CMN_PLL1_LOCK_PLLCNT_START},
  2522. {0x0005, CMN_PLL0_LOCK_PLLCNT_THR},
  2523. {0x0005, CMN_PLL1_LOCK_PLLCNT_THR}
  2524. };
  2525. static struct cdns_torrent_vals qsgmii_100_int_ssc_cmn_vals = {
  2526. .reg_pairs = qsgmii_100_int_ssc_cmn_regs,
  2527. .num_regs = ARRAY_SIZE(qsgmii_100_int_ssc_cmn_regs),
  2528. };
  2529. /* Single SGMII/QSGMII link configuration */
  2530. static struct cdns_reg_pairs sl_sgmii_link_cmn_regs[] = {
  2531. {0x0000, PHY_PLL_CFG},
  2532. {0x0601, CMN_PDIAG_PLL0_CLK_SEL_M0}
  2533. };
  2534. static struct cdns_reg_pairs sl_sgmii_xcvr_diag_ln_regs[] = {
  2535. {0x0000, XCVR_DIAG_HSCLK_SEL},
  2536. {0x0003, XCVR_DIAG_HSCLK_DIV},
  2537. {0x0013, XCVR_DIAG_PLLDRC_CTRL}
  2538. };
  2539. static struct cdns_torrent_vals sl_sgmii_link_cmn_vals = {
  2540. .reg_pairs = sl_sgmii_link_cmn_regs,
  2541. .num_regs = ARRAY_SIZE(sl_sgmii_link_cmn_regs),
  2542. };
  2543. static struct cdns_torrent_vals sl_sgmii_xcvr_diag_ln_vals = {
  2544. .reg_pairs = sl_sgmii_xcvr_diag_ln_regs,
  2545. .num_regs = ARRAY_SIZE(sl_sgmii_xcvr_diag_ln_regs),
  2546. };
  2547. /* Multi link PCIe, 100 MHz Ref clk, internal SSC */
  2548. static struct cdns_reg_pairs pcie_100_int_ssc_cmn_regs[] = {
  2549. {0x0004, CMN_PLL0_DSM_DIAG_M0},
  2550. {0x0004, CMN_PLL0_DSM_DIAG_M1},
  2551. {0x0004, CMN_PLL1_DSM_DIAG_M0},
  2552. {0x0509, CMN_PDIAG_PLL0_CP_PADJ_M0},
  2553. {0x0509, CMN_PDIAG_PLL0_CP_PADJ_M1},
  2554. {0x0509, CMN_PDIAG_PLL1_CP_PADJ_M0},
  2555. {0x0F00, CMN_PDIAG_PLL0_CP_IADJ_M0},
  2556. {0x0F00, CMN_PDIAG_PLL0_CP_IADJ_M1},
  2557. {0x0F00, CMN_PDIAG_PLL1_CP_IADJ_M0},
  2558. {0x0F08, CMN_PDIAG_PLL0_FILT_PADJ_M0},
  2559. {0x0F08, CMN_PDIAG_PLL0_FILT_PADJ_M1},
  2560. {0x0F08, CMN_PDIAG_PLL1_FILT_PADJ_M0},
  2561. {0x0064, CMN_PLL0_INTDIV_M0},
  2562. {0x0050, CMN_PLL0_INTDIV_M1},
  2563. {0x0064, CMN_PLL1_INTDIV_M0},
  2564. {0x0002, CMN_PLL0_FRACDIVH_M0},
  2565. {0x0002, CMN_PLL0_FRACDIVH_M1},
  2566. {0x0002, CMN_PLL1_FRACDIVH_M0},
  2567. {0x0044, CMN_PLL0_HIGH_THR_M0},
  2568. {0x0036, CMN_PLL0_HIGH_THR_M1},
  2569. {0x0044, CMN_PLL1_HIGH_THR_M0},
  2570. {0x0002, CMN_PDIAG_PLL0_CTRL_M0},
  2571. {0x0002, CMN_PDIAG_PLL0_CTRL_M1},
  2572. {0x0002, CMN_PDIAG_PLL1_CTRL_M0},
  2573. {0x0001, CMN_PLL0_SS_CTRL1_M0},
  2574. {0x0001, CMN_PLL0_SS_CTRL1_M1},
  2575. {0x0001, CMN_PLL1_SS_CTRL1_M0},
  2576. {0x011B, CMN_PLL0_SS_CTRL2_M0},
  2577. {0x011B, CMN_PLL0_SS_CTRL2_M1},
  2578. {0x011B, CMN_PLL1_SS_CTRL2_M0},
  2579. {0x006E, CMN_PLL0_SS_CTRL3_M0},
  2580. {0x0058, CMN_PLL0_SS_CTRL3_M1},
  2581. {0x006E, CMN_PLL1_SS_CTRL3_M0},
  2582. {0x000E, CMN_PLL0_SS_CTRL4_M0},
  2583. {0x0012, CMN_PLL0_SS_CTRL4_M1},
  2584. {0x000E, CMN_PLL1_SS_CTRL4_M0},
  2585. {0x0C5E, CMN_PLL0_VCOCAL_REFTIM_START},
  2586. {0x0C5E, CMN_PLL1_VCOCAL_REFTIM_START},
  2587. {0x0C56, CMN_PLL0_VCOCAL_PLLCNT_START},
  2588. {0x0C56, CMN_PLL1_VCOCAL_PLLCNT_START},
  2589. {0x0003, CMN_PLL0_VCOCAL_TCTRL},
  2590. {0x0003, CMN_PLL1_VCOCAL_TCTRL},
  2591. {0x00C7, CMN_PLL0_LOCK_REFCNT_START},
  2592. {0x00C7, CMN_PLL1_LOCK_REFCNT_START},
  2593. {0x00C7, CMN_PLL0_LOCK_PLLCNT_START},
  2594. {0x00C7, CMN_PLL1_LOCK_PLLCNT_START},
  2595. {0x0005, CMN_PLL0_LOCK_PLLCNT_THR},
  2596. {0x0005, CMN_PLL1_LOCK_PLLCNT_THR}
  2597. };
  2598. static struct cdns_torrent_vals pcie_100_int_ssc_cmn_vals = {
  2599. .reg_pairs = pcie_100_int_ssc_cmn_regs,
  2600. .num_regs = ARRAY_SIZE(pcie_100_int_ssc_cmn_regs),
  2601. };
  2602. /* Single link PCIe, 100 MHz Ref clk, internal SSC */
  2603. static struct cdns_reg_pairs sl_pcie_100_int_ssc_cmn_regs[] = {
  2604. {0x0004, CMN_PLL0_DSM_DIAG_M0},
  2605. {0x0004, CMN_PLL0_DSM_DIAG_M1},
  2606. {0x0004, CMN_PLL1_DSM_DIAG_M0},
  2607. {0x0509, CMN_PDIAG_PLL0_CP_PADJ_M0},
  2608. {0x0509, CMN_PDIAG_PLL0_CP_PADJ_M1},
  2609. {0x0509, CMN_PDIAG_PLL1_CP_PADJ_M0},
  2610. {0x0F00, CMN_PDIAG_PLL0_CP_IADJ_M0},
  2611. {0x0F00, CMN_PDIAG_PLL0_CP_IADJ_M1},
  2612. {0x0F00, CMN_PDIAG_PLL1_CP_IADJ_M0},
  2613. {0x0F08, CMN_PDIAG_PLL0_FILT_PADJ_M0},
  2614. {0x0F08, CMN_PDIAG_PLL0_FILT_PADJ_M1},
  2615. {0x0F08, CMN_PDIAG_PLL1_FILT_PADJ_M0},
  2616. {0x0064, CMN_PLL0_INTDIV_M0},
  2617. {0x0050, CMN_PLL0_INTDIV_M1},
  2618. {0x0050, CMN_PLL1_INTDIV_M0},
  2619. {0x0002, CMN_PLL0_FRACDIVH_M0},
  2620. {0x0002, CMN_PLL0_FRACDIVH_M1},
  2621. {0x0002, CMN_PLL1_FRACDIVH_M0},
  2622. {0x0044, CMN_PLL0_HIGH_THR_M0},
  2623. {0x0036, CMN_PLL0_HIGH_THR_M1},
  2624. {0x0036, CMN_PLL1_HIGH_THR_M0},
  2625. {0x0002, CMN_PDIAG_PLL0_CTRL_M0},
  2626. {0x0002, CMN_PDIAG_PLL0_CTRL_M1},
  2627. {0x0002, CMN_PDIAG_PLL1_CTRL_M0},
  2628. {0x0001, CMN_PLL0_SS_CTRL1_M0},
  2629. {0x0001, CMN_PLL0_SS_CTRL1_M1},
  2630. {0x0001, CMN_PLL1_SS_CTRL1_M0},
  2631. {0x011B, CMN_PLL0_SS_CTRL2_M0},
  2632. {0x011B, CMN_PLL0_SS_CTRL2_M1},
  2633. {0x011B, CMN_PLL1_SS_CTRL2_M0},
  2634. {0x006E, CMN_PLL0_SS_CTRL3_M0},
  2635. {0x0058, CMN_PLL0_SS_CTRL3_M1},
  2636. {0x0058, CMN_PLL1_SS_CTRL3_M0},
  2637. {0x000E, CMN_PLL0_SS_CTRL4_M0},
  2638. {0x0012, CMN_PLL0_SS_CTRL4_M1},
  2639. {0x0012, CMN_PLL1_SS_CTRL4_M0},
  2640. {0x0C5E, CMN_PLL0_VCOCAL_REFTIM_START},
  2641. {0x0C5E, CMN_PLL1_VCOCAL_REFTIM_START},
  2642. {0x0C56, CMN_PLL0_VCOCAL_PLLCNT_START},
  2643. {0x0C56, CMN_PLL1_VCOCAL_PLLCNT_START},
  2644. {0x0003, CMN_PLL0_VCOCAL_TCTRL},
  2645. {0x0003, CMN_PLL1_VCOCAL_TCTRL},
  2646. {0x00C7, CMN_PLL0_LOCK_REFCNT_START},
  2647. {0x00C7, CMN_PLL1_LOCK_REFCNT_START},
  2648. {0x00C7, CMN_PLL0_LOCK_PLLCNT_START},
  2649. {0x00C7, CMN_PLL1_LOCK_PLLCNT_START},
  2650. {0x0005, CMN_PLL0_LOCK_PLLCNT_THR},
  2651. {0x0005, CMN_PLL1_LOCK_PLLCNT_THR}
  2652. };
  2653. static struct cdns_torrent_vals sl_pcie_100_int_ssc_cmn_vals = {
  2654. .reg_pairs = sl_pcie_100_int_ssc_cmn_regs,
  2655. .num_regs = ARRAY_SIZE(sl_pcie_100_int_ssc_cmn_regs),
  2656. };
  2657. /* PCIe, 100 MHz Ref clk, no SSC & external SSC */
  2658. static struct cdns_reg_pairs pcie_100_ext_no_ssc_cmn_regs[] = {
  2659. {0x0003, CMN_PLL0_VCOCAL_TCTRL},
  2660. {0x0003, CMN_PLL1_VCOCAL_TCTRL}
  2661. };
  2662. static struct cdns_reg_pairs pcie_100_ext_no_ssc_rx_ln_regs[] = {
  2663. {0x0019, RX_REE_TAP1_CLIP},
  2664. {0x0019, RX_REE_TAP2TON_CLIP},
  2665. {0x0001, RX_DIAG_ACYA}
  2666. };
  2667. static struct cdns_torrent_vals pcie_100_no_ssc_cmn_vals = {
  2668. .reg_pairs = pcie_100_ext_no_ssc_cmn_regs,
  2669. .num_regs = ARRAY_SIZE(pcie_100_ext_no_ssc_cmn_regs),
  2670. };
  2671. static struct cdns_torrent_vals pcie_100_no_ssc_rx_ln_vals = {
  2672. .reg_pairs = pcie_100_ext_no_ssc_rx_ln_regs,
  2673. .num_regs = ARRAY_SIZE(pcie_100_ext_no_ssc_rx_ln_regs),
  2674. };
  2675. static const struct cdns_torrent_data cdns_map_torrent = {
  2676. .block_offset_shift = 0x2,
  2677. .reg_offset_shift = 0x2,
  2678. .link_cmn_vals = {
  2679. [TYPE_PCIE] = {
  2680. [TYPE_NONE] = {
  2681. [NO_SSC] = NULL,
  2682. [EXTERNAL_SSC] = NULL,
  2683. [INTERNAL_SSC] = NULL,
  2684. },
  2685. [TYPE_SGMII] = {
  2686. [NO_SSC] = &pcie_sgmii_link_cmn_vals,
  2687. [EXTERNAL_SSC] = &pcie_sgmii_link_cmn_vals,
  2688. [INTERNAL_SSC] = &pcie_sgmii_link_cmn_vals,
  2689. },
  2690. [TYPE_QSGMII] = {
  2691. [NO_SSC] = &pcie_sgmii_link_cmn_vals,
  2692. [EXTERNAL_SSC] = &pcie_sgmii_link_cmn_vals,
  2693. [INTERNAL_SSC] = &pcie_sgmii_link_cmn_vals,
  2694. },
  2695. [TYPE_USB] = {
  2696. [NO_SSC] = &pcie_usb_link_cmn_vals,
  2697. [EXTERNAL_SSC] = &pcie_usb_link_cmn_vals,
  2698. [INTERNAL_SSC] = &pcie_usb_link_cmn_vals,
  2699. },
  2700. },
  2701. [TYPE_SGMII] = {
  2702. [TYPE_NONE] = {
  2703. [NO_SSC] = &sl_sgmii_link_cmn_vals,
  2704. },
  2705. [TYPE_PCIE] = {
  2706. [NO_SSC] = &pcie_sgmii_link_cmn_vals,
  2707. [EXTERNAL_SSC] = &pcie_sgmii_link_cmn_vals,
  2708. [INTERNAL_SSC] = &pcie_sgmii_link_cmn_vals,
  2709. },
  2710. [TYPE_USB] = {
  2711. [NO_SSC] = &usb_sgmii_link_cmn_vals,
  2712. [EXTERNAL_SSC] = &usb_sgmii_link_cmn_vals,
  2713. [INTERNAL_SSC] = &usb_sgmii_link_cmn_vals,
  2714. },
  2715. },
  2716. [TYPE_QSGMII] = {
  2717. [TYPE_NONE] = {
  2718. [NO_SSC] = &sl_sgmii_link_cmn_vals,
  2719. },
  2720. [TYPE_PCIE] = {
  2721. [NO_SSC] = &pcie_sgmii_link_cmn_vals,
  2722. [EXTERNAL_SSC] = &pcie_sgmii_link_cmn_vals,
  2723. [INTERNAL_SSC] = &pcie_sgmii_link_cmn_vals,
  2724. },
  2725. [TYPE_USB] = {
  2726. [NO_SSC] = &usb_sgmii_link_cmn_vals,
  2727. [EXTERNAL_SSC] = &usb_sgmii_link_cmn_vals,
  2728. [INTERNAL_SSC] = &usb_sgmii_link_cmn_vals,
  2729. },
  2730. },
  2731. [TYPE_USB] = {
  2732. [TYPE_NONE] = {
  2733. [NO_SSC] = &sl_usb_link_cmn_vals,
  2734. [EXTERNAL_SSC] = &sl_usb_link_cmn_vals,
  2735. [INTERNAL_SSC] = &sl_usb_link_cmn_vals,
  2736. },
  2737. [TYPE_PCIE] = {
  2738. [NO_SSC] = &pcie_usb_link_cmn_vals,
  2739. [EXTERNAL_SSC] = &pcie_usb_link_cmn_vals,
  2740. [INTERNAL_SSC] = &pcie_usb_link_cmn_vals,
  2741. },
  2742. [TYPE_SGMII] = {
  2743. [NO_SSC] = &usb_sgmii_link_cmn_vals,
  2744. [EXTERNAL_SSC] = &usb_sgmii_link_cmn_vals,
  2745. [INTERNAL_SSC] = &usb_sgmii_link_cmn_vals,
  2746. },
  2747. [TYPE_QSGMII] = {
  2748. [NO_SSC] = &usb_sgmii_link_cmn_vals,
  2749. [EXTERNAL_SSC] = &usb_sgmii_link_cmn_vals,
  2750. [INTERNAL_SSC] = &usb_sgmii_link_cmn_vals,
  2751. },
  2752. },
  2753. },
  2754. .xcvr_diag_vals = {
  2755. [TYPE_PCIE] = {
  2756. [TYPE_NONE] = {
  2757. [NO_SSC] = NULL,
  2758. [EXTERNAL_SSC] = NULL,
  2759. [INTERNAL_SSC] = NULL,
  2760. },
  2761. [TYPE_SGMII] = {
  2762. [NO_SSC] = &pcie_sgmii_xcvr_diag_ln_vals,
  2763. [EXTERNAL_SSC] = &pcie_sgmii_xcvr_diag_ln_vals,
  2764. [INTERNAL_SSC] = &pcie_sgmii_xcvr_diag_ln_vals,
  2765. },
  2766. [TYPE_QSGMII] = {
  2767. [NO_SSC] = &pcie_sgmii_xcvr_diag_ln_vals,
  2768. [EXTERNAL_SSC] = &pcie_sgmii_xcvr_diag_ln_vals,
  2769. [INTERNAL_SSC] = &pcie_sgmii_xcvr_diag_ln_vals,
  2770. },
  2771. [TYPE_USB] = {
  2772. [NO_SSC] = &pcie_usb_xcvr_diag_ln_vals,
  2773. [EXTERNAL_SSC] = &pcie_usb_xcvr_diag_ln_vals,
  2774. [INTERNAL_SSC] = &pcie_usb_xcvr_diag_ln_vals,
  2775. },
  2776. },
  2777. [TYPE_SGMII] = {
  2778. [TYPE_NONE] = {
  2779. [NO_SSC] = &sl_sgmii_xcvr_diag_ln_vals,
  2780. },
  2781. [TYPE_PCIE] = {
  2782. [NO_SSC] = &sgmii_pcie_xcvr_diag_ln_vals,
  2783. [EXTERNAL_SSC] = &sgmii_pcie_xcvr_diag_ln_vals,
  2784. [INTERNAL_SSC] = &sgmii_pcie_xcvr_diag_ln_vals,
  2785. },
  2786. [TYPE_USB] = {
  2787. [NO_SSC] = &sgmii_usb_xcvr_diag_ln_vals,
  2788. [EXTERNAL_SSC] = &sgmii_usb_xcvr_diag_ln_vals,
  2789. [INTERNAL_SSC] = &sgmii_usb_xcvr_diag_ln_vals,
  2790. },
  2791. },
  2792. [TYPE_QSGMII] = {
  2793. [TYPE_NONE] = {
  2794. [NO_SSC] = &sl_sgmii_xcvr_diag_ln_vals,
  2795. },
  2796. [TYPE_PCIE] = {
  2797. [NO_SSC] = &sgmii_pcie_xcvr_diag_ln_vals,
  2798. [EXTERNAL_SSC] = &sgmii_pcie_xcvr_diag_ln_vals,
  2799. [INTERNAL_SSC] = &sgmii_pcie_xcvr_diag_ln_vals,
  2800. },
  2801. [TYPE_USB] = {
  2802. [NO_SSC] = &sgmii_usb_xcvr_diag_ln_vals,
  2803. [EXTERNAL_SSC] = &sgmii_usb_xcvr_diag_ln_vals,
  2804. [INTERNAL_SSC] = &sgmii_usb_xcvr_diag_ln_vals,
  2805. },
  2806. },
  2807. [TYPE_USB] = {
  2808. [TYPE_NONE] = {
  2809. [NO_SSC] = &sl_usb_xcvr_diag_ln_vals,
  2810. [EXTERNAL_SSC] = &sl_usb_xcvr_diag_ln_vals,
  2811. [INTERNAL_SSC] = &sl_usb_xcvr_diag_ln_vals,
  2812. },
  2813. [TYPE_PCIE] = {
  2814. [NO_SSC] = &usb_pcie_xcvr_diag_ln_vals,
  2815. [EXTERNAL_SSC] = &usb_pcie_xcvr_diag_ln_vals,
  2816. [INTERNAL_SSC] = &usb_pcie_xcvr_diag_ln_vals,
  2817. },
  2818. [TYPE_SGMII] = {
  2819. [NO_SSC] = &usb_sgmii_xcvr_diag_ln_vals,
  2820. [EXTERNAL_SSC] = &usb_sgmii_xcvr_diag_ln_vals,
  2821. [INTERNAL_SSC] = &usb_sgmii_xcvr_diag_ln_vals,
  2822. },
  2823. [TYPE_QSGMII] = {
  2824. [NO_SSC] = &usb_sgmii_xcvr_diag_ln_vals,
  2825. [EXTERNAL_SSC] = &usb_sgmii_xcvr_diag_ln_vals,
  2826. [INTERNAL_SSC] = &usb_sgmii_xcvr_diag_ln_vals,
  2827. },
  2828. },
  2829. },
  2830. .pcs_cmn_vals = {
  2831. [TYPE_USB] = {
  2832. [TYPE_NONE] = {
  2833. [NO_SSC] = &usb_phy_pcs_cmn_vals,
  2834. [EXTERNAL_SSC] = &usb_phy_pcs_cmn_vals,
  2835. [INTERNAL_SSC] = &usb_phy_pcs_cmn_vals,
  2836. },
  2837. [TYPE_PCIE] = {
  2838. [NO_SSC] = &usb_phy_pcs_cmn_vals,
  2839. [EXTERNAL_SSC] = &usb_phy_pcs_cmn_vals,
  2840. [INTERNAL_SSC] = &usb_phy_pcs_cmn_vals,
  2841. },
  2842. [TYPE_SGMII] = {
  2843. [NO_SSC] = &usb_phy_pcs_cmn_vals,
  2844. [EXTERNAL_SSC] = &usb_phy_pcs_cmn_vals,
  2845. [INTERNAL_SSC] = &usb_phy_pcs_cmn_vals,
  2846. },
  2847. [TYPE_QSGMII] = {
  2848. [NO_SSC] = &usb_phy_pcs_cmn_vals,
  2849. [EXTERNAL_SSC] = &usb_phy_pcs_cmn_vals,
  2850. [INTERNAL_SSC] = &usb_phy_pcs_cmn_vals,
  2851. },
  2852. },
  2853. },
  2854. .cmn_vals = {
  2855. [TYPE_PCIE] = {
  2856. [TYPE_NONE] = {
  2857. [NO_SSC] = &pcie_100_no_ssc_cmn_vals,
  2858. [EXTERNAL_SSC] = &pcie_100_no_ssc_cmn_vals,
  2859. [INTERNAL_SSC] = &sl_pcie_100_int_ssc_cmn_vals,
  2860. },
  2861. [TYPE_SGMII] = {
  2862. [NO_SSC] = &pcie_100_no_ssc_cmn_vals,
  2863. [EXTERNAL_SSC] = &pcie_100_no_ssc_cmn_vals,
  2864. [INTERNAL_SSC] = &pcie_100_int_ssc_cmn_vals,
  2865. },
  2866. [TYPE_QSGMII] = {
  2867. [NO_SSC] = &pcie_100_no_ssc_cmn_vals,
  2868. [EXTERNAL_SSC] = &pcie_100_no_ssc_cmn_vals,
  2869. [INTERNAL_SSC] = &pcie_100_int_ssc_cmn_vals,
  2870. },
  2871. [TYPE_USB] = {
  2872. [NO_SSC] = &pcie_100_no_ssc_cmn_vals,
  2873. [EXTERNAL_SSC] = &pcie_100_no_ssc_cmn_vals,
  2874. [INTERNAL_SSC] = &pcie_100_int_ssc_cmn_vals,
  2875. },
  2876. },
  2877. [TYPE_SGMII] = {
  2878. [TYPE_NONE] = {
  2879. [NO_SSC] = &sgmii_100_no_ssc_cmn_vals,
  2880. },
  2881. [TYPE_PCIE] = {
  2882. [NO_SSC] = &sgmii_100_no_ssc_cmn_vals,
  2883. [EXTERNAL_SSC] = &sgmii_100_no_ssc_cmn_vals,
  2884. [INTERNAL_SSC] = &sgmii_100_int_ssc_cmn_vals,
  2885. },
  2886. [TYPE_USB] = {
  2887. [NO_SSC] = &sgmii_100_no_ssc_cmn_vals,
  2888. [EXTERNAL_SSC] = &sgmii_100_no_ssc_cmn_vals,
  2889. [INTERNAL_SSC] = &sgmii_100_no_ssc_cmn_vals,
  2890. },
  2891. },
  2892. [TYPE_QSGMII] = {
  2893. [TYPE_NONE] = {
  2894. [NO_SSC] = &qsgmii_100_no_ssc_cmn_vals,
  2895. },
  2896. [TYPE_PCIE] = {
  2897. [NO_SSC] = &qsgmii_100_no_ssc_cmn_vals,
  2898. [EXTERNAL_SSC] = &qsgmii_100_no_ssc_cmn_vals,
  2899. [INTERNAL_SSC] = &qsgmii_100_int_ssc_cmn_vals,
  2900. },
  2901. [TYPE_USB] = {
  2902. [NO_SSC] = &qsgmii_100_no_ssc_cmn_vals,
  2903. [EXTERNAL_SSC] = &qsgmii_100_no_ssc_cmn_vals,
  2904. [INTERNAL_SSC] = &qsgmii_100_no_ssc_cmn_vals,
  2905. },
  2906. },
  2907. [TYPE_USB] = {
  2908. [TYPE_NONE] = {
  2909. [NO_SSC] = &usb_100_no_ssc_cmn_vals,
  2910. [EXTERNAL_SSC] = &usb_100_no_ssc_cmn_vals,
  2911. [INTERNAL_SSC] = &sl_usb_100_int_ssc_cmn_vals,
  2912. },
  2913. [TYPE_PCIE] = {
  2914. [NO_SSC] = &usb_100_no_ssc_cmn_vals,
  2915. [EXTERNAL_SSC] = &usb_100_no_ssc_cmn_vals,
  2916. [INTERNAL_SSC] = &usb_100_int_ssc_cmn_vals,
  2917. },
  2918. [TYPE_SGMII] = {
  2919. [NO_SSC] = &usb_100_no_ssc_cmn_vals,
  2920. [EXTERNAL_SSC] = &usb_100_no_ssc_cmn_vals,
  2921. [INTERNAL_SSC] = &sl_usb_100_int_ssc_cmn_vals,
  2922. },
  2923. [TYPE_QSGMII] = {
  2924. [NO_SSC] = &usb_100_no_ssc_cmn_vals,
  2925. [EXTERNAL_SSC] = &usb_100_no_ssc_cmn_vals,
  2926. [INTERNAL_SSC] = &sl_usb_100_int_ssc_cmn_vals,
  2927. },
  2928. },
  2929. },
  2930. .tx_ln_vals = {
  2931. [TYPE_PCIE] = {
  2932. [TYPE_NONE] = {
  2933. [NO_SSC] = NULL,
  2934. [EXTERNAL_SSC] = NULL,
  2935. [INTERNAL_SSC] = NULL,
  2936. },
  2937. [TYPE_SGMII] = {
  2938. [NO_SSC] = NULL,
  2939. [EXTERNAL_SSC] = NULL,
  2940. [INTERNAL_SSC] = NULL,
  2941. },
  2942. [TYPE_QSGMII] = {
  2943. [NO_SSC] = NULL,
  2944. [EXTERNAL_SSC] = NULL,
  2945. [INTERNAL_SSC] = NULL,
  2946. },
  2947. [TYPE_USB] = {
  2948. [NO_SSC] = NULL,
  2949. [EXTERNAL_SSC] = NULL,
  2950. [INTERNAL_SSC] = NULL,
  2951. },
  2952. },
  2953. [TYPE_SGMII] = {
  2954. [TYPE_NONE] = {
  2955. [NO_SSC] = &sgmii_100_no_ssc_tx_ln_vals,
  2956. },
  2957. [TYPE_PCIE] = {
  2958. [NO_SSC] = &sgmii_100_no_ssc_tx_ln_vals,
  2959. [EXTERNAL_SSC] = &sgmii_100_no_ssc_tx_ln_vals,
  2960. [INTERNAL_SSC] = &sgmii_100_no_ssc_tx_ln_vals,
  2961. },
  2962. [TYPE_USB] = {
  2963. [NO_SSC] = &sgmii_100_no_ssc_tx_ln_vals,
  2964. [EXTERNAL_SSC] = &sgmii_100_no_ssc_tx_ln_vals,
  2965. [INTERNAL_SSC] = &sgmii_100_no_ssc_tx_ln_vals,
  2966. },
  2967. },
  2968. [TYPE_QSGMII] = {
  2969. [TYPE_NONE] = {
  2970. [NO_SSC] = &qsgmii_100_no_ssc_tx_ln_vals,
  2971. },
  2972. [TYPE_PCIE] = {
  2973. [NO_SSC] = &qsgmii_100_no_ssc_tx_ln_vals,
  2974. [EXTERNAL_SSC] = &qsgmii_100_no_ssc_tx_ln_vals,
  2975. [INTERNAL_SSC] = &qsgmii_100_no_ssc_tx_ln_vals,
  2976. },
  2977. [TYPE_USB] = {
  2978. [NO_SSC] = &qsgmii_100_no_ssc_tx_ln_vals,
  2979. [EXTERNAL_SSC] = &qsgmii_100_no_ssc_tx_ln_vals,
  2980. [INTERNAL_SSC] = &qsgmii_100_no_ssc_tx_ln_vals,
  2981. },
  2982. },
  2983. [TYPE_USB] = {
  2984. [TYPE_NONE] = {
  2985. [NO_SSC] = &usb_100_no_ssc_tx_ln_vals,
  2986. [EXTERNAL_SSC] = &usb_100_no_ssc_tx_ln_vals,
  2987. [INTERNAL_SSC] = &usb_100_no_ssc_tx_ln_vals,
  2988. },
  2989. [TYPE_PCIE] = {
  2990. [NO_SSC] = &usb_100_no_ssc_tx_ln_vals,
  2991. [EXTERNAL_SSC] = &usb_100_no_ssc_tx_ln_vals,
  2992. [INTERNAL_SSC] = &usb_100_no_ssc_tx_ln_vals,
  2993. },
  2994. [TYPE_SGMII] = {
  2995. [NO_SSC] = &usb_100_no_ssc_tx_ln_vals,
  2996. [EXTERNAL_SSC] = &usb_100_no_ssc_tx_ln_vals,
  2997. [INTERNAL_SSC] = &usb_100_no_ssc_tx_ln_vals,
  2998. },
  2999. [TYPE_QSGMII] = {
  3000. [NO_SSC] = &usb_100_no_ssc_tx_ln_vals,
  3001. [EXTERNAL_SSC] = &usb_100_no_ssc_tx_ln_vals,
  3002. [INTERNAL_SSC] = &usb_100_no_ssc_tx_ln_vals,
  3003. },
  3004. },
  3005. },
  3006. .rx_ln_vals = {
  3007. [TYPE_PCIE] = {
  3008. [TYPE_NONE] = {
  3009. [NO_SSC] = &pcie_100_no_ssc_rx_ln_vals,
  3010. [EXTERNAL_SSC] = &pcie_100_no_ssc_rx_ln_vals,
  3011. [INTERNAL_SSC] = &pcie_100_no_ssc_rx_ln_vals,
  3012. },
  3013. [TYPE_SGMII] = {
  3014. [NO_SSC] = &pcie_100_no_ssc_rx_ln_vals,
  3015. [EXTERNAL_SSC] = &pcie_100_no_ssc_rx_ln_vals,
  3016. [INTERNAL_SSC] = &pcie_100_no_ssc_rx_ln_vals,
  3017. },
  3018. [TYPE_QSGMII] = {
  3019. [NO_SSC] = &pcie_100_no_ssc_rx_ln_vals,
  3020. [EXTERNAL_SSC] = &pcie_100_no_ssc_rx_ln_vals,
  3021. [INTERNAL_SSC] = &pcie_100_no_ssc_rx_ln_vals,
  3022. },
  3023. [TYPE_USB] = {
  3024. [NO_SSC] = &pcie_100_no_ssc_rx_ln_vals,
  3025. [EXTERNAL_SSC] = &pcie_100_no_ssc_rx_ln_vals,
  3026. [INTERNAL_SSC] = &pcie_100_no_ssc_rx_ln_vals,
  3027. },
  3028. },
  3029. [TYPE_SGMII] = {
  3030. [TYPE_NONE] = {
  3031. [NO_SSC] = &sgmii_100_no_ssc_rx_ln_vals,
  3032. },
  3033. [TYPE_PCIE] = {
  3034. [NO_SSC] = &sgmii_100_no_ssc_rx_ln_vals,
  3035. [EXTERNAL_SSC] = &sgmii_100_no_ssc_rx_ln_vals,
  3036. [INTERNAL_SSC] = &sgmii_100_no_ssc_rx_ln_vals,
  3037. },
  3038. [TYPE_USB] = {
  3039. [NO_SSC] = &sgmii_100_no_ssc_rx_ln_vals,
  3040. [EXTERNAL_SSC] = &sgmii_100_no_ssc_rx_ln_vals,
  3041. [INTERNAL_SSC] = &sgmii_100_no_ssc_rx_ln_vals,
  3042. },
  3043. },
  3044. [TYPE_QSGMII] = {
  3045. [TYPE_NONE] = {
  3046. [NO_SSC] = &qsgmii_100_no_ssc_rx_ln_vals,
  3047. },
  3048. [TYPE_PCIE] = {
  3049. [NO_SSC] = &qsgmii_100_no_ssc_rx_ln_vals,
  3050. [EXTERNAL_SSC] = &qsgmii_100_no_ssc_rx_ln_vals,
  3051. [INTERNAL_SSC] = &qsgmii_100_no_ssc_rx_ln_vals,
  3052. },
  3053. [TYPE_USB] = {
  3054. [NO_SSC] = &qsgmii_100_no_ssc_rx_ln_vals,
  3055. [EXTERNAL_SSC] = &qsgmii_100_no_ssc_rx_ln_vals,
  3056. [INTERNAL_SSC] = &qsgmii_100_no_ssc_rx_ln_vals,
  3057. },
  3058. },
  3059. [TYPE_USB] = {
  3060. [TYPE_NONE] = {
  3061. [NO_SSC] = &usb_100_no_ssc_rx_ln_vals,
  3062. [EXTERNAL_SSC] = &usb_100_no_ssc_rx_ln_vals,
  3063. [INTERNAL_SSC] = &usb_100_no_ssc_rx_ln_vals,
  3064. },
  3065. [TYPE_PCIE] = {
  3066. [NO_SSC] = &usb_100_no_ssc_rx_ln_vals,
  3067. [EXTERNAL_SSC] = &usb_100_no_ssc_rx_ln_vals,
  3068. [INTERNAL_SSC] = &usb_100_no_ssc_rx_ln_vals,
  3069. },
  3070. [TYPE_SGMII] = {
  3071. [NO_SSC] = &usb_100_no_ssc_rx_ln_vals,
  3072. [EXTERNAL_SSC] = &usb_100_no_ssc_rx_ln_vals,
  3073. [INTERNAL_SSC] = &usb_100_no_ssc_rx_ln_vals,
  3074. },
  3075. [TYPE_QSGMII] = {
  3076. [NO_SSC] = &usb_100_no_ssc_rx_ln_vals,
  3077. [EXTERNAL_SSC] = &usb_100_no_ssc_rx_ln_vals,
  3078. [INTERNAL_SSC] = &usb_100_no_ssc_rx_ln_vals,
  3079. },
  3080. },
  3081. },
  3082. };
  3083. static const struct cdns_torrent_data ti_j721e_map_torrent = {
  3084. .block_offset_shift = 0x0,
  3085. .reg_offset_shift = 0x1,
  3086. .link_cmn_vals = {
  3087. [TYPE_PCIE] = {
  3088. [TYPE_NONE] = {
  3089. [NO_SSC] = NULL,
  3090. [EXTERNAL_SSC] = NULL,
  3091. [INTERNAL_SSC] = NULL,
  3092. },
  3093. [TYPE_SGMII] = {
  3094. [NO_SSC] = &pcie_sgmii_link_cmn_vals,
  3095. [EXTERNAL_SSC] = &pcie_sgmii_link_cmn_vals,
  3096. [INTERNAL_SSC] = &pcie_sgmii_link_cmn_vals,
  3097. },
  3098. [TYPE_QSGMII] = {
  3099. [NO_SSC] = &pcie_sgmii_link_cmn_vals,
  3100. [EXTERNAL_SSC] = &pcie_sgmii_link_cmn_vals,
  3101. [INTERNAL_SSC] = &pcie_sgmii_link_cmn_vals,
  3102. },
  3103. [TYPE_USB] = {
  3104. [NO_SSC] = &pcie_usb_link_cmn_vals,
  3105. [EXTERNAL_SSC] = &pcie_usb_link_cmn_vals,
  3106. [INTERNAL_SSC] = &pcie_usb_link_cmn_vals,
  3107. },
  3108. },
  3109. [TYPE_SGMII] = {
  3110. [TYPE_NONE] = {
  3111. [NO_SSC] = &sl_sgmii_link_cmn_vals,
  3112. },
  3113. [TYPE_PCIE] = {
  3114. [NO_SSC] = &pcie_sgmii_link_cmn_vals,
  3115. [EXTERNAL_SSC] = &pcie_sgmii_link_cmn_vals,
  3116. [INTERNAL_SSC] = &pcie_sgmii_link_cmn_vals,
  3117. },
  3118. [TYPE_USB] = {
  3119. [NO_SSC] = &usb_sgmii_link_cmn_vals,
  3120. [EXTERNAL_SSC] = &usb_sgmii_link_cmn_vals,
  3121. [INTERNAL_SSC] = &usb_sgmii_link_cmn_vals,
  3122. },
  3123. },
  3124. [TYPE_QSGMII] = {
  3125. [TYPE_NONE] = {
  3126. [NO_SSC] = &sl_sgmii_link_cmn_vals,
  3127. },
  3128. [TYPE_PCIE] = {
  3129. [NO_SSC] = &pcie_sgmii_link_cmn_vals,
  3130. [EXTERNAL_SSC] = &pcie_sgmii_link_cmn_vals,
  3131. [INTERNAL_SSC] = &pcie_sgmii_link_cmn_vals,
  3132. },
  3133. [TYPE_USB] = {
  3134. [NO_SSC] = &usb_sgmii_link_cmn_vals,
  3135. [EXTERNAL_SSC] = &usb_sgmii_link_cmn_vals,
  3136. [INTERNAL_SSC] = &usb_sgmii_link_cmn_vals,
  3137. },
  3138. },
  3139. [TYPE_USB] = {
  3140. [TYPE_NONE] = {
  3141. [NO_SSC] = &sl_usb_link_cmn_vals,
  3142. [EXTERNAL_SSC] = &sl_usb_link_cmn_vals,
  3143. [INTERNAL_SSC] = &sl_usb_link_cmn_vals,
  3144. },
  3145. [TYPE_PCIE] = {
  3146. [NO_SSC] = &pcie_usb_link_cmn_vals,
  3147. [EXTERNAL_SSC] = &pcie_usb_link_cmn_vals,
  3148. [INTERNAL_SSC] = &pcie_usb_link_cmn_vals,
  3149. },
  3150. [TYPE_SGMII] = {
  3151. [NO_SSC] = &usb_sgmii_link_cmn_vals,
  3152. [EXTERNAL_SSC] = &usb_sgmii_link_cmn_vals,
  3153. [INTERNAL_SSC] = &usb_sgmii_link_cmn_vals,
  3154. },
  3155. [TYPE_QSGMII] = {
  3156. [NO_SSC] = &usb_sgmii_link_cmn_vals,
  3157. [EXTERNAL_SSC] = &usb_sgmii_link_cmn_vals,
  3158. [INTERNAL_SSC] = &usb_sgmii_link_cmn_vals,
  3159. },
  3160. },
  3161. },
  3162. .xcvr_diag_vals = {
  3163. [TYPE_PCIE] = {
  3164. [TYPE_NONE] = {
  3165. [NO_SSC] = NULL,
  3166. [EXTERNAL_SSC] = NULL,
  3167. [INTERNAL_SSC] = NULL,
  3168. },
  3169. [TYPE_SGMII] = {
  3170. [NO_SSC] = &pcie_sgmii_xcvr_diag_ln_vals,
  3171. [EXTERNAL_SSC] = &pcie_sgmii_xcvr_diag_ln_vals,
  3172. [INTERNAL_SSC] = &pcie_sgmii_xcvr_diag_ln_vals,
  3173. },
  3174. [TYPE_QSGMII] = {
  3175. [NO_SSC] = &pcie_sgmii_xcvr_diag_ln_vals,
  3176. [EXTERNAL_SSC] = &pcie_sgmii_xcvr_diag_ln_vals,
  3177. [INTERNAL_SSC] = &pcie_sgmii_xcvr_diag_ln_vals,
  3178. },
  3179. [TYPE_USB] = {
  3180. [NO_SSC] = &pcie_usb_xcvr_diag_ln_vals,
  3181. [EXTERNAL_SSC] = &pcie_usb_xcvr_diag_ln_vals,
  3182. [INTERNAL_SSC] = &pcie_usb_xcvr_diag_ln_vals,
  3183. },
  3184. },
  3185. [TYPE_SGMII] = {
  3186. [TYPE_NONE] = {
  3187. [NO_SSC] = &sl_sgmii_xcvr_diag_ln_vals,
  3188. },
  3189. [TYPE_PCIE] = {
  3190. [NO_SSC] = &sgmii_pcie_xcvr_diag_ln_vals,
  3191. [EXTERNAL_SSC] = &sgmii_pcie_xcvr_diag_ln_vals,
  3192. [INTERNAL_SSC] = &sgmii_pcie_xcvr_diag_ln_vals,
  3193. },
  3194. [TYPE_USB] = {
  3195. [NO_SSC] = &sgmii_usb_xcvr_diag_ln_vals,
  3196. [EXTERNAL_SSC] = &sgmii_usb_xcvr_diag_ln_vals,
  3197. [INTERNAL_SSC] = &sgmii_usb_xcvr_diag_ln_vals,
  3198. },
  3199. },
  3200. [TYPE_QSGMII] = {
  3201. [TYPE_NONE] = {
  3202. [NO_SSC] = &sl_sgmii_xcvr_diag_ln_vals,
  3203. },
  3204. [TYPE_PCIE] = {
  3205. [NO_SSC] = &sgmii_pcie_xcvr_diag_ln_vals,
  3206. [EXTERNAL_SSC] = &sgmii_pcie_xcvr_diag_ln_vals,
  3207. [INTERNAL_SSC] = &sgmii_pcie_xcvr_diag_ln_vals,
  3208. },
  3209. [TYPE_USB] = {
  3210. [NO_SSC] = &sgmii_usb_xcvr_diag_ln_vals,
  3211. [EXTERNAL_SSC] = &sgmii_usb_xcvr_diag_ln_vals,
  3212. [INTERNAL_SSC] = &sgmii_usb_xcvr_diag_ln_vals,
  3213. },
  3214. },
  3215. [TYPE_USB] = {
  3216. [TYPE_NONE] = {
  3217. [NO_SSC] = &sl_usb_xcvr_diag_ln_vals,
  3218. [EXTERNAL_SSC] = &sl_usb_xcvr_diag_ln_vals,
  3219. [INTERNAL_SSC] = &sl_usb_xcvr_diag_ln_vals,
  3220. },
  3221. [TYPE_PCIE] = {
  3222. [NO_SSC] = &usb_pcie_xcvr_diag_ln_vals,
  3223. [EXTERNAL_SSC] = &usb_pcie_xcvr_diag_ln_vals,
  3224. [INTERNAL_SSC] = &usb_pcie_xcvr_diag_ln_vals,
  3225. },
  3226. [TYPE_SGMII] = {
  3227. [NO_SSC] = &usb_sgmii_xcvr_diag_ln_vals,
  3228. [EXTERNAL_SSC] = &usb_sgmii_xcvr_diag_ln_vals,
  3229. [INTERNAL_SSC] = &usb_sgmii_xcvr_diag_ln_vals,
  3230. },
  3231. [TYPE_QSGMII] = {
  3232. [NO_SSC] = &usb_sgmii_xcvr_diag_ln_vals,
  3233. [EXTERNAL_SSC] = &usb_sgmii_xcvr_diag_ln_vals,
  3234. [INTERNAL_SSC] = &usb_sgmii_xcvr_diag_ln_vals,
  3235. },
  3236. },
  3237. },
  3238. .pcs_cmn_vals = {
  3239. [TYPE_USB] = {
  3240. [TYPE_NONE] = {
  3241. [NO_SSC] = &usb_phy_pcs_cmn_vals,
  3242. [EXTERNAL_SSC] = &usb_phy_pcs_cmn_vals,
  3243. [INTERNAL_SSC] = &usb_phy_pcs_cmn_vals,
  3244. },
  3245. [TYPE_PCIE] = {
  3246. [NO_SSC] = &usb_phy_pcs_cmn_vals,
  3247. [EXTERNAL_SSC] = &usb_phy_pcs_cmn_vals,
  3248. [INTERNAL_SSC] = &usb_phy_pcs_cmn_vals,
  3249. },
  3250. [TYPE_SGMII] = {
  3251. [NO_SSC] = &usb_phy_pcs_cmn_vals,
  3252. [EXTERNAL_SSC] = &usb_phy_pcs_cmn_vals,
  3253. [INTERNAL_SSC] = &usb_phy_pcs_cmn_vals,
  3254. },
  3255. [TYPE_QSGMII] = {
  3256. [NO_SSC] = &usb_phy_pcs_cmn_vals,
  3257. [EXTERNAL_SSC] = &usb_phy_pcs_cmn_vals,
  3258. [INTERNAL_SSC] = &usb_phy_pcs_cmn_vals,
  3259. },
  3260. },
  3261. },
  3262. .cmn_vals = {
  3263. [TYPE_PCIE] = {
  3264. [TYPE_NONE] = {
  3265. [NO_SSC] = &pcie_100_no_ssc_cmn_vals,
  3266. [EXTERNAL_SSC] = &pcie_100_no_ssc_cmn_vals,
  3267. [INTERNAL_SSC] = &sl_pcie_100_int_ssc_cmn_vals,
  3268. },
  3269. [TYPE_SGMII] = {
  3270. [NO_SSC] = &pcie_100_no_ssc_cmn_vals,
  3271. [EXTERNAL_SSC] = &pcie_100_no_ssc_cmn_vals,
  3272. [INTERNAL_SSC] = &pcie_100_int_ssc_cmn_vals,
  3273. },
  3274. [TYPE_QSGMII] = {
  3275. [NO_SSC] = &pcie_100_no_ssc_cmn_vals,
  3276. [EXTERNAL_SSC] = &pcie_100_no_ssc_cmn_vals,
  3277. [INTERNAL_SSC] = &pcie_100_int_ssc_cmn_vals,
  3278. },
  3279. [TYPE_USB] = {
  3280. [NO_SSC] = &pcie_100_no_ssc_cmn_vals,
  3281. [EXTERNAL_SSC] = &pcie_100_no_ssc_cmn_vals,
  3282. [INTERNAL_SSC] = &pcie_100_int_ssc_cmn_vals,
  3283. },
  3284. },
  3285. [TYPE_SGMII] = {
  3286. [TYPE_NONE] = {
  3287. [NO_SSC] = &sgmii_100_no_ssc_cmn_vals,
  3288. },
  3289. [TYPE_PCIE] = {
  3290. [NO_SSC] = &sgmii_100_no_ssc_cmn_vals,
  3291. [EXTERNAL_SSC] = &sgmii_100_no_ssc_cmn_vals,
  3292. [INTERNAL_SSC] = &sgmii_100_int_ssc_cmn_vals,
  3293. },
  3294. [TYPE_USB] = {
  3295. [NO_SSC] = &sgmii_100_no_ssc_cmn_vals,
  3296. [EXTERNAL_SSC] = &sgmii_100_no_ssc_cmn_vals,
  3297. [INTERNAL_SSC] = &sgmii_100_no_ssc_cmn_vals,
  3298. },
  3299. },
  3300. [TYPE_QSGMII] = {
  3301. [TYPE_NONE] = {
  3302. [NO_SSC] = &qsgmii_100_no_ssc_cmn_vals,
  3303. },
  3304. [TYPE_PCIE] = {
  3305. [NO_SSC] = &qsgmii_100_no_ssc_cmn_vals,
  3306. [EXTERNAL_SSC] = &qsgmii_100_no_ssc_cmn_vals,
  3307. [INTERNAL_SSC] = &qsgmii_100_int_ssc_cmn_vals,
  3308. },
  3309. [TYPE_USB] = {
  3310. [NO_SSC] = &qsgmii_100_no_ssc_cmn_vals,
  3311. [EXTERNAL_SSC] = &qsgmii_100_no_ssc_cmn_vals,
  3312. [INTERNAL_SSC] = &qsgmii_100_no_ssc_cmn_vals,
  3313. },
  3314. },
  3315. [TYPE_USB] = {
  3316. [TYPE_NONE] = {
  3317. [NO_SSC] = &usb_100_no_ssc_cmn_vals,
  3318. [EXTERNAL_SSC] = &usb_100_no_ssc_cmn_vals,
  3319. [INTERNAL_SSC] = &sl_usb_100_int_ssc_cmn_vals,
  3320. },
  3321. [TYPE_PCIE] = {
  3322. [NO_SSC] = &usb_100_no_ssc_cmn_vals,
  3323. [EXTERNAL_SSC] = &usb_100_no_ssc_cmn_vals,
  3324. [INTERNAL_SSC] = &usb_100_int_ssc_cmn_vals,
  3325. },
  3326. [TYPE_SGMII] = {
  3327. [NO_SSC] = &usb_100_no_ssc_cmn_vals,
  3328. [EXTERNAL_SSC] = &usb_100_no_ssc_cmn_vals,
  3329. [INTERNAL_SSC] = &sl_usb_100_int_ssc_cmn_vals,
  3330. },
  3331. [TYPE_QSGMII] = {
  3332. [NO_SSC] = &usb_100_no_ssc_cmn_vals,
  3333. [EXTERNAL_SSC] = &usb_100_no_ssc_cmn_vals,
  3334. [INTERNAL_SSC] = &sl_usb_100_int_ssc_cmn_vals,
  3335. },
  3336. },
  3337. },
  3338. .tx_ln_vals = {
  3339. [TYPE_PCIE] = {
  3340. [TYPE_NONE] = {
  3341. [NO_SSC] = NULL,
  3342. [EXTERNAL_SSC] = NULL,
  3343. [INTERNAL_SSC] = NULL,
  3344. },
  3345. [TYPE_SGMII] = {
  3346. [NO_SSC] = NULL,
  3347. [EXTERNAL_SSC] = NULL,
  3348. [INTERNAL_SSC] = NULL,
  3349. },
  3350. [TYPE_QSGMII] = {
  3351. [NO_SSC] = NULL,
  3352. [EXTERNAL_SSC] = NULL,
  3353. [INTERNAL_SSC] = NULL,
  3354. },
  3355. [TYPE_USB] = {
  3356. [NO_SSC] = NULL,
  3357. [EXTERNAL_SSC] = NULL,
  3358. [INTERNAL_SSC] = NULL,
  3359. },
  3360. },
  3361. [TYPE_SGMII] = {
  3362. [TYPE_NONE] = {
  3363. [NO_SSC] = &sgmii_100_no_ssc_tx_ln_vals,
  3364. },
  3365. [TYPE_PCIE] = {
  3366. [NO_SSC] = &sgmii_100_no_ssc_tx_ln_vals,
  3367. [EXTERNAL_SSC] = &sgmii_100_no_ssc_tx_ln_vals,
  3368. [INTERNAL_SSC] = &sgmii_100_no_ssc_tx_ln_vals,
  3369. },
  3370. [TYPE_USB] = {
  3371. [NO_SSC] = &sgmii_100_no_ssc_tx_ln_vals,
  3372. [EXTERNAL_SSC] = &sgmii_100_no_ssc_tx_ln_vals,
  3373. [INTERNAL_SSC] = &sgmii_100_no_ssc_tx_ln_vals,
  3374. },
  3375. },
  3376. [TYPE_QSGMII] = {
  3377. [TYPE_NONE] = {
  3378. [NO_SSC] = &qsgmii_100_no_ssc_tx_ln_vals,
  3379. },
  3380. [TYPE_PCIE] = {
  3381. [NO_SSC] = &qsgmii_100_no_ssc_tx_ln_vals,
  3382. [EXTERNAL_SSC] = &qsgmii_100_no_ssc_tx_ln_vals,
  3383. [INTERNAL_SSC] = &qsgmii_100_no_ssc_tx_ln_vals,
  3384. },
  3385. [TYPE_USB] = {
  3386. [NO_SSC] = &qsgmii_100_no_ssc_tx_ln_vals,
  3387. [EXTERNAL_SSC] = &qsgmii_100_no_ssc_tx_ln_vals,
  3388. [INTERNAL_SSC] = &qsgmii_100_no_ssc_tx_ln_vals,
  3389. },
  3390. },
  3391. [TYPE_USB] = {
  3392. [TYPE_NONE] = {
  3393. [NO_SSC] = &usb_100_no_ssc_tx_ln_vals,
  3394. [EXTERNAL_SSC] = &usb_100_no_ssc_tx_ln_vals,
  3395. [INTERNAL_SSC] = &usb_100_no_ssc_tx_ln_vals,
  3396. },
  3397. [TYPE_PCIE] = {
  3398. [NO_SSC] = &usb_100_no_ssc_tx_ln_vals,
  3399. [EXTERNAL_SSC] = &usb_100_no_ssc_tx_ln_vals,
  3400. [INTERNAL_SSC] = &usb_100_no_ssc_tx_ln_vals,
  3401. },
  3402. [TYPE_SGMII] = {
  3403. [NO_SSC] = &usb_100_no_ssc_tx_ln_vals,
  3404. [EXTERNAL_SSC] = &usb_100_no_ssc_tx_ln_vals,
  3405. [INTERNAL_SSC] = &usb_100_no_ssc_tx_ln_vals,
  3406. },
  3407. [TYPE_QSGMII] = {
  3408. [NO_SSC] = &usb_100_no_ssc_tx_ln_vals,
  3409. [EXTERNAL_SSC] = &usb_100_no_ssc_tx_ln_vals,
  3410. [INTERNAL_SSC] = &usb_100_no_ssc_tx_ln_vals,
  3411. },
  3412. },
  3413. },
  3414. .rx_ln_vals = {
  3415. [TYPE_PCIE] = {
  3416. [TYPE_NONE] = {
  3417. [NO_SSC] = &pcie_100_no_ssc_rx_ln_vals,
  3418. [EXTERNAL_SSC] = &pcie_100_no_ssc_rx_ln_vals,
  3419. [INTERNAL_SSC] = &pcie_100_no_ssc_rx_ln_vals,
  3420. },
  3421. [TYPE_SGMII] = {
  3422. [NO_SSC] = &pcie_100_no_ssc_rx_ln_vals,
  3423. [EXTERNAL_SSC] = &pcie_100_no_ssc_rx_ln_vals,
  3424. [INTERNAL_SSC] = &pcie_100_no_ssc_rx_ln_vals,
  3425. },
  3426. [TYPE_QSGMII] = {
  3427. [NO_SSC] = &pcie_100_no_ssc_rx_ln_vals,
  3428. [EXTERNAL_SSC] = &pcie_100_no_ssc_rx_ln_vals,
  3429. [INTERNAL_SSC] = &pcie_100_no_ssc_rx_ln_vals,
  3430. },
  3431. [TYPE_USB] = {
  3432. [NO_SSC] = &pcie_100_no_ssc_rx_ln_vals,
  3433. [EXTERNAL_SSC] = &pcie_100_no_ssc_rx_ln_vals,
  3434. [INTERNAL_SSC] = &pcie_100_no_ssc_rx_ln_vals,
  3435. },
  3436. },
  3437. [TYPE_SGMII] = {
  3438. [TYPE_NONE] = {
  3439. [NO_SSC] = &sgmii_100_no_ssc_rx_ln_vals,
  3440. },
  3441. [TYPE_PCIE] = {
  3442. [NO_SSC] = &sgmii_100_no_ssc_rx_ln_vals,
  3443. [EXTERNAL_SSC] = &sgmii_100_no_ssc_rx_ln_vals,
  3444. [INTERNAL_SSC] = &sgmii_100_no_ssc_rx_ln_vals,
  3445. },
  3446. [TYPE_USB] = {
  3447. [NO_SSC] = &sgmii_100_no_ssc_rx_ln_vals,
  3448. [EXTERNAL_SSC] = &sgmii_100_no_ssc_rx_ln_vals,
  3449. [INTERNAL_SSC] = &sgmii_100_no_ssc_rx_ln_vals,
  3450. },
  3451. },
  3452. [TYPE_QSGMII] = {
  3453. [TYPE_NONE] = {
  3454. [NO_SSC] = &qsgmii_100_no_ssc_rx_ln_vals,
  3455. },
  3456. [TYPE_PCIE] = {
  3457. [NO_SSC] = &qsgmii_100_no_ssc_rx_ln_vals,
  3458. [EXTERNAL_SSC] = &qsgmii_100_no_ssc_rx_ln_vals,
  3459. [INTERNAL_SSC] = &qsgmii_100_no_ssc_rx_ln_vals,
  3460. },
  3461. [TYPE_USB] = {
  3462. [NO_SSC] = &qsgmii_100_no_ssc_rx_ln_vals,
  3463. [EXTERNAL_SSC] = &qsgmii_100_no_ssc_rx_ln_vals,
  3464. [INTERNAL_SSC] = &qsgmii_100_no_ssc_rx_ln_vals,
  3465. },
  3466. },
  3467. [TYPE_USB] = {
  3468. [TYPE_NONE] = {
  3469. [NO_SSC] = &usb_100_no_ssc_rx_ln_vals,
  3470. [EXTERNAL_SSC] = &usb_100_no_ssc_rx_ln_vals,
  3471. [INTERNAL_SSC] = &usb_100_no_ssc_rx_ln_vals,
  3472. },
  3473. [TYPE_PCIE] = {
  3474. [NO_SSC] = &usb_100_no_ssc_rx_ln_vals,
  3475. [EXTERNAL_SSC] = &usb_100_no_ssc_rx_ln_vals,
  3476. [INTERNAL_SSC] = &usb_100_no_ssc_rx_ln_vals,
  3477. },
  3478. [TYPE_SGMII] = {
  3479. [NO_SSC] = &usb_100_no_ssc_rx_ln_vals,
  3480. [EXTERNAL_SSC] = &usb_100_no_ssc_rx_ln_vals,
  3481. [INTERNAL_SSC] = &usb_100_no_ssc_rx_ln_vals,
  3482. },
  3483. [TYPE_QSGMII] = {
  3484. [NO_SSC] = &usb_100_no_ssc_rx_ln_vals,
  3485. [EXTERNAL_SSC] = &usb_100_no_ssc_rx_ln_vals,
  3486. [INTERNAL_SSC] = &usb_100_no_ssc_rx_ln_vals,
  3487. },
  3488. },
  3489. },
  3490. };
  3491. static const struct of_device_id cdns_torrent_phy_of_match[] = {
  3492. {
  3493. .compatible = "cdns,torrent-phy",
  3494. .data = &cdns_map_torrent,
  3495. },
  3496. {
  3497. .compatible = "ti,j721e-serdes-10g",
  3498. .data = &ti_j721e_map_torrent,
  3499. },
  3500. {}
  3501. };
  3502. MODULE_DEVICE_TABLE(of, cdns_torrent_phy_of_match);
  3503. static struct platform_driver cdns_torrent_phy_driver = {
  3504. .probe = cdns_torrent_phy_probe,
  3505. .remove = cdns_torrent_phy_remove,
  3506. .driver = {
  3507. .name = "cdns-torrent-phy",
  3508. .of_match_table = cdns_torrent_phy_of_match,
  3509. }
  3510. };
  3511. module_platform_driver(cdns_torrent_phy_driver);
  3512. MODULE_AUTHOR("Cadence Design Systems, Inc.");
  3513. MODULE_DESCRIPTION("Cadence Torrent PHY driver");
  3514. MODULE_LICENSE("GPL v2");