phy-cadence-sierra.c 24 KB

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  1. // SPDX-License-Identifier: GPL-2.0
  2. /*
  3. * Cadence Sierra PHY Driver
  4. *
  5. * Copyright (c) 2018 Cadence Design Systems
  6. * Author: Alan Douglas <adouglas@cadence.com>
  7. *
  8. */
  9. #include <linux/clk.h>
  10. #include <linux/delay.h>
  11. #include <linux/err.h>
  12. #include <linux/io.h>
  13. #include <linux/module.h>
  14. #include <linux/phy/phy.h>
  15. #include <linux/platform_device.h>
  16. #include <linux/pm_runtime.h>
  17. #include <linux/regmap.h>
  18. #include <linux/reset.h>
  19. #include <linux/slab.h>
  20. #include <linux/of.h>
  21. #include <linux/of_platform.h>
  22. #include <dt-bindings/phy/phy.h>
  23. /* PHY register offsets */
  24. #define SIERRA_COMMON_CDB_OFFSET 0x0
  25. #define SIERRA_MACRO_ID_REG 0x0
  26. #define SIERRA_CMN_PLLLC_MODE_PREG 0x48
  27. #define SIERRA_CMN_PLLLC_LF_COEFF_MODE1_PREG 0x49
  28. #define SIERRA_CMN_PLLLC_LF_COEFF_MODE0_PREG 0x4A
  29. #define SIERRA_CMN_PLLLC_LOCK_CNTSTART_PREG 0x4B
  30. #define SIERRA_CMN_PLLLC_BWCAL_MODE1_PREG 0x4F
  31. #define SIERRA_CMN_PLLLC_BWCAL_MODE0_PREG 0x50
  32. #define SIERRA_CMN_PLLLC_SS_TIME_STEPSIZE_MODE_PREG 0x62
  33. #define SIERRA_LANE_CDB_OFFSET(ln, block_offset, reg_offset) \
  34. ((0x4000 << (block_offset)) + \
  35. (((ln) << 9) << (reg_offset)))
  36. #define SIERRA_DET_STANDEC_A_PREG 0x000
  37. #define SIERRA_DET_STANDEC_B_PREG 0x001
  38. #define SIERRA_DET_STANDEC_C_PREG 0x002
  39. #define SIERRA_DET_STANDEC_D_PREG 0x003
  40. #define SIERRA_DET_STANDEC_E_PREG 0x004
  41. #define SIERRA_PSM_LANECAL_DLY_A1_RESETS_PREG 0x008
  42. #define SIERRA_PSM_A0IN_TMR_PREG 0x009
  43. #define SIERRA_PSM_DIAG_PREG 0x015
  44. #define SIERRA_PSC_TX_A0_PREG 0x028
  45. #define SIERRA_PSC_TX_A1_PREG 0x029
  46. #define SIERRA_PSC_TX_A2_PREG 0x02A
  47. #define SIERRA_PSC_TX_A3_PREG 0x02B
  48. #define SIERRA_PSC_RX_A0_PREG 0x030
  49. #define SIERRA_PSC_RX_A1_PREG 0x031
  50. #define SIERRA_PSC_RX_A2_PREG 0x032
  51. #define SIERRA_PSC_RX_A3_PREG 0x033
  52. #define SIERRA_PLLCTRL_SUBRATE_PREG 0x03A
  53. #define SIERRA_PLLCTRL_GEN_D_PREG 0x03E
  54. #define SIERRA_PLLCTRL_CPGAIN_MODE_PREG 0x03F
  55. #define SIERRA_PLLCTRL_STATUS_PREG 0x044
  56. #define SIERRA_CLKPATH_BIASTRIM_PREG 0x04B
  57. #define SIERRA_DFE_BIASTRIM_PREG 0x04C
  58. #define SIERRA_DRVCTRL_ATTEN_PREG 0x06A
  59. #define SIERRA_CLKPATHCTRL_TMR_PREG 0x081
  60. #define SIERRA_RX_CREQ_FLTR_A_MODE3_PREG 0x085
  61. #define SIERRA_RX_CREQ_FLTR_A_MODE2_PREG 0x086
  62. #define SIERRA_RX_CREQ_FLTR_A_MODE1_PREG 0x087
  63. #define SIERRA_RX_CREQ_FLTR_A_MODE0_PREG 0x088
  64. #define SIERRA_CREQ_CCLKDET_MODE01_PREG 0x08E
  65. #define SIERRA_RX_CTLE_MAINTENANCE_PREG 0x091
  66. #define SIERRA_CREQ_FSMCLK_SEL_PREG 0x092
  67. #define SIERRA_CREQ_EQ_CTRL_PREG 0x093
  68. #define SIERRA_CREQ_SPARE_PREG 0x096
  69. #define SIERRA_CREQ_EQ_OPEN_EYE_THRESH_PREG 0x097
  70. #define SIERRA_CTLELUT_CTRL_PREG 0x098
  71. #define SIERRA_DFE_ECMP_RATESEL_PREG 0x0C0
  72. #define SIERRA_DFE_SMP_RATESEL_PREG 0x0C1
  73. #define SIERRA_DEQ_PHALIGN_CTRL 0x0C4
  74. #define SIERRA_DEQ_CONCUR_CTRL1_PREG 0x0C8
  75. #define SIERRA_DEQ_CONCUR_CTRL2_PREG 0x0C9
  76. #define SIERRA_DEQ_EPIPWR_CTRL2_PREG 0x0CD
  77. #define SIERRA_DEQ_FAST_MAINT_CYCLES_PREG 0x0CE
  78. #define SIERRA_DEQ_ERRCMP_CTRL_PREG 0x0D0
  79. #define SIERRA_DEQ_OFFSET_CTRL_PREG 0x0D8
  80. #define SIERRA_DEQ_GAIN_CTRL_PREG 0x0E0
  81. #define SIERRA_DEQ_VGATUNE_CTRL_PREG 0x0E1
  82. #define SIERRA_DEQ_GLUT0 0x0E8
  83. #define SIERRA_DEQ_GLUT1 0x0E9
  84. #define SIERRA_DEQ_GLUT2 0x0EA
  85. #define SIERRA_DEQ_GLUT3 0x0EB
  86. #define SIERRA_DEQ_GLUT4 0x0EC
  87. #define SIERRA_DEQ_GLUT5 0x0ED
  88. #define SIERRA_DEQ_GLUT6 0x0EE
  89. #define SIERRA_DEQ_GLUT7 0x0EF
  90. #define SIERRA_DEQ_GLUT8 0x0F0
  91. #define SIERRA_DEQ_GLUT9 0x0F1
  92. #define SIERRA_DEQ_GLUT10 0x0F2
  93. #define SIERRA_DEQ_GLUT11 0x0F3
  94. #define SIERRA_DEQ_GLUT12 0x0F4
  95. #define SIERRA_DEQ_GLUT13 0x0F5
  96. #define SIERRA_DEQ_GLUT14 0x0F6
  97. #define SIERRA_DEQ_GLUT15 0x0F7
  98. #define SIERRA_DEQ_GLUT16 0x0F8
  99. #define SIERRA_DEQ_ALUT0 0x108
  100. #define SIERRA_DEQ_ALUT1 0x109
  101. #define SIERRA_DEQ_ALUT2 0x10A
  102. #define SIERRA_DEQ_ALUT3 0x10B
  103. #define SIERRA_DEQ_ALUT4 0x10C
  104. #define SIERRA_DEQ_ALUT5 0x10D
  105. #define SIERRA_DEQ_ALUT6 0x10E
  106. #define SIERRA_DEQ_ALUT7 0x10F
  107. #define SIERRA_DEQ_ALUT8 0x110
  108. #define SIERRA_DEQ_ALUT9 0x111
  109. #define SIERRA_DEQ_ALUT10 0x112
  110. #define SIERRA_DEQ_ALUT11 0x113
  111. #define SIERRA_DEQ_ALUT12 0x114
  112. #define SIERRA_DEQ_ALUT13 0x115
  113. #define SIERRA_DEQ_DFETAP_CTRL_PREG 0x128
  114. #define SIERRA_DFE_EN_1010_IGNORE_PREG 0x134
  115. #define SIERRA_DEQ_TAU_CTRL1_SLOW_MAINT_PREG 0x150
  116. #define SIERRA_DEQ_TAU_CTRL2_PREG 0x151
  117. #define SIERRA_DEQ_PICTRL_PREG 0x161
  118. #define SIERRA_CPICAL_TMRVAL_MODE1_PREG 0x170
  119. #define SIERRA_CPICAL_TMRVAL_MODE0_PREG 0x171
  120. #define SIERRA_CPICAL_PICNT_MODE1_PREG 0x174
  121. #define SIERRA_CPI_OUTBUF_RATESEL_PREG 0x17C
  122. #define SIERRA_CPICAL_RES_STARTCODE_MODE23_PREG 0x183
  123. #define SIERRA_LFPSDET_SUPPORT_PREG 0x188
  124. #define SIERRA_LFPSFILT_NS_PREG 0x18A
  125. #define SIERRA_LFPSFILT_RD_PREG 0x18B
  126. #define SIERRA_LFPSFILT_MP_PREG 0x18C
  127. #define SIERRA_SIGDET_SUPPORT_PREG 0x190
  128. #define SIERRA_SDFILT_H2L_A_PREG 0x191
  129. #define SIERRA_SDFILT_L2H_PREG 0x193
  130. #define SIERRA_RXBUFFER_CTLECTRL_PREG 0x19E
  131. #define SIERRA_RXBUFFER_RCDFECTRL_PREG 0x19F
  132. #define SIERRA_RXBUFFER_DFECTRL_PREG 0x1A0
  133. #define SIERRA_DEQ_TAU_CTRL1_FAST_MAINT_PREG 0x14F
  134. #define SIERRA_DEQ_TAU_CTRL1_SLOW_MAINT_PREG 0x150
  135. #define SIERRA_PHY_CONFIG_CTRL_OFFSET(block_offset) \
  136. (0xc000 << (block_offset))
  137. #define SIERRA_PHY_PLL_CFG 0xe
  138. #define SIERRA_MACRO_ID 0x00007364
  139. #define SIERRA_MAX_LANES 16
  140. #define PLL_LOCK_TIME 100000
  141. static const struct reg_field macro_id_type =
  142. REG_FIELD(SIERRA_MACRO_ID_REG, 0, 15);
  143. static const struct reg_field phy_pll_cfg_1 =
  144. REG_FIELD(SIERRA_PHY_PLL_CFG, 1, 1);
  145. static const struct reg_field pllctrl_lock =
  146. REG_FIELD(SIERRA_PLLCTRL_STATUS_PREG, 0, 0);
  147. struct cdns_sierra_inst {
  148. struct phy *phy;
  149. u32 phy_type;
  150. u32 num_lanes;
  151. u32 mlane;
  152. struct reset_control *lnk_rst;
  153. };
  154. struct cdns_reg_pairs {
  155. u16 val;
  156. u32 off;
  157. };
  158. struct cdns_sierra_data {
  159. u32 id_value;
  160. u8 block_offset_shift;
  161. u8 reg_offset_shift;
  162. u32 pcie_cmn_regs;
  163. u32 pcie_ln_regs;
  164. u32 usb_cmn_regs;
  165. u32 usb_ln_regs;
  166. const struct cdns_reg_pairs *pcie_cmn_vals;
  167. const struct cdns_reg_pairs *pcie_ln_vals;
  168. const struct cdns_reg_pairs *usb_cmn_vals;
  169. const struct cdns_reg_pairs *usb_ln_vals;
  170. };
  171. struct cdns_regmap_cdb_context {
  172. struct device *dev;
  173. void __iomem *base;
  174. u8 reg_offset_shift;
  175. };
  176. struct cdns_sierra_phy {
  177. struct device *dev;
  178. struct regmap *regmap;
  179. struct cdns_sierra_data *init_data;
  180. struct cdns_sierra_inst phys[SIERRA_MAX_LANES];
  181. struct reset_control *phy_rst;
  182. struct reset_control *apb_rst;
  183. struct regmap *regmap_lane_cdb[SIERRA_MAX_LANES];
  184. struct regmap *regmap_phy_config_ctrl;
  185. struct regmap *regmap_common_cdb;
  186. struct regmap_field *macro_id_type;
  187. struct regmap_field *phy_pll_cfg_1;
  188. struct regmap_field *pllctrl_lock[SIERRA_MAX_LANES];
  189. struct clk *clk;
  190. struct clk *cmn_refclk_dig_div;
  191. struct clk *cmn_refclk1_dig_div;
  192. int nsubnodes;
  193. u32 num_lanes;
  194. bool autoconf;
  195. };
  196. static int cdns_regmap_write(void *context, unsigned int reg, unsigned int val)
  197. {
  198. struct cdns_regmap_cdb_context *ctx = context;
  199. u32 offset = reg << ctx->reg_offset_shift;
  200. writew(val, ctx->base + offset);
  201. return 0;
  202. }
  203. static int cdns_regmap_read(void *context, unsigned int reg, unsigned int *val)
  204. {
  205. struct cdns_regmap_cdb_context *ctx = context;
  206. u32 offset = reg << ctx->reg_offset_shift;
  207. *val = readw(ctx->base + offset);
  208. return 0;
  209. }
  210. #define SIERRA_LANE_CDB_REGMAP_CONF(n) \
  211. { \
  212. .name = "sierra_lane" n "_cdb", \
  213. .reg_stride = 1, \
  214. .fast_io = true, \
  215. .reg_write = cdns_regmap_write, \
  216. .reg_read = cdns_regmap_read, \
  217. }
  218. static const struct regmap_config cdns_sierra_lane_cdb_config[] = {
  219. SIERRA_LANE_CDB_REGMAP_CONF("0"),
  220. SIERRA_LANE_CDB_REGMAP_CONF("1"),
  221. SIERRA_LANE_CDB_REGMAP_CONF("2"),
  222. SIERRA_LANE_CDB_REGMAP_CONF("3"),
  223. SIERRA_LANE_CDB_REGMAP_CONF("4"),
  224. SIERRA_LANE_CDB_REGMAP_CONF("5"),
  225. SIERRA_LANE_CDB_REGMAP_CONF("6"),
  226. SIERRA_LANE_CDB_REGMAP_CONF("7"),
  227. SIERRA_LANE_CDB_REGMAP_CONF("8"),
  228. SIERRA_LANE_CDB_REGMAP_CONF("9"),
  229. SIERRA_LANE_CDB_REGMAP_CONF("10"),
  230. SIERRA_LANE_CDB_REGMAP_CONF("11"),
  231. SIERRA_LANE_CDB_REGMAP_CONF("12"),
  232. SIERRA_LANE_CDB_REGMAP_CONF("13"),
  233. SIERRA_LANE_CDB_REGMAP_CONF("14"),
  234. SIERRA_LANE_CDB_REGMAP_CONF("15"),
  235. };
  236. static const struct regmap_config cdns_sierra_common_cdb_config = {
  237. .name = "sierra_common_cdb",
  238. .reg_stride = 1,
  239. .fast_io = true,
  240. .reg_write = cdns_regmap_write,
  241. .reg_read = cdns_regmap_read,
  242. };
  243. static const struct regmap_config cdns_sierra_phy_config_ctrl_config = {
  244. .name = "sierra_phy_config_ctrl",
  245. .reg_stride = 1,
  246. .fast_io = true,
  247. .reg_write = cdns_regmap_write,
  248. .reg_read = cdns_regmap_read,
  249. };
  250. static int cdns_sierra_phy_init(struct phy *gphy)
  251. {
  252. struct cdns_sierra_inst *ins = phy_get_drvdata(gphy);
  253. struct cdns_sierra_phy *phy = dev_get_drvdata(gphy->dev.parent);
  254. struct regmap *regmap;
  255. int i, j;
  256. const struct cdns_reg_pairs *cmn_vals, *ln_vals;
  257. u32 num_cmn_regs, num_ln_regs;
  258. /* Initialise the PHY registers, unless auto configured */
  259. if (phy->autoconf)
  260. return 0;
  261. clk_set_rate(phy->cmn_refclk_dig_div, 25000000);
  262. clk_set_rate(phy->cmn_refclk1_dig_div, 25000000);
  263. if (ins->phy_type == PHY_TYPE_PCIE) {
  264. num_cmn_regs = phy->init_data->pcie_cmn_regs;
  265. num_ln_regs = phy->init_data->pcie_ln_regs;
  266. cmn_vals = phy->init_data->pcie_cmn_vals;
  267. ln_vals = phy->init_data->pcie_ln_vals;
  268. } else if (ins->phy_type == PHY_TYPE_USB3) {
  269. num_cmn_regs = phy->init_data->usb_cmn_regs;
  270. num_ln_regs = phy->init_data->usb_ln_regs;
  271. cmn_vals = phy->init_data->usb_cmn_vals;
  272. ln_vals = phy->init_data->usb_ln_vals;
  273. } else {
  274. return -EINVAL;
  275. }
  276. regmap = phy->regmap_common_cdb;
  277. for (j = 0; j < num_cmn_regs ; j++)
  278. regmap_write(regmap, cmn_vals[j].off, cmn_vals[j].val);
  279. for (i = 0; i < ins->num_lanes; i++) {
  280. for (j = 0; j < num_ln_regs ; j++) {
  281. regmap = phy->regmap_lane_cdb[i + ins->mlane];
  282. regmap_write(regmap, ln_vals[j].off, ln_vals[j].val);
  283. }
  284. }
  285. return 0;
  286. }
  287. static int cdns_sierra_phy_on(struct phy *gphy)
  288. {
  289. struct cdns_sierra_phy *sp = dev_get_drvdata(gphy->dev.parent);
  290. struct cdns_sierra_inst *ins = phy_get_drvdata(gphy);
  291. struct device *dev = sp->dev;
  292. u32 val;
  293. int ret;
  294. ret = reset_control_deassert(sp->phy_rst);
  295. if (ret) {
  296. dev_err(dev, "Failed to take the PHY out of reset\n");
  297. return ret;
  298. }
  299. /* Take the PHY lane group out of reset */
  300. ret = reset_control_deassert(ins->lnk_rst);
  301. if (ret) {
  302. dev_err(dev, "Failed to take the PHY lane out of reset\n");
  303. return ret;
  304. }
  305. ret = regmap_field_read_poll_timeout(sp->pllctrl_lock[ins->mlane],
  306. val, val, 1000, PLL_LOCK_TIME);
  307. if (ret < 0)
  308. dev_err(dev, "PLL lock of lane failed\n");
  309. return ret;
  310. }
  311. static int cdns_sierra_phy_off(struct phy *gphy)
  312. {
  313. struct cdns_sierra_inst *ins = phy_get_drvdata(gphy);
  314. return reset_control_assert(ins->lnk_rst);
  315. }
  316. static int cdns_sierra_phy_reset(struct phy *gphy)
  317. {
  318. struct cdns_sierra_phy *sp = dev_get_drvdata(gphy->dev.parent);
  319. reset_control_assert(sp->phy_rst);
  320. reset_control_deassert(sp->phy_rst);
  321. return 0;
  322. };
  323. static const struct phy_ops ops = {
  324. .init = cdns_sierra_phy_init,
  325. .power_on = cdns_sierra_phy_on,
  326. .power_off = cdns_sierra_phy_off,
  327. .reset = cdns_sierra_phy_reset,
  328. .owner = THIS_MODULE,
  329. };
  330. static int cdns_sierra_get_optional(struct cdns_sierra_inst *inst,
  331. struct device_node *child)
  332. {
  333. if (of_property_read_u32(child, "reg", &inst->mlane))
  334. return -EINVAL;
  335. if (of_property_read_u32(child, "cdns,num-lanes", &inst->num_lanes))
  336. return -EINVAL;
  337. if (of_property_read_u32(child, "cdns,phy-type", &inst->phy_type))
  338. return -EINVAL;
  339. return 0;
  340. }
  341. static const struct of_device_id cdns_sierra_id_table[];
  342. static struct regmap *cdns_regmap_init(struct device *dev, void __iomem *base,
  343. u32 block_offset, u8 reg_offset_shift,
  344. const struct regmap_config *config)
  345. {
  346. struct cdns_regmap_cdb_context *ctx;
  347. ctx = devm_kzalloc(dev, sizeof(*ctx), GFP_KERNEL);
  348. if (!ctx)
  349. return ERR_PTR(-ENOMEM);
  350. ctx->dev = dev;
  351. ctx->base = base + block_offset;
  352. ctx->reg_offset_shift = reg_offset_shift;
  353. return devm_regmap_init(dev, NULL, ctx, config);
  354. }
  355. static int cdns_regfield_init(struct cdns_sierra_phy *sp)
  356. {
  357. struct device *dev = sp->dev;
  358. struct regmap_field *field;
  359. struct regmap *regmap;
  360. int i;
  361. regmap = sp->regmap_common_cdb;
  362. field = devm_regmap_field_alloc(dev, regmap, macro_id_type);
  363. if (IS_ERR(field)) {
  364. dev_err(dev, "MACRO_ID_TYPE reg field init failed\n");
  365. return PTR_ERR(field);
  366. }
  367. sp->macro_id_type = field;
  368. regmap = sp->regmap_phy_config_ctrl;
  369. field = devm_regmap_field_alloc(dev, regmap, phy_pll_cfg_1);
  370. if (IS_ERR(field)) {
  371. dev_err(dev, "PHY_PLL_CFG_1 reg field init failed\n");
  372. return PTR_ERR(field);
  373. }
  374. sp->phy_pll_cfg_1 = field;
  375. for (i = 0; i < SIERRA_MAX_LANES; i++) {
  376. regmap = sp->regmap_lane_cdb[i];
  377. field = devm_regmap_field_alloc(dev, regmap, pllctrl_lock);
  378. if (IS_ERR(field)) {
  379. dev_err(dev, "P%d_ENABLE reg field init failed\n", i);
  380. return PTR_ERR(field);
  381. }
  382. sp->pllctrl_lock[i] = field;
  383. }
  384. return 0;
  385. }
  386. static int cdns_regmap_init_blocks(struct cdns_sierra_phy *sp,
  387. void __iomem *base, u8 block_offset_shift,
  388. u8 reg_offset_shift)
  389. {
  390. struct device *dev = sp->dev;
  391. struct regmap *regmap;
  392. u32 block_offset;
  393. int i;
  394. for (i = 0; i < SIERRA_MAX_LANES; i++) {
  395. block_offset = SIERRA_LANE_CDB_OFFSET(i, block_offset_shift,
  396. reg_offset_shift);
  397. regmap = cdns_regmap_init(dev, base, block_offset,
  398. reg_offset_shift,
  399. &cdns_sierra_lane_cdb_config[i]);
  400. if (IS_ERR(regmap)) {
  401. dev_err(dev, "Failed to init lane CDB regmap\n");
  402. return PTR_ERR(regmap);
  403. }
  404. sp->regmap_lane_cdb[i] = regmap;
  405. }
  406. regmap = cdns_regmap_init(dev, base, SIERRA_COMMON_CDB_OFFSET,
  407. reg_offset_shift,
  408. &cdns_sierra_common_cdb_config);
  409. if (IS_ERR(regmap)) {
  410. dev_err(dev, "Failed to init common CDB regmap\n");
  411. return PTR_ERR(regmap);
  412. }
  413. sp->regmap_common_cdb = regmap;
  414. block_offset = SIERRA_PHY_CONFIG_CTRL_OFFSET(block_offset_shift);
  415. regmap = cdns_regmap_init(dev, base, block_offset, reg_offset_shift,
  416. &cdns_sierra_phy_config_ctrl_config);
  417. if (IS_ERR(regmap)) {
  418. dev_err(dev, "Failed to init PHY config and control regmap\n");
  419. return PTR_ERR(regmap);
  420. }
  421. sp->regmap_phy_config_ctrl = regmap;
  422. return 0;
  423. }
  424. static int cdns_sierra_phy_probe(struct platform_device *pdev)
  425. {
  426. struct cdns_sierra_phy *sp;
  427. struct phy_provider *phy_provider;
  428. struct device *dev = &pdev->dev;
  429. const struct of_device_id *match;
  430. struct cdns_sierra_data *data;
  431. unsigned int id_value;
  432. struct resource *res;
  433. int i, ret, node = 0;
  434. void __iomem *base;
  435. struct clk *clk;
  436. struct device_node *dn = dev->of_node, *child;
  437. if (of_get_child_count(dn) == 0)
  438. return -ENODEV;
  439. /* Get init data for this PHY */
  440. match = of_match_device(cdns_sierra_id_table, dev);
  441. if (!match)
  442. return -EINVAL;
  443. data = (struct cdns_sierra_data *)match->data;
  444. sp = devm_kzalloc(dev, sizeof(*sp), GFP_KERNEL);
  445. if (!sp)
  446. return -ENOMEM;
  447. dev_set_drvdata(dev, sp);
  448. sp->dev = dev;
  449. sp->init_data = data;
  450. res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
  451. base = devm_ioremap_resource(dev, res);
  452. if (IS_ERR(base)) {
  453. dev_err(dev, "missing \"reg\"\n");
  454. return PTR_ERR(base);
  455. }
  456. ret = cdns_regmap_init_blocks(sp, base, data->block_offset_shift,
  457. data->reg_offset_shift);
  458. if (ret)
  459. return ret;
  460. ret = cdns_regfield_init(sp);
  461. if (ret)
  462. return ret;
  463. platform_set_drvdata(pdev, sp);
  464. sp->clk = devm_clk_get_optional(dev, "phy_clk");
  465. if (IS_ERR(sp->clk)) {
  466. dev_err(dev, "failed to get clock phy_clk\n");
  467. return PTR_ERR(sp->clk);
  468. }
  469. sp->phy_rst = devm_reset_control_get(dev, "sierra_reset");
  470. if (IS_ERR(sp->phy_rst)) {
  471. dev_err(dev, "failed to get reset\n");
  472. return PTR_ERR(sp->phy_rst);
  473. }
  474. sp->apb_rst = devm_reset_control_get_optional(dev, "sierra_apb");
  475. if (IS_ERR(sp->apb_rst)) {
  476. dev_err(dev, "failed to get apb reset\n");
  477. return PTR_ERR(sp->apb_rst);
  478. }
  479. clk = devm_clk_get_optional(dev, "cmn_refclk_dig_div");
  480. if (IS_ERR(clk)) {
  481. dev_err(dev, "cmn_refclk_dig_div clock not found\n");
  482. ret = PTR_ERR(clk);
  483. return ret;
  484. }
  485. sp->cmn_refclk_dig_div = clk;
  486. clk = devm_clk_get_optional(dev, "cmn_refclk1_dig_div");
  487. if (IS_ERR(clk)) {
  488. dev_err(dev, "cmn_refclk1_dig_div clock not found\n");
  489. ret = PTR_ERR(clk);
  490. return ret;
  491. }
  492. sp->cmn_refclk1_dig_div = clk;
  493. ret = clk_prepare_enable(sp->clk);
  494. if (ret)
  495. return ret;
  496. /* Enable APB */
  497. reset_control_deassert(sp->apb_rst);
  498. /* Check that PHY is present */
  499. regmap_field_read(sp->macro_id_type, &id_value);
  500. if (sp->init_data->id_value != id_value) {
  501. ret = -EINVAL;
  502. goto clk_disable;
  503. }
  504. sp->autoconf = of_property_read_bool(dn, "cdns,autoconf");
  505. for_each_available_child_of_node(dn, child) {
  506. struct phy *gphy;
  507. sp->phys[node].lnk_rst =
  508. of_reset_control_array_get_exclusive(child);
  509. if (IS_ERR(sp->phys[node].lnk_rst)) {
  510. dev_err(dev, "failed to get reset %s\n",
  511. child->full_name);
  512. ret = PTR_ERR(sp->phys[node].lnk_rst);
  513. goto put_child2;
  514. }
  515. if (!sp->autoconf) {
  516. ret = cdns_sierra_get_optional(&sp->phys[node], child);
  517. if (ret) {
  518. dev_err(dev, "missing property in node %s\n",
  519. child->name);
  520. goto put_child;
  521. }
  522. }
  523. sp->num_lanes += sp->phys[node].num_lanes;
  524. gphy = devm_phy_create(dev, child, &ops);
  525. if (IS_ERR(gphy)) {
  526. ret = PTR_ERR(gphy);
  527. goto put_child;
  528. }
  529. sp->phys[node].phy = gphy;
  530. phy_set_drvdata(gphy, &sp->phys[node]);
  531. node++;
  532. }
  533. sp->nsubnodes = node;
  534. if (sp->num_lanes > SIERRA_MAX_LANES) {
  535. ret = -EINVAL;
  536. dev_err(dev, "Invalid lane configuration\n");
  537. goto put_child2;
  538. }
  539. /* If more than one subnode, configure the PHY as multilink */
  540. if (!sp->autoconf && sp->nsubnodes > 1)
  541. regmap_field_write(sp->phy_pll_cfg_1, 0x1);
  542. pm_runtime_enable(dev);
  543. phy_provider = devm_of_phy_provider_register(dev, of_phy_simple_xlate);
  544. return PTR_ERR_OR_ZERO(phy_provider);
  545. put_child:
  546. node++;
  547. put_child2:
  548. for (i = 0; i < node; i++)
  549. reset_control_put(sp->phys[i].lnk_rst);
  550. of_node_put(child);
  551. clk_disable:
  552. clk_disable_unprepare(sp->clk);
  553. reset_control_assert(sp->apb_rst);
  554. return ret;
  555. }
  556. static int cdns_sierra_phy_remove(struct platform_device *pdev)
  557. {
  558. struct cdns_sierra_phy *phy = platform_get_drvdata(pdev);
  559. int i;
  560. reset_control_assert(phy->phy_rst);
  561. reset_control_assert(phy->apb_rst);
  562. pm_runtime_disable(&pdev->dev);
  563. /*
  564. * The device level resets will be put automatically.
  565. * Need to put the subnode resets here though.
  566. */
  567. for (i = 0; i < phy->nsubnodes; i++) {
  568. reset_control_assert(phy->phys[i].lnk_rst);
  569. reset_control_put(phy->phys[i].lnk_rst);
  570. }
  571. return 0;
  572. }
  573. /* refclk100MHz_32b_PCIe_cmn_pll_ext_ssc */
  574. static const struct cdns_reg_pairs cdns_pcie_cmn_regs_ext_ssc[] = {
  575. {0x2106, SIERRA_CMN_PLLLC_LF_COEFF_MODE1_PREG},
  576. {0x2106, SIERRA_CMN_PLLLC_LF_COEFF_MODE0_PREG},
  577. {0x8A06, SIERRA_CMN_PLLLC_BWCAL_MODE1_PREG},
  578. {0x8A06, SIERRA_CMN_PLLLC_BWCAL_MODE0_PREG},
  579. {0x1B1B, SIERRA_CMN_PLLLC_SS_TIME_STEPSIZE_MODE_PREG}
  580. };
  581. /* refclk100MHz_32b_PCIe_ln_ext_ssc */
  582. static const struct cdns_reg_pairs cdns_pcie_ln_regs_ext_ssc[] = {
  583. {0x813E, SIERRA_CLKPATHCTRL_TMR_PREG},
  584. {0x8047, SIERRA_RX_CREQ_FLTR_A_MODE3_PREG},
  585. {0x808F, SIERRA_RX_CREQ_FLTR_A_MODE2_PREG},
  586. {0x808F, SIERRA_RX_CREQ_FLTR_A_MODE1_PREG},
  587. {0x808F, SIERRA_RX_CREQ_FLTR_A_MODE0_PREG},
  588. {0x033C, SIERRA_RX_CTLE_MAINTENANCE_PREG},
  589. {0x44CC, SIERRA_CREQ_EQ_OPEN_EYE_THRESH_PREG}
  590. };
  591. /* refclk100MHz_20b_USB_cmn_pll_ext_ssc */
  592. static const struct cdns_reg_pairs cdns_usb_cmn_regs_ext_ssc[] = {
  593. {0x2085, SIERRA_CMN_PLLLC_LF_COEFF_MODE1_PREG},
  594. {0x2085, SIERRA_CMN_PLLLC_LF_COEFF_MODE0_PREG},
  595. {0x0000, SIERRA_CMN_PLLLC_BWCAL_MODE0_PREG},
  596. {0x0000, SIERRA_CMN_PLLLC_SS_TIME_STEPSIZE_MODE_PREG}
  597. };
  598. /* refclk100MHz_20b_USB_ln_ext_ssc */
  599. static const struct cdns_reg_pairs cdns_usb_ln_regs_ext_ssc[] = {
  600. {0xFE0A, SIERRA_DET_STANDEC_A_PREG},
  601. {0x000F, SIERRA_DET_STANDEC_B_PREG},
  602. {0x55A5, SIERRA_DET_STANDEC_C_PREG},
  603. {0x69ad, SIERRA_DET_STANDEC_D_PREG},
  604. {0x0241, SIERRA_DET_STANDEC_E_PREG},
  605. {0x0110, SIERRA_PSM_LANECAL_DLY_A1_RESETS_PREG},
  606. {0x0014, SIERRA_PSM_A0IN_TMR_PREG},
  607. {0xCF00, SIERRA_PSM_DIAG_PREG},
  608. {0x001F, SIERRA_PSC_TX_A0_PREG},
  609. {0x0007, SIERRA_PSC_TX_A1_PREG},
  610. {0x0003, SIERRA_PSC_TX_A2_PREG},
  611. {0x0003, SIERRA_PSC_TX_A3_PREG},
  612. {0x0FFF, SIERRA_PSC_RX_A0_PREG},
  613. {0x0003, SIERRA_PSC_RX_A1_PREG},
  614. {0x0003, SIERRA_PSC_RX_A2_PREG},
  615. {0x0001, SIERRA_PSC_RX_A3_PREG},
  616. {0x0001, SIERRA_PLLCTRL_SUBRATE_PREG},
  617. {0x0406, SIERRA_PLLCTRL_GEN_D_PREG},
  618. {0x5233, SIERRA_PLLCTRL_CPGAIN_MODE_PREG},
  619. {0x00CA, SIERRA_CLKPATH_BIASTRIM_PREG},
  620. {0x2512, SIERRA_DFE_BIASTRIM_PREG},
  621. {0x0000, SIERRA_DRVCTRL_ATTEN_PREG},
  622. {0x823E, SIERRA_CLKPATHCTRL_TMR_PREG},
  623. {0x078F, SIERRA_RX_CREQ_FLTR_A_MODE1_PREG},
  624. {0x078F, SIERRA_RX_CREQ_FLTR_A_MODE0_PREG},
  625. {0x7B3C, SIERRA_CREQ_CCLKDET_MODE01_PREG},
  626. {0x023C, SIERRA_RX_CTLE_MAINTENANCE_PREG},
  627. {0x3232, SIERRA_CREQ_FSMCLK_SEL_PREG},
  628. {0x0000, SIERRA_CREQ_EQ_CTRL_PREG},
  629. {0x0000, SIERRA_CREQ_SPARE_PREG},
  630. {0xCC44, SIERRA_CREQ_EQ_OPEN_EYE_THRESH_PREG},
  631. {0x8452, SIERRA_CTLELUT_CTRL_PREG},
  632. {0x4121, SIERRA_DFE_ECMP_RATESEL_PREG},
  633. {0x4121, SIERRA_DFE_SMP_RATESEL_PREG},
  634. {0x0003, SIERRA_DEQ_PHALIGN_CTRL},
  635. {0x3200, SIERRA_DEQ_CONCUR_CTRL1_PREG},
  636. {0x5064, SIERRA_DEQ_CONCUR_CTRL2_PREG},
  637. {0x0030, SIERRA_DEQ_EPIPWR_CTRL2_PREG},
  638. {0x0048, SIERRA_DEQ_FAST_MAINT_CYCLES_PREG},
  639. {0x5A5A, SIERRA_DEQ_ERRCMP_CTRL_PREG},
  640. {0x02F5, SIERRA_DEQ_OFFSET_CTRL_PREG},
  641. {0x02F5, SIERRA_DEQ_GAIN_CTRL_PREG},
  642. {0x9999, SIERRA_DEQ_VGATUNE_CTRL_PREG},
  643. {0x0014, SIERRA_DEQ_GLUT0},
  644. {0x0014, SIERRA_DEQ_GLUT1},
  645. {0x0014, SIERRA_DEQ_GLUT2},
  646. {0x0014, SIERRA_DEQ_GLUT3},
  647. {0x0014, SIERRA_DEQ_GLUT4},
  648. {0x0014, SIERRA_DEQ_GLUT5},
  649. {0x0014, SIERRA_DEQ_GLUT6},
  650. {0x0014, SIERRA_DEQ_GLUT7},
  651. {0x0014, SIERRA_DEQ_GLUT8},
  652. {0x0014, SIERRA_DEQ_GLUT9},
  653. {0x0014, SIERRA_DEQ_GLUT10},
  654. {0x0014, SIERRA_DEQ_GLUT11},
  655. {0x0014, SIERRA_DEQ_GLUT12},
  656. {0x0014, SIERRA_DEQ_GLUT13},
  657. {0x0014, SIERRA_DEQ_GLUT14},
  658. {0x0014, SIERRA_DEQ_GLUT15},
  659. {0x0014, SIERRA_DEQ_GLUT16},
  660. {0x0BAE, SIERRA_DEQ_ALUT0},
  661. {0x0AEB, SIERRA_DEQ_ALUT1},
  662. {0x0A28, SIERRA_DEQ_ALUT2},
  663. {0x0965, SIERRA_DEQ_ALUT3},
  664. {0x08A2, SIERRA_DEQ_ALUT4},
  665. {0x07DF, SIERRA_DEQ_ALUT5},
  666. {0x071C, SIERRA_DEQ_ALUT6},
  667. {0x0659, SIERRA_DEQ_ALUT7},
  668. {0x0596, SIERRA_DEQ_ALUT8},
  669. {0x0514, SIERRA_DEQ_ALUT9},
  670. {0x0492, SIERRA_DEQ_ALUT10},
  671. {0x0410, SIERRA_DEQ_ALUT11},
  672. {0x038E, SIERRA_DEQ_ALUT12},
  673. {0x030C, SIERRA_DEQ_ALUT13},
  674. {0x03F4, SIERRA_DEQ_DFETAP_CTRL_PREG},
  675. {0x0001, SIERRA_DFE_EN_1010_IGNORE_PREG},
  676. {0x3C01, SIERRA_DEQ_TAU_CTRL1_FAST_MAINT_PREG},
  677. {0x3C40, SIERRA_DEQ_TAU_CTRL1_SLOW_MAINT_PREG},
  678. {0x1C08, SIERRA_DEQ_TAU_CTRL2_PREG},
  679. {0x0033, SIERRA_DEQ_PICTRL_PREG},
  680. {0x0400, SIERRA_CPICAL_TMRVAL_MODE1_PREG},
  681. {0x0330, SIERRA_CPICAL_TMRVAL_MODE0_PREG},
  682. {0x01FF, SIERRA_CPICAL_PICNT_MODE1_PREG},
  683. {0x0009, SIERRA_CPI_OUTBUF_RATESEL_PREG},
  684. {0x3232, SIERRA_CPICAL_RES_STARTCODE_MODE23_PREG},
  685. {0x0005, SIERRA_LFPSDET_SUPPORT_PREG},
  686. {0x000F, SIERRA_LFPSFILT_NS_PREG},
  687. {0x0009, SIERRA_LFPSFILT_RD_PREG},
  688. {0x0001, SIERRA_LFPSFILT_MP_PREG},
  689. {0x6013, SIERRA_SIGDET_SUPPORT_PREG},
  690. {0x8013, SIERRA_SDFILT_H2L_A_PREG},
  691. {0x8009, SIERRA_SDFILT_L2H_PREG},
  692. {0x0024, SIERRA_RXBUFFER_CTLECTRL_PREG},
  693. {0x0020, SIERRA_RXBUFFER_RCDFECTRL_PREG},
  694. {0x4243, SIERRA_RXBUFFER_DFECTRL_PREG}
  695. };
  696. static const struct cdns_sierra_data cdns_map_sierra = {
  697. SIERRA_MACRO_ID,
  698. 0x2,
  699. 0x2,
  700. ARRAY_SIZE(cdns_pcie_cmn_regs_ext_ssc),
  701. ARRAY_SIZE(cdns_pcie_ln_regs_ext_ssc),
  702. ARRAY_SIZE(cdns_usb_cmn_regs_ext_ssc),
  703. ARRAY_SIZE(cdns_usb_ln_regs_ext_ssc),
  704. cdns_pcie_cmn_regs_ext_ssc,
  705. cdns_pcie_ln_regs_ext_ssc,
  706. cdns_usb_cmn_regs_ext_ssc,
  707. cdns_usb_ln_regs_ext_ssc,
  708. };
  709. static const struct cdns_sierra_data cdns_ti_map_sierra = {
  710. SIERRA_MACRO_ID,
  711. 0x0,
  712. 0x1,
  713. ARRAY_SIZE(cdns_pcie_cmn_regs_ext_ssc),
  714. ARRAY_SIZE(cdns_pcie_ln_regs_ext_ssc),
  715. ARRAY_SIZE(cdns_usb_cmn_regs_ext_ssc),
  716. ARRAY_SIZE(cdns_usb_ln_regs_ext_ssc),
  717. cdns_pcie_cmn_regs_ext_ssc,
  718. cdns_pcie_ln_regs_ext_ssc,
  719. cdns_usb_cmn_regs_ext_ssc,
  720. cdns_usb_ln_regs_ext_ssc,
  721. };
  722. static const struct of_device_id cdns_sierra_id_table[] = {
  723. {
  724. .compatible = "cdns,sierra-phy-t0",
  725. .data = &cdns_map_sierra,
  726. },
  727. {
  728. .compatible = "ti,sierra-phy-t0",
  729. .data = &cdns_ti_map_sierra,
  730. },
  731. {}
  732. };
  733. MODULE_DEVICE_TABLE(of, cdns_sierra_id_table);
  734. static struct platform_driver cdns_sierra_driver = {
  735. .probe = cdns_sierra_phy_probe,
  736. .remove = cdns_sierra_phy_remove,
  737. .driver = {
  738. .name = "cdns-sierra-phy",
  739. .of_match_table = cdns_sierra_id_table,
  740. },
  741. };
  742. module_platform_driver(cdns_sierra_driver);
  743. MODULE_ALIAS("platform:cdns_sierra");
  744. MODULE_AUTHOR("Cadence Design Systems");
  745. MODULE_DESCRIPTION("CDNS sierra phy driver");
  746. MODULE_LICENSE("GPL v2");