cdns-dphy.c 10 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * Copyright: 2017-2018 Cadence Design Systems, Inc.
  4. */
  5. #include <linux/bitops.h>
  6. #include <linux/clk.h>
  7. #include <linux/io.h>
  8. #include <linux/module.h>
  9. #include <linux/of_address.h>
  10. #include <linux/of_device.h>
  11. #include <linux/platform_device.h>
  12. #include <linux/reset.h>
  13. #include <linux/phy/phy.h>
  14. #include <linux/phy/phy-mipi-dphy.h>
  15. #define REG_WAKEUP_TIME_NS 800
  16. #define DPHY_PLL_RATE_HZ 108000000
  17. /* DPHY registers */
  18. #define DPHY_PMA_CMN(reg) (reg)
  19. #define DPHY_PMA_LCLK(reg) (0x100 + (reg))
  20. #define DPHY_PMA_LDATA(lane, reg) (0x200 + ((lane) * 0x100) + (reg))
  21. #define DPHY_PMA_RCLK(reg) (0x600 + (reg))
  22. #define DPHY_PMA_RDATA(lane, reg) (0x700 + ((lane) * 0x100) + (reg))
  23. #define DPHY_PCS(reg) (0xb00 + (reg))
  24. #define DPHY_CMN_SSM DPHY_PMA_CMN(0x20)
  25. #define DPHY_CMN_SSM_EN BIT(0)
  26. #define DPHY_CMN_TX_MODE_EN BIT(9)
  27. #define DPHY_CMN_PWM DPHY_PMA_CMN(0x40)
  28. #define DPHY_CMN_PWM_DIV(x) ((x) << 20)
  29. #define DPHY_CMN_PWM_LOW(x) ((x) << 10)
  30. #define DPHY_CMN_PWM_HIGH(x) (x)
  31. #define DPHY_CMN_FBDIV DPHY_PMA_CMN(0x4c)
  32. #define DPHY_CMN_FBDIV_VAL(low, high) (((high) << 11) | ((low) << 22))
  33. #define DPHY_CMN_FBDIV_FROM_REG (BIT(10) | BIT(21))
  34. #define DPHY_CMN_OPIPDIV DPHY_PMA_CMN(0x50)
  35. #define DPHY_CMN_IPDIV_FROM_REG BIT(0)
  36. #define DPHY_CMN_IPDIV(x) ((x) << 1)
  37. #define DPHY_CMN_OPDIV_FROM_REG BIT(6)
  38. #define DPHY_CMN_OPDIV(x) ((x) << 7)
  39. #define DPHY_PSM_CFG DPHY_PCS(0x4)
  40. #define DPHY_PSM_CFG_FROM_REG BIT(0)
  41. #define DPHY_PSM_CLK_DIV(x) ((x) << 1)
  42. #define DSI_HBP_FRAME_OVERHEAD 12
  43. #define DSI_HSA_FRAME_OVERHEAD 14
  44. #define DSI_HFP_FRAME_OVERHEAD 6
  45. #define DSI_HSS_VSS_VSE_FRAME_OVERHEAD 4
  46. #define DSI_BLANKING_FRAME_OVERHEAD 6
  47. #define DSI_NULL_FRAME_OVERHEAD 6
  48. #define DSI_EOT_PKT_SIZE 4
  49. struct cdns_dphy_cfg {
  50. u8 pll_ipdiv;
  51. u8 pll_opdiv;
  52. u16 pll_fbdiv;
  53. unsigned int nlanes;
  54. };
  55. enum cdns_dphy_clk_lane_cfg {
  56. DPHY_CLK_CFG_LEFT_DRIVES_ALL = 0,
  57. DPHY_CLK_CFG_LEFT_DRIVES_RIGHT = 1,
  58. DPHY_CLK_CFG_LEFT_DRIVES_LEFT = 2,
  59. DPHY_CLK_CFG_RIGHT_DRIVES_ALL = 3,
  60. };
  61. struct cdns_dphy;
  62. struct cdns_dphy_ops {
  63. int (*probe)(struct cdns_dphy *dphy);
  64. void (*remove)(struct cdns_dphy *dphy);
  65. void (*set_psm_div)(struct cdns_dphy *dphy, u8 div);
  66. void (*set_clk_lane_cfg)(struct cdns_dphy *dphy,
  67. enum cdns_dphy_clk_lane_cfg cfg);
  68. void (*set_pll_cfg)(struct cdns_dphy *dphy,
  69. const struct cdns_dphy_cfg *cfg);
  70. unsigned long (*get_wakeup_time_ns)(struct cdns_dphy *dphy);
  71. };
  72. struct cdns_dphy {
  73. struct cdns_dphy_cfg cfg;
  74. void __iomem *regs;
  75. struct clk *psm_clk;
  76. struct clk *pll_ref_clk;
  77. const struct cdns_dphy_ops *ops;
  78. struct phy *phy;
  79. };
  80. static int cdns_dsi_get_dphy_pll_cfg(struct cdns_dphy *dphy,
  81. struct cdns_dphy_cfg *cfg,
  82. struct phy_configure_opts_mipi_dphy *opts,
  83. unsigned int *dsi_hfp_ext)
  84. {
  85. unsigned long pll_ref_hz = clk_get_rate(dphy->pll_ref_clk);
  86. u64 dlane_bps;
  87. memset(cfg, 0, sizeof(*cfg));
  88. if (pll_ref_hz < 9600000 || pll_ref_hz >= 150000000)
  89. return -EINVAL;
  90. else if (pll_ref_hz < 19200000)
  91. cfg->pll_ipdiv = 1;
  92. else if (pll_ref_hz < 38400000)
  93. cfg->pll_ipdiv = 2;
  94. else if (pll_ref_hz < 76800000)
  95. cfg->pll_ipdiv = 4;
  96. else
  97. cfg->pll_ipdiv = 8;
  98. dlane_bps = opts->hs_clk_rate;
  99. if (dlane_bps > 2500000000UL || dlane_bps < 160000000UL)
  100. return -EINVAL;
  101. else if (dlane_bps >= 1250000000)
  102. cfg->pll_opdiv = 1;
  103. else if (dlane_bps >= 630000000)
  104. cfg->pll_opdiv = 2;
  105. else if (dlane_bps >= 320000000)
  106. cfg->pll_opdiv = 4;
  107. else if (dlane_bps >= 160000000)
  108. cfg->pll_opdiv = 8;
  109. cfg->pll_fbdiv = DIV_ROUND_UP_ULL(dlane_bps * 2 * cfg->pll_opdiv *
  110. cfg->pll_ipdiv,
  111. pll_ref_hz);
  112. return 0;
  113. }
  114. static int cdns_dphy_setup_psm(struct cdns_dphy *dphy)
  115. {
  116. unsigned long psm_clk_hz = clk_get_rate(dphy->psm_clk);
  117. unsigned long psm_div;
  118. if (!psm_clk_hz || psm_clk_hz > 100000000)
  119. return -EINVAL;
  120. psm_div = DIV_ROUND_CLOSEST(psm_clk_hz, 1000000);
  121. if (dphy->ops->set_psm_div)
  122. dphy->ops->set_psm_div(dphy, psm_div);
  123. return 0;
  124. }
  125. static void cdns_dphy_set_clk_lane_cfg(struct cdns_dphy *dphy,
  126. enum cdns_dphy_clk_lane_cfg cfg)
  127. {
  128. if (dphy->ops->set_clk_lane_cfg)
  129. dphy->ops->set_clk_lane_cfg(dphy, cfg);
  130. }
  131. static void cdns_dphy_set_pll_cfg(struct cdns_dphy *dphy,
  132. const struct cdns_dphy_cfg *cfg)
  133. {
  134. if (dphy->ops->set_pll_cfg)
  135. dphy->ops->set_pll_cfg(dphy, cfg);
  136. }
  137. static unsigned long cdns_dphy_get_wakeup_time_ns(struct cdns_dphy *dphy)
  138. {
  139. return dphy->ops->get_wakeup_time_ns(dphy);
  140. }
  141. static unsigned long cdns_dphy_ref_get_wakeup_time_ns(struct cdns_dphy *dphy)
  142. {
  143. /* Default wakeup time is 800 ns (in a simulated environment). */
  144. return 800;
  145. }
  146. static void cdns_dphy_ref_set_pll_cfg(struct cdns_dphy *dphy,
  147. const struct cdns_dphy_cfg *cfg)
  148. {
  149. u32 fbdiv_low, fbdiv_high;
  150. fbdiv_low = (cfg->pll_fbdiv / 4) - 2;
  151. fbdiv_high = cfg->pll_fbdiv - fbdiv_low - 2;
  152. writel(DPHY_CMN_IPDIV_FROM_REG | DPHY_CMN_OPDIV_FROM_REG |
  153. DPHY_CMN_IPDIV(cfg->pll_ipdiv) |
  154. DPHY_CMN_OPDIV(cfg->pll_opdiv),
  155. dphy->regs + DPHY_CMN_OPIPDIV);
  156. writel(DPHY_CMN_FBDIV_FROM_REG |
  157. DPHY_CMN_FBDIV_VAL(fbdiv_low, fbdiv_high),
  158. dphy->regs + DPHY_CMN_FBDIV);
  159. writel(DPHY_CMN_PWM_HIGH(6) | DPHY_CMN_PWM_LOW(0x101) |
  160. DPHY_CMN_PWM_DIV(0x8),
  161. dphy->regs + DPHY_CMN_PWM);
  162. }
  163. static void cdns_dphy_ref_set_psm_div(struct cdns_dphy *dphy, u8 div)
  164. {
  165. writel(DPHY_PSM_CFG_FROM_REG | DPHY_PSM_CLK_DIV(div),
  166. dphy->regs + DPHY_PSM_CFG);
  167. }
  168. /*
  169. * This is the reference implementation of DPHY hooks. Specific integration of
  170. * this IP may have to re-implement some of them depending on how they decided
  171. * to wire things in the SoC.
  172. */
  173. static const struct cdns_dphy_ops ref_dphy_ops = {
  174. .get_wakeup_time_ns = cdns_dphy_ref_get_wakeup_time_ns,
  175. .set_pll_cfg = cdns_dphy_ref_set_pll_cfg,
  176. .set_psm_div = cdns_dphy_ref_set_psm_div,
  177. };
  178. static int cdns_dphy_config_from_opts(struct phy *phy,
  179. struct phy_configure_opts_mipi_dphy *opts,
  180. struct cdns_dphy_cfg *cfg)
  181. {
  182. struct cdns_dphy *dphy = phy_get_drvdata(phy);
  183. unsigned int dsi_hfp_ext = 0;
  184. int ret;
  185. ret = phy_mipi_dphy_config_validate(opts);
  186. if (ret)
  187. return ret;
  188. ret = cdns_dsi_get_dphy_pll_cfg(dphy, cfg,
  189. opts, &dsi_hfp_ext);
  190. if (ret)
  191. return ret;
  192. opts->wakeup = cdns_dphy_get_wakeup_time_ns(dphy) / 1000;
  193. return 0;
  194. }
  195. static int cdns_dphy_validate(struct phy *phy, enum phy_mode mode, int submode,
  196. union phy_configure_opts *opts)
  197. {
  198. struct cdns_dphy_cfg cfg = { 0 };
  199. if (mode != PHY_MODE_MIPI_DPHY)
  200. return -EINVAL;
  201. return cdns_dphy_config_from_opts(phy, &opts->mipi_dphy, &cfg);
  202. }
  203. static int cdns_dphy_configure(struct phy *phy, union phy_configure_opts *opts)
  204. {
  205. struct cdns_dphy *dphy = phy_get_drvdata(phy);
  206. struct cdns_dphy_cfg cfg = { 0 };
  207. int ret;
  208. ret = cdns_dphy_config_from_opts(phy, &opts->mipi_dphy, &cfg);
  209. if (ret)
  210. return ret;
  211. /*
  212. * Configure the internal PSM clk divider so that the DPHY has a
  213. * 1MHz clk (or something close).
  214. */
  215. ret = cdns_dphy_setup_psm(dphy);
  216. if (ret)
  217. return ret;
  218. /*
  219. * Configure attach clk lanes to data lanes: the DPHY has 2 clk lanes
  220. * and 8 data lanes, each clk lane can be attache different set of
  221. * data lanes. The 2 groups are named 'left' and 'right', so here we
  222. * just say that we want the 'left' clk lane to drive the 'left' data
  223. * lanes.
  224. */
  225. cdns_dphy_set_clk_lane_cfg(dphy, DPHY_CLK_CFG_LEFT_DRIVES_LEFT);
  226. /*
  227. * Configure the DPHY PLL that will be used to generate the TX byte
  228. * clk.
  229. */
  230. cdns_dphy_set_pll_cfg(dphy, &cfg);
  231. return 0;
  232. }
  233. static int cdns_dphy_power_on(struct phy *phy)
  234. {
  235. struct cdns_dphy *dphy = phy_get_drvdata(phy);
  236. clk_prepare_enable(dphy->psm_clk);
  237. clk_prepare_enable(dphy->pll_ref_clk);
  238. /* Start TX state machine. */
  239. writel(DPHY_CMN_SSM_EN | DPHY_CMN_TX_MODE_EN,
  240. dphy->regs + DPHY_CMN_SSM);
  241. return 0;
  242. }
  243. static int cdns_dphy_power_off(struct phy *phy)
  244. {
  245. struct cdns_dphy *dphy = phy_get_drvdata(phy);
  246. clk_disable_unprepare(dphy->pll_ref_clk);
  247. clk_disable_unprepare(dphy->psm_clk);
  248. return 0;
  249. }
  250. static const struct phy_ops cdns_dphy_ops = {
  251. .configure = cdns_dphy_configure,
  252. .validate = cdns_dphy_validate,
  253. .power_on = cdns_dphy_power_on,
  254. .power_off = cdns_dphy_power_off,
  255. };
  256. static int cdns_dphy_probe(struct platform_device *pdev)
  257. {
  258. struct phy_provider *phy_provider;
  259. struct cdns_dphy *dphy;
  260. struct resource *res;
  261. int ret;
  262. dphy = devm_kzalloc(&pdev->dev, sizeof(*dphy), GFP_KERNEL);
  263. if (!dphy)
  264. return -ENOMEM;
  265. dev_set_drvdata(&pdev->dev, dphy);
  266. dphy->ops = of_device_get_match_data(&pdev->dev);
  267. if (!dphy->ops)
  268. return -EINVAL;
  269. res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
  270. dphy->regs = devm_ioremap_resource(&pdev->dev, res);
  271. if (IS_ERR(dphy->regs))
  272. return PTR_ERR(dphy->regs);
  273. dphy->psm_clk = devm_clk_get(&pdev->dev, "psm");
  274. if (IS_ERR(dphy->psm_clk))
  275. return PTR_ERR(dphy->psm_clk);
  276. dphy->pll_ref_clk = devm_clk_get(&pdev->dev, "pll_ref");
  277. if (IS_ERR(dphy->pll_ref_clk))
  278. return PTR_ERR(dphy->pll_ref_clk);
  279. if (dphy->ops->probe) {
  280. ret = dphy->ops->probe(dphy);
  281. if (ret)
  282. return ret;
  283. }
  284. dphy->phy = devm_phy_create(&pdev->dev, NULL, &cdns_dphy_ops);
  285. if (IS_ERR(dphy->phy)) {
  286. dev_err(&pdev->dev, "failed to create PHY\n");
  287. if (dphy->ops->remove)
  288. dphy->ops->remove(dphy);
  289. return PTR_ERR(dphy->phy);
  290. }
  291. phy_set_drvdata(dphy->phy, dphy);
  292. phy_provider = devm_of_phy_provider_register(&pdev->dev,
  293. of_phy_simple_xlate);
  294. return PTR_ERR_OR_ZERO(phy_provider);
  295. }
  296. static int cdns_dphy_remove(struct platform_device *pdev)
  297. {
  298. struct cdns_dphy *dphy = dev_get_drvdata(&pdev->dev);
  299. if (dphy->ops->remove)
  300. dphy->ops->remove(dphy);
  301. return 0;
  302. }
  303. static const struct of_device_id cdns_dphy_of_match[] = {
  304. { .compatible = "cdns,dphy", .data = &ref_dphy_ops },
  305. { /* sentinel */ },
  306. };
  307. MODULE_DEVICE_TABLE(of, cdns_dphy_of_match);
  308. static struct platform_driver cdns_dphy_platform_driver = {
  309. .probe = cdns_dphy_probe,
  310. .remove = cdns_dphy_remove,
  311. .driver = {
  312. .name = "cdns-mipi-dphy",
  313. .of_match_table = cdns_dphy_of_match,
  314. },
  315. };
  316. module_platform_driver(cdns_dphy_platform_driver);
  317. MODULE_AUTHOR("Maxime Ripard <maxime.ripard@bootlin.com>");
  318. MODULE_DESCRIPTION("Cadence MIPI D-PHY Driver");
  319. MODULE_LICENSE("GPL");