phy-bcm-sr-pcie.c 7.4 KB

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  1. // SPDX-License-Identifier: GPL-2.0
  2. /*
  3. * Copyright (C) 2016-2018 Broadcom
  4. */
  5. #include <linux/clk.h>
  6. #include <linux/delay.h>
  7. #include <linux/io.h>
  8. #include <linux/module.h>
  9. #include <linux/mfd/syscon.h>
  10. #include <linux/of.h>
  11. #include <linux/phy/phy.h>
  12. #include <linux/platform_device.h>
  13. #include <linux/regmap.h>
  14. /* we have up to 8 PAXB based RC. The 9th one is always PAXC */
  15. #define SR_NR_PCIE_PHYS 9
  16. #define SR_PAXC_PHY_IDX (SR_NR_PCIE_PHYS - 1)
  17. #define PCIE_PIPEMUX_CFG_OFFSET 0x10c
  18. #define PCIE_PIPEMUX_SELECT_STRAP 0xf
  19. #define CDRU_STRAP_DATA_LSW_OFFSET 0x5c
  20. #define PCIE_PIPEMUX_SHIFT 19
  21. #define PCIE_PIPEMUX_MASK 0xf
  22. #define MHB_MEM_PW_PAXC_OFFSET 0x1c0
  23. #define MHB_PWR_ARR_POWERON 0x8
  24. #define MHB_PWR_ARR_POWEROK 0x4
  25. #define MHB_PWR_POWERON 0x2
  26. #define MHB_PWR_POWEROK 0x1
  27. #define MHB_PWR_STATUS_MASK (MHB_PWR_ARR_POWERON | \
  28. MHB_PWR_ARR_POWEROK | \
  29. MHB_PWR_POWERON | \
  30. MHB_PWR_POWEROK)
  31. struct sr_pcie_phy_core;
  32. /**
  33. * struct sr_pcie_phy - Stingray PCIe PHY
  34. *
  35. * @core: pointer to the Stingray PCIe PHY core control
  36. * @index: PHY index
  37. * @phy: pointer to the kernel PHY device
  38. */
  39. struct sr_pcie_phy {
  40. struct sr_pcie_phy_core *core;
  41. unsigned int index;
  42. struct phy *phy;
  43. };
  44. /**
  45. * struct sr_pcie_phy_core - Stingray PCIe PHY core control
  46. *
  47. * @dev: pointer to device
  48. * @base: base register of PCIe SS
  49. * @cdru: regmap to the CDRU device
  50. * @mhb: regmap to the MHB device
  51. * @pipemux: pipemuex strap
  52. * @phys: array of PCIe PHYs
  53. */
  54. struct sr_pcie_phy_core {
  55. struct device *dev;
  56. void __iomem *base;
  57. struct regmap *cdru;
  58. struct regmap *mhb;
  59. u32 pipemux;
  60. struct sr_pcie_phy phys[SR_NR_PCIE_PHYS];
  61. };
  62. /*
  63. * PCIe PIPEMUX lookup table
  64. *
  65. * Each array index represents a PIPEMUX strap setting
  66. * The array element represents a bitmap where a set bit means the PCIe
  67. * core and associated serdes has been enabled as RC and is available for use
  68. */
  69. static const u8 pipemux_table[] = {
  70. /* PIPEMUX = 0, EP 1x16 */
  71. 0x00,
  72. /* PIPEMUX = 1, EP 1x8 + RC 1x8, core 7 */
  73. 0x80,
  74. /* PIPEMUX = 2, EP 4x4 */
  75. 0x00,
  76. /* PIPEMUX = 3, RC 2x8, cores 0, 7 */
  77. 0x81,
  78. /* PIPEMUX = 4, RC 4x4, cores 0, 1, 6, 7 */
  79. 0xc3,
  80. /* PIPEMUX = 5, RC 8x2, all 8 cores */
  81. 0xff,
  82. /* PIPEMUX = 6, RC 3x4 + 2x2, cores 0, 2, 3, 6, 7 */
  83. 0xcd,
  84. /* PIPEMUX = 7, RC 1x4 + 6x2, cores 0, 2, 3, 4, 5, 6, 7 */
  85. 0xfd,
  86. /* PIPEMUX = 8, EP 1x8 + RC 4x2, cores 4, 5, 6, 7 */
  87. 0xf0,
  88. /* PIPEMUX = 9, EP 1x8 + RC 2x4, cores 6, 7 */
  89. 0xc0,
  90. /* PIPEMUX = 10, EP 2x4 + RC 2x4, cores 1, 6 */
  91. 0x42,
  92. /* PIPEMUX = 11, EP 2x4 + RC 4x2, cores 2, 3, 4, 5 */
  93. 0x3c,
  94. /* PIPEMUX = 12, EP 1x4 + RC 6x2, cores 2, 3, 4, 5, 6, 7 */
  95. 0xfc,
  96. /* PIPEMUX = 13, RC 2x4 + RC 1x4 + 2x2, cores 2, 3, 6 */
  97. 0x4c,
  98. };
  99. /*
  100. * Return true if the strap setting is valid
  101. */
  102. static bool pipemux_strap_is_valid(u32 pipemux)
  103. {
  104. return !!(pipemux < ARRAY_SIZE(pipemux_table));
  105. }
  106. /*
  107. * Read the PCIe PIPEMUX from strap
  108. */
  109. static u32 pipemux_strap_read(struct sr_pcie_phy_core *core)
  110. {
  111. u32 pipemux;
  112. /*
  113. * Read PIPEMUX configuration register to determine the pipemux setting
  114. *
  115. * In the case when the value indicates using HW strap, fall back to
  116. * use HW strap
  117. */
  118. pipemux = readl(core->base + PCIE_PIPEMUX_CFG_OFFSET);
  119. pipemux &= PCIE_PIPEMUX_MASK;
  120. if (pipemux == PCIE_PIPEMUX_SELECT_STRAP) {
  121. regmap_read(core->cdru, CDRU_STRAP_DATA_LSW_OFFSET, &pipemux);
  122. pipemux >>= PCIE_PIPEMUX_SHIFT;
  123. pipemux &= PCIE_PIPEMUX_MASK;
  124. }
  125. return pipemux;
  126. }
  127. /*
  128. * Given a PIPEMUX strap and PCIe core index, this function returns true if the
  129. * PCIe core needs to be enabled
  130. */
  131. static bool pcie_core_is_for_rc(struct sr_pcie_phy *phy)
  132. {
  133. struct sr_pcie_phy_core *core = phy->core;
  134. unsigned int core_idx = phy->index;
  135. return !!((pipemux_table[core->pipemux] >> core_idx) & 0x1);
  136. }
  137. static int sr_pcie_phy_init(struct phy *p)
  138. {
  139. struct sr_pcie_phy *phy = phy_get_drvdata(p);
  140. /*
  141. * Check whether this PHY is for root complex or not. If yes, return
  142. * zero so the host driver can proceed to enumeration. If not, return
  143. * an error and that will force the host driver to bail out
  144. */
  145. if (pcie_core_is_for_rc(phy))
  146. return 0;
  147. return -ENODEV;
  148. }
  149. static int sr_paxc_phy_init(struct phy *p)
  150. {
  151. struct sr_pcie_phy *phy = phy_get_drvdata(p);
  152. struct sr_pcie_phy_core *core = phy->core;
  153. unsigned int core_idx = phy->index;
  154. u32 val;
  155. if (core_idx != SR_PAXC_PHY_IDX)
  156. return -EINVAL;
  157. regmap_read(core->mhb, MHB_MEM_PW_PAXC_OFFSET, &val);
  158. if ((val & MHB_PWR_STATUS_MASK) != MHB_PWR_STATUS_MASK) {
  159. dev_err(core->dev, "PAXC is not powered up\n");
  160. return -ENODEV;
  161. }
  162. return 0;
  163. }
  164. static const struct phy_ops sr_pcie_phy_ops = {
  165. .init = sr_pcie_phy_init,
  166. .owner = THIS_MODULE,
  167. };
  168. static const struct phy_ops sr_paxc_phy_ops = {
  169. .init = sr_paxc_phy_init,
  170. .owner = THIS_MODULE,
  171. };
  172. static struct phy *sr_pcie_phy_xlate(struct device *dev,
  173. struct of_phandle_args *args)
  174. {
  175. struct sr_pcie_phy_core *core;
  176. int phy_idx;
  177. core = dev_get_drvdata(dev);
  178. if (!core)
  179. return ERR_PTR(-EINVAL);
  180. phy_idx = args->args[0];
  181. if (WARN_ON(phy_idx >= SR_NR_PCIE_PHYS))
  182. return ERR_PTR(-ENODEV);
  183. return core->phys[phy_idx].phy;
  184. }
  185. static int sr_pcie_phy_probe(struct platform_device *pdev)
  186. {
  187. struct device *dev = &pdev->dev;
  188. struct device_node *node = dev->of_node;
  189. struct sr_pcie_phy_core *core;
  190. struct resource *res;
  191. struct phy_provider *provider;
  192. unsigned int phy_idx = 0;
  193. core = devm_kzalloc(dev, sizeof(*core), GFP_KERNEL);
  194. if (!core)
  195. return -ENOMEM;
  196. core->dev = dev;
  197. res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
  198. core->base = devm_ioremap_resource(core->dev, res);
  199. if (IS_ERR(core->base))
  200. return PTR_ERR(core->base);
  201. core->cdru = syscon_regmap_lookup_by_phandle(node, "brcm,sr-cdru");
  202. if (IS_ERR(core->cdru)) {
  203. dev_err(core->dev, "unable to find CDRU device\n");
  204. return PTR_ERR(core->cdru);
  205. }
  206. core->mhb = syscon_regmap_lookup_by_phandle(node, "brcm,sr-mhb");
  207. if (IS_ERR(core->mhb)) {
  208. dev_err(core->dev, "unable to find MHB device\n");
  209. return PTR_ERR(core->mhb);
  210. }
  211. /* read the PCIe PIPEMUX strap setting */
  212. core->pipemux = pipemux_strap_read(core);
  213. if (!pipemux_strap_is_valid(core->pipemux)) {
  214. dev_err(core->dev, "invalid PCIe PIPEMUX strap %u\n",
  215. core->pipemux);
  216. return -EIO;
  217. }
  218. for (phy_idx = 0; phy_idx < SR_NR_PCIE_PHYS; phy_idx++) {
  219. struct sr_pcie_phy *p = &core->phys[phy_idx];
  220. const struct phy_ops *ops;
  221. if (phy_idx == SR_PAXC_PHY_IDX)
  222. ops = &sr_paxc_phy_ops;
  223. else
  224. ops = &sr_pcie_phy_ops;
  225. p->phy = devm_phy_create(dev, NULL, ops);
  226. if (IS_ERR(p->phy)) {
  227. dev_err(dev, "failed to create PCIe PHY\n");
  228. return PTR_ERR(p->phy);
  229. }
  230. p->core = core;
  231. p->index = phy_idx;
  232. phy_set_drvdata(p->phy, p);
  233. }
  234. dev_set_drvdata(dev, core);
  235. provider = devm_of_phy_provider_register(dev, sr_pcie_phy_xlate);
  236. if (IS_ERR(provider)) {
  237. dev_err(dev, "failed to register PHY provider\n");
  238. return PTR_ERR(provider);
  239. }
  240. dev_info(dev, "Stingray PCIe PHY driver initialized\n");
  241. return 0;
  242. }
  243. static const struct of_device_id sr_pcie_phy_match_table[] = {
  244. { .compatible = "brcm,sr-pcie-phy" },
  245. { }
  246. };
  247. MODULE_DEVICE_TABLE(of, sr_pcie_phy_match_table);
  248. static struct platform_driver sr_pcie_phy_driver = {
  249. .driver = {
  250. .name = "sr-pcie-phy",
  251. .of_match_table = sr_pcie_phy_match_table,
  252. },
  253. .probe = sr_pcie_phy_probe,
  254. };
  255. module_platform_driver(sr_pcie_phy_driver);
  256. MODULE_AUTHOR("Ray Jui <ray.jui@broadcom.com>");
  257. MODULE_DESCRIPTION("Broadcom Stingray PCIe PHY driver");
  258. MODULE_LICENSE("GPL v2");