xgene_pmu.c 56 KB

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  1. // SPDX-License-Identifier: GPL-2.0-or-later
  2. /*
  3. * APM X-Gene SoC PMU (Performance Monitor Unit)
  4. *
  5. * Copyright (c) 2016, Applied Micro Circuits Corporation
  6. * Author: Hoan Tran <hotran@apm.com>
  7. * Tai Nguyen <ttnguyen@apm.com>
  8. */
  9. #include <linux/acpi.h>
  10. #include <linux/clk.h>
  11. #include <linux/cpuhotplug.h>
  12. #include <linux/cpumask.h>
  13. #include <linux/interrupt.h>
  14. #include <linux/io.h>
  15. #include <linux/mfd/syscon.h>
  16. #include <linux/module.h>
  17. #include <linux/of_address.h>
  18. #include <linux/of_fdt.h>
  19. #include <linux/of_irq.h>
  20. #include <linux/of_platform.h>
  21. #include <linux/perf_event.h>
  22. #include <linux/platform_device.h>
  23. #include <linux/regmap.h>
  24. #include <linux/slab.h>
  25. #define CSW_CSWCR 0x0000
  26. #define CSW_CSWCR_DUALMCB_MASK BIT(0)
  27. #define CSW_CSWCR_MCB0_ROUTING(x) (((x) & 0x0C) >> 2)
  28. #define CSW_CSWCR_MCB1_ROUTING(x) (((x) & 0x30) >> 4)
  29. #define MCBADDRMR 0x0000
  30. #define MCBADDRMR_DUALMCU_MODE_MASK BIT(2)
  31. #define PCPPMU_INTSTATUS_REG 0x000
  32. #define PCPPMU_INTMASK_REG 0x004
  33. #define PCPPMU_INTMASK 0x0000000F
  34. #define PCPPMU_INTENMASK 0xFFFFFFFF
  35. #define PCPPMU_INTCLRMASK 0xFFFFFFF0
  36. #define PCPPMU_INT_MCU BIT(0)
  37. #define PCPPMU_INT_MCB BIT(1)
  38. #define PCPPMU_INT_L3C BIT(2)
  39. #define PCPPMU_INT_IOB BIT(3)
  40. #define PCPPMU_V3_INTMASK 0x00FF33FF
  41. #define PCPPMU_V3_INTENMASK 0xFFFFFFFF
  42. #define PCPPMU_V3_INTCLRMASK 0xFF00CC00
  43. #define PCPPMU_V3_INT_MCU 0x000000FF
  44. #define PCPPMU_V3_INT_MCB 0x00000300
  45. #define PCPPMU_V3_INT_L3C 0x00FF0000
  46. #define PCPPMU_V3_INT_IOB 0x00003000
  47. #define PMU_MAX_COUNTERS 4
  48. #define PMU_CNT_MAX_PERIOD 0xFFFFFFFFULL
  49. #define PMU_V3_CNT_MAX_PERIOD 0xFFFFFFFFFFFFFFFFULL
  50. #define PMU_OVERFLOW_MASK 0xF
  51. #define PMU_PMCR_E BIT(0)
  52. #define PMU_PMCR_P BIT(1)
  53. #define PMU_PMEVCNTR0 0x000
  54. #define PMU_PMEVCNTR1 0x004
  55. #define PMU_PMEVCNTR2 0x008
  56. #define PMU_PMEVCNTR3 0x00C
  57. #define PMU_PMEVTYPER0 0x400
  58. #define PMU_PMEVTYPER1 0x404
  59. #define PMU_PMEVTYPER2 0x408
  60. #define PMU_PMEVTYPER3 0x40C
  61. #define PMU_PMAMR0 0xA00
  62. #define PMU_PMAMR1 0xA04
  63. #define PMU_PMCNTENSET 0xC00
  64. #define PMU_PMCNTENCLR 0xC20
  65. #define PMU_PMINTENSET 0xC40
  66. #define PMU_PMINTENCLR 0xC60
  67. #define PMU_PMOVSR 0xC80
  68. #define PMU_PMCR 0xE04
  69. /* PMU registers for V3 */
  70. #define PMU_PMOVSCLR 0xC80
  71. #define PMU_PMOVSSET 0xCC0
  72. #define to_pmu_dev(p) container_of(p, struct xgene_pmu_dev, pmu)
  73. #define GET_CNTR(ev) (ev->hw.idx)
  74. #define GET_EVENTID(ev) (ev->hw.config & 0xFFULL)
  75. #define GET_AGENTID(ev) (ev->hw.config_base & 0xFFFFFFFFUL)
  76. #define GET_AGENT1ID(ev) ((ev->hw.config_base >> 32) & 0xFFFFFFFFUL)
  77. struct hw_pmu_info {
  78. u32 type;
  79. u32 enable_mask;
  80. void __iomem *csr;
  81. };
  82. struct xgene_pmu_dev {
  83. struct hw_pmu_info *inf;
  84. struct xgene_pmu *parent;
  85. struct pmu pmu;
  86. u8 max_counters;
  87. DECLARE_BITMAP(cntr_assign_mask, PMU_MAX_COUNTERS);
  88. u64 max_period;
  89. const struct attribute_group **attr_groups;
  90. struct perf_event *pmu_counter_event[PMU_MAX_COUNTERS];
  91. };
  92. struct xgene_pmu_ops {
  93. void (*mask_int)(struct xgene_pmu *pmu);
  94. void (*unmask_int)(struct xgene_pmu *pmu);
  95. u64 (*read_counter)(struct xgene_pmu_dev *pmu, int idx);
  96. void (*write_counter)(struct xgene_pmu_dev *pmu, int idx, u64 val);
  97. void (*write_evttype)(struct xgene_pmu_dev *pmu_dev, int idx, u32 val);
  98. void (*write_agentmsk)(struct xgene_pmu_dev *pmu_dev, u32 val);
  99. void (*write_agent1msk)(struct xgene_pmu_dev *pmu_dev, u32 val);
  100. void (*enable_counter)(struct xgene_pmu_dev *pmu_dev, int idx);
  101. void (*disable_counter)(struct xgene_pmu_dev *pmu_dev, int idx);
  102. void (*enable_counter_int)(struct xgene_pmu_dev *pmu_dev, int idx);
  103. void (*disable_counter_int)(struct xgene_pmu_dev *pmu_dev, int idx);
  104. void (*reset_counters)(struct xgene_pmu_dev *pmu_dev);
  105. void (*start_counters)(struct xgene_pmu_dev *pmu_dev);
  106. void (*stop_counters)(struct xgene_pmu_dev *pmu_dev);
  107. };
  108. struct xgene_pmu {
  109. struct device *dev;
  110. struct hlist_node node;
  111. int version;
  112. void __iomem *pcppmu_csr;
  113. u32 mcb_active_mask;
  114. u32 mc_active_mask;
  115. u32 l3c_active_mask;
  116. cpumask_t cpu;
  117. int irq;
  118. raw_spinlock_t lock;
  119. const struct xgene_pmu_ops *ops;
  120. struct list_head l3cpmus;
  121. struct list_head iobpmus;
  122. struct list_head mcbpmus;
  123. struct list_head mcpmus;
  124. };
  125. struct xgene_pmu_dev_ctx {
  126. char *name;
  127. struct list_head next;
  128. struct xgene_pmu_dev *pmu_dev;
  129. struct hw_pmu_info inf;
  130. };
  131. struct xgene_pmu_data {
  132. int id;
  133. u32 data;
  134. };
  135. enum xgene_pmu_version {
  136. PCP_PMU_V1 = 1,
  137. PCP_PMU_V2,
  138. PCP_PMU_V3,
  139. };
  140. enum xgene_pmu_dev_type {
  141. PMU_TYPE_L3C = 0,
  142. PMU_TYPE_IOB,
  143. PMU_TYPE_IOB_SLOW,
  144. PMU_TYPE_MCB,
  145. PMU_TYPE_MC,
  146. };
  147. /*
  148. * sysfs format attributes
  149. */
  150. static ssize_t xgene_pmu_format_show(struct device *dev,
  151. struct device_attribute *attr, char *buf)
  152. {
  153. struct dev_ext_attribute *eattr;
  154. eattr = container_of(attr, struct dev_ext_attribute, attr);
  155. return sprintf(buf, "%s\n", (char *) eattr->var);
  156. }
  157. #define XGENE_PMU_FORMAT_ATTR(_name, _config) \
  158. (&((struct dev_ext_attribute[]) { \
  159. { .attr = __ATTR(_name, S_IRUGO, xgene_pmu_format_show, NULL), \
  160. .var = (void *) _config, } \
  161. })[0].attr.attr)
  162. static struct attribute *l3c_pmu_format_attrs[] = {
  163. XGENE_PMU_FORMAT_ATTR(l3c_eventid, "config:0-7"),
  164. XGENE_PMU_FORMAT_ATTR(l3c_agentid, "config1:0-9"),
  165. NULL,
  166. };
  167. static struct attribute *iob_pmu_format_attrs[] = {
  168. XGENE_PMU_FORMAT_ATTR(iob_eventid, "config:0-7"),
  169. XGENE_PMU_FORMAT_ATTR(iob_agentid, "config1:0-63"),
  170. NULL,
  171. };
  172. static struct attribute *mcb_pmu_format_attrs[] = {
  173. XGENE_PMU_FORMAT_ATTR(mcb_eventid, "config:0-5"),
  174. XGENE_PMU_FORMAT_ATTR(mcb_agentid, "config1:0-9"),
  175. NULL,
  176. };
  177. static struct attribute *mc_pmu_format_attrs[] = {
  178. XGENE_PMU_FORMAT_ATTR(mc_eventid, "config:0-28"),
  179. NULL,
  180. };
  181. static const struct attribute_group l3c_pmu_format_attr_group = {
  182. .name = "format",
  183. .attrs = l3c_pmu_format_attrs,
  184. };
  185. static const struct attribute_group iob_pmu_format_attr_group = {
  186. .name = "format",
  187. .attrs = iob_pmu_format_attrs,
  188. };
  189. static const struct attribute_group mcb_pmu_format_attr_group = {
  190. .name = "format",
  191. .attrs = mcb_pmu_format_attrs,
  192. };
  193. static const struct attribute_group mc_pmu_format_attr_group = {
  194. .name = "format",
  195. .attrs = mc_pmu_format_attrs,
  196. };
  197. static struct attribute *l3c_pmu_v3_format_attrs[] = {
  198. XGENE_PMU_FORMAT_ATTR(l3c_eventid, "config:0-39"),
  199. NULL,
  200. };
  201. static struct attribute *iob_pmu_v3_format_attrs[] = {
  202. XGENE_PMU_FORMAT_ATTR(iob_eventid, "config:0-47"),
  203. NULL,
  204. };
  205. static struct attribute *iob_slow_pmu_v3_format_attrs[] = {
  206. XGENE_PMU_FORMAT_ATTR(iob_slow_eventid, "config:0-16"),
  207. NULL,
  208. };
  209. static struct attribute *mcb_pmu_v3_format_attrs[] = {
  210. XGENE_PMU_FORMAT_ATTR(mcb_eventid, "config:0-35"),
  211. NULL,
  212. };
  213. static struct attribute *mc_pmu_v3_format_attrs[] = {
  214. XGENE_PMU_FORMAT_ATTR(mc_eventid, "config:0-44"),
  215. NULL,
  216. };
  217. static const struct attribute_group l3c_pmu_v3_format_attr_group = {
  218. .name = "format",
  219. .attrs = l3c_pmu_v3_format_attrs,
  220. };
  221. static const struct attribute_group iob_pmu_v3_format_attr_group = {
  222. .name = "format",
  223. .attrs = iob_pmu_v3_format_attrs,
  224. };
  225. static const struct attribute_group iob_slow_pmu_v3_format_attr_group = {
  226. .name = "format",
  227. .attrs = iob_slow_pmu_v3_format_attrs,
  228. };
  229. static const struct attribute_group mcb_pmu_v3_format_attr_group = {
  230. .name = "format",
  231. .attrs = mcb_pmu_v3_format_attrs,
  232. };
  233. static const struct attribute_group mc_pmu_v3_format_attr_group = {
  234. .name = "format",
  235. .attrs = mc_pmu_v3_format_attrs,
  236. };
  237. /*
  238. * sysfs event attributes
  239. */
  240. static ssize_t xgene_pmu_event_show(struct device *dev,
  241. struct device_attribute *attr, char *buf)
  242. {
  243. struct dev_ext_attribute *eattr;
  244. eattr = container_of(attr, struct dev_ext_attribute, attr);
  245. return sprintf(buf, "config=0x%lx\n", (unsigned long) eattr->var);
  246. }
  247. #define XGENE_PMU_EVENT_ATTR(_name, _config) \
  248. (&((struct dev_ext_attribute[]) { \
  249. { .attr = __ATTR(_name, S_IRUGO, xgene_pmu_event_show, NULL), \
  250. .var = (void *) _config, } \
  251. })[0].attr.attr)
  252. static struct attribute *l3c_pmu_events_attrs[] = {
  253. XGENE_PMU_EVENT_ATTR(cycle-count, 0x00),
  254. XGENE_PMU_EVENT_ATTR(cycle-count-div-64, 0x01),
  255. XGENE_PMU_EVENT_ATTR(read-hit, 0x02),
  256. XGENE_PMU_EVENT_ATTR(read-miss, 0x03),
  257. XGENE_PMU_EVENT_ATTR(write-need-replacement, 0x06),
  258. XGENE_PMU_EVENT_ATTR(write-not-need-replacement, 0x07),
  259. XGENE_PMU_EVENT_ATTR(tq-full, 0x08),
  260. XGENE_PMU_EVENT_ATTR(ackq-full, 0x09),
  261. XGENE_PMU_EVENT_ATTR(wdb-full, 0x0a),
  262. XGENE_PMU_EVENT_ATTR(bank-fifo-full, 0x0b),
  263. XGENE_PMU_EVENT_ATTR(odb-full, 0x0c),
  264. XGENE_PMU_EVENT_ATTR(wbq-full, 0x0d),
  265. XGENE_PMU_EVENT_ATTR(bank-conflict-fifo-issue, 0x0e),
  266. XGENE_PMU_EVENT_ATTR(bank-fifo-issue, 0x0f),
  267. NULL,
  268. };
  269. static struct attribute *iob_pmu_events_attrs[] = {
  270. XGENE_PMU_EVENT_ATTR(cycle-count, 0x00),
  271. XGENE_PMU_EVENT_ATTR(cycle-count-div-64, 0x01),
  272. XGENE_PMU_EVENT_ATTR(axi0-read, 0x02),
  273. XGENE_PMU_EVENT_ATTR(axi0-read-partial, 0x03),
  274. XGENE_PMU_EVENT_ATTR(axi1-read, 0x04),
  275. XGENE_PMU_EVENT_ATTR(axi1-read-partial, 0x05),
  276. XGENE_PMU_EVENT_ATTR(csw-read-block, 0x06),
  277. XGENE_PMU_EVENT_ATTR(csw-read-partial, 0x07),
  278. XGENE_PMU_EVENT_ATTR(axi0-write, 0x10),
  279. XGENE_PMU_EVENT_ATTR(axi0-write-partial, 0x11),
  280. XGENE_PMU_EVENT_ATTR(axi1-write, 0x13),
  281. XGENE_PMU_EVENT_ATTR(axi1-write-partial, 0x14),
  282. XGENE_PMU_EVENT_ATTR(csw-inbound-dirty, 0x16),
  283. NULL,
  284. };
  285. static struct attribute *mcb_pmu_events_attrs[] = {
  286. XGENE_PMU_EVENT_ATTR(cycle-count, 0x00),
  287. XGENE_PMU_EVENT_ATTR(cycle-count-div-64, 0x01),
  288. XGENE_PMU_EVENT_ATTR(csw-read, 0x02),
  289. XGENE_PMU_EVENT_ATTR(csw-write-request, 0x03),
  290. XGENE_PMU_EVENT_ATTR(mcb-csw-stall, 0x04),
  291. XGENE_PMU_EVENT_ATTR(cancel-read-gack, 0x05),
  292. NULL,
  293. };
  294. static struct attribute *mc_pmu_events_attrs[] = {
  295. XGENE_PMU_EVENT_ATTR(cycle-count, 0x00),
  296. XGENE_PMU_EVENT_ATTR(cycle-count-div-64, 0x01),
  297. XGENE_PMU_EVENT_ATTR(act-cmd-sent, 0x02),
  298. XGENE_PMU_EVENT_ATTR(pre-cmd-sent, 0x03),
  299. XGENE_PMU_EVENT_ATTR(rd-cmd-sent, 0x04),
  300. XGENE_PMU_EVENT_ATTR(rda-cmd-sent, 0x05),
  301. XGENE_PMU_EVENT_ATTR(wr-cmd-sent, 0x06),
  302. XGENE_PMU_EVENT_ATTR(wra-cmd-sent, 0x07),
  303. XGENE_PMU_EVENT_ATTR(pde-cmd-sent, 0x08),
  304. XGENE_PMU_EVENT_ATTR(sre-cmd-sent, 0x09),
  305. XGENE_PMU_EVENT_ATTR(prea-cmd-sent, 0x0a),
  306. XGENE_PMU_EVENT_ATTR(ref-cmd-sent, 0x0b),
  307. XGENE_PMU_EVENT_ATTR(rd-rda-cmd-sent, 0x0c),
  308. XGENE_PMU_EVENT_ATTR(wr-wra-cmd-sent, 0x0d),
  309. XGENE_PMU_EVENT_ATTR(in-rd-collision, 0x0e),
  310. XGENE_PMU_EVENT_ATTR(in-wr-collision, 0x0f),
  311. XGENE_PMU_EVENT_ATTR(collision-queue-not-empty, 0x10),
  312. XGENE_PMU_EVENT_ATTR(collision-queue-full, 0x11),
  313. XGENE_PMU_EVENT_ATTR(mcu-request, 0x12),
  314. XGENE_PMU_EVENT_ATTR(mcu-rd-request, 0x13),
  315. XGENE_PMU_EVENT_ATTR(mcu-hp-rd-request, 0x14),
  316. XGENE_PMU_EVENT_ATTR(mcu-wr-request, 0x15),
  317. XGENE_PMU_EVENT_ATTR(mcu-rd-proceed-all, 0x16),
  318. XGENE_PMU_EVENT_ATTR(mcu-rd-proceed-cancel, 0x17),
  319. XGENE_PMU_EVENT_ATTR(mcu-rd-response, 0x18),
  320. XGENE_PMU_EVENT_ATTR(mcu-rd-proceed-speculative-all, 0x19),
  321. XGENE_PMU_EVENT_ATTR(mcu-rd-proceed-speculative-cancel, 0x1a),
  322. XGENE_PMU_EVENT_ATTR(mcu-wr-proceed-all, 0x1b),
  323. XGENE_PMU_EVENT_ATTR(mcu-wr-proceed-cancel, 0x1c),
  324. NULL,
  325. };
  326. static const struct attribute_group l3c_pmu_events_attr_group = {
  327. .name = "events",
  328. .attrs = l3c_pmu_events_attrs,
  329. };
  330. static const struct attribute_group iob_pmu_events_attr_group = {
  331. .name = "events",
  332. .attrs = iob_pmu_events_attrs,
  333. };
  334. static const struct attribute_group mcb_pmu_events_attr_group = {
  335. .name = "events",
  336. .attrs = mcb_pmu_events_attrs,
  337. };
  338. static const struct attribute_group mc_pmu_events_attr_group = {
  339. .name = "events",
  340. .attrs = mc_pmu_events_attrs,
  341. };
  342. static struct attribute *l3c_pmu_v3_events_attrs[] = {
  343. XGENE_PMU_EVENT_ATTR(cycle-count, 0x00),
  344. XGENE_PMU_EVENT_ATTR(read-hit, 0x01),
  345. XGENE_PMU_EVENT_ATTR(read-miss, 0x02),
  346. XGENE_PMU_EVENT_ATTR(index-flush-eviction, 0x03),
  347. XGENE_PMU_EVENT_ATTR(write-caused-replacement, 0x04),
  348. XGENE_PMU_EVENT_ATTR(write-not-caused-replacement, 0x05),
  349. XGENE_PMU_EVENT_ATTR(clean-eviction, 0x06),
  350. XGENE_PMU_EVENT_ATTR(dirty-eviction, 0x07),
  351. XGENE_PMU_EVENT_ATTR(read, 0x08),
  352. XGENE_PMU_EVENT_ATTR(write, 0x09),
  353. XGENE_PMU_EVENT_ATTR(request, 0x0a),
  354. XGENE_PMU_EVENT_ATTR(tq-bank-conflict-issue-stall, 0x0b),
  355. XGENE_PMU_EVENT_ATTR(tq-full, 0x0c),
  356. XGENE_PMU_EVENT_ATTR(ackq-full, 0x0d),
  357. XGENE_PMU_EVENT_ATTR(wdb-full, 0x0e),
  358. XGENE_PMU_EVENT_ATTR(odb-full, 0x10),
  359. XGENE_PMU_EVENT_ATTR(wbq-full, 0x11),
  360. XGENE_PMU_EVENT_ATTR(input-req-async-fifo-stall, 0x12),
  361. XGENE_PMU_EVENT_ATTR(output-req-async-fifo-stall, 0x13),
  362. XGENE_PMU_EVENT_ATTR(output-data-async-fifo-stall, 0x14),
  363. XGENE_PMU_EVENT_ATTR(total-insertion, 0x15),
  364. XGENE_PMU_EVENT_ATTR(sip-insertions-r-set, 0x16),
  365. XGENE_PMU_EVENT_ATTR(sip-insertions-r-clear, 0x17),
  366. XGENE_PMU_EVENT_ATTR(dip-insertions-r-set, 0x18),
  367. XGENE_PMU_EVENT_ATTR(dip-insertions-r-clear, 0x19),
  368. XGENE_PMU_EVENT_ATTR(dip-insertions-force-r-set, 0x1a),
  369. XGENE_PMU_EVENT_ATTR(egression, 0x1b),
  370. XGENE_PMU_EVENT_ATTR(replacement, 0x1c),
  371. XGENE_PMU_EVENT_ATTR(old-replacement, 0x1d),
  372. XGENE_PMU_EVENT_ATTR(young-replacement, 0x1e),
  373. XGENE_PMU_EVENT_ATTR(r-set-replacement, 0x1f),
  374. XGENE_PMU_EVENT_ATTR(r-clear-replacement, 0x20),
  375. XGENE_PMU_EVENT_ATTR(old-r-replacement, 0x21),
  376. XGENE_PMU_EVENT_ATTR(old-nr-replacement, 0x22),
  377. XGENE_PMU_EVENT_ATTR(young-r-replacement, 0x23),
  378. XGENE_PMU_EVENT_ATTR(young-nr-replacement, 0x24),
  379. XGENE_PMU_EVENT_ATTR(bloomfilter-clearing, 0x25),
  380. XGENE_PMU_EVENT_ATTR(generation-flip, 0x26),
  381. XGENE_PMU_EVENT_ATTR(vcc-droop-detected, 0x27),
  382. NULL,
  383. };
  384. static struct attribute *iob_fast_pmu_v3_events_attrs[] = {
  385. XGENE_PMU_EVENT_ATTR(cycle-count, 0x00),
  386. XGENE_PMU_EVENT_ATTR(pa-req-buf-alloc-all, 0x01),
  387. XGENE_PMU_EVENT_ATTR(pa-req-buf-alloc-rd, 0x02),
  388. XGENE_PMU_EVENT_ATTR(pa-req-buf-alloc-wr, 0x03),
  389. XGENE_PMU_EVENT_ATTR(pa-all-cp-req, 0x04),
  390. XGENE_PMU_EVENT_ATTR(pa-cp-blk-req, 0x05),
  391. XGENE_PMU_EVENT_ATTR(pa-cp-ptl-req, 0x06),
  392. XGENE_PMU_EVENT_ATTR(pa-cp-rd-req, 0x07),
  393. XGENE_PMU_EVENT_ATTR(pa-cp-wr-req, 0x08),
  394. XGENE_PMU_EVENT_ATTR(ba-all-req, 0x09),
  395. XGENE_PMU_EVENT_ATTR(ba-rd-req, 0x0a),
  396. XGENE_PMU_EVENT_ATTR(ba-wr-req, 0x0b),
  397. XGENE_PMU_EVENT_ATTR(pa-rd-shared-req-issued, 0x10),
  398. XGENE_PMU_EVENT_ATTR(pa-rd-exclusive-req-issued, 0x11),
  399. XGENE_PMU_EVENT_ATTR(pa-wr-invalidate-req-issued-stashable, 0x12),
  400. XGENE_PMU_EVENT_ATTR(pa-wr-invalidate-req-issued-nonstashable, 0x13),
  401. XGENE_PMU_EVENT_ATTR(pa-wr-back-req-issued-stashable, 0x14),
  402. XGENE_PMU_EVENT_ATTR(pa-wr-back-req-issued-nonstashable, 0x15),
  403. XGENE_PMU_EVENT_ATTR(pa-ptl-wr-req, 0x16),
  404. XGENE_PMU_EVENT_ATTR(pa-ptl-rd-req, 0x17),
  405. XGENE_PMU_EVENT_ATTR(pa-wr-back-clean-data, 0x18),
  406. XGENE_PMU_EVENT_ATTR(pa-wr-back-cancelled-on-SS, 0x1b),
  407. XGENE_PMU_EVENT_ATTR(pa-barrier-occurrence, 0x1c),
  408. XGENE_PMU_EVENT_ATTR(pa-barrier-cycles, 0x1d),
  409. XGENE_PMU_EVENT_ATTR(pa-total-cp-snoops, 0x20),
  410. XGENE_PMU_EVENT_ATTR(pa-rd-shared-snoop, 0x21),
  411. XGENE_PMU_EVENT_ATTR(pa-rd-shared-snoop-hit, 0x22),
  412. XGENE_PMU_EVENT_ATTR(pa-rd-exclusive-snoop, 0x23),
  413. XGENE_PMU_EVENT_ATTR(pa-rd-exclusive-snoop-hit, 0x24),
  414. XGENE_PMU_EVENT_ATTR(pa-rd-wr-invalid-snoop, 0x25),
  415. XGENE_PMU_EVENT_ATTR(pa-rd-wr-invalid-snoop-hit, 0x26),
  416. XGENE_PMU_EVENT_ATTR(pa-req-buffer-full, 0x28),
  417. XGENE_PMU_EVENT_ATTR(cswlf-outbound-req-fifo-full, 0x29),
  418. XGENE_PMU_EVENT_ATTR(cswlf-inbound-snoop-fifo-backpressure, 0x2a),
  419. XGENE_PMU_EVENT_ATTR(cswlf-outbound-lack-fifo-full, 0x2b),
  420. XGENE_PMU_EVENT_ATTR(cswlf-inbound-gack-fifo-backpressure, 0x2c),
  421. XGENE_PMU_EVENT_ATTR(cswlf-outbound-data-fifo-full, 0x2d),
  422. XGENE_PMU_EVENT_ATTR(cswlf-inbound-data-fifo-backpressure, 0x2e),
  423. XGENE_PMU_EVENT_ATTR(cswlf-inbound-req-backpressure, 0x2f),
  424. NULL,
  425. };
  426. static struct attribute *iob_slow_pmu_v3_events_attrs[] = {
  427. XGENE_PMU_EVENT_ATTR(cycle-count, 0x00),
  428. XGENE_PMU_EVENT_ATTR(pa-axi0-rd-req, 0x01),
  429. XGENE_PMU_EVENT_ATTR(pa-axi0-wr-req, 0x02),
  430. XGENE_PMU_EVENT_ATTR(pa-axi1-rd-req, 0x03),
  431. XGENE_PMU_EVENT_ATTR(pa-axi1-wr-req, 0x04),
  432. XGENE_PMU_EVENT_ATTR(ba-all-axi-req, 0x07),
  433. XGENE_PMU_EVENT_ATTR(ba-axi-rd-req, 0x08),
  434. XGENE_PMU_EVENT_ATTR(ba-axi-wr-req, 0x09),
  435. XGENE_PMU_EVENT_ATTR(ba-free-list-empty, 0x10),
  436. NULL,
  437. };
  438. static struct attribute *mcb_pmu_v3_events_attrs[] = {
  439. XGENE_PMU_EVENT_ATTR(cycle-count, 0x00),
  440. XGENE_PMU_EVENT_ATTR(req-receive, 0x01),
  441. XGENE_PMU_EVENT_ATTR(rd-req-recv, 0x02),
  442. XGENE_PMU_EVENT_ATTR(rd-req-recv-2, 0x03),
  443. XGENE_PMU_EVENT_ATTR(wr-req-recv, 0x04),
  444. XGENE_PMU_EVENT_ATTR(wr-req-recv-2, 0x05),
  445. XGENE_PMU_EVENT_ATTR(rd-req-sent-to-mcu, 0x06),
  446. XGENE_PMU_EVENT_ATTR(rd-req-sent-to-mcu-2, 0x07),
  447. XGENE_PMU_EVENT_ATTR(rd-req-sent-to-spec-mcu, 0x08),
  448. XGENE_PMU_EVENT_ATTR(rd-req-sent-to-spec-mcu-2, 0x09),
  449. XGENE_PMU_EVENT_ATTR(glbl-ack-recv-for-rd-sent-to-spec-mcu, 0x0a),
  450. XGENE_PMU_EVENT_ATTR(glbl-ack-go-recv-for-rd-sent-to-spec-mcu, 0x0b),
  451. XGENE_PMU_EVENT_ATTR(glbl-ack-nogo-recv-for-rd-sent-to-spec-mcu, 0x0c),
  452. XGENE_PMU_EVENT_ATTR(glbl-ack-go-recv-any-rd-req, 0x0d),
  453. XGENE_PMU_EVENT_ATTR(glbl-ack-go-recv-any-rd-req-2, 0x0e),
  454. XGENE_PMU_EVENT_ATTR(wr-req-sent-to-mcu, 0x0f),
  455. XGENE_PMU_EVENT_ATTR(gack-recv, 0x10),
  456. XGENE_PMU_EVENT_ATTR(rd-gack-recv, 0x11),
  457. XGENE_PMU_EVENT_ATTR(wr-gack-recv, 0x12),
  458. XGENE_PMU_EVENT_ATTR(cancel-rd-gack, 0x13),
  459. XGENE_PMU_EVENT_ATTR(cancel-wr-gack, 0x14),
  460. XGENE_PMU_EVENT_ATTR(mcb-csw-req-stall, 0x15),
  461. XGENE_PMU_EVENT_ATTR(mcu-req-intf-blocked, 0x16),
  462. XGENE_PMU_EVENT_ATTR(mcb-mcu-rd-intf-stall, 0x17),
  463. XGENE_PMU_EVENT_ATTR(csw-rd-intf-blocked, 0x18),
  464. XGENE_PMU_EVENT_ATTR(csw-local-ack-intf-blocked, 0x19),
  465. XGENE_PMU_EVENT_ATTR(mcu-req-table-full, 0x1a),
  466. XGENE_PMU_EVENT_ATTR(mcu-stat-table-full, 0x1b),
  467. XGENE_PMU_EVENT_ATTR(mcu-wr-table-full, 0x1c),
  468. XGENE_PMU_EVENT_ATTR(mcu-rdreceipt-resp, 0x1d),
  469. XGENE_PMU_EVENT_ATTR(mcu-wrcomplete-resp, 0x1e),
  470. XGENE_PMU_EVENT_ATTR(mcu-retryack-resp, 0x1f),
  471. XGENE_PMU_EVENT_ATTR(mcu-pcrdgrant-resp, 0x20),
  472. XGENE_PMU_EVENT_ATTR(mcu-req-from-lastload, 0x21),
  473. XGENE_PMU_EVENT_ATTR(mcu-req-from-bypass, 0x22),
  474. XGENE_PMU_EVENT_ATTR(volt-droop-detect, 0x23),
  475. NULL,
  476. };
  477. static struct attribute *mc_pmu_v3_events_attrs[] = {
  478. XGENE_PMU_EVENT_ATTR(cycle-count, 0x00),
  479. XGENE_PMU_EVENT_ATTR(act-sent, 0x01),
  480. XGENE_PMU_EVENT_ATTR(pre-sent, 0x02),
  481. XGENE_PMU_EVENT_ATTR(rd-sent, 0x03),
  482. XGENE_PMU_EVENT_ATTR(rda-sent, 0x04),
  483. XGENE_PMU_EVENT_ATTR(wr-sent, 0x05),
  484. XGENE_PMU_EVENT_ATTR(wra-sent, 0x06),
  485. XGENE_PMU_EVENT_ATTR(pd-entry-vld, 0x07),
  486. XGENE_PMU_EVENT_ATTR(sref-entry-vld, 0x08),
  487. XGENE_PMU_EVENT_ATTR(prea-sent, 0x09),
  488. XGENE_PMU_EVENT_ATTR(ref-sent, 0x0a),
  489. XGENE_PMU_EVENT_ATTR(rd-rda-sent, 0x0b),
  490. XGENE_PMU_EVENT_ATTR(wr-wra-sent, 0x0c),
  491. XGENE_PMU_EVENT_ATTR(raw-hazard, 0x0d),
  492. XGENE_PMU_EVENT_ATTR(war-hazard, 0x0e),
  493. XGENE_PMU_EVENT_ATTR(waw-hazard, 0x0f),
  494. XGENE_PMU_EVENT_ATTR(rar-hazard, 0x10),
  495. XGENE_PMU_EVENT_ATTR(raw-war-waw-hazard, 0x11),
  496. XGENE_PMU_EVENT_ATTR(hprd-lprd-wr-req-vld, 0x12),
  497. XGENE_PMU_EVENT_ATTR(lprd-req-vld, 0x13),
  498. XGENE_PMU_EVENT_ATTR(hprd-req-vld, 0x14),
  499. XGENE_PMU_EVENT_ATTR(hprd-lprd-req-vld, 0x15),
  500. XGENE_PMU_EVENT_ATTR(wr-req-vld, 0x16),
  501. XGENE_PMU_EVENT_ATTR(partial-wr-req-vld, 0x17),
  502. XGENE_PMU_EVENT_ATTR(rd-retry, 0x18),
  503. XGENE_PMU_EVENT_ATTR(wr-retry, 0x19),
  504. XGENE_PMU_EVENT_ATTR(retry-gnt, 0x1a),
  505. XGENE_PMU_EVENT_ATTR(rank-change, 0x1b),
  506. XGENE_PMU_EVENT_ATTR(dir-change, 0x1c),
  507. XGENE_PMU_EVENT_ATTR(rank-dir-change, 0x1d),
  508. XGENE_PMU_EVENT_ATTR(rank-active, 0x1e),
  509. XGENE_PMU_EVENT_ATTR(rank-idle, 0x1f),
  510. XGENE_PMU_EVENT_ATTR(rank-pd, 0x20),
  511. XGENE_PMU_EVENT_ATTR(rank-sref, 0x21),
  512. XGENE_PMU_EVENT_ATTR(queue-fill-gt-thresh, 0x22),
  513. XGENE_PMU_EVENT_ATTR(queue-rds-gt-thresh, 0x23),
  514. XGENE_PMU_EVENT_ATTR(queue-wrs-gt-thresh, 0x24),
  515. XGENE_PMU_EVENT_ATTR(phy-updt-complt, 0x25),
  516. XGENE_PMU_EVENT_ATTR(tz-fail, 0x26),
  517. XGENE_PMU_EVENT_ATTR(dram-errc, 0x27),
  518. XGENE_PMU_EVENT_ATTR(dram-errd, 0x28),
  519. XGENE_PMU_EVENT_ATTR(rd-enq, 0x29),
  520. XGENE_PMU_EVENT_ATTR(wr-enq, 0x2a),
  521. XGENE_PMU_EVENT_ATTR(tmac-limit-reached, 0x2b),
  522. XGENE_PMU_EVENT_ATTR(tmaw-tracker-full, 0x2c),
  523. NULL,
  524. };
  525. static const struct attribute_group l3c_pmu_v3_events_attr_group = {
  526. .name = "events",
  527. .attrs = l3c_pmu_v3_events_attrs,
  528. };
  529. static const struct attribute_group iob_fast_pmu_v3_events_attr_group = {
  530. .name = "events",
  531. .attrs = iob_fast_pmu_v3_events_attrs,
  532. };
  533. static const struct attribute_group iob_slow_pmu_v3_events_attr_group = {
  534. .name = "events",
  535. .attrs = iob_slow_pmu_v3_events_attrs,
  536. };
  537. static const struct attribute_group mcb_pmu_v3_events_attr_group = {
  538. .name = "events",
  539. .attrs = mcb_pmu_v3_events_attrs,
  540. };
  541. static const struct attribute_group mc_pmu_v3_events_attr_group = {
  542. .name = "events",
  543. .attrs = mc_pmu_v3_events_attrs,
  544. };
  545. /*
  546. * sysfs cpumask attributes
  547. */
  548. static ssize_t xgene_pmu_cpumask_show(struct device *dev,
  549. struct device_attribute *attr, char *buf)
  550. {
  551. struct xgene_pmu_dev *pmu_dev = to_pmu_dev(dev_get_drvdata(dev));
  552. return cpumap_print_to_pagebuf(true, buf, &pmu_dev->parent->cpu);
  553. }
  554. static DEVICE_ATTR(cpumask, S_IRUGO, xgene_pmu_cpumask_show, NULL);
  555. static struct attribute *xgene_pmu_cpumask_attrs[] = {
  556. &dev_attr_cpumask.attr,
  557. NULL,
  558. };
  559. static const struct attribute_group pmu_cpumask_attr_group = {
  560. .attrs = xgene_pmu_cpumask_attrs,
  561. };
  562. /*
  563. * Per PMU device attribute groups of PMU v1 and v2
  564. */
  565. static const struct attribute_group *l3c_pmu_attr_groups[] = {
  566. &l3c_pmu_format_attr_group,
  567. &pmu_cpumask_attr_group,
  568. &l3c_pmu_events_attr_group,
  569. NULL
  570. };
  571. static const struct attribute_group *iob_pmu_attr_groups[] = {
  572. &iob_pmu_format_attr_group,
  573. &pmu_cpumask_attr_group,
  574. &iob_pmu_events_attr_group,
  575. NULL
  576. };
  577. static const struct attribute_group *mcb_pmu_attr_groups[] = {
  578. &mcb_pmu_format_attr_group,
  579. &pmu_cpumask_attr_group,
  580. &mcb_pmu_events_attr_group,
  581. NULL
  582. };
  583. static const struct attribute_group *mc_pmu_attr_groups[] = {
  584. &mc_pmu_format_attr_group,
  585. &pmu_cpumask_attr_group,
  586. &mc_pmu_events_attr_group,
  587. NULL
  588. };
  589. /*
  590. * Per PMU device attribute groups of PMU v3
  591. */
  592. static const struct attribute_group *l3c_pmu_v3_attr_groups[] = {
  593. &l3c_pmu_v3_format_attr_group,
  594. &pmu_cpumask_attr_group,
  595. &l3c_pmu_v3_events_attr_group,
  596. NULL
  597. };
  598. static const struct attribute_group *iob_fast_pmu_v3_attr_groups[] = {
  599. &iob_pmu_v3_format_attr_group,
  600. &pmu_cpumask_attr_group,
  601. &iob_fast_pmu_v3_events_attr_group,
  602. NULL
  603. };
  604. static const struct attribute_group *iob_slow_pmu_v3_attr_groups[] = {
  605. &iob_slow_pmu_v3_format_attr_group,
  606. &pmu_cpumask_attr_group,
  607. &iob_slow_pmu_v3_events_attr_group,
  608. NULL
  609. };
  610. static const struct attribute_group *mcb_pmu_v3_attr_groups[] = {
  611. &mcb_pmu_v3_format_attr_group,
  612. &pmu_cpumask_attr_group,
  613. &mcb_pmu_v3_events_attr_group,
  614. NULL
  615. };
  616. static const struct attribute_group *mc_pmu_v3_attr_groups[] = {
  617. &mc_pmu_v3_format_attr_group,
  618. &pmu_cpumask_attr_group,
  619. &mc_pmu_v3_events_attr_group,
  620. NULL
  621. };
  622. static int get_next_avail_cntr(struct xgene_pmu_dev *pmu_dev)
  623. {
  624. int cntr;
  625. cntr = find_first_zero_bit(pmu_dev->cntr_assign_mask,
  626. pmu_dev->max_counters);
  627. if (cntr == pmu_dev->max_counters)
  628. return -ENOSPC;
  629. set_bit(cntr, pmu_dev->cntr_assign_mask);
  630. return cntr;
  631. }
  632. static void clear_avail_cntr(struct xgene_pmu_dev *pmu_dev, int cntr)
  633. {
  634. clear_bit(cntr, pmu_dev->cntr_assign_mask);
  635. }
  636. static inline void xgene_pmu_mask_int(struct xgene_pmu *xgene_pmu)
  637. {
  638. writel(PCPPMU_INTENMASK, xgene_pmu->pcppmu_csr + PCPPMU_INTMASK_REG);
  639. }
  640. static inline void xgene_pmu_v3_mask_int(struct xgene_pmu *xgene_pmu)
  641. {
  642. writel(PCPPMU_V3_INTENMASK, xgene_pmu->pcppmu_csr + PCPPMU_INTMASK_REG);
  643. }
  644. static inline void xgene_pmu_unmask_int(struct xgene_pmu *xgene_pmu)
  645. {
  646. writel(PCPPMU_INTCLRMASK, xgene_pmu->pcppmu_csr + PCPPMU_INTMASK_REG);
  647. }
  648. static inline void xgene_pmu_v3_unmask_int(struct xgene_pmu *xgene_pmu)
  649. {
  650. writel(PCPPMU_V3_INTCLRMASK,
  651. xgene_pmu->pcppmu_csr + PCPPMU_INTMASK_REG);
  652. }
  653. static inline u64 xgene_pmu_read_counter32(struct xgene_pmu_dev *pmu_dev,
  654. int idx)
  655. {
  656. return readl(pmu_dev->inf->csr + PMU_PMEVCNTR0 + (4 * idx));
  657. }
  658. static inline u64 xgene_pmu_read_counter64(struct xgene_pmu_dev *pmu_dev,
  659. int idx)
  660. {
  661. u32 lo, hi;
  662. /*
  663. * v3 has 64-bit counter registers composed by 2 32-bit registers
  664. * This can be a problem if the counter increases and carries
  665. * out of bit [31] between 2 reads. The extra reads would help
  666. * to prevent this issue.
  667. */
  668. do {
  669. hi = xgene_pmu_read_counter32(pmu_dev, 2 * idx + 1);
  670. lo = xgene_pmu_read_counter32(pmu_dev, 2 * idx);
  671. } while (hi != xgene_pmu_read_counter32(pmu_dev, 2 * idx + 1));
  672. return (((u64)hi << 32) | lo);
  673. }
  674. static inline void
  675. xgene_pmu_write_counter32(struct xgene_pmu_dev *pmu_dev, int idx, u64 val)
  676. {
  677. writel(val, pmu_dev->inf->csr + PMU_PMEVCNTR0 + (4 * idx));
  678. }
  679. static inline void
  680. xgene_pmu_write_counter64(struct xgene_pmu_dev *pmu_dev, int idx, u64 val)
  681. {
  682. u32 cnt_lo, cnt_hi;
  683. cnt_hi = upper_32_bits(val);
  684. cnt_lo = lower_32_bits(val);
  685. /* v3 has 64-bit counter registers composed by 2 32-bit registers */
  686. xgene_pmu_write_counter32(pmu_dev, 2 * idx, cnt_lo);
  687. xgene_pmu_write_counter32(pmu_dev, 2 * idx + 1, cnt_hi);
  688. }
  689. static inline void
  690. xgene_pmu_write_evttype(struct xgene_pmu_dev *pmu_dev, int idx, u32 val)
  691. {
  692. writel(val, pmu_dev->inf->csr + PMU_PMEVTYPER0 + (4 * idx));
  693. }
  694. static inline void
  695. xgene_pmu_write_agentmsk(struct xgene_pmu_dev *pmu_dev, u32 val)
  696. {
  697. writel(val, pmu_dev->inf->csr + PMU_PMAMR0);
  698. }
  699. static inline void
  700. xgene_pmu_v3_write_agentmsk(struct xgene_pmu_dev *pmu_dev, u32 val) { }
  701. static inline void
  702. xgene_pmu_write_agent1msk(struct xgene_pmu_dev *pmu_dev, u32 val)
  703. {
  704. writel(val, pmu_dev->inf->csr + PMU_PMAMR1);
  705. }
  706. static inline void
  707. xgene_pmu_v3_write_agent1msk(struct xgene_pmu_dev *pmu_dev, u32 val) { }
  708. static inline void
  709. xgene_pmu_enable_counter(struct xgene_pmu_dev *pmu_dev, int idx)
  710. {
  711. u32 val;
  712. val = readl(pmu_dev->inf->csr + PMU_PMCNTENSET);
  713. val |= 1 << idx;
  714. writel(val, pmu_dev->inf->csr + PMU_PMCNTENSET);
  715. }
  716. static inline void
  717. xgene_pmu_disable_counter(struct xgene_pmu_dev *pmu_dev, int idx)
  718. {
  719. u32 val;
  720. val = readl(pmu_dev->inf->csr + PMU_PMCNTENCLR);
  721. val |= 1 << idx;
  722. writel(val, pmu_dev->inf->csr + PMU_PMCNTENCLR);
  723. }
  724. static inline void
  725. xgene_pmu_enable_counter_int(struct xgene_pmu_dev *pmu_dev, int idx)
  726. {
  727. u32 val;
  728. val = readl(pmu_dev->inf->csr + PMU_PMINTENSET);
  729. val |= 1 << idx;
  730. writel(val, pmu_dev->inf->csr + PMU_PMINTENSET);
  731. }
  732. static inline void
  733. xgene_pmu_disable_counter_int(struct xgene_pmu_dev *pmu_dev, int idx)
  734. {
  735. u32 val;
  736. val = readl(pmu_dev->inf->csr + PMU_PMINTENCLR);
  737. val |= 1 << idx;
  738. writel(val, pmu_dev->inf->csr + PMU_PMINTENCLR);
  739. }
  740. static inline void xgene_pmu_reset_counters(struct xgene_pmu_dev *pmu_dev)
  741. {
  742. u32 val;
  743. val = readl(pmu_dev->inf->csr + PMU_PMCR);
  744. val |= PMU_PMCR_P;
  745. writel(val, pmu_dev->inf->csr + PMU_PMCR);
  746. }
  747. static inline void xgene_pmu_start_counters(struct xgene_pmu_dev *pmu_dev)
  748. {
  749. u32 val;
  750. val = readl(pmu_dev->inf->csr + PMU_PMCR);
  751. val |= PMU_PMCR_E;
  752. writel(val, pmu_dev->inf->csr + PMU_PMCR);
  753. }
  754. static inline void xgene_pmu_stop_counters(struct xgene_pmu_dev *pmu_dev)
  755. {
  756. u32 val;
  757. val = readl(pmu_dev->inf->csr + PMU_PMCR);
  758. val &= ~PMU_PMCR_E;
  759. writel(val, pmu_dev->inf->csr + PMU_PMCR);
  760. }
  761. static void xgene_perf_pmu_enable(struct pmu *pmu)
  762. {
  763. struct xgene_pmu_dev *pmu_dev = to_pmu_dev(pmu);
  764. struct xgene_pmu *xgene_pmu = pmu_dev->parent;
  765. int enabled = bitmap_weight(pmu_dev->cntr_assign_mask,
  766. pmu_dev->max_counters);
  767. if (!enabled)
  768. return;
  769. xgene_pmu->ops->start_counters(pmu_dev);
  770. }
  771. static void xgene_perf_pmu_disable(struct pmu *pmu)
  772. {
  773. struct xgene_pmu_dev *pmu_dev = to_pmu_dev(pmu);
  774. struct xgene_pmu *xgene_pmu = pmu_dev->parent;
  775. xgene_pmu->ops->stop_counters(pmu_dev);
  776. }
  777. static int xgene_perf_event_init(struct perf_event *event)
  778. {
  779. struct xgene_pmu_dev *pmu_dev = to_pmu_dev(event->pmu);
  780. struct hw_perf_event *hw = &event->hw;
  781. struct perf_event *sibling;
  782. /* Test the event attr type check for PMU enumeration */
  783. if (event->attr.type != event->pmu->type)
  784. return -ENOENT;
  785. /*
  786. * SOC PMU counters are shared across all cores.
  787. * Therefore, it does not support per-process mode.
  788. * Also, it does not support event sampling mode.
  789. */
  790. if (is_sampling_event(event) || event->attach_state & PERF_ATTACH_TASK)
  791. return -EINVAL;
  792. if (event->cpu < 0)
  793. return -EINVAL;
  794. /*
  795. * Many perf core operations (eg. events rotation) operate on a
  796. * single CPU context. This is obvious for CPU PMUs, where one
  797. * expects the same sets of events being observed on all CPUs,
  798. * but can lead to issues for off-core PMUs, where each
  799. * event could be theoretically assigned to a different CPU. To
  800. * mitigate this, we enforce CPU assignment to one, selected
  801. * processor (the one described in the "cpumask" attribute).
  802. */
  803. event->cpu = cpumask_first(&pmu_dev->parent->cpu);
  804. hw->config = event->attr.config;
  805. /*
  806. * Each bit of the config1 field represents an agent from which the
  807. * request of the event come. The event is counted only if it's caused
  808. * by a request of an agent has the bit cleared.
  809. * By default, the event is counted for all agents.
  810. */
  811. hw->config_base = event->attr.config1;
  812. /*
  813. * We must NOT create groups containing mixed PMUs, although software
  814. * events are acceptable
  815. */
  816. if (event->group_leader->pmu != event->pmu &&
  817. !is_software_event(event->group_leader))
  818. return -EINVAL;
  819. for_each_sibling_event(sibling, event->group_leader) {
  820. if (sibling->pmu != event->pmu &&
  821. !is_software_event(sibling))
  822. return -EINVAL;
  823. }
  824. return 0;
  825. }
  826. static void xgene_perf_enable_event(struct perf_event *event)
  827. {
  828. struct xgene_pmu_dev *pmu_dev = to_pmu_dev(event->pmu);
  829. struct xgene_pmu *xgene_pmu = pmu_dev->parent;
  830. xgene_pmu->ops->write_evttype(pmu_dev, GET_CNTR(event),
  831. GET_EVENTID(event));
  832. xgene_pmu->ops->write_agentmsk(pmu_dev, ~((u32)GET_AGENTID(event)));
  833. if (pmu_dev->inf->type == PMU_TYPE_IOB)
  834. xgene_pmu->ops->write_agent1msk(pmu_dev,
  835. ~((u32)GET_AGENT1ID(event)));
  836. xgene_pmu->ops->enable_counter(pmu_dev, GET_CNTR(event));
  837. xgene_pmu->ops->enable_counter_int(pmu_dev, GET_CNTR(event));
  838. }
  839. static void xgene_perf_disable_event(struct perf_event *event)
  840. {
  841. struct xgene_pmu_dev *pmu_dev = to_pmu_dev(event->pmu);
  842. struct xgene_pmu *xgene_pmu = pmu_dev->parent;
  843. xgene_pmu->ops->disable_counter(pmu_dev, GET_CNTR(event));
  844. xgene_pmu->ops->disable_counter_int(pmu_dev, GET_CNTR(event));
  845. }
  846. static void xgene_perf_event_set_period(struct perf_event *event)
  847. {
  848. struct xgene_pmu_dev *pmu_dev = to_pmu_dev(event->pmu);
  849. struct xgene_pmu *xgene_pmu = pmu_dev->parent;
  850. struct hw_perf_event *hw = &event->hw;
  851. /*
  852. * For 32 bit counter, it has a period of 2^32. To account for the
  853. * possibility of extreme interrupt latency we program for a period of
  854. * half that. Hopefully, we can handle the interrupt before another 2^31
  855. * events occur and the counter overtakes its previous value.
  856. * For 64 bit counter, we don't expect it overflow.
  857. */
  858. u64 val = 1ULL << 31;
  859. local64_set(&hw->prev_count, val);
  860. xgene_pmu->ops->write_counter(pmu_dev, hw->idx, val);
  861. }
  862. static void xgene_perf_event_update(struct perf_event *event)
  863. {
  864. struct xgene_pmu_dev *pmu_dev = to_pmu_dev(event->pmu);
  865. struct xgene_pmu *xgene_pmu = pmu_dev->parent;
  866. struct hw_perf_event *hw = &event->hw;
  867. u64 delta, prev_raw_count, new_raw_count;
  868. again:
  869. prev_raw_count = local64_read(&hw->prev_count);
  870. new_raw_count = xgene_pmu->ops->read_counter(pmu_dev, GET_CNTR(event));
  871. if (local64_cmpxchg(&hw->prev_count, prev_raw_count,
  872. new_raw_count) != prev_raw_count)
  873. goto again;
  874. delta = (new_raw_count - prev_raw_count) & pmu_dev->max_period;
  875. local64_add(delta, &event->count);
  876. }
  877. static void xgene_perf_read(struct perf_event *event)
  878. {
  879. xgene_perf_event_update(event);
  880. }
  881. static void xgene_perf_start(struct perf_event *event, int flags)
  882. {
  883. struct xgene_pmu_dev *pmu_dev = to_pmu_dev(event->pmu);
  884. struct xgene_pmu *xgene_pmu = pmu_dev->parent;
  885. struct hw_perf_event *hw = &event->hw;
  886. if (WARN_ON_ONCE(!(hw->state & PERF_HES_STOPPED)))
  887. return;
  888. WARN_ON_ONCE(!(hw->state & PERF_HES_UPTODATE));
  889. hw->state = 0;
  890. xgene_perf_event_set_period(event);
  891. if (flags & PERF_EF_RELOAD) {
  892. u64 prev_raw_count = local64_read(&hw->prev_count);
  893. xgene_pmu->ops->write_counter(pmu_dev, GET_CNTR(event),
  894. prev_raw_count);
  895. }
  896. xgene_perf_enable_event(event);
  897. perf_event_update_userpage(event);
  898. }
  899. static void xgene_perf_stop(struct perf_event *event, int flags)
  900. {
  901. struct hw_perf_event *hw = &event->hw;
  902. if (hw->state & PERF_HES_UPTODATE)
  903. return;
  904. xgene_perf_disable_event(event);
  905. WARN_ON_ONCE(hw->state & PERF_HES_STOPPED);
  906. hw->state |= PERF_HES_STOPPED;
  907. if (hw->state & PERF_HES_UPTODATE)
  908. return;
  909. xgene_perf_read(event);
  910. hw->state |= PERF_HES_UPTODATE;
  911. }
  912. static int xgene_perf_add(struct perf_event *event, int flags)
  913. {
  914. struct xgene_pmu_dev *pmu_dev = to_pmu_dev(event->pmu);
  915. struct hw_perf_event *hw = &event->hw;
  916. hw->state = PERF_HES_UPTODATE | PERF_HES_STOPPED;
  917. /* Allocate an event counter */
  918. hw->idx = get_next_avail_cntr(pmu_dev);
  919. if (hw->idx < 0)
  920. return -EAGAIN;
  921. /* Update counter event pointer for Interrupt handler */
  922. pmu_dev->pmu_counter_event[hw->idx] = event;
  923. if (flags & PERF_EF_START)
  924. xgene_perf_start(event, PERF_EF_RELOAD);
  925. return 0;
  926. }
  927. static void xgene_perf_del(struct perf_event *event, int flags)
  928. {
  929. struct xgene_pmu_dev *pmu_dev = to_pmu_dev(event->pmu);
  930. struct hw_perf_event *hw = &event->hw;
  931. xgene_perf_stop(event, PERF_EF_UPDATE);
  932. /* clear the assigned counter */
  933. clear_avail_cntr(pmu_dev, GET_CNTR(event));
  934. perf_event_update_userpage(event);
  935. pmu_dev->pmu_counter_event[hw->idx] = NULL;
  936. }
  937. static int xgene_init_perf(struct xgene_pmu_dev *pmu_dev, char *name)
  938. {
  939. struct xgene_pmu *xgene_pmu;
  940. if (pmu_dev->parent->version == PCP_PMU_V3)
  941. pmu_dev->max_period = PMU_V3_CNT_MAX_PERIOD;
  942. else
  943. pmu_dev->max_period = PMU_CNT_MAX_PERIOD;
  944. /* First version PMU supports only single event counter */
  945. xgene_pmu = pmu_dev->parent;
  946. if (xgene_pmu->version == PCP_PMU_V1)
  947. pmu_dev->max_counters = 1;
  948. else
  949. pmu_dev->max_counters = PMU_MAX_COUNTERS;
  950. /* Perf driver registration */
  951. pmu_dev->pmu = (struct pmu) {
  952. .attr_groups = pmu_dev->attr_groups,
  953. .task_ctx_nr = perf_invalid_context,
  954. .pmu_enable = xgene_perf_pmu_enable,
  955. .pmu_disable = xgene_perf_pmu_disable,
  956. .event_init = xgene_perf_event_init,
  957. .add = xgene_perf_add,
  958. .del = xgene_perf_del,
  959. .start = xgene_perf_start,
  960. .stop = xgene_perf_stop,
  961. .read = xgene_perf_read,
  962. .capabilities = PERF_PMU_CAP_NO_EXCLUDE,
  963. };
  964. /* Hardware counter init */
  965. xgene_pmu->ops->stop_counters(pmu_dev);
  966. xgene_pmu->ops->reset_counters(pmu_dev);
  967. return perf_pmu_register(&pmu_dev->pmu, name, -1);
  968. }
  969. static int
  970. xgene_pmu_dev_add(struct xgene_pmu *xgene_pmu, struct xgene_pmu_dev_ctx *ctx)
  971. {
  972. struct device *dev = xgene_pmu->dev;
  973. struct xgene_pmu_dev *pmu;
  974. pmu = devm_kzalloc(dev, sizeof(*pmu), GFP_KERNEL);
  975. if (!pmu)
  976. return -ENOMEM;
  977. pmu->parent = xgene_pmu;
  978. pmu->inf = &ctx->inf;
  979. ctx->pmu_dev = pmu;
  980. switch (pmu->inf->type) {
  981. case PMU_TYPE_L3C:
  982. if (!(xgene_pmu->l3c_active_mask & pmu->inf->enable_mask))
  983. return -ENODEV;
  984. if (xgene_pmu->version == PCP_PMU_V3)
  985. pmu->attr_groups = l3c_pmu_v3_attr_groups;
  986. else
  987. pmu->attr_groups = l3c_pmu_attr_groups;
  988. break;
  989. case PMU_TYPE_IOB:
  990. if (xgene_pmu->version == PCP_PMU_V3)
  991. pmu->attr_groups = iob_fast_pmu_v3_attr_groups;
  992. else
  993. pmu->attr_groups = iob_pmu_attr_groups;
  994. break;
  995. case PMU_TYPE_IOB_SLOW:
  996. if (xgene_pmu->version == PCP_PMU_V3)
  997. pmu->attr_groups = iob_slow_pmu_v3_attr_groups;
  998. break;
  999. case PMU_TYPE_MCB:
  1000. if (!(xgene_pmu->mcb_active_mask & pmu->inf->enable_mask))
  1001. return -ENODEV;
  1002. if (xgene_pmu->version == PCP_PMU_V3)
  1003. pmu->attr_groups = mcb_pmu_v3_attr_groups;
  1004. else
  1005. pmu->attr_groups = mcb_pmu_attr_groups;
  1006. break;
  1007. case PMU_TYPE_MC:
  1008. if (!(xgene_pmu->mc_active_mask & pmu->inf->enable_mask))
  1009. return -ENODEV;
  1010. if (xgene_pmu->version == PCP_PMU_V3)
  1011. pmu->attr_groups = mc_pmu_v3_attr_groups;
  1012. else
  1013. pmu->attr_groups = mc_pmu_attr_groups;
  1014. break;
  1015. default:
  1016. return -EINVAL;
  1017. }
  1018. if (xgene_init_perf(pmu, ctx->name)) {
  1019. dev_err(dev, "%s PMU: Failed to init perf driver\n", ctx->name);
  1020. return -ENODEV;
  1021. }
  1022. dev_info(dev, "%s PMU registered\n", ctx->name);
  1023. return 0;
  1024. }
  1025. static void _xgene_pmu_isr(int irq, struct xgene_pmu_dev *pmu_dev)
  1026. {
  1027. struct xgene_pmu *xgene_pmu = pmu_dev->parent;
  1028. void __iomem *csr = pmu_dev->inf->csr;
  1029. u32 pmovsr;
  1030. int idx;
  1031. xgene_pmu->ops->stop_counters(pmu_dev);
  1032. if (xgene_pmu->version == PCP_PMU_V3)
  1033. pmovsr = readl(csr + PMU_PMOVSSET) & PMU_OVERFLOW_MASK;
  1034. else
  1035. pmovsr = readl(csr + PMU_PMOVSR) & PMU_OVERFLOW_MASK;
  1036. if (!pmovsr)
  1037. goto out;
  1038. /* Clear interrupt flag */
  1039. if (xgene_pmu->version == PCP_PMU_V1)
  1040. writel(0x0, csr + PMU_PMOVSR);
  1041. else if (xgene_pmu->version == PCP_PMU_V2)
  1042. writel(pmovsr, csr + PMU_PMOVSR);
  1043. else
  1044. writel(pmovsr, csr + PMU_PMOVSCLR);
  1045. for (idx = 0; idx < PMU_MAX_COUNTERS; idx++) {
  1046. struct perf_event *event = pmu_dev->pmu_counter_event[idx];
  1047. int overflowed = pmovsr & BIT(idx);
  1048. /* Ignore if we don't have an event. */
  1049. if (!event || !overflowed)
  1050. continue;
  1051. xgene_perf_event_update(event);
  1052. xgene_perf_event_set_period(event);
  1053. }
  1054. out:
  1055. xgene_pmu->ops->start_counters(pmu_dev);
  1056. }
  1057. static irqreturn_t xgene_pmu_isr(int irq, void *dev_id)
  1058. {
  1059. u32 intr_mcu, intr_mcb, intr_l3c, intr_iob;
  1060. struct xgene_pmu_dev_ctx *ctx;
  1061. struct xgene_pmu *xgene_pmu = dev_id;
  1062. unsigned long flags;
  1063. u32 val;
  1064. raw_spin_lock_irqsave(&xgene_pmu->lock, flags);
  1065. /* Get Interrupt PMU source */
  1066. val = readl(xgene_pmu->pcppmu_csr + PCPPMU_INTSTATUS_REG);
  1067. if (xgene_pmu->version == PCP_PMU_V3) {
  1068. intr_mcu = PCPPMU_V3_INT_MCU;
  1069. intr_mcb = PCPPMU_V3_INT_MCB;
  1070. intr_l3c = PCPPMU_V3_INT_L3C;
  1071. intr_iob = PCPPMU_V3_INT_IOB;
  1072. } else {
  1073. intr_mcu = PCPPMU_INT_MCU;
  1074. intr_mcb = PCPPMU_INT_MCB;
  1075. intr_l3c = PCPPMU_INT_L3C;
  1076. intr_iob = PCPPMU_INT_IOB;
  1077. }
  1078. if (val & intr_mcu) {
  1079. list_for_each_entry(ctx, &xgene_pmu->mcpmus, next) {
  1080. _xgene_pmu_isr(irq, ctx->pmu_dev);
  1081. }
  1082. }
  1083. if (val & intr_mcb) {
  1084. list_for_each_entry(ctx, &xgene_pmu->mcbpmus, next) {
  1085. _xgene_pmu_isr(irq, ctx->pmu_dev);
  1086. }
  1087. }
  1088. if (val & intr_l3c) {
  1089. list_for_each_entry(ctx, &xgene_pmu->l3cpmus, next) {
  1090. _xgene_pmu_isr(irq, ctx->pmu_dev);
  1091. }
  1092. }
  1093. if (val & intr_iob) {
  1094. list_for_each_entry(ctx, &xgene_pmu->iobpmus, next) {
  1095. _xgene_pmu_isr(irq, ctx->pmu_dev);
  1096. }
  1097. }
  1098. raw_spin_unlock_irqrestore(&xgene_pmu->lock, flags);
  1099. return IRQ_HANDLED;
  1100. }
  1101. static int acpi_pmu_probe_active_mcb_mcu_l3c(struct xgene_pmu *xgene_pmu,
  1102. struct platform_device *pdev)
  1103. {
  1104. void __iomem *csw_csr, *mcba_csr, *mcbb_csr;
  1105. unsigned int reg;
  1106. csw_csr = devm_platform_ioremap_resource(pdev, 1);
  1107. if (IS_ERR(csw_csr)) {
  1108. dev_err(&pdev->dev, "ioremap failed for CSW CSR resource\n");
  1109. return PTR_ERR(csw_csr);
  1110. }
  1111. mcba_csr = devm_platform_ioremap_resource(pdev, 2);
  1112. if (IS_ERR(mcba_csr)) {
  1113. dev_err(&pdev->dev, "ioremap failed for MCBA CSR resource\n");
  1114. return PTR_ERR(mcba_csr);
  1115. }
  1116. mcbb_csr = devm_platform_ioremap_resource(pdev, 3);
  1117. if (IS_ERR(mcbb_csr)) {
  1118. dev_err(&pdev->dev, "ioremap failed for MCBB CSR resource\n");
  1119. return PTR_ERR(mcbb_csr);
  1120. }
  1121. xgene_pmu->l3c_active_mask = 0x1;
  1122. reg = readl(csw_csr + CSW_CSWCR);
  1123. if (reg & CSW_CSWCR_DUALMCB_MASK) {
  1124. /* Dual MCB active */
  1125. xgene_pmu->mcb_active_mask = 0x3;
  1126. /* Probe all active MC(s) */
  1127. reg = readl(mcbb_csr + CSW_CSWCR);
  1128. xgene_pmu->mc_active_mask =
  1129. (reg & MCBADDRMR_DUALMCU_MODE_MASK) ? 0xF : 0x5;
  1130. } else {
  1131. /* Single MCB active */
  1132. xgene_pmu->mcb_active_mask = 0x1;
  1133. /* Probe all active MC(s) */
  1134. reg = readl(mcba_csr + CSW_CSWCR);
  1135. xgene_pmu->mc_active_mask =
  1136. (reg & MCBADDRMR_DUALMCU_MODE_MASK) ? 0x3 : 0x1;
  1137. }
  1138. return 0;
  1139. }
  1140. static int acpi_pmu_v3_probe_active_mcb_mcu_l3c(struct xgene_pmu *xgene_pmu,
  1141. struct platform_device *pdev)
  1142. {
  1143. void __iomem *csw_csr;
  1144. unsigned int reg;
  1145. u32 mcb0routing;
  1146. u32 mcb1routing;
  1147. csw_csr = devm_platform_ioremap_resource(pdev, 1);
  1148. if (IS_ERR(csw_csr)) {
  1149. dev_err(&pdev->dev, "ioremap failed for CSW CSR resource\n");
  1150. return PTR_ERR(csw_csr);
  1151. }
  1152. reg = readl(csw_csr + CSW_CSWCR);
  1153. mcb0routing = CSW_CSWCR_MCB0_ROUTING(reg);
  1154. mcb1routing = CSW_CSWCR_MCB1_ROUTING(reg);
  1155. if (reg & CSW_CSWCR_DUALMCB_MASK) {
  1156. /* Dual MCB active */
  1157. xgene_pmu->mcb_active_mask = 0x3;
  1158. /* Probe all active L3C(s), maximum is 8 */
  1159. xgene_pmu->l3c_active_mask = 0xFF;
  1160. /* Probe all active MC(s), maximum is 8 */
  1161. if ((mcb0routing == 0x2) && (mcb1routing == 0x2))
  1162. xgene_pmu->mc_active_mask = 0xFF;
  1163. else if ((mcb0routing == 0x1) && (mcb1routing == 0x1))
  1164. xgene_pmu->mc_active_mask = 0x33;
  1165. else
  1166. xgene_pmu->mc_active_mask = 0x11;
  1167. } else {
  1168. /* Single MCB active */
  1169. xgene_pmu->mcb_active_mask = 0x1;
  1170. /* Probe all active L3C(s), maximum is 4 */
  1171. xgene_pmu->l3c_active_mask = 0x0F;
  1172. /* Probe all active MC(s), maximum is 4 */
  1173. if (mcb0routing == 0x2)
  1174. xgene_pmu->mc_active_mask = 0x0F;
  1175. else if (mcb0routing == 0x1)
  1176. xgene_pmu->mc_active_mask = 0x03;
  1177. else
  1178. xgene_pmu->mc_active_mask = 0x01;
  1179. }
  1180. return 0;
  1181. }
  1182. static int fdt_pmu_probe_active_mcb_mcu_l3c(struct xgene_pmu *xgene_pmu,
  1183. struct platform_device *pdev)
  1184. {
  1185. struct regmap *csw_map, *mcba_map, *mcbb_map;
  1186. struct device_node *np = pdev->dev.of_node;
  1187. unsigned int reg;
  1188. csw_map = syscon_regmap_lookup_by_phandle(np, "regmap-csw");
  1189. if (IS_ERR(csw_map)) {
  1190. dev_err(&pdev->dev, "unable to get syscon regmap csw\n");
  1191. return PTR_ERR(csw_map);
  1192. }
  1193. mcba_map = syscon_regmap_lookup_by_phandle(np, "regmap-mcba");
  1194. if (IS_ERR(mcba_map)) {
  1195. dev_err(&pdev->dev, "unable to get syscon regmap mcba\n");
  1196. return PTR_ERR(mcba_map);
  1197. }
  1198. mcbb_map = syscon_regmap_lookup_by_phandle(np, "regmap-mcbb");
  1199. if (IS_ERR(mcbb_map)) {
  1200. dev_err(&pdev->dev, "unable to get syscon regmap mcbb\n");
  1201. return PTR_ERR(mcbb_map);
  1202. }
  1203. xgene_pmu->l3c_active_mask = 0x1;
  1204. if (regmap_read(csw_map, CSW_CSWCR, &reg))
  1205. return -EINVAL;
  1206. if (reg & CSW_CSWCR_DUALMCB_MASK) {
  1207. /* Dual MCB active */
  1208. xgene_pmu->mcb_active_mask = 0x3;
  1209. /* Probe all active MC(s) */
  1210. if (regmap_read(mcbb_map, MCBADDRMR, &reg))
  1211. return 0;
  1212. xgene_pmu->mc_active_mask =
  1213. (reg & MCBADDRMR_DUALMCU_MODE_MASK) ? 0xF : 0x5;
  1214. } else {
  1215. /* Single MCB active */
  1216. xgene_pmu->mcb_active_mask = 0x1;
  1217. /* Probe all active MC(s) */
  1218. if (regmap_read(mcba_map, MCBADDRMR, &reg))
  1219. return 0;
  1220. xgene_pmu->mc_active_mask =
  1221. (reg & MCBADDRMR_DUALMCU_MODE_MASK) ? 0x3 : 0x1;
  1222. }
  1223. return 0;
  1224. }
  1225. static int xgene_pmu_probe_active_mcb_mcu_l3c(struct xgene_pmu *xgene_pmu,
  1226. struct platform_device *pdev)
  1227. {
  1228. if (has_acpi_companion(&pdev->dev)) {
  1229. if (xgene_pmu->version == PCP_PMU_V3)
  1230. return acpi_pmu_v3_probe_active_mcb_mcu_l3c(xgene_pmu,
  1231. pdev);
  1232. else
  1233. return acpi_pmu_probe_active_mcb_mcu_l3c(xgene_pmu,
  1234. pdev);
  1235. }
  1236. return fdt_pmu_probe_active_mcb_mcu_l3c(xgene_pmu, pdev);
  1237. }
  1238. static char *xgene_pmu_dev_name(struct device *dev, u32 type, int id)
  1239. {
  1240. switch (type) {
  1241. case PMU_TYPE_L3C:
  1242. return devm_kasprintf(dev, GFP_KERNEL, "l3c%d", id);
  1243. case PMU_TYPE_IOB:
  1244. return devm_kasprintf(dev, GFP_KERNEL, "iob%d", id);
  1245. case PMU_TYPE_IOB_SLOW:
  1246. return devm_kasprintf(dev, GFP_KERNEL, "iob_slow%d", id);
  1247. case PMU_TYPE_MCB:
  1248. return devm_kasprintf(dev, GFP_KERNEL, "mcb%d", id);
  1249. case PMU_TYPE_MC:
  1250. return devm_kasprintf(dev, GFP_KERNEL, "mc%d", id);
  1251. default:
  1252. return devm_kasprintf(dev, GFP_KERNEL, "unknown");
  1253. }
  1254. }
  1255. #if defined(CONFIG_ACPI)
  1256. static struct
  1257. xgene_pmu_dev_ctx *acpi_get_pmu_hw_inf(struct xgene_pmu *xgene_pmu,
  1258. struct acpi_device *adev, u32 type)
  1259. {
  1260. struct device *dev = xgene_pmu->dev;
  1261. struct list_head resource_list;
  1262. struct xgene_pmu_dev_ctx *ctx;
  1263. const union acpi_object *obj;
  1264. struct hw_pmu_info *inf;
  1265. void __iomem *dev_csr;
  1266. struct resource res;
  1267. struct resource_entry *rentry;
  1268. int enable_bit;
  1269. int rc;
  1270. ctx = devm_kzalloc(dev, sizeof(*ctx), GFP_KERNEL);
  1271. if (!ctx)
  1272. return NULL;
  1273. INIT_LIST_HEAD(&resource_list);
  1274. rc = acpi_dev_get_resources(adev, &resource_list, NULL, NULL);
  1275. if (rc <= 0) {
  1276. dev_err(dev, "PMU type %d: No resources found\n", type);
  1277. return NULL;
  1278. }
  1279. list_for_each_entry(rentry, &resource_list, node) {
  1280. if (resource_type(rentry->res) == IORESOURCE_MEM) {
  1281. res = *rentry->res;
  1282. rentry = NULL;
  1283. break;
  1284. }
  1285. }
  1286. acpi_dev_free_resource_list(&resource_list);
  1287. if (rentry) {
  1288. dev_err(dev, "PMU type %d: No memory resource found\n", type);
  1289. return NULL;
  1290. }
  1291. dev_csr = devm_ioremap_resource(dev, &res);
  1292. if (IS_ERR(dev_csr)) {
  1293. dev_err(dev, "PMU type %d: Fail to map resource\n", type);
  1294. return NULL;
  1295. }
  1296. /* A PMU device node without enable-bit-index is always enabled */
  1297. rc = acpi_dev_get_property(adev, "enable-bit-index",
  1298. ACPI_TYPE_INTEGER, &obj);
  1299. if (rc < 0)
  1300. enable_bit = 0;
  1301. else
  1302. enable_bit = (int) obj->integer.value;
  1303. ctx->name = xgene_pmu_dev_name(dev, type, enable_bit);
  1304. if (!ctx->name) {
  1305. dev_err(dev, "PMU type %d: Fail to get device name\n", type);
  1306. return NULL;
  1307. }
  1308. inf = &ctx->inf;
  1309. inf->type = type;
  1310. inf->csr = dev_csr;
  1311. inf->enable_mask = 1 << enable_bit;
  1312. return ctx;
  1313. }
  1314. static const struct acpi_device_id xgene_pmu_acpi_type_match[] = {
  1315. {"APMC0D5D", PMU_TYPE_L3C},
  1316. {"APMC0D5E", PMU_TYPE_IOB},
  1317. {"APMC0D5F", PMU_TYPE_MCB},
  1318. {"APMC0D60", PMU_TYPE_MC},
  1319. {"APMC0D84", PMU_TYPE_L3C},
  1320. {"APMC0D85", PMU_TYPE_IOB},
  1321. {"APMC0D86", PMU_TYPE_IOB_SLOW},
  1322. {"APMC0D87", PMU_TYPE_MCB},
  1323. {"APMC0D88", PMU_TYPE_MC},
  1324. {},
  1325. };
  1326. static const struct acpi_device_id *xgene_pmu_acpi_match_type(
  1327. const struct acpi_device_id *ids,
  1328. struct acpi_device *adev)
  1329. {
  1330. const struct acpi_device_id *match_id = NULL;
  1331. const struct acpi_device_id *id;
  1332. for (id = ids; id->id[0] || id->cls; id++) {
  1333. if (!acpi_match_device_ids(adev, id))
  1334. match_id = id;
  1335. else if (match_id)
  1336. break;
  1337. }
  1338. return match_id;
  1339. }
  1340. static acpi_status acpi_pmu_dev_add(acpi_handle handle, u32 level,
  1341. void *data, void **return_value)
  1342. {
  1343. const struct acpi_device_id *acpi_id;
  1344. struct xgene_pmu *xgene_pmu = data;
  1345. struct xgene_pmu_dev_ctx *ctx;
  1346. struct acpi_device *adev;
  1347. if (acpi_bus_get_device(handle, &adev))
  1348. return AE_OK;
  1349. if (acpi_bus_get_status(adev) || !adev->status.present)
  1350. return AE_OK;
  1351. acpi_id = xgene_pmu_acpi_match_type(xgene_pmu_acpi_type_match, adev);
  1352. if (!acpi_id)
  1353. return AE_OK;
  1354. ctx = acpi_get_pmu_hw_inf(xgene_pmu, adev, (u32)acpi_id->driver_data);
  1355. if (!ctx)
  1356. return AE_OK;
  1357. if (xgene_pmu_dev_add(xgene_pmu, ctx)) {
  1358. /* Can't add the PMU device, skip it */
  1359. devm_kfree(xgene_pmu->dev, ctx);
  1360. return AE_OK;
  1361. }
  1362. switch (ctx->inf.type) {
  1363. case PMU_TYPE_L3C:
  1364. list_add(&ctx->next, &xgene_pmu->l3cpmus);
  1365. break;
  1366. case PMU_TYPE_IOB:
  1367. list_add(&ctx->next, &xgene_pmu->iobpmus);
  1368. break;
  1369. case PMU_TYPE_IOB_SLOW:
  1370. list_add(&ctx->next, &xgene_pmu->iobpmus);
  1371. break;
  1372. case PMU_TYPE_MCB:
  1373. list_add(&ctx->next, &xgene_pmu->mcbpmus);
  1374. break;
  1375. case PMU_TYPE_MC:
  1376. list_add(&ctx->next, &xgene_pmu->mcpmus);
  1377. break;
  1378. }
  1379. return AE_OK;
  1380. }
  1381. static int acpi_pmu_probe_pmu_dev(struct xgene_pmu *xgene_pmu,
  1382. struct platform_device *pdev)
  1383. {
  1384. struct device *dev = xgene_pmu->dev;
  1385. acpi_handle handle;
  1386. acpi_status status;
  1387. handle = ACPI_HANDLE(dev);
  1388. if (!handle)
  1389. return -EINVAL;
  1390. status = acpi_walk_namespace(ACPI_TYPE_DEVICE, handle, 1,
  1391. acpi_pmu_dev_add, NULL, xgene_pmu, NULL);
  1392. if (ACPI_FAILURE(status)) {
  1393. dev_err(dev, "failed to probe PMU devices\n");
  1394. return -ENODEV;
  1395. }
  1396. return 0;
  1397. }
  1398. #else
  1399. static int acpi_pmu_probe_pmu_dev(struct xgene_pmu *xgene_pmu,
  1400. struct platform_device *pdev)
  1401. {
  1402. return 0;
  1403. }
  1404. #endif
  1405. static struct
  1406. xgene_pmu_dev_ctx *fdt_get_pmu_hw_inf(struct xgene_pmu *xgene_pmu,
  1407. struct device_node *np, u32 type)
  1408. {
  1409. struct device *dev = xgene_pmu->dev;
  1410. struct xgene_pmu_dev_ctx *ctx;
  1411. struct hw_pmu_info *inf;
  1412. void __iomem *dev_csr;
  1413. struct resource res;
  1414. int enable_bit;
  1415. ctx = devm_kzalloc(dev, sizeof(*ctx), GFP_KERNEL);
  1416. if (!ctx)
  1417. return NULL;
  1418. if (of_address_to_resource(np, 0, &res) < 0) {
  1419. dev_err(dev, "PMU type %d: No resource address found\n", type);
  1420. return NULL;
  1421. }
  1422. dev_csr = devm_ioremap_resource(dev, &res);
  1423. if (IS_ERR(dev_csr)) {
  1424. dev_err(dev, "PMU type %d: Fail to map resource\n", type);
  1425. return NULL;
  1426. }
  1427. /* A PMU device node without enable-bit-index is always enabled */
  1428. if (of_property_read_u32(np, "enable-bit-index", &enable_bit))
  1429. enable_bit = 0;
  1430. ctx->name = xgene_pmu_dev_name(dev, type, enable_bit);
  1431. if (!ctx->name) {
  1432. dev_err(dev, "PMU type %d: Fail to get device name\n", type);
  1433. return NULL;
  1434. }
  1435. inf = &ctx->inf;
  1436. inf->type = type;
  1437. inf->csr = dev_csr;
  1438. inf->enable_mask = 1 << enable_bit;
  1439. return ctx;
  1440. }
  1441. static int fdt_pmu_probe_pmu_dev(struct xgene_pmu *xgene_pmu,
  1442. struct platform_device *pdev)
  1443. {
  1444. struct xgene_pmu_dev_ctx *ctx;
  1445. struct device_node *np;
  1446. for_each_child_of_node(pdev->dev.of_node, np) {
  1447. if (!of_device_is_available(np))
  1448. continue;
  1449. if (of_device_is_compatible(np, "apm,xgene-pmu-l3c"))
  1450. ctx = fdt_get_pmu_hw_inf(xgene_pmu, np, PMU_TYPE_L3C);
  1451. else if (of_device_is_compatible(np, "apm,xgene-pmu-iob"))
  1452. ctx = fdt_get_pmu_hw_inf(xgene_pmu, np, PMU_TYPE_IOB);
  1453. else if (of_device_is_compatible(np, "apm,xgene-pmu-mcb"))
  1454. ctx = fdt_get_pmu_hw_inf(xgene_pmu, np, PMU_TYPE_MCB);
  1455. else if (of_device_is_compatible(np, "apm,xgene-pmu-mc"))
  1456. ctx = fdt_get_pmu_hw_inf(xgene_pmu, np, PMU_TYPE_MC);
  1457. else
  1458. ctx = NULL;
  1459. if (!ctx)
  1460. continue;
  1461. if (xgene_pmu_dev_add(xgene_pmu, ctx)) {
  1462. /* Can't add the PMU device, skip it */
  1463. devm_kfree(xgene_pmu->dev, ctx);
  1464. continue;
  1465. }
  1466. switch (ctx->inf.type) {
  1467. case PMU_TYPE_L3C:
  1468. list_add(&ctx->next, &xgene_pmu->l3cpmus);
  1469. break;
  1470. case PMU_TYPE_IOB:
  1471. list_add(&ctx->next, &xgene_pmu->iobpmus);
  1472. break;
  1473. case PMU_TYPE_IOB_SLOW:
  1474. list_add(&ctx->next, &xgene_pmu->iobpmus);
  1475. break;
  1476. case PMU_TYPE_MCB:
  1477. list_add(&ctx->next, &xgene_pmu->mcbpmus);
  1478. break;
  1479. case PMU_TYPE_MC:
  1480. list_add(&ctx->next, &xgene_pmu->mcpmus);
  1481. break;
  1482. }
  1483. }
  1484. return 0;
  1485. }
  1486. static int xgene_pmu_probe_pmu_dev(struct xgene_pmu *xgene_pmu,
  1487. struct platform_device *pdev)
  1488. {
  1489. if (has_acpi_companion(&pdev->dev))
  1490. return acpi_pmu_probe_pmu_dev(xgene_pmu, pdev);
  1491. return fdt_pmu_probe_pmu_dev(xgene_pmu, pdev);
  1492. }
  1493. static const struct xgene_pmu_data xgene_pmu_data = {
  1494. .id = PCP_PMU_V1,
  1495. };
  1496. static const struct xgene_pmu_data xgene_pmu_v2_data = {
  1497. .id = PCP_PMU_V2,
  1498. };
  1499. static const struct xgene_pmu_ops xgene_pmu_ops = {
  1500. .mask_int = xgene_pmu_mask_int,
  1501. .unmask_int = xgene_pmu_unmask_int,
  1502. .read_counter = xgene_pmu_read_counter32,
  1503. .write_counter = xgene_pmu_write_counter32,
  1504. .write_evttype = xgene_pmu_write_evttype,
  1505. .write_agentmsk = xgene_pmu_write_agentmsk,
  1506. .write_agent1msk = xgene_pmu_write_agent1msk,
  1507. .enable_counter = xgene_pmu_enable_counter,
  1508. .disable_counter = xgene_pmu_disable_counter,
  1509. .enable_counter_int = xgene_pmu_enable_counter_int,
  1510. .disable_counter_int = xgene_pmu_disable_counter_int,
  1511. .reset_counters = xgene_pmu_reset_counters,
  1512. .start_counters = xgene_pmu_start_counters,
  1513. .stop_counters = xgene_pmu_stop_counters,
  1514. };
  1515. static const struct xgene_pmu_ops xgene_pmu_v3_ops = {
  1516. .mask_int = xgene_pmu_v3_mask_int,
  1517. .unmask_int = xgene_pmu_v3_unmask_int,
  1518. .read_counter = xgene_pmu_read_counter64,
  1519. .write_counter = xgene_pmu_write_counter64,
  1520. .write_evttype = xgene_pmu_write_evttype,
  1521. .write_agentmsk = xgene_pmu_v3_write_agentmsk,
  1522. .write_agent1msk = xgene_pmu_v3_write_agent1msk,
  1523. .enable_counter = xgene_pmu_enable_counter,
  1524. .disable_counter = xgene_pmu_disable_counter,
  1525. .enable_counter_int = xgene_pmu_enable_counter_int,
  1526. .disable_counter_int = xgene_pmu_disable_counter_int,
  1527. .reset_counters = xgene_pmu_reset_counters,
  1528. .start_counters = xgene_pmu_start_counters,
  1529. .stop_counters = xgene_pmu_stop_counters,
  1530. };
  1531. static const struct of_device_id xgene_pmu_of_match[] = {
  1532. { .compatible = "apm,xgene-pmu", .data = &xgene_pmu_data },
  1533. { .compatible = "apm,xgene-pmu-v2", .data = &xgene_pmu_v2_data },
  1534. {},
  1535. };
  1536. MODULE_DEVICE_TABLE(of, xgene_pmu_of_match);
  1537. #ifdef CONFIG_ACPI
  1538. static const struct acpi_device_id xgene_pmu_acpi_match[] = {
  1539. {"APMC0D5B", PCP_PMU_V1},
  1540. {"APMC0D5C", PCP_PMU_V2},
  1541. {"APMC0D83", PCP_PMU_V3},
  1542. {},
  1543. };
  1544. MODULE_DEVICE_TABLE(acpi, xgene_pmu_acpi_match);
  1545. #endif
  1546. static int xgene_pmu_online_cpu(unsigned int cpu, struct hlist_node *node)
  1547. {
  1548. struct xgene_pmu *xgene_pmu = hlist_entry_safe(node, struct xgene_pmu,
  1549. node);
  1550. if (cpumask_empty(&xgene_pmu->cpu))
  1551. cpumask_set_cpu(cpu, &xgene_pmu->cpu);
  1552. /* Overflow interrupt also should use the same CPU */
  1553. WARN_ON(irq_set_affinity(xgene_pmu->irq, &xgene_pmu->cpu));
  1554. return 0;
  1555. }
  1556. static int xgene_pmu_offline_cpu(unsigned int cpu, struct hlist_node *node)
  1557. {
  1558. struct xgene_pmu *xgene_pmu = hlist_entry_safe(node, struct xgene_pmu,
  1559. node);
  1560. struct xgene_pmu_dev_ctx *ctx;
  1561. unsigned int target;
  1562. if (!cpumask_test_and_clear_cpu(cpu, &xgene_pmu->cpu))
  1563. return 0;
  1564. target = cpumask_any_but(cpu_online_mask, cpu);
  1565. if (target >= nr_cpu_ids)
  1566. return 0;
  1567. list_for_each_entry(ctx, &xgene_pmu->mcpmus, next) {
  1568. perf_pmu_migrate_context(&ctx->pmu_dev->pmu, cpu, target);
  1569. }
  1570. list_for_each_entry(ctx, &xgene_pmu->mcbpmus, next) {
  1571. perf_pmu_migrate_context(&ctx->pmu_dev->pmu, cpu, target);
  1572. }
  1573. list_for_each_entry(ctx, &xgene_pmu->l3cpmus, next) {
  1574. perf_pmu_migrate_context(&ctx->pmu_dev->pmu, cpu, target);
  1575. }
  1576. list_for_each_entry(ctx, &xgene_pmu->iobpmus, next) {
  1577. perf_pmu_migrate_context(&ctx->pmu_dev->pmu, cpu, target);
  1578. }
  1579. cpumask_set_cpu(target, &xgene_pmu->cpu);
  1580. /* Overflow interrupt also should use the same CPU */
  1581. WARN_ON(irq_set_affinity(xgene_pmu->irq, &xgene_pmu->cpu));
  1582. return 0;
  1583. }
  1584. static int xgene_pmu_probe(struct platform_device *pdev)
  1585. {
  1586. const struct xgene_pmu_data *dev_data;
  1587. const struct of_device_id *of_id;
  1588. struct xgene_pmu *xgene_pmu;
  1589. struct resource *res;
  1590. int irq, rc;
  1591. int version;
  1592. /* Install a hook to update the reader CPU in case it goes offline */
  1593. rc = cpuhp_setup_state_multi(CPUHP_AP_PERF_ARM_APM_XGENE_ONLINE,
  1594. "CPUHP_AP_PERF_ARM_APM_XGENE_ONLINE",
  1595. xgene_pmu_online_cpu,
  1596. xgene_pmu_offline_cpu);
  1597. if (rc)
  1598. return rc;
  1599. xgene_pmu = devm_kzalloc(&pdev->dev, sizeof(*xgene_pmu), GFP_KERNEL);
  1600. if (!xgene_pmu)
  1601. return -ENOMEM;
  1602. xgene_pmu->dev = &pdev->dev;
  1603. platform_set_drvdata(pdev, xgene_pmu);
  1604. version = -EINVAL;
  1605. of_id = of_match_device(xgene_pmu_of_match, &pdev->dev);
  1606. if (of_id) {
  1607. dev_data = (const struct xgene_pmu_data *) of_id->data;
  1608. version = dev_data->id;
  1609. }
  1610. #ifdef CONFIG_ACPI
  1611. if (ACPI_COMPANION(&pdev->dev)) {
  1612. const struct acpi_device_id *acpi_id;
  1613. acpi_id = acpi_match_device(xgene_pmu_acpi_match, &pdev->dev);
  1614. if (acpi_id)
  1615. version = (int) acpi_id->driver_data;
  1616. }
  1617. #endif
  1618. if (version < 0)
  1619. return -ENODEV;
  1620. if (version == PCP_PMU_V3)
  1621. xgene_pmu->ops = &xgene_pmu_v3_ops;
  1622. else
  1623. xgene_pmu->ops = &xgene_pmu_ops;
  1624. INIT_LIST_HEAD(&xgene_pmu->l3cpmus);
  1625. INIT_LIST_HEAD(&xgene_pmu->iobpmus);
  1626. INIT_LIST_HEAD(&xgene_pmu->mcbpmus);
  1627. INIT_LIST_HEAD(&xgene_pmu->mcpmus);
  1628. xgene_pmu->version = version;
  1629. dev_info(&pdev->dev, "X-Gene PMU version %d\n", xgene_pmu->version);
  1630. res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
  1631. xgene_pmu->pcppmu_csr = devm_ioremap_resource(&pdev->dev, res);
  1632. if (IS_ERR(xgene_pmu->pcppmu_csr)) {
  1633. dev_err(&pdev->dev, "ioremap failed for PCP PMU resource\n");
  1634. return PTR_ERR(xgene_pmu->pcppmu_csr);
  1635. }
  1636. irq = platform_get_irq(pdev, 0);
  1637. if (irq < 0)
  1638. return -EINVAL;
  1639. rc = devm_request_irq(&pdev->dev, irq, xgene_pmu_isr,
  1640. IRQF_NOBALANCING | IRQF_NO_THREAD,
  1641. dev_name(&pdev->dev), xgene_pmu);
  1642. if (rc) {
  1643. dev_err(&pdev->dev, "Could not request IRQ %d\n", irq);
  1644. return rc;
  1645. }
  1646. xgene_pmu->irq = irq;
  1647. raw_spin_lock_init(&xgene_pmu->lock);
  1648. /* Check for active MCBs and MCUs */
  1649. rc = xgene_pmu_probe_active_mcb_mcu_l3c(xgene_pmu, pdev);
  1650. if (rc) {
  1651. dev_warn(&pdev->dev, "Unknown MCB/MCU active status\n");
  1652. xgene_pmu->mcb_active_mask = 0x1;
  1653. xgene_pmu->mc_active_mask = 0x1;
  1654. }
  1655. /* Add this instance to the list used by the hotplug callback */
  1656. rc = cpuhp_state_add_instance(CPUHP_AP_PERF_ARM_APM_XGENE_ONLINE,
  1657. &xgene_pmu->node);
  1658. if (rc) {
  1659. dev_err(&pdev->dev, "Error %d registering hotplug", rc);
  1660. return rc;
  1661. }
  1662. /* Walk through the tree for all PMU perf devices */
  1663. rc = xgene_pmu_probe_pmu_dev(xgene_pmu, pdev);
  1664. if (rc) {
  1665. dev_err(&pdev->dev, "No PMU perf devices found!\n");
  1666. goto out_unregister;
  1667. }
  1668. /* Enable interrupt */
  1669. xgene_pmu->ops->unmask_int(xgene_pmu);
  1670. return 0;
  1671. out_unregister:
  1672. cpuhp_state_remove_instance(CPUHP_AP_PERF_ARM_APM_XGENE_ONLINE,
  1673. &xgene_pmu->node);
  1674. return rc;
  1675. }
  1676. static void
  1677. xgene_pmu_dev_cleanup(struct xgene_pmu *xgene_pmu, struct list_head *pmus)
  1678. {
  1679. struct xgene_pmu_dev_ctx *ctx;
  1680. list_for_each_entry(ctx, pmus, next) {
  1681. perf_pmu_unregister(&ctx->pmu_dev->pmu);
  1682. }
  1683. }
  1684. static int xgene_pmu_remove(struct platform_device *pdev)
  1685. {
  1686. struct xgene_pmu *xgene_pmu = dev_get_drvdata(&pdev->dev);
  1687. xgene_pmu_dev_cleanup(xgene_pmu, &xgene_pmu->l3cpmus);
  1688. xgene_pmu_dev_cleanup(xgene_pmu, &xgene_pmu->iobpmus);
  1689. xgene_pmu_dev_cleanup(xgene_pmu, &xgene_pmu->mcbpmus);
  1690. xgene_pmu_dev_cleanup(xgene_pmu, &xgene_pmu->mcpmus);
  1691. cpuhp_state_remove_instance(CPUHP_AP_PERF_ARM_APM_XGENE_ONLINE,
  1692. &xgene_pmu->node);
  1693. return 0;
  1694. }
  1695. static struct platform_driver xgene_pmu_driver = {
  1696. .probe = xgene_pmu_probe,
  1697. .remove = xgene_pmu_remove,
  1698. .driver = {
  1699. .name = "xgene-pmu",
  1700. .of_match_table = xgene_pmu_of_match,
  1701. .acpi_match_table = ACPI_PTR(xgene_pmu_acpi_match),
  1702. .suppress_bind_attrs = true,
  1703. },
  1704. };
  1705. builtin_platform_driver(xgene_pmu_driver);