hisi_uncore_pmu.c 12 KB

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  1. // SPDX-License-Identifier: GPL-2.0-only
  2. /*
  3. * HiSilicon SoC Hardware event counters support
  4. *
  5. * Copyright (C) 2017 Hisilicon Limited
  6. * Author: Anurup M <anurup.m@huawei.com>
  7. * Shaokun Zhang <zhangshaokun@hisilicon.com>
  8. *
  9. * This code is based on the uncore PMUs like arm-cci and arm-ccn.
  10. */
  11. #include <linux/bitmap.h>
  12. #include <linux/bitops.h>
  13. #include <linux/bug.h>
  14. #include <linux/err.h>
  15. #include <linux/errno.h>
  16. #include <linux/interrupt.h>
  17. #include <asm/cputype.h>
  18. #include <asm/local64.h>
  19. #include "hisi_uncore_pmu.h"
  20. #define HISI_GET_EVENTID(ev) (ev->hw.config_base & 0xff)
  21. #define HISI_MAX_PERIOD(nr) (BIT_ULL(nr) - 1)
  22. /*
  23. * PMU format attributes
  24. */
  25. ssize_t hisi_format_sysfs_show(struct device *dev,
  26. struct device_attribute *attr, char *buf)
  27. {
  28. struct dev_ext_attribute *eattr;
  29. eattr = container_of(attr, struct dev_ext_attribute, attr);
  30. return sprintf(buf, "%s\n", (char *)eattr->var);
  31. }
  32. EXPORT_SYMBOL_GPL(hisi_format_sysfs_show);
  33. /*
  34. * PMU event attributes
  35. */
  36. ssize_t hisi_event_sysfs_show(struct device *dev,
  37. struct device_attribute *attr, char *page)
  38. {
  39. struct dev_ext_attribute *eattr;
  40. eattr = container_of(attr, struct dev_ext_attribute, attr);
  41. return sprintf(page, "config=0x%lx\n", (unsigned long)eattr->var);
  42. }
  43. EXPORT_SYMBOL_GPL(hisi_event_sysfs_show);
  44. /*
  45. * sysfs cpumask attributes. For uncore PMU, we only have a single CPU to show
  46. */
  47. ssize_t hisi_cpumask_sysfs_show(struct device *dev,
  48. struct device_attribute *attr, char *buf)
  49. {
  50. struct hisi_pmu *hisi_pmu = to_hisi_pmu(dev_get_drvdata(dev));
  51. return sprintf(buf, "%d\n", hisi_pmu->on_cpu);
  52. }
  53. EXPORT_SYMBOL_GPL(hisi_cpumask_sysfs_show);
  54. static bool hisi_validate_event_group(struct perf_event *event)
  55. {
  56. struct perf_event *sibling, *leader = event->group_leader;
  57. struct hisi_pmu *hisi_pmu = to_hisi_pmu(event->pmu);
  58. /* Include count for the event */
  59. int counters = 1;
  60. if (!is_software_event(leader)) {
  61. /*
  62. * We must NOT create groups containing mixed PMUs, although
  63. * software events are acceptable
  64. */
  65. if (leader->pmu != event->pmu)
  66. return false;
  67. /* Increment counter for the leader */
  68. if (leader != event)
  69. counters++;
  70. }
  71. for_each_sibling_event(sibling, event->group_leader) {
  72. if (is_software_event(sibling))
  73. continue;
  74. if (sibling->pmu != event->pmu)
  75. return false;
  76. /* Increment counter for each sibling */
  77. counters++;
  78. }
  79. /* The group can not count events more than the counters in the HW */
  80. return counters <= hisi_pmu->num_counters;
  81. }
  82. int hisi_uncore_pmu_counter_valid(struct hisi_pmu *hisi_pmu, int idx)
  83. {
  84. return idx >= 0 && idx < hisi_pmu->num_counters;
  85. }
  86. EXPORT_SYMBOL_GPL(hisi_uncore_pmu_counter_valid);
  87. int hisi_uncore_pmu_get_event_idx(struct perf_event *event)
  88. {
  89. struct hisi_pmu *hisi_pmu = to_hisi_pmu(event->pmu);
  90. unsigned long *used_mask = hisi_pmu->pmu_events.used_mask;
  91. u32 num_counters = hisi_pmu->num_counters;
  92. int idx;
  93. idx = find_first_zero_bit(used_mask, num_counters);
  94. if (idx == num_counters)
  95. return -EAGAIN;
  96. set_bit(idx, used_mask);
  97. return idx;
  98. }
  99. EXPORT_SYMBOL_GPL(hisi_uncore_pmu_get_event_idx);
  100. static void hisi_uncore_pmu_clear_event_idx(struct hisi_pmu *hisi_pmu, int idx)
  101. {
  102. if (!hisi_uncore_pmu_counter_valid(hisi_pmu, idx)) {
  103. dev_err(hisi_pmu->dev, "Unsupported event index:%d!\n", idx);
  104. return;
  105. }
  106. clear_bit(idx, hisi_pmu->pmu_events.used_mask);
  107. }
  108. int hisi_uncore_pmu_event_init(struct perf_event *event)
  109. {
  110. struct hw_perf_event *hwc = &event->hw;
  111. struct hisi_pmu *hisi_pmu;
  112. if (event->attr.type != event->pmu->type)
  113. return -ENOENT;
  114. /*
  115. * We do not support sampling as the counters are all
  116. * shared by all CPU cores in a CPU die(SCCL). Also we
  117. * do not support attach to a task(per-process mode)
  118. */
  119. if (is_sampling_event(event) || event->attach_state & PERF_ATTACH_TASK)
  120. return -EOPNOTSUPP;
  121. /*
  122. * The uncore counters not specific to any CPU, so cannot
  123. * support per-task
  124. */
  125. if (event->cpu < 0)
  126. return -EINVAL;
  127. /*
  128. * Validate if the events in group does not exceed the
  129. * available counters in hardware.
  130. */
  131. if (!hisi_validate_event_group(event))
  132. return -EINVAL;
  133. hisi_pmu = to_hisi_pmu(event->pmu);
  134. if (event->attr.config > hisi_pmu->check_event)
  135. return -EINVAL;
  136. if (hisi_pmu->on_cpu == -1)
  137. return -EINVAL;
  138. /*
  139. * We don't assign an index until we actually place the event onto
  140. * hardware. Use -1 to signify that we haven't decided where to put it
  141. * yet.
  142. */
  143. hwc->idx = -1;
  144. hwc->config_base = event->attr.config;
  145. /* Enforce to use the same CPU for all events in this PMU */
  146. event->cpu = hisi_pmu->on_cpu;
  147. return 0;
  148. }
  149. EXPORT_SYMBOL_GPL(hisi_uncore_pmu_event_init);
  150. /*
  151. * Set the counter to count the event that we're interested in,
  152. * and enable interrupt and counter.
  153. */
  154. static void hisi_uncore_pmu_enable_event(struct perf_event *event)
  155. {
  156. struct hisi_pmu *hisi_pmu = to_hisi_pmu(event->pmu);
  157. struct hw_perf_event *hwc = &event->hw;
  158. hisi_pmu->ops->write_evtype(hisi_pmu, hwc->idx,
  159. HISI_GET_EVENTID(event));
  160. hisi_pmu->ops->enable_counter_int(hisi_pmu, hwc);
  161. hisi_pmu->ops->enable_counter(hisi_pmu, hwc);
  162. }
  163. /*
  164. * Disable counter and interrupt.
  165. */
  166. static void hisi_uncore_pmu_disable_event(struct perf_event *event)
  167. {
  168. struct hisi_pmu *hisi_pmu = to_hisi_pmu(event->pmu);
  169. struct hw_perf_event *hwc = &event->hw;
  170. hisi_pmu->ops->disable_counter(hisi_pmu, hwc);
  171. hisi_pmu->ops->disable_counter_int(hisi_pmu, hwc);
  172. }
  173. void hisi_uncore_pmu_set_event_period(struct perf_event *event)
  174. {
  175. struct hisi_pmu *hisi_pmu = to_hisi_pmu(event->pmu);
  176. struct hw_perf_event *hwc = &event->hw;
  177. /*
  178. * The HiSilicon PMU counters support 32 bits or 48 bits, depending on
  179. * the PMU. We reduce it to 2^(counter_bits - 1) to account for the
  180. * extreme interrupt latency. So we could hopefully handle the overflow
  181. * interrupt before another 2^(counter_bits - 1) events occur and the
  182. * counter overtakes its previous value.
  183. */
  184. u64 val = BIT_ULL(hisi_pmu->counter_bits - 1);
  185. local64_set(&hwc->prev_count, val);
  186. /* Write start value to the hardware event counter */
  187. hisi_pmu->ops->write_counter(hisi_pmu, hwc, val);
  188. }
  189. EXPORT_SYMBOL_GPL(hisi_uncore_pmu_set_event_period);
  190. void hisi_uncore_pmu_event_update(struct perf_event *event)
  191. {
  192. struct hisi_pmu *hisi_pmu = to_hisi_pmu(event->pmu);
  193. struct hw_perf_event *hwc = &event->hw;
  194. u64 delta, prev_raw_count, new_raw_count;
  195. do {
  196. /* Read the count from the counter register */
  197. new_raw_count = hisi_pmu->ops->read_counter(hisi_pmu, hwc);
  198. prev_raw_count = local64_read(&hwc->prev_count);
  199. } while (local64_cmpxchg(&hwc->prev_count, prev_raw_count,
  200. new_raw_count) != prev_raw_count);
  201. /*
  202. * compute the delta
  203. */
  204. delta = (new_raw_count - prev_raw_count) &
  205. HISI_MAX_PERIOD(hisi_pmu->counter_bits);
  206. local64_add(delta, &event->count);
  207. }
  208. EXPORT_SYMBOL_GPL(hisi_uncore_pmu_event_update);
  209. void hisi_uncore_pmu_start(struct perf_event *event, int flags)
  210. {
  211. struct hisi_pmu *hisi_pmu = to_hisi_pmu(event->pmu);
  212. struct hw_perf_event *hwc = &event->hw;
  213. if (WARN_ON_ONCE(!(hwc->state & PERF_HES_STOPPED)))
  214. return;
  215. WARN_ON_ONCE(!(hwc->state & PERF_HES_UPTODATE));
  216. hwc->state = 0;
  217. hisi_uncore_pmu_set_event_period(event);
  218. if (flags & PERF_EF_RELOAD) {
  219. u64 prev_raw_count = local64_read(&hwc->prev_count);
  220. hisi_pmu->ops->write_counter(hisi_pmu, hwc, prev_raw_count);
  221. }
  222. hisi_uncore_pmu_enable_event(event);
  223. perf_event_update_userpage(event);
  224. }
  225. EXPORT_SYMBOL_GPL(hisi_uncore_pmu_start);
  226. void hisi_uncore_pmu_stop(struct perf_event *event, int flags)
  227. {
  228. struct hw_perf_event *hwc = &event->hw;
  229. hisi_uncore_pmu_disable_event(event);
  230. WARN_ON_ONCE(hwc->state & PERF_HES_STOPPED);
  231. hwc->state |= PERF_HES_STOPPED;
  232. if (hwc->state & PERF_HES_UPTODATE)
  233. return;
  234. /* Read hardware counter and update the perf counter statistics */
  235. hisi_uncore_pmu_event_update(event);
  236. hwc->state |= PERF_HES_UPTODATE;
  237. }
  238. EXPORT_SYMBOL_GPL(hisi_uncore_pmu_stop);
  239. int hisi_uncore_pmu_add(struct perf_event *event, int flags)
  240. {
  241. struct hisi_pmu *hisi_pmu = to_hisi_pmu(event->pmu);
  242. struct hw_perf_event *hwc = &event->hw;
  243. int idx;
  244. hwc->state = PERF_HES_STOPPED | PERF_HES_UPTODATE;
  245. /* Get an available counter index for counting */
  246. idx = hisi_pmu->ops->get_event_idx(event);
  247. if (idx < 0)
  248. return idx;
  249. event->hw.idx = idx;
  250. hisi_pmu->pmu_events.hw_events[idx] = event;
  251. if (flags & PERF_EF_START)
  252. hisi_uncore_pmu_start(event, PERF_EF_RELOAD);
  253. return 0;
  254. }
  255. EXPORT_SYMBOL_GPL(hisi_uncore_pmu_add);
  256. void hisi_uncore_pmu_del(struct perf_event *event, int flags)
  257. {
  258. struct hisi_pmu *hisi_pmu = to_hisi_pmu(event->pmu);
  259. struct hw_perf_event *hwc = &event->hw;
  260. hisi_uncore_pmu_stop(event, PERF_EF_UPDATE);
  261. hisi_uncore_pmu_clear_event_idx(hisi_pmu, hwc->idx);
  262. perf_event_update_userpage(event);
  263. hisi_pmu->pmu_events.hw_events[hwc->idx] = NULL;
  264. }
  265. EXPORT_SYMBOL_GPL(hisi_uncore_pmu_del);
  266. void hisi_uncore_pmu_read(struct perf_event *event)
  267. {
  268. /* Read hardware counter and update the perf counter statistics */
  269. hisi_uncore_pmu_event_update(event);
  270. }
  271. EXPORT_SYMBOL_GPL(hisi_uncore_pmu_read);
  272. void hisi_uncore_pmu_enable(struct pmu *pmu)
  273. {
  274. struct hisi_pmu *hisi_pmu = to_hisi_pmu(pmu);
  275. int enabled = bitmap_weight(hisi_pmu->pmu_events.used_mask,
  276. hisi_pmu->num_counters);
  277. if (!enabled)
  278. return;
  279. hisi_pmu->ops->start_counters(hisi_pmu);
  280. }
  281. EXPORT_SYMBOL_GPL(hisi_uncore_pmu_enable);
  282. void hisi_uncore_pmu_disable(struct pmu *pmu)
  283. {
  284. struct hisi_pmu *hisi_pmu = to_hisi_pmu(pmu);
  285. hisi_pmu->ops->stop_counters(hisi_pmu);
  286. }
  287. EXPORT_SYMBOL_GPL(hisi_uncore_pmu_disable);
  288. /*
  289. * The Super CPU Cluster (SCCL) and CPU Cluster (CCL) IDs can be
  290. * determined from the MPIDR_EL1, but the encoding varies by CPU:
  291. *
  292. * - For MT variants of TSV110:
  293. * SCCL is Aff2[7:3], CCL is Aff2[2:0]
  294. *
  295. * - For other MT parts:
  296. * SCCL is Aff3[7:0], CCL is Aff2[7:0]
  297. *
  298. * - For non-MT parts:
  299. * SCCL is Aff2[7:0], CCL is Aff1[7:0]
  300. */
  301. static void hisi_read_sccl_and_ccl_id(int *scclp, int *cclp)
  302. {
  303. u64 mpidr = read_cpuid_mpidr();
  304. int aff3 = MPIDR_AFFINITY_LEVEL(mpidr, 3);
  305. int aff2 = MPIDR_AFFINITY_LEVEL(mpidr, 2);
  306. int aff1 = MPIDR_AFFINITY_LEVEL(mpidr, 1);
  307. bool mt = mpidr & MPIDR_MT_BITMASK;
  308. int sccl, ccl;
  309. if (mt && read_cpuid_part_number() == HISI_CPU_PART_TSV110) {
  310. sccl = aff2 >> 3;
  311. ccl = aff2 & 0x7;
  312. } else if (mt) {
  313. sccl = aff3;
  314. ccl = aff2;
  315. } else {
  316. sccl = aff2;
  317. ccl = aff1;
  318. }
  319. if (scclp)
  320. *scclp = sccl;
  321. if (cclp)
  322. *cclp = ccl;
  323. }
  324. /*
  325. * Check whether the CPU is associated with this uncore PMU
  326. */
  327. static bool hisi_pmu_cpu_is_associated_pmu(struct hisi_pmu *hisi_pmu)
  328. {
  329. int sccl_id, ccl_id;
  330. if (hisi_pmu->ccl_id == -1) {
  331. /* If CCL_ID is -1, the PMU only shares the same SCCL */
  332. hisi_read_sccl_and_ccl_id(&sccl_id, NULL);
  333. return sccl_id == hisi_pmu->sccl_id;
  334. }
  335. hisi_read_sccl_and_ccl_id(&sccl_id, &ccl_id);
  336. return sccl_id == hisi_pmu->sccl_id && ccl_id == hisi_pmu->ccl_id;
  337. }
  338. int hisi_uncore_pmu_online_cpu(unsigned int cpu, struct hlist_node *node)
  339. {
  340. struct hisi_pmu *hisi_pmu = hlist_entry_safe(node, struct hisi_pmu,
  341. node);
  342. if (!hisi_pmu_cpu_is_associated_pmu(hisi_pmu))
  343. return 0;
  344. cpumask_set_cpu(cpu, &hisi_pmu->associated_cpus);
  345. /* If another CPU is already managing this PMU, simply return. */
  346. if (hisi_pmu->on_cpu != -1)
  347. return 0;
  348. /* Use this CPU in cpumask for event counting */
  349. hisi_pmu->on_cpu = cpu;
  350. /* Overflow interrupt also should use the same CPU */
  351. WARN_ON(irq_set_affinity_hint(hisi_pmu->irq, cpumask_of(cpu)));
  352. return 0;
  353. }
  354. EXPORT_SYMBOL_GPL(hisi_uncore_pmu_online_cpu);
  355. int hisi_uncore_pmu_offline_cpu(unsigned int cpu, struct hlist_node *node)
  356. {
  357. struct hisi_pmu *hisi_pmu = hlist_entry_safe(node, struct hisi_pmu,
  358. node);
  359. cpumask_t pmu_online_cpus;
  360. unsigned int target;
  361. if (!cpumask_test_and_clear_cpu(cpu, &hisi_pmu->associated_cpus))
  362. return 0;
  363. /* Nothing to do if this CPU doesn't own the PMU */
  364. if (hisi_pmu->on_cpu != cpu)
  365. return 0;
  366. /* Give up ownership of the PMU */
  367. hisi_pmu->on_cpu = -1;
  368. /* Choose a new CPU to migrate ownership of the PMU to */
  369. cpumask_and(&pmu_online_cpus, &hisi_pmu->associated_cpus,
  370. cpu_online_mask);
  371. target = cpumask_any_but(&pmu_online_cpus, cpu);
  372. if (target >= nr_cpu_ids)
  373. return 0;
  374. perf_pmu_migrate_context(&hisi_pmu->pmu, cpu, target);
  375. /* Use this CPU for event counting */
  376. hisi_pmu->on_cpu = target;
  377. WARN_ON(irq_set_affinity_hint(hisi_pmu->irq, cpumask_of(target)));
  378. return 0;
  379. }
  380. EXPORT_SYMBOL_GPL(hisi_uncore_pmu_offline_cpu);
  381. MODULE_LICENSE("GPL v2");