hisi_uncore_l3c_pmu.c 12 KB

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  1. // SPDX-License-Identifier: GPL-2.0-only
  2. /*
  3. * HiSilicon SoC L3C uncore Hardware event counters support
  4. *
  5. * Copyright (C) 2017 Hisilicon Limited
  6. * Author: Anurup M <anurup.m@huawei.com>
  7. * Shaokun Zhang <zhangshaokun@hisilicon.com>
  8. *
  9. * This code is based on the uncore PMUs like arm-cci and arm-ccn.
  10. */
  11. #include <linux/acpi.h>
  12. #include <linux/bug.h>
  13. #include <linux/cpuhotplug.h>
  14. #include <linux/interrupt.h>
  15. #include <linux/irq.h>
  16. #include <linux/list.h>
  17. #include <linux/platform_device.h>
  18. #include <linux/smp.h>
  19. #include "hisi_uncore_pmu.h"
  20. /* L3C register definition */
  21. #define L3C_PERF_CTRL 0x0408
  22. #define L3C_INT_MASK 0x0800
  23. #define L3C_INT_STATUS 0x0808
  24. #define L3C_INT_CLEAR 0x080c
  25. #define L3C_EVENT_CTRL 0x1c00
  26. #define L3C_EVENT_TYPE0 0x1d00
  27. /*
  28. * Each counter is 48-bits and [48:63] are reserved
  29. * which are Read-As-Zero and Writes-Ignored.
  30. */
  31. #define L3C_CNTR0_LOWER 0x1e00
  32. /* L3C has 8-counters */
  33. #define L3C_NR_COUNTERS 0x8
  34. #define L3C_PERF_CTRL_EN 0x10000
  35. #define L3C_EVTYPE_NONE 0xff
  36. /*
  37. * Select the counter register offset using the counter index
  38. */
  39. static u32 hisi_l3c_pmu_get_counter_offset(int cntr_idx)
  40. {
  41. return (L3C_CNTR0_LOWER + (cntr_idx * 8));
  42. }
  43. static u64 hisi_l3c_pmu_read_counter(struct hisi_pmu *l3c_pmu,
  44. struct hw_perf_event *hwc)
  45. {
  46. u32 idx = hwc->idx;
  47. if (!hisi_uncore_pmu_counter_valid(l3c_pmu, idx)) {
  48. dev_err(l3c_pmu->dev, "Unsupported event index:%d!\n", idx);
  49. return 0;
  50. }
  51. /* Read 64-bits and the upper 16 bits are RAZ */
  52. return readq(l3c_pmu->base + hisi_l3c_pmu_get_counter_offset(idx));
  53. }
  54. static void hisi_l3c_pmu_write_counter(struct hisi_pmu *l3c_pmu,
  55. struct hw_perf_event *hwc, u64 val)
  56. {
  57. u32 idx = hwc->idx;
  58. if (!hisi_uncore_pmu_counter_valid(l3c_pmu, idx)) {
  59. dev_err(l3c_pmu->dev, "Unsupported event index:%d!\n", idx);
  60. return;
  61. }
  62. /* Write 64-bits and the upper 16 bits are WI */
  63. writeq(val, l3c_pmu->base + hisi_l3c_pmu_get_counter_offset(idx));
  64. }
  65. static void hisi_l3c_pmu_write_evtype(struct hisi_pmu *l3c_pmu, int idx,
  66. u32 type)
  67. {
  68. u32 reg, reg_idx, shift, val;
  69. /*
  70. * Select the appropriate event select register(L3C_EVENT_TYPE0/1).
  71. * There are 2 event select registers for the 8 hardware counters.
  72. * Event code is 8-bits and for the former 4 hardware counters,
  73. * L3C_EVENT_TYPE0 is chosen. For the latter 4 hardware counters,
  74. * L3C_EVENT_TYPE1 is chosen.
  75. */
  76. reg = L3C_EVENT_TYPE0 + (idx / 4) * 4;
  77. reg_idx = idx % 4;
  78. shift = 8 * reg_idx;
  79. /* Write event code to L3C_EVENT_TYPEx Register */
  80. val = readl(l3c_pmu->base + reg);
  81. val &= ~(L3C_EVTYPE_NONE << shift);
  82. val |= (type << shift);
  83. writel(val, l3c_pmu->base + reg);
  84. }
  85. static void hisi_l3c_pmu_start_counters(struct hisi_pmu *l3c_pmu)
  86. {
  87. u32 val;
  88. /*
  89. * Set perf_enable bit in L3C_PERF_CTRL register to start counting
  90. * for all enabled counters.
  91. */
  92. val = readl(l3c_pmu->base + L3C_PERF_CTRL);
  93. val |= L3C_PERF_CTRL_EN;
  94. writel(val, l3c_pmu->base + L3C_PERF_CTRL);
  95. }
  96. static void hisi_l3c_pmu_stop_counters(struct hisi_pmu *l3c_pmu)
  97. {
  98. u32 val;
  99. /*
  100. * Clear perf_enable bit in L3C_PERF_CTRL register to stop counting
  101. * for all enabled counters.
  102. */
  103. val = readl(l3c_pmu->base + L3C_PERF_CTRL);
  104. val &= ~(L3C_PERF_CTRL_EN);
  105. writel(val, l3c_pmu->base + L3C_PERF_CTRL);
  106. }
  107. static void hisi_l3c_pmu_enable_counter(struct hisi_pmu *l3c_pmu,
  108. struct hw_perf_event *hwc)
  109. {
  110. u32 val;
  111. /* Enable counter index in L3C_EVENT_CTRL register */
  112. val = readl(l3c_pmu->base + L3C_EVENT_CTRL);
  113. val |= (1 << hwc->idx);
  114. writel(val, l3c_pmu->base + L3C_EVENT_CTRL);
  115. }
  116. static void hisi_l3c_pmu_disable_counter(struct hisi_pmu *l3c_pmu,
  117. struct hw_perf_event *hwc)
  118. {
  119. u32 val;
  120. /* Clear counter index in L3C_EVENT_CTRL register */
  121. val = readl(l3c_pmu->base + L3C_EVENT_CTRL);
  122. val &= ~(1 << hwc->idx);
  123. writel(val, l3c_pmu->base + L3C_EVENT_CTRL);
  124. }
  125. static void hisi_l3c_pmu_enable_counter_int(struct hisi_pmu *l3c_pmu,
  126. struct hw_perf_event *hwc)
  127. {
  128. u32 val;
  129. val = readl(l3c_pmu->base + L3C_INT_MASK);
  130. /* Write 0 to enable interrupt */
  131. val &= ~(1 << hwc->idx);
  132. writel(val, l3c_pmu->base + L3C_INT_MASK);
  133. }
  134. static void hisi_l3c_pmu_disable_counter_int(struct hisi_pmu *l3c_pmu,
  135. struct hw_perf_event *hwc)
  136. {
  137. u32 val;
  138. val = readl(l3c_pmu->base + L3C_INT_MASK);
  139. /* Write 1 to mask interrupt */
  140. val |= (1 << hwc->idx);
  141. writel(val, l3c_pmu->base + L3C_INT_MASK);
  142. }
  143. static irqreturn_t hisi_l3c_pmu_isr(int irq, void *dev_id)
  144. {
  145. struct hisi_pmu *l3c_pmu = dev_id;
  146. struct perf_event *event;
  147. unsigned long overflown;
  148. int idx;
  149. /* Read L3C_INT_STATUS register */
  150. overflown = readl(l3c_pmu->base + L3C_INT_STATUS);
  151. if (!overflown)
  152. return IRQ_NONE;
  153. /*
  154. * Find the counter index which overflowed if the bit was set
  155. * and handle it.
  156. */
  157. for_each_set_bit(idx, &overflown, L3C_NR_COUNTERS) {
  158. /* Write 1 to clear the IRQ status flag */
  159. writel((1 << idx), l3c_pmu->base + L3C_INT_CLEAR);
  160. /* Get the corresponding event struct */
  161. event = l3c_pmu->pmu_events.hw_events[idx];
  162. if (!event)
  163. continue;
  164. hisi_uncore_pmu_event_update(event);
  165. hisi_uncore_pmu_set_event_period(event);
  166. }
  167. return IRQ_HANDLED;
  168. }
  169. static int hisi_l3c_pmu_init_irq(struct hisi_pmu *l3c_pmu,
  170. struct platform_device *pdev)
  171. {
  172. int irq, ret;
  173. /* Read and init IRQ */
  174. irq = platform_get_irq(pdev, 0);
  175. if (irq < 0)
  176. return irq;
  177. ret = devm_request_irq(&pdev->dev, irq, hisi_l3c_pmu_isr,
  178. IRQF_NOBALANCING | IRQF_NO_THREAD,
  179. dev_name(&pdev->dev), l3c_pmu);
  180. if (ret < 0) {
  181. dev_err(&pdev->dev,
  182. "Fail to request IRQ:%d ret:%d\n", irq, ret);
  183. return ret;
  184. }
  185. l3c_pmu->irq = irq;
  186. return 0;
  187. }
  188. static const struct acpi_device_id hisi_l3c_pmu_acpi_match[] = {
  189. { "HISI0213", },
  190. {},
  191. };
  192. MODULE_DEVICE_TABLE(acpi, hisi_l3c_pmu_acpi_match);
  193. static int hisi_l3c_pmu_init_data(struct platform_device *pdev,
  194. struct hisi_pmu *l3c_pmu)
  195. {
  196. unsigned long long id;
  197. acpi_status status;
  198. status = acpi_evaluate_integer(ACPI_HANDLE(&pdev->dev),
  199. "_UID", NULL, &id);
  200. if (ACPI_FAILURE(status))
  201. return -EINVAL;
  202. l3c_pmu->index_id = id;
  203. /*
  204. * Use the SCCL_ID and CCL_ID to identify the L3C PMU, while
  205. * SCCL_ID is in MPIDR[aff2] and CCL_ID is in MPIDR[aff1].
  206. */
  207. if (device_property_read_u32(&pdev->dev, "hisilicon,scl-id",
  208. &l3c_pmu->sccl_id)) {
  209. dev_err(&pdev->dev, "Can not read l3c sccl-id!\n");
  210. return -EINVAL;
  211. }
  212. if (device_property_read_u32(&pdev->dev, "hisilicon,ccl-id",
  213. &l3c_pmu->ccl_id)) {
  214. dev_err(&pdev->dev, "Can not read l3c ccl-id!\n");
  215. return -EINVAL;
  216. }
  217. l3c_pmu->base = devm_platform_ioremap_resource(pdev, 0);
  218. if (IS_ERR(l3c_pmu->base)) {
  219. dev_err(&pdev->dev, "ioremap failed for l3c_pmu resource\n");
  220. return PTR_ERR(l3c_pmu->base);
  221. }
  222. return 0;
  223. }
  224. static struct attribute *hisi_l3c_pmu_format_attr[] = {
  225. HISI_PMU_FORMAT_ATTR(event, "config:0-7"),
  226. NULL,
  227. };
  228. static const struct attribute_group hisi_l3c_pmu_format_group = {
  229. .name = "format",
  230. .attrs = hisi_l3c_pmu_format_attr,
  231. };
  232. static struct attribute *hisi_l3c_pmu_events_attr[] = {
  233. HISI_PMU_EVENT_ATTR(rd_cpipe, 0x00),
  234. HISI_PMU_EVENT_ATTR(wr_cpipe, 0x01),
  235. HISI_PMU_EVENT_ATTR(rd_hit_cpipe, 0x02),
  236. HISI_PMU_EVENT_ATTR(wr_hit_cpipe, 0x03),
  237. HISI_PMU_EVENT_ATTR(victim_num, 0x04),
  238. HISI_PMU_EVENT_ATTR(rd_spipe, 0x20),
  239. HISI_PMU_EVENT_ATTR(wr_spipe, 0x21),
  240. HISI_PMU_EVENT_ATTR(rd_hit_spipe, 0x22),
  241. HISI_PMU_EVENT_ATTR(wr_hit_spipe, 0x23),
  242. HISI_PMU_EVENT_ATTR(back_invalid, 0x29),
  243. HISI_PMU_EVENT_ATTR(retry_cpu, 0x40),
  244. HISI_PMU_EVENT_ATTR(retry_ring, 0x41),
  245. HISI_PMU_EVENT_ATTR(prefetch_drop, 0x42),
  246. NULL,
  247. };
  248. static const struct attribute_group hisi_l3c_pmu_events_group = {
  249. .name = "events",
  250. .attrs = hisi_l3c_pmu_events_attr,
  251. };
  252. static DEVICE_ATTR(cpumask, 0444, hisi_cpumask_sysfs_show, NULL);
  253. static struct attribute *hisi_l3c_pmu_cpumask_attrs[] = {
  254. &dev_attr_cpumask.attr,
  255. NULL,
  256. };
  257. static const struct attribute_group hisi_l3c_pmu_cpumask_attr_group = {
  258. .attrs = hisi_l3c_pmu_cpumask_attrs,
  259. };
  260. static const struct attribute_group *hisi_l3c_pmu_attr_groups[] = {
  261. &hisi_l3c_pmu_format_group,
  262. &hisi_l3c_pmu_events_group,
  263. &hisi_l3c_pmu_cpumask_attr_group,
  264. NULL,
  265. };
  266. static const struct hisi_uncore_ops hisi_uncore_l3c_ops = {
  267. .write_evtype = hisi_l3c_pmu_write_evtype,
  268. .get_event_idx = hisi_uncore_pmu_get_event_idx,
  269. .start_counters = hisi_l3c_pmu_start_counters,
  270. .stop_counters = hisi_l3c_pmu_stop_counters,
  271. .enable_counter = hisi_l3c_pmu_enable_counter,
  272. .disable_counter = hisi_l3c_pmu_disable_counter,
  273. .enable_counter_int = hisi_l3c_pmu_enable_counter_int,
  274. .disable_counter_int = hisi_l3c_pmu_disable_counter_int,
  275. .write_counter = hisi_l3c_pmu_write_counter,
  276. .read_counter = hisi_l3c_pmu_read_counter,
  277. };
  278. static int hisi_l3c_pmu_dev_probe(struct platform_device *pdev,
  279. struct hisi_pmu *l3c_pmu)
  280. {
  281. int ret;
  282. ret = hisi_l3c_pmu_init_data(pdev, l3c_pmu);
  283. if (ret)
  284. return ret;
  285. ret = hisi_l3c_pmu_init_irq(l3c_pmu, pdev);
  286. if (ret)
  287. return ret;
  288. l3c_pmu->num_counters = L3C_NR_COUNTERS;
  289. l3c_pmu->counter_bits = 48;
  290. l3c_pmu->ops = &hisi_uncore_l3c_ops;
  291. l3c_pmu->dev = &pdev->dev;
  292. l3c_pmu->on_cpu = -1;
  293. l3c_pmu->check_event = 0x59;
  294. return 0;
  295. }
  296. static int hisi_l3c_pmu_probe(struct platform_device *pdev)
  297. {
  298. struct hisi_pmu *l3c_pmu;
  299. char *name;
  300. int ret;
  301. l3c_pmu = devm_kzalloc(&pdev->dev, sizeof(*l3c_pmu), GFP_KERNEL);
  302. if (!l3c_pmu)
  303. return -ENOMEM;
  304. platform_set_drvdata(pdev, l3c_pmu);
  305. ret = hisi_l3c_pmu_dev_probe(pdev, l3c_pmu);
  306. if (ret)
  307. return ret;
  308. ret = cpuhp_state_add_instance(CPUHP_AP_PERF_ARM_HISI_L3_ONLINE,
  309. &l3c_pmu->node);
  310. if (ret) {
  311. dev_err(&pdev->dev, "Error %d registering hotplug\n", ret);
  312. return ret;
  313. }
  314. name = devm_kasprintf(&pdev->dev, GFP_KERNEL, "hisi_sccl%u_l3c%u",
  315. l3c_pmu->sccl_id, l3c_pmu->index_id);
  316. l3c_pmu->pmu = (struct pmu) {
  317. .name = name,
  318. .module = THIS_MODULE,
  319. .task_ctx_nr = perf_invalid_context,
  320. .event_init = hisi_uncore_pmu_event_init,
  321. .pmu_enable = hisi_uncore_pmu_enable,
  322. .pmu_disable = hisi_uncore_pmu_disable,
  323. .add = hisi_uncore_pmu_add,
  324. .del = hisi_uncore_pmu_del,
  325. .start = hisi_uncore_pmu_start,
  326. .stop = hisi_uncore_pmu_stop,
  327. .read = hisi_uncore_pmu_read,
  328. .attr_groups = hisi_l3c_pmu_attr_groups,
  329. .capabilities = PERF_PMU_CAP_NO_EXCLUDE,
  330. };
  331. ret = perf_pmu_register(&l3c_pmu->pmu, name, -1);
  332. if (ret) {
  333. dev_err(l3c_pmu->dev, "L3C PMU register failed!\n");
  334. cpuhp_state_remove_instance_nocalls(
  335. CPUHP_AP_PERF_ARM_HISI_L3_ONLINE, &l3c_pmu->node);
  336. irq_set_affinity_hint(l3c_pmu->irq, NULL);
  337. }
  338. return ret;
  339. }
  340. static int hisi_l3c_pmu_remove(struct platform_device *pdev)
  341. {
  342. struct hisi_pmu *l3c_pmu = platform_get_drvdata(pdev);
  343. perf_pmu_unregister(&l3c_pmu->pmu);
  344. cpuhp_state_remove_instance_nocalls(CPUHP_AP_PERF_ARM_HISI_L3_ONLINE,
  345. &l3c_pmu->node);
  346. irq_set_affinity_hint(l3c_pmu->irq, NULL);
  347. return 0;
  348. }
  349. static struct platform_driver hisi_l3c_pmu_driver = {
  350. .driver = {
  351. .name = "hisi_l3c_pmu",
  352. .acpi_match_table = ACPI_PTR(hisi_l3c_pmu_acpi_match),
  353. .suppress_bind_attrs = true,
  354. },
  355. .probe = hisi_l3c_pmu_probe,
  356. .remove = hisi_l3c_pmu_remove,
  357. };
  358. static int __init hisi_l3c_pmu_module_init(void)
  359. {
  360. int ret;
  361. ret = cpuhp_setup_state_multi(CPUHP_AP_PERF_ARM_HISI_L3_ONLINE,
  362. "AP_PERF_ARM_HISI_L3_ONLINE",
  363. hisi_uncore_pmu_online_cpu,
  364. hisi_uncore_pmu_offline_cpu);
  365. if (ret) {
  366. pr_err("L3C PMU: Error setup hotplug, ret = %d\n", ret);
  367. return ret;
  368. }
  369. ret = platform_driver_register(&hisi_l3c_pmu_driver);
  370. if (ret)
  371. cpuhp_remove_multi_state(CPUHP_AP_PERF_ARM_HISI_L3_ONLINE);
  372. return ret;
  373. }
  374. module_init(hisi_l3c_pmu_module_init);
  375. static void __exit hisi_l3c_pmu_module_exit(void)
  376. {
  377. platform_driver_unregister(&hisi_l3c_pmu_driver);
  378. cpuhp_remove_multi_state(CPUHP_AP_PERF_ARM_HISI_L3_ONLINE);
  379. }
  380. module_exit(hisi_l3c_pmu_module_exit);
  381. MODULE_DESCRIPTION("HiSilicon SoC L3C uncore PMU driver");
  382. MODULE_LICENSE("GPL v2");
  383. MODULE_AUTHOR("Anurup M <anurup.m@huawei.com>");
  384. MODULE_AUTHOR("Shaokun Zhang <zhangshaokun@hisilicon.com>");