hisi_uncore_hha_pmu.c 12 KB

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  1. // SPDX-License-Identifier: GPL-2.0-only
  2. /*
  3. * HiSilicon SoC HHA uncore Hardware event counters support
  4. *
  5. * Copyright (C) 2017 Hisilicon Limited
  6. * Author: Shaokun Zhang <zhangshaokun@hisilicon.com>
  7. * Anurup M <anurup.m@huawei.com>
  8. *
  9. * This code is based on the uncore PMUs like arm-cci and arm-ccn.
  10. */
  11. #include <linux/acpi.h>
  12. #include <linux/bug.h>
  13. #include <linux/cpuhotplug.h>
  14. #include <linux/interrupt.h>
  15. #include <linux/irq.h>
  16. #include <linux/list.h>
  17. #include <linux/platform_device.h>
  18. #include <linux/smp.h>
  19. #include "hisi_uncore_pmu.h"
  20. /* HHA register definition */
  21. #define HHA_INT_MASK 0x0804
  22. #define HHA_INT_STATUS 0x0808
  23. #define HHA_INT_CLEAR 0x080C
  24. #define HHA_PERF_CTRL 0x1E00
  25. #define HHA_EVENT_CTRL 0x1E04
  26. #define HHA_EVENT_TYPE0 0x1E80
  27. /*
  28. * Each counter is 48-bits and [48:63] are reserved
  29. * which are Read-As-Zero and Writes-Ignored.
  30. */
  31. #define HHA_CNT0_LOWER 0x1F00
  32. /* HHA has 16-counters */
  33. #define HHA_NR_COUNTERS 0x10
  34. #define HHA_PERF_CTRL_EN 0x1
  35. #define HHA_EVTYPE_NONE 0xff
  36. /*
  37. * Select the counter register offset using the counter index
  38. * each counter is 48-bits.
  39. */
  40. static u32 hisi_hha_pmu_get_counter_offset(int cntr_idx)
  41. {
  42. return (HHA_CNT0_LOWER + (cntr_idx * 8));
  43. }
  44. static u64 hisi_hha_pmu_read_counter(struct hisi_pmu *hha_pmu,
  45. struct hw_perf_event *hwc)
  46. {
  47. u32 idx = hwc->idx;
  48. if (!hisi_uncore_pmu_counter_valid(hha_pmu, idx)) {
  49. dev_err(hha_pmu->dev, "Unsupported event index:%d!\n", idx);
  50. return 0;
  51. }
  52. /* Read 64 bits and like L3C, top 16 bits are RAZ */
  53. return readq(hha_pmu->base + hisi_hha_pmu_get_counter_offset(idx));
  54. }
  55. static void hisi_hha_pmu_write_counter(struct hisi_pmu *hha_pmu,
  56. struct hw_perf_event *hwc, u64 val)
  57. {
  58. u32 idx = hwc->idx;
  59. if (!hisi_uncore_pmu_counter_valid(hha_pmu, idx)) {
  60. dev_err(hha_pmu->dev, "Unsupported event index:%d!\n", idx);
  61. return;
  62. }
  63. /* Write 64 bits and like L3C, top 16 bits are WI */
  64. writeq(val, hha_pmu->base + hisi_hha_pmu_get_counter_offset(idx));
  65. }
  66. static void hisi_hha_pmu_write_evtype(struct hisi_pmu *hha_pmu, int idx,
  67. u32 type)
  68. {
  69. u32 reg, reg_idx, shift, val;
  70. /*
  71. * Select the appropriate event select register(HHA_EVENT_TYPEx).
  72. * There are 4 event select registers for the 16 hardware counters.
  73. * Event code is 8-bits and for the first 4 hardware counters,
  74. * HHA_EVENT_TYPE0 is chosen. For the next 4 hardware counters,
  75. * HHA_EVENT_TYPE1 is chosen and so on.
  76. */
  77. reg = HHA_EVENT_TYPE0 + 4 * (idx / 4);
  78. reg_idx = idx % 4;
  79. shift = 8 * reg_idx;
  80. /* Write event code to HHA_EVENT_TYPEx register */
  81. val = readl(hha_pmu->base + reg);
  82. val &= ~(HHA_EVTYPE_NONE << shift);
  83. val |= (type << shift);
  84. writel(val, hha_pmu->base + reg);
  85. }
  86. static void hisi_hha_pmu_start_counters(struct hisi_pmu *hha_pmu)
  87. {
  88. u32 val;
  89. /*
  90. * Set perf_enable bit in HHA_PERF_CTRL to start event
  91. * counting for all enabled counters.
  92. */
  93. val = readl(hha_pmu->base + HHA_PERF_CTRL);
  94. val |= HHA_PERF_CTRL_EN;
  95. writel(val, hha_pmu->base + HHA_PERF_CTRL);
  96. }
  97. static void hisi_hha_pmu_stop_counters(struct hisi_pmu *hha_pmu)
  98. {
  99. u32 val;
  100. /*
  101. * Clear perf_enable bit in HHA_PERF_CTRL to stop event
  102. * counting for all enabled counters.
  103. */
  104. val = readl(hha_pmu->base + HHA_PERF_CTRL);
  105. val &= ~(HHA_PERF_CTRL_EN);
  106. writel(val, hha_pmu->base + HHA_PERF_CTRL);
  107. }
  108. static void hisi_hha_pmu_enable_counter(struct hisi_pmu *hha_pmu,
  109. struct hw_perf_event *hwc)
  110. {
  111. u32 val;
  112. /* Enable counter index in HHA_EVENT_CTRL register */
  113. val = readl(hha_pmu->base + HHA_EVENT_CTRL);
  114. val |= (1 << hwc->idx);
  115. writel(val, hha_pmu->base + HHA_EVENT_CTRL);
  116. }
  117. static void hisi_hha_pmu_disable_counter(struct hisi_pmu *hha_pmu,
  118. struct hw_perf_event *hwc)
  119. {
  120. u32 val;
  121. /* Clear counter index in HHA_EVENT_CTRL register */
  122. val = readl(hha_pmu->base + HHA_EVENT_CTRL);
  123. val &= ~(1 << hwc->idx);
  124. writel(val, hha_pmu->base + HHA_EVENT_CTRL);
  125. }
  126. static void hisi_hha_pmu_enable_counter_int(struct hisi_pmu *hha_pmu,
  127. struct hw_perf_event *hwc)
  128. {
  129. u32 val;
  130. /* Write 0 to enable interrupt */
  131. val = readl(hha_pmu->base + HHA_INT_MASK);
  132. val &= ~(1 << hwc->idx);
  133. writel(val, hha_pmu->base + HHA_INT_MASK);
  134. }
  135. static void hisi_hha_pmu_disable_counter_int(struct hisi_pmu *hha_pmu,
  136. struct hw_perf_event *hwc)
  137. {
  138. u32 val;
  139. /* Write 1 to mask interrupt */
  140. val = readl(hha_pmu->base + HHA_INT_MASK);
  141. val |= (1 << hwc->idx);
  142. writel(val, hha_pmu->base + HHA_INT_MASK);
  143. }
  144. static irqreturn_t hisi_hha_pmu_isr(int irq, void *dev_id)
  145. {
  146. struct hisi_pmu *hha_pmu = dev_id;
  147. struct perf_event *event;
  148. unsigned long overflown;
  149. int idx;
  150. /* Read HHA_INT_STATUS register */
  151. overflown = readl(hha_pmu->base + HHA_INT_STATUS);
  152. if (!overflown)
  153. return IRQ_NONE;
  154. /*
  155. * Find the counter index which overflowed if the bit was set
  156. * and handle it
  157. */
  158. for_each_set_bit(idx, &overflown, HHA_NR_COUNTERS) {
  159. /* Write 1 to clear the IRQ status flag */
  160. writel((1 << idx), hha_pmu->base + HHA_INT_CLEAR);
  161. /* Get the corresponding event struct */
  162. event = hha_pmu->pmu_events.hw_events[idx];
  163. if (!event)
  164. continue;
  165. hisi_uncore_pmu_event_update(event);
  166. hisi_uncore_pmu_set_event_period(event);
  167. }
  168. return IRQ_HANDLED;
  169. }
  170. static int hisi_hha_pmu_init_irq(struct hisi_pmu *hha_pmu,
  171. struct platform_device *pdev)
  172. {
  173. int irq, ret;
  174. /* Read and init IRQ */
  175. irq = platform_get_irq(pdev, 0);
  176. if (irq < 0)
  177. return irq;
  178. ret = devm_request_irq(&pdev->dev, irq, hisi_hha_pmu_isr,
  179. IRQF_NOBALANCING | IRQF_NO_THREAD,
  180. dev_name(&pdev->dev), hha_pmu);
  181. if (ret < 0) {
  182. dev_err(&pdev->dev,
  183. "Fail to request IRQ:%d ret:%d\n", irq, ret);
  184. return ret;
  185. }
  186. hha_pmu->irq = irq;
  187. return 0;
  188. }
  189. static const struct acpi_device_id hisi_hha_pmu_acpi_match[] = {
  190. { "HISI0243", },
  191. {},
  192. };
  193. MODULE_DEVICE_TABLE(acpi, hisi_hha_pmu_acpi_match);
  194. static int hisi_hha_pmu_init_data(struct platform_device *pdev,
  195. struct hisi_pmu *hha_pmu)
  196. {
  197. unsigned long long id;
  198. acpi_status status;
  199. status = acpi_evaluate_integer(ACPI_HANDLE(&pdev->dev),
  200. "_UID", NULL, &id);
  201. if (ACPI_FAILURE(status))
  202. return -EINVAL;
  203. hha_pmu->index_id = id;
  204. /*
  205. * Use SCCL_ID and UID to identify the HHA PMU, while
  206. * SCCL_ID is in MPIDR[aff2].
  207. */
  208. if (device_property_read_u32(&pdev->dev, "hisilicon,scl-id",
  209. &hha_pmu->sccl_id)) {
  210. dev_err(&pdev->dev, "Can not read hha sccl-id!\n");
  211. return -EINVAL;
  212. }
  213. /* HHA PMUs only share the same SCCL */
  214. hha_pmu->ccl_id = -1;
  215. hha_pmu->base = devm_platform_ioremap_resource(pdev, 0);
  216. if (IS_ERR(hha_pmu->base)) {
  217. dev_err(&pdev->dev, "ioremap failed for hha_pmu resource\n");
  218. return PTR_ERR(hha_pmu->base);
  219. }
  220. return 0;
  221. }
  222. static struct attribute *hisi_hha_pmu_format_attr[] = {
  223. HISI_PMU_FORMAT_ATTR(event, "config:0-7"),
  224. NULL,
  225. };
  226. static const struct attribute_group hisi_hha_pmu_format_group = {
  227. .name = "format",
  228. .attrs = hisi_hha_pmu_format_attr,
  229. };
  230. static struct attribute *hisi_hha_pmu_events_attr[] = {
  231. HISI_PMU_EVENT_ATTR(rx_ops_num, 0x00),
  232. HISI_PMU_EVENT_ATTR(rx_outer, 0x01),
  233. HISI_PMU_EVENT_ATTR(rx_sccl, 0x02),
  234. HISI_PMU_EVENT_ATTR(rx_ccix, 0x03),
  235. HISI_PMU_EVENT_ATTR(rx_wbi, 0x04),
  236. HISI_PMU_EVENT_ATTR(rx_wbip, 0x05),
  237. HISI_PMU_EVENT_ATTR(rx_wtistash, 0x11),
  238. HISI_PMU_EVENT_ATTR(rd_ddr_64b, 0x1c),
  239. HISI_PMU_EVENT_ATTR(wr_ddr_64b, 0x1d),
  240. HISI_PMU_EVENT_ATTR(rd_ddr_128b, 0x1e),
  241. HISI_PMU_EVENT_ATTR(wr_ddr_128b, 0x1f),
  242. HISI_PMU_EVENT_ATTR(spill_num, 0x20),
  243. HISI_PMU_EVENT_ATTR(spill_success, 0x21),
  244. HISI_PMU_EVENT_ATTR(bi_num, 0x23),
  245. HISI_PMU_EVENT_ATTR(mediated_num, 0x32),
  246. HISI_PMU_EVENT_ATTR(tx_snp_num, 0x33),
  247. HISI_PMU_EVENT_ATTR(tx_snp_outer, 0x34),
  248. HISI_PMU_EVENT_ATTR(tx_snp_ccix, 0x35),
  249. HISI_PMU_EVENT_ATTR(rx_snprspdata, 0x38),
  250. HISI_PMU_EVENT_ATTR(rx_snprsp_outer, 0x3c),
  251. HISI_PMU_EVENT_ATTR(sdir-lookup, 0x40),
  252. HISI_PMU_EVENT_ATTR(edir-lookup, 0x41),
  253. HISI_PMU_EVENT_ATTR(sdir-hit, 0x42),
  254. HISI_PMU_EVENT_ATTR(edir-hit, 0x43),
  255. HISI_PMU_EVENT_ATTR(sdir-home-migrate, 0x4c),
  256. HISI_PMU_EVENT_ATTR(edir-home-migrate, 0x4d),
  257. NULL,
  258. };
  259. static const struct attribute_group hisi_hha_pmu_events_group = {
  260. .name = "events",
  261. .attrs = hisi_hha_pmu_events_attr,
  262. };
  263. static DEVICE_ATTR(cpumask, 0444, hisi_cpumask_sysfs_show, NULL);
  264. static struct attribute *hisi_hha_pmu_cpumask_attrs[] = {
  265. &dev_attr_cpumask.attr,
  266. NULL,
  267. };
  268. static const struct attribute_group hisi_hha_pmu_cpumask_attr_group = {
  269. .attrs = hisi_hha_pmu_cpumask_attrs,
  270. };
  271. static const struct attribute_group *hisi_hha_pmu_attr_groups[] = {
  272. &hisi_hha_pmu_format_group,
  273. &hisi_hha_pmu_events_group,
  274. &hisi_hha_pmu_cpumask_attr_group,
  275. NULL,
  276. };
  277. static const struct hisi_uncore_ops hisi_uncore_hha_ops = {
  278. .write_evtype = hisi_hha_pmu_write_evtype,
  279. .get_event_idx = hisi_uncore_pmu_get_event_idx,
  280. .start_counters = hisi_hha_pmu_start_counters,
  281. .stop_counters = hisi_hha_pmu_stop_counters,
  282. .enable_counter = hisi_hha_pmu_enable_counter,
  283. .disable_counter = hisi_hha_pmu_disable_counter,
  284. .enable_counter_int = hisi_hha_pmu_enable_counter_int,
  285. .disable_counter_int = hisi_hha_pmu_disable_counter_int,
  286. .write_counter = hisi_hha_pmu_write_counter,
  287. .read_counter = hisi_hha_pmu_read_counter,
  288. };
  289. static int hisi_hha_pmu_dev_probe(struct platform_device *pdev,
  290. struct hisi_pmu *hha_pmu)
  291. {
  292. int ret;
  293. ret = hisi_hha_pmu_init_data(pdev, hha_pmu);
  294. if (ret)
  295. return ret;
  296. ret = hisi_hha_pmu_init_irq(hha_pmu, pdev);
  297. if (ret)
  298. return ret;
  299. hha_pmu->num_counters = HHA_NR_COUNTERS;
  300. hha_pmu->counter_bits = 48;
  301. hha_pmu->ops = &hisi_uncore_hha_ops;
  302. hha_pmu->dev = &pdev->dev;
  303. hha_pmu->on_cpu = -1;
  304. hha_pmu->check_event = 0x65;
  305. return 0;
  306. }
  307. static int hisi_hha_pmu_probe(struct platform_device *pdev)
  308. {
  309. struct hisi_pmu *hha_pmu;
  310. char *name;
  311. int ret;
  312. hha_pmu = devm_kzalloc(&pdev->dev, sizeof(*hha_pmu), GFP_KERNEL);
  313. if (!hha_pmu)
  314. return -ENOMEM;
  315. platform_set_drvdata(pdev, hha_pmu);
  316. ret = hisi_hha_pmu_dev_probe(pdev, hha_pmu);
  317. if (ret)
  318. return ret;
  319. ret = cpuhp_state_add_instance(CPUHP_AP_PERF_ARM_HISI_HHA_ONLINE,
  320. &hha_pmu->node);
  321. if (ret) {
  322. dev_err(&pdev->dev, "Error %d registering hotplug\n", ret);
  323. return ret;
  324. }
  325. name = devm_kasprintf(&pdev->dev, GFP_KERNEL, "hisi_sccl%u_hha%u",
  326. hha_pmu->sccl_id, hha_pmu->index_id);
  327. hha_pmu->pmu = (struct pmu) {
  328. .name = name,
  329. .module = THIS_MODULE,
  330. .task_ctx_nr = perf_invalid_context,
  331. .event_init = hisi_uncore_pmu_event_init,
  332. .pmu_enable = hisi_uncore_pmu_enable,
  333. .pmu_disable = hisi_uncore_pmu_disable,
  334. .add = hisi_uncore_pmu_add,
  335. .del = hisi_uncore_pmu_del,
  336. .start = hisi_uncore_pmu_start,
  337. .stop = hisi_uncore_pmu_stop,
  338. .read = hisi_uncore_pmu_read,
  339. .attr_groups = hisi_hha_pmu_attr_groups,
  340. .capabilities = PERF_PMU_CAP_NO_EXCLUDE,
  341. };
  342. ret = perf_pmu_register(&hha_pmu->pmu, name, -1);
  343. if (ret) {
  344. dev_err(hha_pmu->dev, "HHA PMU register failed!\n");
  345. cpuhp_state_remove_instance_nocalls(
  346. CPUHP_AP_PERF_ARM_HISI_HHA_ONLINE, &hha_pmu->node);
  347. irq_set_affinity_hint(hha_pmu->irq, NULL);
  348. }
  349. return ret;
  350. }
  351. static int hisi_hha_pmu_remove(struct platform_device *pdev)
  352. {
  353. struct hisi_pmu *hha_pmu = platform_get_drvdata(pdev);
  354. perf_pmu_unregister(&hha_pmu->pmu);
  355. cpuhp_state_remove_instance_nocalls(CPUHP_AP_PERF_ARM_HISI_HHA_ONLINE,
  356. &hha_pmu->node);
  357. irq_set_affinity_hint(hha_pmu->irq, NULL);
  358. return 0;
  359. }
  360. static struct platform_driver hisi_hha_pmu_driver = {
  361. .driver = {
  362. .name = "hisi_hha_pmu",
  363. .acpi_match_table = ACPI_PTR(hisi_hha_pmu_acpi_match),
  364. .suppress_bind_attrs = true,
  365. },
  366. .probe = hisi_hha_pmu_probe,
  367. .remove = hisi_hha_pmu_remove,
  368. };
  369. static int __init hisi_hha_pmu_module_init(void)
  370. {
  371. int ret;
  372. ret = cpuhp_setup_state_multi(CPUHP_AP_PERF_ARM_HISI_HHA_ONLINE,
  373. "AP_PERF_ARM_HISI_HHA_ONLINE",
  374. hisi_uncore_pmu_online_cpu,
  375. hisi_uncore_pmu_offline_cpu);
  376. if (ret) {
  377. pr_err("HHA PMU: Error setup hotplug, ret = %d;\n", ret);
  378. return ret;
  379. }
  380. ret = platform_driver_register(&hisi_hha_pmu_driver);
  381. if (ret)
  382. cpuhp_remove_multi_state(CPUHP_AP_PERF_ARM_HISI_HHA_ONLINE);
  383. return ret;
  384. }
  385. module_init(hisi_hha_pmu_module_init);
  386. static void __exit hisi_hha_pmu_module_exit(void)
  387. {
  388. platform_driver_unregister(&hisi_hha_pmu_driver);
  389. cpuhp_remove_multi_state(CPUHP_AP_PERF_ARM_HISI_HHA_ONLINE);
  390. }
  391. module_exit(hisi_hha_pmu_module_exit);
  392. MODULE_DESCRIPTION("HiSilicon SoC HHA uncore PMU driver");
  393. MODULE_LICENSE("GPL v2");
  394. MODULE_AUTHOR("Shaokun Zhang <zhangshaokun@hisilicon.com>");
  395. MODULE_AUTHOR("Anurup M <anurup.m@huawei.com>");