arm_smmuv3_pmu.c 25 KB

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  1. // SPDX-License-Identifier: GPL-2.0
  2. /*
  3. * This driver adds support for perf events to use the Performance
  4. * Monitor Counter Groups (PMCG) associated with an SMMUv3 node
  5. * to monitor that node.
  6. *
  7. * SMMUv3 PMCG devices are named as smmuv3_pmcg_<phys_addr_page> where
  8. * <phys_addr_page> is the physical page address of the SMMU PMCG wrapped
  9. * to 4K boundary. For example, the PMCG at 0xff88840000 is named
  10. * smmuv3_pmcg_ff88840
  11. *
  12. * Filtering by stream id is done by specifying filtering parameters
  13. * with the event. options are:
  14. * filter_enable - 0 = no filtering, 1 = filtering enabled
  15. * filter_span - 0 = exact match, 1 = pattern match
  16. * filter_stream_id - pattern to filter against
  17. *
  18. * To match a partial StreamID where the X most-significant bits must match
  19. * but the Y least-significant bits might differ, STREAMID is programmed
  20. * with a value that contains:
  21. * STREAMID[Y - 1] == 0.
  22. * STREAMID[Y - 2:0] == 1 (where Y > 1).
  23. * The remainder of implemented bits of STREAMID (X bits, from bit Y upwards)
  24. * contain a value to match from the corresponding bits of event StreamID.
  25. *
  26. * Example: perf stat -e smmuv3_pmcg_ff88840/transaction,filter_enable=1,
  27. * filter_span=1,filter_stream_id=0x42/ -a netperf
  28. * Applies filter pattern 0x42 to transaction events, which means events
  29. * matching stream ids 0x42 and 0x43 are counted. Further filtering
  30. * information is available in the SMMU documentation.
  31. *
  32. * SMMU events are not attributable to a CPU, so task mode and sampling
  33. * are not supported.
  34. */
  35. #include <linux/acpi.h>
  36. #include <linux/acpi_iort.h>
  37. #include <linux/bitfield.h>
  38. #include <linux/bitops.h>
  39. #include <linux/cpuhotplug.h>
  40. #include <linux/cpumask.h>
  41. #include <linux/device.h>
  42. #include <linux/errno.h>
  43. #include <linux/interrupt.h>
  44. #include <linux/irq.h>
  45. #include <linux/kernel.h>
  46. #include <linux/list.h>
  47. #include <linux/msi.h>
  48. #include <linux/perf_event.h>
  49. #include <linux/platform_device.h>
  50. #include <linux/smp.h>
  51. #include <linux/sysfs.h>
  52. #include <linux/types.h>
  53. #define SMMU_PMCG_EVCNTR0 0x0
  54. #define SMMU_PMCG_EVCNTR(n, stride) (SMMU_PMCG_EVCNTR0 + (n) * (stride))
  55. #define SMMU_PMCG_EVTYPER0 0x400
  56. #define SMMU_PMCG_EVTYPER(n) (SMMU_PMCG_EVTYPER0 + (n) * 4)
  57. #define SMMU_PMCG_SID_SPAN_SHIFT 29
  58. #define SMMU_PMCG_SMR0 0xA00
  59. #define SMMU_PMCG_SMR(n) (SMMU_PMCG_SMR0 + (n) * 4)
  60. #define SMMU_PMCG_CNTENSET0 0xC00
  61. #define SMMU_PMCG_CNTENCLR0 0xC20
  62. #define SMMU_PMCG_INTENSET0 0xC40
  63. #define SMMU_PMCG_INTENCLR0 0xC60
  64. #define SMMU_PMCG_OVSCLR0 0xC80
  65. #define SMMU_PMCG_OVSSET0 0xCC0
  66. #define SMMU_PMCG_CFGR 0xE00
  67. #define SMMU_PMCG_CFGR_SID_FILTER_TYPE BIT(23)
  68. #define SMMU_PMCG_CFGR_MSI BIT(21)
  69. #define SMMU_PMCG_CFGR_RELOC_CTRS BIT(20)
  70. #define SMMU_PMCG_CFGR_SIZE GENMASK(13, 8)
  71. #define SMMU_PMCG_CFGR_NCTR GENMASK(5, 0)
  72. #define SMMU_PMCG_CR 0xE04
  73. #define SMMU_PMCG_CR_ENABLE BIT(0)
  74. #define SMMU_PMCG_CEID0 0xE20
  75. #define SMMU_PMCG_CEID1 0xE28
  76. #define SMMU_PMCG_IRQ_CTRL 0xE50
  77. #define SMMU_PMCG_IRQ_CTRL_IRQEN BIT(0)
  78. #define SMMU_PMCG_IRQ_CFG0 0xE58
  79. #define SMMU_PMCG_IRQ_CFG1 0xE60
  80. #define SMMU_PMCG_IRQ_CFG2 0xE64
  81. /* MSI config fields */
  82. #define MSI_CFG0_ADDR_MASK GENMASK_ULL(51, 2)
  83. #define MSI_CFG2_MEMATTR_DEVICE_nGnRE 0x1
  84. #define SMMU_PMCG_DEFAULT_FILTER_SPAN 1
  85. #define SMMU_PMCG_DEFAULT_FILTER_SID GENMASK(31, 0)
  86. #define SMMU_PMCG_MAX_COUNTERS 64
  87. #define SMMU_PMCG_ARCH_MAX_EVENTS 128
  88. #define SMMU_PMCG_PA_SHIFT 12
  89. #define SMMU_PMCG_EVCNTR_RDONLY BIT(0)
  90. static int cpuhp_state_num;
  91. struct smmu_pmu {
  92. struct hlist_node node;
  93. struct perf_event *events[SMMU_PMCG_MAX_COUNTERS];
  94. DECLARE_BITMAP(used_counters, SMMU_PMCG_MAX_COUNTERS);
  95. DECLARE_BITMAP(supported_events, SMMU_PMCG_ARCH_MAX_EVENTS);
  96. unsigned int irq;
  97. unsigned int on_cpu;
  98. struct pmu pmu;
  99. unsigned int num_counters;
  100. struct device *dev;
  101. void __iomem *reg_base;
  102. void __iomem *reloc_base;
  103. u64 counter_mask;
  104. u32 options;
  105. bool global_filter;
  106. };
  107. #define to_smmu_pmu(p) (container_of(p, struct smmu_pmu, pmu))
  108. #define SMMU_PMU_EVENT_ATTR_EXTRACTOR(_name, _config, _start, _end) \
  109. static inline u32 get_##_name(struct perf_event *event) \
  110. { \
  111. return FIELD_GET(GENMASK_ULL(_end, _start), \
  112. event->attr._config); \
  113. } \
  114. SMMU_PMU_EVENT_ATTR_EXTRACTOR(event, config, 0, 15);
  115. SMMU_PMU_EVENT_ATTR_EXTRACTOR(filter_stream_id, config1, 0, 31);
  116. SMMU_PMU_EVENT_ATTR_EXTRACTOR(filter_span, config1, 32, 32);
  117. SMMU_PMU_EVENT_ATTR_EXTRACTOR(filter_enable, config1, 33, 33);
  118. static inline void smmu_pmu_enable(struct pmu *pmu)
  119. {
  120. struct smmu_pmu *smmu_pmu = to_smmu_pmu(pmu);
  121. writel(SMMU_PMCG_IRQ_CTRL_IRQEN,
  122. smmu_pmu->reg_base + SMMU_PMCG_IRQ_CTRL);
  123. writel(SMMU_PMCG_CR_ENABLE, smmu_pmu->reg_base + SMMU_PMCG_CR);
  124. }
  125. static inline void smmu_pmu_disable(struct pmu *pmu)
  126. {
  127. struct smmu_pmu *smmu_pmu = to_smmu_pmu(pmu);
  128. writel(0, smmu_pmu->reg_base + SMMU_PMCG_CR);
  129. writel(0, smmu_pmu->reg_base + SMMU_PMCG_IRQ_CTRL);
  130. }
  131. static inline void smmu_pmu_counter_set_value(struct smmu_pmu *smmu_pmu,
  132. u32 idx, u64 value)
  133. {
  134. if (smmu_pmu->counter_mask & BIT(32))
  135. writeq(value, smmu_pmu->reloc_base + SMMU_PMCG_EVCNTR(idx, 8));
  136. else
  137. writel(value, smmu_pmu->reloc_base + SMMU_PMCG_EVCNTR(idx, 4));
  138. }
  139. static inline u64 smmu_pmu_counter_get_value(struct smmu_pmu *smmu_pmu, u32 idx)
  140. {
  141. u64 value;
  142. if (smmu_pmu->counter_mask & BIT(32))
  143. value = readq(smmu_pmu->reloc_base + SMMU_PMCG_EVCNTR(idx, 8));
  144. else
  145. value = readl(smmu_pmu->reloc_base + SMMU_PMCG_EVCNTR(idx, 4));
  146. return value;
  147. }
  148. static inline void smmu_pmu_counter_enable(struct smmu_pmu *smmu_pmu, u32 idx)
  149. {
  150. writeq(BIT(idx), smmu_pmu->reg_base + SMMU_PMCG_CNTENSET0);
  151. }
  152. static inline void smmu_pmu_counter_disable(struct smmu_pmu *smmu_pmu, u32 idx)
  153. {
  154. writeq(BIT(idx), smmu_pmu->reg_base + SMMU_PMCG_CNTENCLR0);
  155. }
  156. static inline void smmu_pmu_interrupt_enable(struct smmu_pmu *smmu_pmu, u32 idx)
  157. {
  158. writeq(BIT(idx), smmu_pmu->reg_base + SMMU_PMCG_INTENSET0);
  159. }
  160. static inline void smmu_pmu_interrupt_disable(struct smmu_pmu *smmu_pmu,
  161. u32 idx)
  162. {
  163. writeq(BIT(idx), smmu_pmu->reg_base + SMMU_PMCG_INTENCLR0);
  164. }
  165. static inline void smmu_pmu_set_evtyper(struct smmu_pmu *smmu_pmu, u32 idx,
  166. u32 val)
  167. {
  168. writel(val, smmu_pmu->reg_base + SMMU_PMCG_EVTYPER(idx));
  169. }
  170. static inline void smmu_pmu_set_smr(struct smmu_pmu *smmu_pmu, u32 idx, u32 val)
  171. {
  172. writel(val, smmu_pmu->reg_base + SMMU_PMCG_SMR(idx));
  173. }
  174. static void smmu_pmu_event_update(struct perf_event *event)
  175. {
  176. struct hw_perf_event *hwc = &event->hw;
  177. struct smmu_pmu *smmu_pmu = to_smmu_pmu(event->pmu);
  178. u64 delta, prev, now;
  179. u32 idx = hwc->idx;
  180. do {
  181. prev = local64_read(&hwc->prev_count);
  182. now = smmu_pmu_counter_get_value(smmu_pmu, idx);
  183. } while (local64_cmpxchg(&hwc->prev_count, prev, now) != prev);
  184. /* handle overflow. */
  185. delta = now - prev;
  186. delta &= smmu_pmu->counter_mask;
  187. local64_add(delta, &event->count);
  188. }
  189. static void smmu_pmu_set_period(struct smmu_pmu *smmu_pmu,
  190. struct hw_perf_event *hwc)
  191. {
  192. u32 idx = hwc->idx;
  193. u64 new;
  194. if (smmu_pmu->options & SMMU_PMCG_EVCNTR_RDONLY) {
  195. /*
  196. * On platforms that require this quirk, if the counter starts
  197. * at < half_counter value and wraps, the current logic of
  198. * handling the overflow may not work. It is expected that,
  199. * those platforms will have full 64 counter bits implemented
  200. * so that such a possibility is remote(eg: HiSilicon HIP08).
  201. */
  202. new = smmu_pmu_counter_get_value(smmu_pmu, idx);
  203. } else {
  204. /*
  205. * We limit the max period to half the max counter value
  206. * of the counter size, so that even in the case of extreme
  207. * interrupt latency the counter will (hopefully) not wrap
  208. * past its initial value.
  209. */
  210. new = smmu_pmu->counter_mask >> 1;
  211. smmu_pmu_counter_set_value(smmu_pmu, idx, new);
  212. }
  213. local64_set(&hwc->prev_count, new);
  214. }
  215. static void smmu_pmu_set_event_filter(struct perf_event *event,
  216. int idx, u32 span, u32 sid)
  217. {
  218. struct smmu_pmu *smmu_pmu = to_smmu_pmu(event->pmu);
  219. u32 evtyper;
  220. evtyper = get_event(event) | span << SMMU_PMCG_SID_SPAN_SHIFT;
  221. smmu_pmu_set_evtyper(smmu_pmu, idx, evtyper);
  222. smmu_pmu_set_smr(smmu_pmu, idx, sid);
  223. }
  224. static bool smmu_pmu_check_global_filter(struct perf_event *curr,
  225. struct perf_event *new)
  226. {
  227. if (get_filter_enable(new) != get_filter_enable(curr))
  228. return false;
  229. if (!get_filter_enable(new))
  230. return true;
  231. return get_filter_span(new) == get_filter_span(curr) &&
  232. get_filter_stream_id(new) == get_filter_stream_id(curr);
  233. }
  234. static int smmu_pmu_apply_event_filter(struct smmu_pmu *smmu_pmu,
  235. struct perf_event *event, int idx)
  236. {
  237. u32 span, sid;
  238. unsigned int cur_idx, num_ctrs = smmu_pmu->num_counters;
  239. bool filter_en = !!get_filter_enable(event);
  240. span = filter_en ? get_filter_span(event) :
  241. SMMU_PMCG_DEFAULT_FILTER_SPAN;
  242. sid = filter_en ? get_filter_stream_id(event) :
  243. SMMU_PMCG_DEFAULT_FILTER_SID;
  244. cur_idx = find_first_bit(smmu_pmu->used_counters, num_ctrs);
  245. /*
  246. * Per-counter filtering, or scheduling the first globally-filtered
  247. * event into an empty PMU so idx == 0 and it works out equivalent.
  248. */
  249. if (!smmu_pmu->global_filter || cur_idx == num_ctrs) {
  250. smmu_pmu_set_event_filter(event, idx, span, sid);
  251. return 0;
  252. }
  253. /* Otherwise, must match whatever's currently scheduled */
  254. if (smmu_pmu_check_global_filter(smmu_pmu->events[cur_idx], event)) {
  255. smmu_pmu_set_evtyper(smmu_pmu, idx, get_event(event));
  256. return 0;
  257. }
  258. return -EAGAIN;
  259. }
  260. static int smmu_pmu_get_event_idx(struct smmu_pmu *smmu_pmu,
  261. struct perf_event *event)
  262. {
  263. int idx, err;
  264. unsigned int num_ctrs = smmu_pmu->num_counters;
  265. idx = find_first_zero_bit(smmu_pmu->used_counters, num_ctrs);
  266. if (idx == num_ctrs)
  267. /* The counters are all in use. */
  268. return -EAGAIN;
  269. err = smmu_pmu_apply_event_filter(smmu_pmu, event, idx);
  270. if (err)
  271. return err;
  272. set_bit(idx, smmu_pmu->used_counters);
  273. return idx;
  274. }
  275. static bool smmu_pmu_events_compatible(struct perf_event *curr,
  276. struct perf_event *new)
  277. {
  278. if (new->pmu != curr->pmu)
  279. return false;
  280. if (to_smmu_pmu(new->pmu)->global_filter &&
  281. !smmu_pmu_check_global_filter(curr, new))
  282. return false;
  283. return true;
  284. }
  285. /*
  286. * Implementation of abstract pmu functionality required by
  287. * the core perf events code.
  288. */
  289. static int smmu_pmu_event_init(struct perf_event *event)
  290. {
  291. struct hw_perf_event *hwc = &event->hw;
  292. struct smmu_pmu *smmu_pmu = to_smmu_pmu(event->pmu);
  293. struct device *dev = smmu_pmu->dev;
  294. struct perf_event *sibling;
  295. int group_num_events = 1;
  296. u16 event_id;
  297. if (event->attr.type != event->pmu->type)
  298. return -ENOENT;
  299. if (hwc->sample_period) {
  300. dev_dbg(dev, "Sampling not supported\n");
  301. return -EOPNOTSUPP;
  302. }
  303. if (event->cpu < 0) {
  304. dev_dbg(dev, "Per-task mode not supported\n");
  305. return -EOPNOTSUPP;
  306. }
  307. /* Verify specified event is supported on this PMU */
  308. event_id = get_event(event);
  309. if (event_id < SMMU_PMCG_ARCH_MAX_EVENTS &&
  310. (!test_bit(event_id, smmu_pmu->supported_events))) {
  311. dev_dbg(dev, "Invalid event %d for this PMU\n", event_id);
  312. return -EINVAL;
  313. }
  314. /* Don't allow groups with mixed PMUs, except for s/w events */
  315. if (!is_software_event(event->group_leader)) {
  316. if (!smmu_pmu_events_compatible(event->group_leader, event))
  317. return -EINVAL;
  318. if (++group_num_events > smmu_pmu->num_counters)
  319. return -EINVAL;
  320. }
  321. for_each_sibling_event(sibling, event->group_leader) {
  322. if (is_software_event(sibling))
  323. continue;
  324. if (!smmu_pmu_events_compatible(sibling, event))
  325. return -EINVAL;
  326. if (++group_num_events > smmu_pmu->num_counters)
  327. return -EINVAL;
  328. }
  329. hwc->idx = -1;
  330. /*
  331. * Ensure all events are on the same cpu so all events are in the
  332. * same cpu context, to avoid races on pmu_enable etc.
  333. */
  334. event->cpu = smmu_pmu->on_cpu;
  335. return 0;
  336. }
  337. static void smmu_pmu_event_start(struct perf_event *event, int flags)
  338. {
  339. struct smmu_pmu *smmu_pmu = to_smmu_pmu(event->pmu);
  340. struct hw_perf_event *hwc = &event->hw;
  341. int idx = hwc->idx;
  342. hwc->state = 0;
  343. smmu_pmu_set_period(smmu_pmu, hwc);
  344. smmu_pmu_counter_enable(smmu_pmu, idx);
  345. }
  346. static void smmu_pmu_event_stop(struct perf_event *event, int flags)
  347. {
  348. struct smmu_pmu *smmu_pmu = to_smmu_pmu(event->pmu);
  349. struct hw_perf_event *hwc = &event->hw;
  350. int idx = hwc->idx;
  351. if (hwc->state & PERF_HES_STOPPED)
  352. return;
  353. smmu_pmu_counter_disable(smmu_pmu, idx);
  354. /* As the counter gets updated on _start, ignore PERF_EF_UPDATE */
  355. smmu_pmu_event_update(event);
  356. hwc->state |= PERF_HES_STOPPED | PERF_HES_UPTODATE;
  357. }
  358. static int smmu_pmu_event_add(struct perf_event *event, int flags)
  359. {
  360. struct hw_perf_event *hwc = &event->hw;
  361. int idx;
  362. struct smmu_pmu *smmu_pmu = to_smmu_pmu(event->pmu);
  363. idx = smmu_pmu_get_event_idx(smmu_pmu, event);
  364. if (idx < 0)
  365. return idx;
  366. hwc->idx = idx;
  367. hwc->state = PERF_HES_STOPPED | PERF_HES_UPTODATE;
  368. smmu_pmu->events[idx] = event;
  369. local64_set(&hwc->prev_count, 0);
  370. smmu_pmu_interrupt_enable(smmu_pmu, idx);
  371. if (flags & PERF_EF_START)
  372. smmu_pmu_event_start(event, flags);
  373. /* Propagate changes to the userspace mapping. */
  374. perf_event_update_userpage(event);
  375. return 0;
  376. }
  377. static void smmu_pmu_event_del(struct perf_event *event, int flags)
  378. {
  379. struct hw_perf_event *hwc = &event->hw;
  380. struct smmu_pmu *smmu_pmu = to_smmu_pmu(event->pmu);
  381. int idx = hwc->idx;
  382. smmu_pmu_event_stop(event, flags | PERF_EF_UPDATE);
  383. smmu_pmu_interrupt_disable(smmu_pmu, idx);
  384. smmu_pmu->events[idx] = NULL;
  385. clear_bit(idx, smmu_pmu->used_counters);
  386. perf_event_update_userpage(event);
  387. }
  388. static void smmu_pmu_event_read(struct perf_event *event)
  389. {
  390. smmu_pmu_event_update(event);
  391. }
  392. /* cpumask */
  393. static ssize_t smmu_pmu_cpumask_show(struct device *dev,
  394. struct device_attribute *attr,
  395. char *buf)
  396. {
  397. struct smmu_pmu *smmu_pmu = to_smmu_pmu(dev_get_drvdata(dev));
  398. return cpumap_print_to_pagebuf(true, buf, cpumask_of(smmu_pmu->on_cpu));
  399. }
  400. static struct device_attribute smmu_pmu_cpumask_attr =
  401. __ATTR(cpumask, 0444, smmu_pmu_cpumask_show, NULL);
  402. static struct attribute *smmu_pmu_cpumask_attrs[] = {
  403. &smmu_pmu_cpumask_attr.attr,
  404. NULL
  405. };
  406. static struct attribute_group smmu_pmu_cpumask_group = {
  407. .attrs = smmu_pmu_cpumask_attrs,
  408. };
  409. /* Events */
  410. static ssize_t smmu_pmu_event_show(struct device *dev,
  411. struct device_attribute *attr, char *page)
  412. {
  413. struct perf_pmu_events_attr *pmu_attr;
  414. pmu_attr = container_of(attr, struct perf_pmu_events_attr, attr);
  415. return sprintf(page, "event=0x%02llx\n", pmu_attr->id);
  416. }
  417. #define SMMU_EVENT_ATTR(name, config) \
  418. PMU_EVENT_ATTR(name, smmu_event_attr_##name, \
  419. config, smmu_pmu_event_show)
  420. SMMU_EVENT_ATTR(cycles, 0);
  421. SMMU_EVENT_ATTR(transaction, 1);
  422. SMMU_EVENT_ATTR(tlb_miss, 2);
  423. SMMU_EVENT_ATTR(config_cache_miss, 3);
  424. SMMU_EVENT_ATTR(trans_table_walk_access, 4);
  425. SMMU_EVENT_ATTR(config_struct_access, 5);
  426. SMMU_EVENT_ATTR(pcie_ats_trans_rq, 6);
  427. SMMU_EVENT_ATTR(pcie_ats_trans_passed, 7);
  428. static struct attribute *smmu_pmu_events[] = {
  429. &smmu_event_attr_cycles.attr.attr,
  430. &smmu_event_attr_transaction.attr.attr,
  431. &smmu_event_attr_tlb_miss.attr.attr,
  432. &smmu_event_attr_config_cache_miss.attr.attr,
  433. &smmu_event_attr_trans_table_walk_access.attr.attr,
  434. &smmu_event_attr_config_struct_access.attr.attr,
  435. &smmu_event_attr_pcie_ats_trans_rq.attr.attr,
  436. &smmu_event_attr_pcie_ats_trans_passed.attr.attr,
  437. NULL
  438. };
  439. static umode_t smmu_pmu_event_is_visible(struct kobject *kobj,
  440. struct attribute *attr, int unused)
  441. {
  442. struct device *dev = kobj_to_dev(kobj);
  443. struct smmu_pmu *smmu_pmu = to_smmu_pmu(dev_get_drvdata(dev));
  444. struct perf_pmu_events_attr *pmu_attr;
  445. pmu_attr = container_of(attr, struct perf_pmu_events_attr, attr.attr);
  446. if (test_bit(pmu_attr->id, smmu_pmu->supported_events))
  447. return attr->mode;
  448. return 0;
  449. }
  450. static struct attribute_group smmu_pmu_events_group = {
  451. .name = "events",
  452. .attrs = smmu_pmu_events,
  453. .is_visible = smmu_pmu_event_is_visible,
  454. };
  455. /* Formats */
  456. PMU_FORMAT_ATTR(event, "config:0-15");
  457. PMU_FORMAT_ATTR(filter_stream_id, "config1:0-31");
  458. PMU_FORMAT_ATTR(filter_span, "config1:32");
  459. PMU_FORMAT_ATTR(filter_enable, "config1:33");
  460. static struct attribute *smmu_pmu_formats[] = {
  461. &format_attr_event.attr,
  462. &format_attr_filter_stream_id.attr,
  463. &format_attr_filter_span.attr,
  464. &format_attr_filter_enable.attr,
  465. NULL
  466. };
  467. static struct attribute_group smmu_pmu_format_group = {
  468. .name = "format",
  469. .attrs = smmu_pmu_formats,
  470. };
  471. static const struct attribute_group *smmu_pmu_attr_grps[] = {
  472. &smmu_pmu_cpumask_group,
  473. &smmu_pmu_events_group,
  474. &smmu_pmu_format_group,
  475. NULL
  476. };
  477. /*
  478. * Generic device handlers
  479. */
  480. static int smmu_pmu_offline_cpu(unsigned int cpu, struct hlist_node *node)
  481. {
  482. struct smmu_pmu *smmu_pmu;
  483. unsigned int target;
  484. smmu_pmu = hlist_entry_safe(node, struct smmu_pmu, node);
  485. if (cpu != smmu_pmu->on_cpu)
  486. return 0;
  487. target = cpumask_any_but(cpu_online_mask, cpu);
  488. if (target >= nr_cpu_ids)
  489. return 0;
  490. perf_pmu_migrate_context(&smmu_pmu->pmu, cpu, target);
  491. smmu_pmu->on_cpu = target;
  492. WARN_ON(irq_set_affinity_hint(smmu_pmu->irq, cpumask_of(target)));
  493. return 0;
  494. }
  495. static irqreturn_t smmu_pmu_handle_irq(int irq_num, void *data)
  496. {
  497. struct smmu_pmu *smmu_pmu = data;
  498. u64 ovsr;
  499. unsigned int idx;
  500. ovsr = readq(smmu_pmu->reloc_base + SMMU_PMCG_OVSSET0);
  501. if (!ovsr)
  502. return IRQ_NONE;
  503. writeq(ovsr, smmu_pmu->reloc_base + SMMU_PMCG_OVSCLR0);
  504. for_each_set_bit(idx, (unsigned long *)&ovsr, smmu_pmu->num_counters) {
  505. struct perf_event *event = smmu_pmu->events[idx];
  506. struct hw_perf_event *hwc;
  507. if (WARN_ON_ONCE(!event))
  508. continue;
  509. smmu_pmu_event_update(event);
  510. hwc = &event->hw;
  511. smmu_pmu_set_period(smmu_pmu, hwc);
  512. }
  513. return IRQ_HANDLED;
  514. }
  515. static void smmu_pmu_free_msis(void *data)
  516. {
  517. struct device *dev = data;
  518. platform_msi_domain_free_irqs(dev);
  519. }
  520. static void smmu_pmu_write_msi_msg(struct msi_desc *desc, struct msi_msg *msg)
  521. {
  522. phys_addr_t doorbell;
  523. struct device *dev = msi_desc_to_dev(desc);
  524. struct smmu_pmu *pmu = dev_get_drvdata(dev);
  525. doorbell = (((u64)msg->address_hi) << 32) | msg->address_lo;
  526. doorbell &= MSI_CFG0_ADDR_MASK;
  527. writeq_relaxed(doorbell, pmu->reg_base + SMMU_PMCG_IRQ_CFG0);
  528. writel_relaxed(msg->data, pmu->reg_base + SMMU_PMCG_IRQ_CFG1);
  529. writel_relaxed(MSI_CFG2_MEMATTR_DEVICE_nGnRE,
  530. pmu->reg_base + SMMU_PMCG_IRQ_CFG2);
  531. }
  532. static void smmu_pmu_setup_msi(struct smmu_pmu *pmu)
  533. {
  534. struct msi_desc *desc;
  535. struct device *dev = pmu->dev;
  536. int ret;
  537. /* Clear MSI address reg */
  538. writeq_relaxed(0, pmu->reg_base + SMMU_PMCG_IRQ_CFG0);
  539. /* MSI supported or not */
  540. if (!(readl(pmu->reg_base + SMMU_PMCG_CFGR) & SMMU_PMCG_CFGR_MSI))
  541. return;
  542. ret = platform_msi_domain_alloc_irqs(dev, 1, smmu_pmu_write_msi_msg);
  543. if (ret) {
  544. dev_warn(dev, "failed to allocate MSIs\n");
  545. return;
  546. }
  547. desc = first_msi_entry(dev);
  548. if (desc)
  549. pmu->irq = desc->irq;
  550. /* Add callback to free MSIs on teardown */
  551. devm_add_action(dev, smmu_pmu_free_msis, dev);
  552. }
  553. static int smmu_pmu_setup_irq(struct smmu_pmu *pmu)
  554. {
  555. unsigned long flags = IRQF_NOBALANCING | IRQF_SHARED | IRQF_NO_THREAD;
  556. int irq, ret = -ENXIO;
  557. smmu_pmu_setup_msi(pmu);
  558. irq = pmu->irq;
  559. if (irq)
  560. ret = devm_request_irq(pmu->dev, irq, smmu_pmu_handle_irq,
  561. flags, "smmuv3-pmu", pmu);
  562. return ret;
  563. }
  564. static void smmu_pmu_reset(struct smmu_pmu *smmu_pmu)
  565. {
  566. u64 counter_present_mask = GENMASK_ULL(smmu_pmu->num_counters - 1, 0);
  567. smmu_pmu_disable(&smmu_pmu->pmu);
  568. /* Disable counter and interrupt */
  569. writeq_relaxed(counter_present_mask,
  570. smmu_pmu->reg_base + SMMU_PMCG_CNTENCLR0);
  571. writeq_relaxed(counter_present_mask,
  572. smmu_pmu->reg_base + SMMU_PMCG_INTENCLR0);
  573. writeq_relaxed(counter_present_mask,
  574. smmu_pmu->reloc_base + SMMU_PMCG_OVSCLR0);
  575. }
  576. static void smmu_pmu_get_acpi_options(struct smmu_pmu *smmu_pmu)
  577. {
  578. u32 model;
  579. model = *(u32 *)dev_get_platdata(smmu_pmu->dev);
  580. switch (model) {
  581. case IORT_SMMU_V3_PMCG_HISI_HIP08:
  582. /* HiSilicon Erratum 162001800 */
  583. smmu_pmu->options |= SMMU_PMCG_EVCNTR_RDONLY;
  584. break;
  585. }
  586. dev_notice(smmu_pmu->dev, "option mask 0x%x\n", smmu_pmu->options);
  587. }
  588. static int smmu_pmu_probe(struct platform_device *pdev)
  589. {
  590. struct smmu_pmu *smmu_pmu;
  591. struct resource *res_0;
  592. u32 cfgr, reg_size;
  593. u64 ceid_64[2];
  594. int irq, err;
  595. char *name;
  596. struct device *dev = &pdev->dev;
  597. smmu_pmu = devm_kzalloc(dev, sizeof(*smmu_pmu), GFP_KERNEL);
  598. if (!smmu_pmu)
  599. return -ENOMEM;
  600. smmu_pmu->dev = dev;
  601. platform_set_drvdata(pdev, smmu_pmu);
  602. smmu_pmu->pmu = (struct pmu) {
  603. .module = THIS_MODULE,
  604. .task_ctx_nr = perf_invalid_context,
  605. .pmu_enable = smmu_pmu_enable,
  606. .pmu_disable = smmu_pmu_disable,
  607. .event_init = smmu_pmu_event_init,
  608. .add = smmu_pmu_event_add,
  609. .del = smmu_pmu_event_del,
  610. .start = smmu_pmu_event_start,
  611. .stop = smmu_pmu_event_stop,
  612. .read = smmu_pmu_event_read,
  613. .attr_groups = smmu_pmu_attr_grps,
  614. .capabilities = PERF_PMU_CAP_NO_EXCLUDE,
  615. };
  616. smmu_pmu->reg_base = devm_platform_get_and_ioremap_resource(pdev, 0, &res_0);
  617. if (IS_ERR(smmu_pmu->reg_base))
  618. return PTR_ERR(smmu_pmu->reg_base);
  619. cfgr = readl_relaxed(smmu_pmu->reg_base + SMMU_PMCG_CFGR);
  620. /* Determine if page 1 is present */
  621. if (cfgr & SMMU_PMCG_CFGR_RELOC_CTRS) {
  622. smmu_pmu->reloc_base = devm_platform_ioremap_resource(pdev, 1);
  623. if (IS_ERR(smmu_pmu->reloc_base))
  624. return PTR_ERR(smmu_pmu->reloc_base);
  625. } else {
  626. smmu_pmu->reloc_base = smmu_pmu->reg_base;
  627. }
  628. irq = platform_get_irq_optional(pdev, 0);
  629. if (irq > 0)
  630. smmu_pmu->irq = irq;
  631. ceid_64[0] = readq_relaxed(smmu_pmu->reg_base + SMMU_PMCG_CEID0);
  632. ceid_64[1] = readq_relaxed(smmu_pmu->reg_base + SMMU_PMCG_CEID1);
  633. bitmap_from_arr32(smmu_pmu->supported_events, (u32 *)ceid_64,
  634. SMMU_PMCG_ARCH_MAX_EVENTS);
  635. smmu_pmu->num_counters = FIELD_GET(SMMU_PMCG_CFGR_NCTR, cfgr) + 1;
  636. smmu_pmu->global_filter = !!(cfgr & SMMU_PMCG_CFGR_SID_FILTER_TYPE);
  637. reg_size = FIELD_GET(SMMU_PMCG_CFGR_SIZE, cfgr);
  638. smmu_pmu->counter_mask = GENMASK_ULL(reg_size, 0);
  639. smmu_pmu_reset(smmu_pmu);
  640. err = smmu_pmu_setup_irq(smmu_pmu);
  641. if (err) {
  642. dev_err(dev, "Setup irq failed, PMU @%pa\n", &res_0->start);
  643. return err;
  644. }
  645. name = devm_kasprintf(&pdev->dev, GFP_KERNEL, "smmuv3_pmcg_%llx",
  646. (res_0->start) >> SMMU_PMCG_PA_SHIFT);
  647. if (!name) {
  648. dev_err(dev, "Create name failed, PMU @%pa\n", &res_0->start);
  649. return -EINVAL;
  650. }
  651. smmu_pmu_get_acpi_options(smmu_pmu);
  652. /* Pick one CPU to be the preferred one to use */
  653. smmu_pmu->on_cpu = raw_smp_processor_id();
  654. WARN_ON(irq_set_affinity_hint(smmu_pmu->irq,
  655. cpumask_of(smmu_pmu->on_cpu)));
  656. err = cpuhp_state_add_instance_nocalls(cpuhp_state_num,
  657. &smmu_pmu->node);
  658. if (err) {
  659. dev_err(dev, "Error %d registering hotplug, PMU @%pa\n",
  660. err, &res_0->start);
  661. goto out_clear_affinity;
  662. }
  663. err = perf_pmu_register(&smmu_pmu->pmu, name, -1);
  664. if (err) {
  665. dev_err(dev, "Error %d registering PMU @%pa\n",
  666. err, &res_0->start);
  667. goto out_unregister;
  668. }
  669. dev_info(dev, "Registered PMU @ %pa using %d counters with %s filter settings\n",
  670. &res_0->start, smmu_pmu->num_counters,
  671. smmu_pmu->global_filter ? "Global(Counter0)" :
  672. "Individual");
  673. return 0;
  674. out_unregister:
  675. cpuhp_state_remove_instance_nocalls(cpuhp_state_num, &smmu_pmu->node);
  676. out_clear_affinity:
  677. irq_set_affinity_hint(smmu_pmu->irq, NULL);
  678. return err;
  679. }
  680. static int smmu_pmu_remove(struct platform_device *pdev)
  681. {
  682. struct smmu_pmu *smmu_pmu = platform_get_drvdata(pdev);
  683. perf_pmu_unregister(&smmu_pmu->pmu);
  684. cpuhp_state_remove_instance_nocalls(cpuhp_state_num, &smmu_pmu->node);
  685. irq_set_affinity_hint(smmu_pmu->irq, NULL);
  686. return 0;
  687. }
  688. static void smmu_pmu_shutdown(struct platform_device *pdev)
  689. {
  690. struct smmu_pmu *smmu_pmu = platform_get_drvdata(pdev);
  691. smmu_pmu_disable(&smmu_pmu->pmu);
  692. }
  693. static struct platform_driver smmu_pmu_driver = {
  694. .driver = {
  695. .name = "arm-smmu-v3-pmcg",
  696. .suppress_bind_attrs = true,
  697. },
  698. .probe = smmu_pmu_probe,
  699. .remove = smmu_pmu_remove,
  700. .shutdown = smmu_pmu_shutdown,
  701. };
  702. static int __init arm_smmu_pmu_init(void)
  703. {
  704. cpuhp_state_num = cpuhp_setup_state_multi(CPUHP_AP_ONLINE_DYN,
  705. "perf/arm/pmcg:online",
  706. NULL,
  707. smmu_pmu_offline_cpu);
  708. if (cpuhp_state_num < 0)
  709. return cpuhp_state_num;
  710. return platform_driver_register(&smmu_pmu_driver);
  711. }
  712. module_init(arm_smmu_pmu_init);
  713. static void __exit arm_smmu_pmu_exit(void)
  714. {
  715. platform_driver_unregister(&smmu_pmu_driver);
  716. cpuhp_remove_multi_state(cpuhp_state_num);
  717. }
  718. module_exit(arm_smmu_pmu_exit);
  719. MODULE_DESCRIPTION("PMU driver for ARM SMMUv3 Performance Monitors Extension");
  720. MODULE_AUTHOR("Neil Leeder <nleeder@codeaurora.org>");
  721. MODULE_AUTHOR("Shameer Kolothum <shameerali.kolothum.thodi@huawei.com>");
  722. MODULE_LICENSE("GPL v2");