arm-cmn.c 44 KB

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  1. // SPDX-License-Identifier: GPL-2.0
  2. // Copyright (C) 2016-2020 Arm Limited
  3. // CMN-600 Coherent Mesh Network PMU driver
  4. #include <linux/acpi.h>
  5. #include <linux/bitfield.h>
  6. #include <linux/bitops.h>
  7. #include <linux/interrupt.h>
  8. #include <linux/io.h>
  9. #include <linux/kernel.h>
  10. #include <linux/list.h>
  11. #include <linux/module.h>
  12. #include <linux/of.h>
  13. #include <linux/perf_event.h>
  14. #include <linux/platform_device.h>
  15. #include <linux/slab.h>
  16. #include <linux/sort.h>
  17. /* Common register stuff */
  18. #define CMN_NODE_INFO 0x0000
  19. #define CMN_NI_NODE_TYPE GENMASK_ULL(15, 0)
  20. #define CMN_NI_NODE_ID GENMASK_ULL(31, 16)
  21. #define CMN_NI_LOGICAL_ID GENMASK_ULL(47, 32)
  22. #define CMN_NODEID_DEVID(reg) ((reg) & 3)
  23. #define CMN_NODEID_PID(reg) (((reg) >> 2) & 1)
  24. #define CMN_NODEID_X(reg, bits) ((reg) >> (3 + (bits)))
  25. #define CMN_NODEID_Y(reg, bits) (((reg) >> 3) & ((1U << (bits)) - 1))
  26. #define CMN_CHILD_INFO 0x0080
  27. #define CMN_CI_CHILD_COUNT GENMASK_ULL(15, 0)
  28. #define CMN_CI_CHILD_PTR_OFFSET GENMASK_ULL(31, 16)
  29. #define CMN_CHILD_NODE_ADDR GENMASK(27,0)
  30. #define CMN_CHILD_NODE_EXTERNAL BIT(31)
  31. #define CMN_ADDR_NODE_PTR GENMASK(27, 14)
  32. #define CMN_NODE_PTR_DEVID(ptr) (((ptr) >> 2) & 3)
  33. #define CMN_NODE_PTR_PID(ptr) ((ptr) & 1)
  34. #define CMN_NODE_PTR_X(ptr, bits) ((ptr) >> (6 + (bits)))
  35. #define CMN_NODE_PTR_Y(ptr, bits) (((ptr) >> 6) & ((1U << (bits)) - 1))
  36. #define CMN_MAX_XPS (8 * 8)
  37. /* The CFG node has one other useful purpose */
  38. #define CMN_CFGM_PERIPH_ID_2 0x0010
  39. #define CMN_CFGM_PID2_REVISION GENMASK(7, 4)
  40. /* PMU registers occupy the 3rd 4KB page of each node's 16KB space */
  41. #define CMN_PMU_OFFSET 0x2000
  42. /* For most nodes, this is all there is */
  43. #define CMN_PMU_EVENT_SEL 0x000
  44. #define CMN_PMU_EVENTn_ID_SHIFT(n) ((n) * 8)
  45. /* DTMs live in the PMU space of XP registers */
  46. #define CMN_DTM_WPn(n) (0x1A0 + (n) * 0x18)
  47. #define CMN_DTM_WPn_CONFIG(n) (CMN_DTM_WPn(n) + 0x00)
  48. #define CMN_DTM_WPn_CONFIG_WP_COMBINE BIT(6)
  49. #define CMN_DTM_WPn_CONFIG_WP_EXCLUSIVE BIT(5)
  50. #define CMN_DTM_WPn_CONFIG_WP_GRP BIT(4)
  51. #define CMN_DTM_WPn_CONFIG_WP_CHN_SEL GENMASK_ULL(3, 1)
  52. #define CMN_DTM_WPn_CONFIG_WP_DEV_SEL BIT(0)
  53. #define CMN_DTM_WPn_VAL(n) (CMN_DTM_WPn(n) + 0x08)
  54. #define CMN_DTM_WPn_MASK(n) (CMN_DTM_WPn(n) + 0x10)
  55. #define CMN_DTM_PMU_CONFIG 0x210
  56. #define CMN__PMEVCNT0_INPUT_SEL GENMASK_ULL(37, 32)
  57. #define CMN__PMEVCNT0_INPUT_SEL_WP 0x00
  58. #define CMN__PMEVCNT0_INPUT_SEL_XP 0x04
  59. #define CMN__PMEVCNT0_INPUT_SEL_DEV 0x10
  60. #define CMN__PMEVCNT0_GLOBAL_NUM GENMASK_ULL(18, 16)
  61. #define CMN__PMEVCNTn_GLOBAL_NUM_SHIFT(n) ((n) * 4)
  62. #define CMN__PMEVCNT_PAIRED(n) BIT(4 + (n))
  63. #define CMN__PMEVCNT23_COMBINED BIT(2)
  64. #define CMN__PMEVCNT01_COMBINED BIT(1)
  65. #define CMN_DTM_PMU_CONFIG_PMU_EN BIT(0)
  66. #define CMN_DTM_PMEVCNT 0x220
  67. #define CMN_DTM_PMEVCNTSR 0x240
  68. #define CMN_DTM_NUM_COUNTERS 4
  69. /* The DTC node is where the magic happens */
  70. #define CMN_DT_DTC_CTL 0x0a00
  71. #define CMN_DT_DTC_CTL_DT_EN BIT(0)
  72. /* DTC counters are paired in 64-bit registers on a 16-byte stride. Yuck */
  73. #define _CMN_DT_CNT_REG(n) ((((n) / 2) * 4 + (n) % 2) * 4)
  74. #define CMN_DT_PMEVCNT(n) (CMN_PMU_OFFSET + _CMN_DT_CNT_REG(n))
  75. #define CMN_DT_PMCCNTR (CMN_PMU_OFFSET + 0x40)
  76. #define CMN_DT_PMEVCNTSR(n) (CMN_PMU_OFFSET + 0x50 + _CMN_DT_CNT_REG(n))
  77. #define CMN_DT_PMCCNTRSR (CMN_PMU_OFFSET + 0x90)
  78. #define CMN_DT_PMCR (CMN_PMU_OFFSET + 0x100)
  79. #define CMN_DT_PMCR_PMU_EN BIT(0)
  80. #define CMN_DT_PMCR_CNTR_RST BIT(5)
  81. #define CMN_DT_PMCR_OVFL_INTR_EN BIT(6)
  82. #define CMN_DT_PMOVSR (CMN_PMU_OFFSET + 0x118)
  83. #define CMN_DT_PMOVSR_CLR (CMN_PMU_OFFSET + 0x120)
  84. #define CMN_DT_PMSSR (CMN_PMU_OFFSET + 0x128)
  85. #define CMN_DT_PMSSR_SS_STATUS(n) BIT(n)
  86. #define CMN_DT_PMSRR (CMN_PMU_OFFSET + 0x130)
  87. #define CMN_DT_PMSRR_SS_REQ BIT(0)
  88. #define CMN_DT_NUM_COUNTERS 8
  89. #define CMN_MAX_DTCS 4
  90. /*
  91. * Even in the worst case a DTC counter can't wrap in fewer than 2^42 cycles,
  92. * so throwing away one bit to make overflow handling easy is no big deal.
  93. */
  94. #define CMN_COUNTER_INIT 0x80000000
  95. /* Similarly for the 40-bit cycle counter */
  96. #define CMN_CC_INIT 0x8000000000ULL
  97. /* Event attributes */
  98. #define CMN_CONFIG_TYPE GENMASK(15, 0)
  99. #define CMN_CONFIG_EVENTID GENMASK(23, 16)
  100. #define CMN_CONFIG_OCCUPID GENMASK(27, 24)
  101. #define CMN_CONFIG_BYNODEID BIT(31)
  102. #define CMN_CONFIG_NODEID GENMASK(47, 32)
  103. #define CMN_EVENT_TYPE(event) FIELD_GET(CMN_CONFIG_TYPE, (event)->attr.config)
  104. #define CMN_EVENT_EVENTID(event) FIELD_GET(CMN_CONFIG_EVENTID, (event)->attr.config)
  105. #define CMN_EVENT_OCCUPID(event) FIELD_GET(CMN_CONFIG_OCCUPID, (event)->attr.config)
  106. #define CMN_EVENT_BYNODEID(event) FIELD_GET(CMN_CONFIG_BYNODEID, (event)->attr.config)
  107. #define CMN_EVENT_NODEID(event) FIELD_GET(CMN_CONFIG_NODEID, (event)->attr.config)
  108. #define CMN_CONFIG_WP_COMBINE GENMASK(27, 24)
  109. #define CMN_CONFIG_WP_DEV_SEL BIT(48)
  110. #define CMN_CONFIG_WP_CHN_SEL GENMASK(50, 49)
  111. #define CMN_CONFIG_WP_GRP BIT(52)
  112. #define CMN_CONFIG_WP_EXCLUSIVE BIT(53)
  113. #define CMN_CONFIG1_WP_VAL GENMASK(63, 0)
  114. #define CMN_CONFIG2_WP_MASK GENMASK(63, 0)
  115. #define CMN_EVENT_WP_COMBINE(event) FIELD_GET(CMN_CONFIG_WP_COMBINE, (event)->attr.config)
  116. #define CMN_EVENT_WP_DEV_SEL(event) FIELD_GET(CMN_CONFIG_WP_DEV_SEL, (event)->attr.config)
  117. #define CMN_EVENT_WP_CHN_SEL(event) FIELD_GET(CMN_CONFIG_WP_CHN_SEL, (event)->attr.config)
  118. #define CMN_EVENT_WP_GRP(event) FIELD_GET(CMN_CONFIG_WP_GRP, (event)->attr.config)
  119. #define CMN_EVENT_WP_EXCLUSIVE(event) FIELD_GET(CMN_CONFIG_WP_EXCLUSIVE, (event)->attr.config)
  120. #define CMN_EVENT_WP_VAL(event) FIELD_GET(CMN_CONFIG1_WP_VAL, (event)->attr.config1)
  121. #define CMN_EVENT_WP_MASK(event) FIELD_GET(CMN_CONFIG2_WP_MASK, (event)->attr.config2)
  122. /* Made-up event IDs for watchpoint direction */
  123. #define CMN_WP_UP 0
  124. #define CMN_WP_DOWN 2
  125. /* r0px probably don't exist in silicon, thankfully */
  126. enum cmn_revision {
  127. CMN600_R1P0,
  128. CMN600_R1P1,
  129. CMN600_R1P2,
  130. CMN600_R1P3,
  131. CMN600_R2P0,
  132. CMN600_R3P0,
  133. };
  134. enum cmn_node_type {
  135. CMN_TYPE_INVALID,
  136. CMN_TYPE_DVM,
  137. CMN_TYPE_CFG,
  138. CMN_TYPE_DTC,
  139. CMN_TYPE_HNI,
  140. CMN_TYPE_HNF,
  141. CMN_TYPE_XP,
  142. CMN_TYPE_SBSX,
  143. CMN_TYPE_RNI = 0xa,
  144. CMN_TYPE_RND = 0xd,
  145. CMN_TYPE_RNSAM = 0xf,
  146. CMN_TYPE_CXRA = 0x100,
  147. CMN_TYPE_CXHA = 0x101,
  148. CMN_TYPE_CXLA = 0x102,
  149. /* Not a real node type */
  150. CMN_TYPE_WP = 0x7770
  151. };
  152. struct arm_cmn_node {
  153. void __iomem *pmu_base;
  154. u16 id, logid;
  155. enum cmn_node_type type;
  156. union {
  157. /* Device node */
  158. struct {
  159. int to_xp;
  160. /* DN/HN-F/CXHA */
  161. unsigned int occupid_val;
  162. unsigned int occupid_count;
  163. };
  164. /* XP */
  165. struct {
  166. int dtc;
  167. u32 pmu_config_low;
  168. union {
  169. u8 input_sel[4];
  170. __le32 pmu_config_high;
  171. };
  172. s8 wp_event[4];
  173. };
  174. };
  175. union {
  176. u8 event[4];
  177. __le32 event_sel;
  178. };
  179. };
  180. struct arm_cmn_dtc {
  181. void __iomem *base;
  182. int irq;
  183. int irq_friend;
  184. bool cc_active;
  185. struct perf_event *counters[CMN_DT_NUM_COUNTERS];
  186. struct perf_event *cycles;
  187. };
  188. #define CMN_STATE_DISABLED BIT(0)
  189. #define CMN_STATE_TXN BIT(1)
  190. struct arm_cmn {
  191. struct device *dev;
  192. void __iomem *base;
  193. enum cmn_revision rev;
  194. u8 mesh_x;
  195. u8 mesh_y;
  196. u16 num_xps;
  197. u16 num_dns;
  198. struct arm_cmn_node *xps;
  199. struct arm_cmn_node *dns;
  200. struct arm_cmn_dtc *dtc;
  201. unsigned int num_dtcs;
  202. int cpu;
  203. struct hlist_node cpuhp_node;
  204. unsigned int state;
  205. struct pmu pmu;
  206. };
  207. #define to_cmn(p) container_of(p, struct arm_cmn, pmu)
  208. static int arm_cmn_hp_state;
  209. struct arm_cmn_hw_event {
  210. struct arm_cmn_node *dn;
  211. u64 dtm_idx[2];
  212. unsigned int dtc_idx;
  213. u8 dtcs_used;
  214. u8 num_dns;
  215. };
  216. #define for_each_hw_dn(hw, dn, i) \
  217. for (i = 0, dn = hw->dn; i < hw->num_dns; i++, dn++)
  218. static struct arm_cmn_hw_event *to_cmn_hw(struct perf_event *event)
  219. {
  220. BUILD_BUG_ON(sizeof(struct arm_cmn_hw_event) > offsetof(struct hw_perf_event, target));
  221. return (struct arm_cmn_hw_event *)&event->hw;
  222. }
  223. static void arm_cmn_set_index(u64 x[], unsigned int pos, unsigned int val)
  224. {
  225. x[pos / 32] |= (u64)val << ((pos % 32) * 2);
  226. }
  227. static unsigned int arm_cmn_get_index(u64 x[], unsigned int pos)
  228. {
  229. return (x[pos / 32] >> ((pos % 32) * 2)) & 3;
  230. }
  231. struct arm_cmn_event_attr {
  232. struct device_attribute attr;
  233. enum cmn_node_type type;
  234. u8 eventid;
  235. u8 occupid;
  236. };
  237. struct arm_cmn_format_attr {
  238. struct device_attribute attr;
  239. u64 field;
  240. int config;
  241. };
  242. static int arm_cmn_xyidbits(const struct arm_cmn *cmn)
  243. {
  244. return cmn->mesh_x > 4 || cmn->mesh_y > 4 ? 3 : 2;
  245. }
  246. static void arm_cmn_init_node_to_xp(const struct arm_cmn *cmn,
  247. struct arm_cmn_node *dn)
  248. {
  249. int bits = arm_cmn_xyidbits(cmn);
  250. int x = CMN_NODEID_X(dn->id, bits);
  251. int y = CMN_NODEID_Y(dn->id, bits);
  252. int xp_idx = cmn->mesh_x * y + x;
  253. dn->to_xp = (cmn->xps + xp_idx) - dn;
  254. }
  255. static struct arm_cmn_node *arm_cmn_node_to_xp(struct arm_cmn_node *dn)
  256. {
  257. return dn->type == CMN_TYPE_XP ? dn : dn + dn->to_xp;
  258. }
  259. static struct arm_cmn_node *arm_cmn_node(const struct arm_cmn *cmn,
  260. enum cmn_node_type type)
  261. {
  262. int i;
  263. for (i = 0; i < cmn->num_dns; i++)
  264. if (cmn->dns[i].type == type)
  265. return &cmn->dns[i];
  266. return NULL;
  267. }
  268. #define CMN_EVENT_ATTR(_name, _type, _eventid, _occupid) \
  269. (&((struct arm_cmn_event_attr[]) {{ \
  270. .attr = __ATTR(_name, 0444, arm_cmn_event_show, NULL), \
  271. .type = _type, \
  272. .eventid = _eventid, \
  273. .occupid = _occupid, \
  274. }})[0].attr.attr)
  275. static bool arm_cmn_is_occup_event(enum cmn_node_type type, unsigned int id)
  276. {
  277. return (type == CMN_TYPE_DVM && id == 0x05) ||
  278. (type == CMN_TYPE_HNF && id == 0x0f);
  279. }
  280. static ssize_t arm_cmn_event_show(struct device *dev,
  281. struct device_attribute *attr, char *buf)
  282. {
  283. struct arm_cmn_event_attr *eattr;
  284. eattr = container_of(attr, typeof(*eattr), attr);
  285. if (eattr->type == CMN_TYPE_DTC)
  286. return snprintf(buf, PAGE_SIZE, "type=0x%x\n", eattr->type);
  287. if (eattr->type == CMN_TYPE_WP)
  288. return snprintf(buf, PAGE_SIZE,
  289. "type=0x%x,eventid=0x%x,wp_dev_sel=?,wp_chn_sel=?,wp_grp=?,wp_val=?,wp_mask=?\n",
  290. eattr->type, eattr->eventid);
  291. if (arm_cmn_is_occup_event(eattr->type, eattr->eventid))
  292. return snprintf(buf, PAGE_SIZE, "type=0x%x,eventid=0x%x,occupid=0x%x\n",
  293. eattr->type, eattr->eventid, eattr->occupid);
  294. return snprintf(buf, PAGE_SIZE, "type=0x%x,eventid=0x%x\n",
  295. eattr->type, eattr->eventid);
  296. }
  297. static umode_t arm_cmn_event_attr_is_visible(struct kobject *kobj,
  298. struct attribute *attr,
  299. int unused)
  300. {
  301. struct device *dev = kobj_to_dev(kobj);
  302. struct arm_cmn *cmn = to_cmn(dev_get_drvdata(dev));
  303. struct arm_cmn_event_attr *eattr;
  304. enum cmn_node_type type;
  305. eattr = container_of(attr, typeof(*eattr), attr.attr);
  306. type = eattr->type;
  307. /* Watchpoints aren't nodes */
  308. if (type == CMN_TYPE_WP)
  309. type = CMN_TYPE_XP;
  310. /* Revision-specific differences */
  311. if (cmn->rev < CMN600_R1P2) {
  312. if (type == CMN_TYPE_HNF && eattr->eventid == 0x1b)
  313. return 0;
  314. }
  315. if (!arm_cmn_node(cmn, type))
  316. return 0;
  317. return attr->mode;
  318. }
  319. #define _CMN_EVENT_DVM(_name, _event, _occup) \
  320. CMN_EVENT_ATTR(dn_##_name, CMN_TYPE_DVM, _event, _occup)
  321. #define CMN_EVENT_DTC(_name) \
  322. CMN_EVENT_ATTR(dtc_##_name, CMN_TYPE_DTC, 0, 0)
  323. #define _CMN_EVENT_HNF(_name, _event, _occup) \
  324. CMN_EVENT_ATTR(hnf_##_name, CMN_TYPE_HNF, _event, _occup)
  325. #define CMN_EVENT_HNI(_name, _event) \
  326. CMN_EVENT_ATTR(hni_##_name, CMN_TYPE_HNI, _event, 0)
  327. #define __CMN_EVENT_XP(_name, _event) \
  328. CMN_EVENT_ATTR(mxp_##_name, CMN_TYPE_XP, _event, 0)
  329. #define CMN_EVENT_SBSX(_name, _event) \
  330. CMN_EVENT_ATTR(sbsx_##_name, CMN_TYPE_SBSX, _event, 0)
  331. #define CMN_EVENT_RNID(_name, _event) \
  332. CMN_EVENT_ATTR(rnid_##_name, CMN_TYPE_RNI, _event, 0)
  333. #define CMN_EVENT_DVM(_name, _event) \
  334. _CMN_EVENT_DVM(_name, _event, 0)
  335. #define CMN_EVENT_HNF(_name, _event) \
  336. _CMN_EVENT_HNF(_name, _event, 0)
  337. #define _CMN_EVENT_XP(_name, _event) \
  338. __CMN_EVENT_XP(e_##_name, (_event) | (0 << 2)), \
  339. __CMN_EVENT_XP(w_##_name, (_event) | (1 << 2)), \
  340. __CMN_EVENT_XP(n_##_name, (_event) | (2 << 2)), \
  341. __CMN_EVENT_XP(s_##_name, (_event) | (3 << 2)), \
  342. __CMN_EVENT_XP(p0_##_name, (_event) | (4 << 2)), \
  343. __CMN_EVENT_XP(p1_##_name, (_event) | (5 << 2))
  344. /* Good thing there are only 3 fundamental XP events... */
  345. #define CMN_EVENT_XP(_name, _event) \
  346. _CMN_EVENT_XP(req_##_name, (_event) | (0 << 5)), \
  347. _CMN_EVENT_XP(rsp_##_name, (_event) | (1 << 5)), \
  348. _CMN_EVENT_XP(snp_##_name, (_event) | (2 << 5)), \
  349. _CMN_EVENT_XP(dat_##_name, (_event) | (3 << 5))
  350. static struct attribute *arm_cmn_event_attrs[] = {
  351. CMN_EVENT_DTC(cycles),
  352. /*
  353. * DVM node events conflict with HN-I events in the equivalent PMU
  354. * slot, but our lazy short-cut of using the DTM counter index for
  355. * the PMU index as well happens to avoid that by construction.
  356. */
  357. CMN_EVENT_DVM(rxreq_dvmop, 0x01),
  358. CMN_EVENT_DVM(rxreq_dvmsync, 0x02),
  359. CMN_EVENT_DVM(rxreq_dvmop_vmid_filtered, 0x03),
  360. CMN_EVENT_DVM(rxreq_retried, 0x04),
  361. _CMN_EVENT_DVM(rxreq_trk_occupancy_all, 0x05, 0),
  362. _CMN_EVENT_DVM(rxreq_trk_occupancy_dvmop, 0x05, 1),
  363. _CMN_EVENT_DVM(rxreq_trk_occupancy_dvmsync, 0x05, 2),
  364. CMN_EVENT_HNF(cache_miss, 0x01),
  365. CMN_EVENT_HNF(slc_sf_cache_access, 0x02),
  366. CMN_EVENT_HNF(cache_fill, 0x03),
  367. CMN_EVENT_HNF(pocq_retry, 0x04),
  368. CMN_EVENT_HNF(pocq_reqs_recvd, 0x05),
  369. CMN_EVENT_HNF(sf_hit, 0x06),
  370. CMN_EVENT_HNF(sf_evictions, 0x07),
  371. CMN_EVENT_HNF(dir_snoops_sent, 0x08),
  372. CMN_EVENT_HNF(brd_snoops_sent, 0x09),
  373. CMN_EVENT_HNF(slc_eviction, 0x0a),
  374. CMN_EVENT_HNF(slc_fill_invalid_way, 0x0b),
  375. CMN_EVENT_HNF(mc_retries, 0x0c),
  376. CMN_EVENT_HNF(mc_reqs, 0x0d),
  377. CMN_EVENT_HNF(qos_hh_retry, 0x0e),
  378. _CMN_EVENT_HNF(qos_pocq_occupancy_all, 0x0f, 0),
  379. _CMN_EVENT_HNF(qos_pocq_occupancy_read, 0x0f, 1),
  380. _CMN_EVENT_HNF(qos_pocq_occupancy_write, 0x0f, 2),
  381. _CMN_EVENT_HNF(qos_pocq_occupancy_atomic, 0x0f, 3),
  382. _CMN_EVENT_HNF(qos_pocq_occupancy_stash, 0x0f, 4),
  383. CMN_EVENT_HNF(pocq_addrhaz, 0x10),
  384. CMN_EVENT_HNF(pocq_atomic_addrhaz, 0x11),
  385. CMN_EVENT_HNF(ld_st_swp_adq_full, 0x12),
  386. CMN_EVENT_HNF(cmp_adq_full, 0x13),
  387. CMN_EVENT_HNF(txdat_stall, 0x14),
  388. CMN_EVENT_HNF(txrsp_stall, 0x15),
  389. CMN_EVENT_HNF(seq_full, 0x16),
  390. CMN_EVENT_HNF(seq_hit, 0x17),
  391. CMN_EVENT_HNF(snp_sent, 0x18),
  392. CMN_EVENT_HNF(sfbi_dir_snp_sent, 0x19),
  393. CMN_EVENT_HNF(sfbi_brd_snp_sent, 0x1a),
  394. CMN_EVENT_HNF(snp_sent_untrk, 0x1b),
  395. CMN_EVENT_HNF(intv_dirty, 0x1c),
  396. CMN_EVENT_HNF(stash_snp_sent, 0x1d),
  397. CMN_EVENT_HNF(stash_data_pull, 0x1e),
  398. CMN_EVENT_HNF(snp_fwded, 0x1f),
  399. CMN_EVENT_HNI(rrt_rd_occ_cnt_ovfl, 0x20),
  400. CMN_EVENT_HNI(rrt_wr_occ_cnt_ovfl, 0x21),
  401. CMN_EVENT_HNI(rdt_rd_occ_cnt_ovfl, 0x22),
  402. CMN_EVENT_HNI(rdt_wr_occ_cnt_ovfl, 0x23),
  403. CMN_EVENT_HNI(wdb_occ_cnt_ovfl, 0x24),
  404. CMN_EVENT_HNI(rrt_rd_alloc, 0x25),
  405. CMN_EVENT_HNI(rrt_wr_alloc, 0x26),
  406. CMN_EVENT_HNI(rdt_rd_alloc, 0x27),
  407. CMN_EVENT_HNI(rdt_wr_alloc, 0x28),
  408. CMN_EVENT_HNI(wdb_alloc, 0x29),
  409. CMN_EVENT_HNI(txrsp_retryack, 0x2a),
  410. CMN_EVENT_HNI(arvalid_no_arready, 0x2b),
  411. CMN_EVENT_HNI(arready_no_arvalid, 0x2c),
  412. CMN_EVENT_HNI(awvalid_no_awready, 0x2d),
  413. CMN_EVENT_HNI(awready_no_awvalid, 0x2e),
  414. CMN_EVENT_HNI(wvalid_no_wready, 0x2f),
  415. CMN_EVENT_HNI(txdat_stall, 0x30),
  416. CMN_EVENT_HNI(nonpcie_serialization, 0x31),
  417. CMN_EVENT_HNI(pcie_serialization, 0x32),
  418. CMN_EVENT_XP(txflit_valid, 0x01),
  419. CMN_EVENT_XP(txflit_stall, 0x02),
  420. CMN_EVENT_XP(partial_dat_flit, 0x03),
  421. /* We treat watchpoints as a special made-up class of XP events */
  422. CMN_EVENT_ATTR(watchpoint_up, CMN_TYPE_WP, 0, 0),
  423. CMN_EVENT_ATTR(watchpoint_down, CMN_TYPE_WP, 2, 0),
  424. CMN_EVENT_SBSX(rd_req, 0x01),
  425. CMN_EVENT_SBSX(wr_req, 0x02),
  426. CMN_EVENT_SBSX(cmo_req, 0x03),
  427. CMN_EVENT_SBSX(txrsp_retryack, 0x04),
  428. CMN_EVENT_SBSX(txdat_flitv, 0x05),
  429. CMN_EVENT_SBSX(txrsp_flitv, 0x06),
  430. CMN_EVENT_SBSX(rd_req_trkr_occ_cnt_ovfl, 0x11),
  431. CMN_EVENT_SBSX(wr_req_trkr_occ_cnt_ovfl, 0x12),
  432. CMN_EVENT_SBSX(cmo_req_trkr_occ_cnt_ovfl, 0x13),
  433. CMN_EVENT_SBSX(wdb_occ_cnt_ovfl, 0x14),
  434. CMN_EVENT_SBSX(rd_axi_trkr_occ_cnt_ovfl, 0x15),
  435. CMN_EVENT_SBSX(cmo_axi_trkr_occ_cnt_ovfl, 0x16),
  436. CMN_EVENT_SBSX(arvalid_no_arready, 0x21),
  437. CMN_EVENT_SBSX(awvalid_no_awready, 0x22),
  438. CMN_EVENT_SBSX(wvalid_no_wready, 0x23),
  439. CMN_EVENT_SBSX(txdat_stall, 0x24),
  440. CMN_EVENT_SBSX(txrsp_stall, 0x25),
  441. CMN_EVENT_RNID(s0_rdata_beats, 0x01),
  442. CMN_EVENT_RNID(s1_rdata_beats, 0x02),
  443. CMN_EVENT_RNID(s2_rdata_beats, 0x03),
  444. CMN_EVENT_RNID(rxdat_flits, 0x04),
  445. CMN_EVENT_RNID(txdat_flits, 0x05),
  446. CMN_EVENT_RNID(txreq_flits_total, 0x06),
  447. CMN_EVENT_RNID(txreq_flits_retried, 0x07),
  448. CMN_EVENT_RNID(rrt_occ_ovfl, 0x08),
  449. CMN_EVENT_RNID(wrt_occ_ovfl, 0x09),
  450. CMN_EVENT_RNID(txreq_flits_replayed, 0x0a),
  451. CMN_EVENT_RNID(wrcancel_sent, 0x0b),
  452. CMN_EVENT_RNID(s0_wdata_beats, 0x0c),
  453. CMN_EVENT_RNID(s1_wdata_beats, 0x0d),
  454. CMN_EVENT_RNID(s2_wdata_beats, 0x0e),
  455. CMN_EVENT_RNID(rrt_alloc, 0x0f),
  456. CMN_EVENT_RNID(wrt_alloc, 0x10),
  457. CMN_EVENT_RNID(rdb_unord, 0x11),
  458. CMN_EVENT_RNID(rdb_replay, 0x12),
  459. CMN_EVENT_RNID(rdb_hybrid, 0x13),
  460. CMN_EVENT_RNID(rdb_ord, 0x14),
  461. NULL
  462. };
  463. static const struct attribute_group arm_cmn_event_attrs_group = {
  464. .name = "events",
  465. .attrs = arm_cmn_event_attrs,
  466. .is_visible = arm_cmn_event_attr_is_visible,
  467. };
  468. static ssize_t arm_cmn_format_show(struct device *dev,
  469. struct device_attribute *attr, char *buf)
  470. {
  471. struct arm_cmn_format_attr *fmt = container_of(attr, typeof(*fmt), attr);
  472. int lo = __ffs(fmt->field), hi = __fls(fmt->field);
  473. if (lo == hi)
  474. return snprintf(buf, PAGE_SIZE, "config:%d\n", lo);
  475. if (!fmt->config)
  476. return snprintf(buf, PAGE_SIZE, "config:%d-%d\n", lo, hi);
  477. return snprintf(buf, PAGE_SIZE, "config%d:%d-%d\n", fmt->config, lo, hi);
  478. }
  479. #define _CMN_FORMAT_ATTR(_name, _cfg, _fld) \
  480. (&((struct arm_cmn_format_attr[]) {{ \
  481. .attr = __ATTR(_name, 0444, arm_cmn_format_show, NULL), \
  482. .config = _cfg, \
  483. .field = _fld, \
  484. }})[0].attr.attr)
  485. #define CMN_FORMAT_ATTR(_name, _fld) _CMN_FORMAT_ATTR(_name, 0, _fld)
  486. static struct attribute *arm_cmn_format_attrs[] = {
  487. CMN_FORMAT_ATTR(type, CMN_CONFIG_TYPE),
  488. CMN_FORMAT_ATTR(eventid, CMN_CONFIG_EVENTID),
  489. CMN_FORMAT_ATTR(occupid, CMN_CONFIG_OCCUPID),
  490. CMN_FORMAT_ATTR(bynodeid, CMN_CONFIG_BYNODEID),
  491. CMN_FORMAT_ATTR(nodeid, CMN_CONFIG_NODEID),
  492. CMN_FORMAT_ATTR(wp_dev_sel, CMN_CONFIG_WP_DEV_SEL),
  493. CMN_FORMAT_ATTR(wp_chn_sel, CMN_CONFIG_WP_CHN_SEL),
  494. CMN_FORMAT_ATTR(wp_grp, CMN_CONFIG_WP_GRP),
  495. CMN_FORMAT_ATTR(wp_exclusive, CMN_CONFIG_WP_EXCLUSIVE),
  496. CMN_FORMAT_ATTR(wp_combine, CMN_CONFIG_WP_COMBINE),
  497. _CMN_FORMAT_ATTR(wp_val, 1, CMN_CONFIG1_WP_VAL),
  498. _CMN_FORMAT_ATTR(wp_mask, 2, CMN_CONFIG2_WP_MASK),
  499. NULL
  500. };
  501. static const struct attribute_group arm_cmn_format_attrs_group = {
  502. .name = "format",
  503. .attrs = arm_cmn_format_attrs,
  504. };
  505. static ssize_t arm_cmn_cpumask_show(struct device *dev,
  506. struct device_attribute *attr, char *buf)
  507. {
  508. struct arm_cmn *cmn = to_cmn(dev_get_drvdata(dev));
  509. return cpumap_print_to_pagebuf(true, buf, cpumask_of(cmn->cpu));
  510. }
  511. static struct device_attribute arm_cmn_cpumask_attr =
  512. __ATTR(cpumask, 0444, arm_cmn_cpumask_show, NULL);
  513. static struct attribute *arm_cmn_cpumask_attrs[] = {
  514. &arm_cmn_cpumask_attr.attr,
  515. NULL,
  516. };
  517. static struct attribute_group arm_cmn_cpumask_attr_group = {
  518. .attrs = arm_cmn_cpumask_attrs,
  519. };
  520. static const struct attribute_group *arm_cmn_attr_groups[] = {
  521. &arm_cmn_event_attrs_group,
  522. &arm_cmn_format_attrs_group,
  523. &arm_cmn_cpumask_attr_group,
  524. NULL
  525. };
  526. static int arm_cmn_wp_idx(struct perf_event *event)
  527. {
  528. return CMN_EVENT_EVENTID(event) + CMN_EVENT_WP_GRP(event);
  529. }
  530. static u32 arm_cmn_wp_config(struct perf_event *event)
  531. {
  532. u32 config;
  533. u32 dev = CMN_EVENT_WP_DEV_SEL(event);
  534. u32 chn = CMN_EVENT_WP_CHN_SEL(event);
  535. u32 grp = CMN_EVENT_WP_GRP(event);
  536. u32 exc = CMN_EVENT_WP_EXCLUSIVE(event);
  537. u32 combine = CMN_EVENT_WP_COMBINE(event);
  538. config = FIELD_PREP(CMN_DTM_WPn_CONFIG_WP_DEV_SEL, dev) |
  539. FIELD_PREP(CMN_DTM_WPn_CONFIG_WP_CHN_SEL, chn) |
  540. FIELD_PREP(CMN_DTM_WPn_CONFIG_WP_GRP, grp) |
  541. FIELD_PREP(CMN_DTM_WPn_CONFIG_WP_EXCLUSIVE, exc);
  542. if (combine && !grp)
  543. config |= CMN_DTM_WPn_CONFIG_WP_COMBINE;
  544. return config;
  545. }
  546. static void arm_cmn_set_state(struct arm_cmn *cmn, u32 state)
  547. {
  548. if (!cmn->state)
  549. writel_relaxed(0, cmn->dtc[0].base + CMN_DT_PMCR);
  550. cmn->state |= state;
  551. }
  552. static void arm_cmn_clear_state(struct arm_cmn *cmn, u32 state)
  553. {
  554. cmn->state &= ~state;
  555. if (!cmn->state)
  556. writel_relaxed(CMN_DT_PMCR_PMU_EN | CMN_DT_PMCR_OVFL_INTR_EN,
  557. cmn->dtc[0].base + CMN_DT_PMCR);
  558. }
  559. static void arm_cmn_pmu_enable(struct pmu *pmu)
  560. {
  561. arm_cmn_clear_state(to_cmn(pmu), CMN_STATE_DISABLED);
  562. }
  563. static void arm_cmn_pmu_disable(struct pmu *pmu)
  564. {
  565. arm_cmn_set_state(to_cmn(pmu), CMN_STATE_DISABLED);
  566. }
  567. static u64 arm_cmn_read_dtm(struct arm_cmn *cmn, struct arm_cmn_hw_event *hw,
  568. bool snapshot)
  569. {
  570. struct arm_cmn_node *dn;
  571. unsigned int i, offset;
  572. u64 count = 0;
  573. offset = snapshot ? CMN_DTM_PMEVCNTSR : CMN_DTM_PMEVCNT;
  574. for_each_hw_dn(hw, dn, i) {
  575. struct arm_cmn_node *xp = arm_cmn_node_to_xp(dn);
  576. int dtm_idx = arm_cmn_get_index(hw->dtm_idx, i);
  577. u64 reg = readq_relaxed(xp->pmu_base + offset);
  578. u16 dtm_count = reg >> (dtm_idx * 16);
  579. count += dtm_count;
  580. }
  581. return count;
  582. }
  583. static u64 arm_cmn_read_cc(struct arm_cmn_dtc *dtc)
  584. {
  585. u64 val = readq_relaxed(dtc->base + CMN_DT_PMCCNTR);
  586. writeq_relaxed(CMN_CC_INIT, dtc->base + CMN_DT_PMCCNTR);
  587. return (val - CMN_CC_INIT) & ((CMN_CC_INIT << 1) - 1);
  588. }
  589. static u32 arm_cmn_read_counter(struct arm_cmn_dtc *dtc, int idx)
  590. {
  591. u32 val, pmevcnt = CMN_DT_PMEVCNT(idx);
  592. val = readl_relaxed(dtc->base + pmevcnt);
  593. writel_relaxed(CMN_COUNTER_INIT, dtc->base + pmevcnt);
  594. return val - CMN_COUNTER_INIT;
  595. }
  596. static void arm_cmn_init_counter(struct perf_event *event)
  597. {
  598. struct arm_cmn *cmn = to_cmn(event->pmu);
  599. struct arm_cmn_hw_event *hw = to_cmn_hw(event);
  600. unsigned int i, pmevcnt = CMN_DT_PMEVCNT(hw->dtc_idx);
  601. u64 count;
  602. for (i = 0; hw->dtcs_used & (1U << i); i++) {
  603. writel_relaxed(CMN_COUNTER_INIT, cmn->dtc[i].base + pmevcnt);
  604. cmn->dtc[i].counters[hw->dtc_idx] = event;
  605. }
  606. count = arm_cmn_read_dtm(cmn, hw, false);
  607. local64_set(&event->hw.prev_count, count);
  608. }
  609. static void arm_cmn_event_read(struct perf_event *event)
  610. {
  611. struct arm_cmn *cmn = to_cmn(event->pmu);
  612. struct arm_cmn_hw_event *hw = to_cmn_hw(event);
  613. u64 delta, new, prev;
  614. unsigned long flags;
  615. unsigned int i;
  616. if (hw->dtc_idx == CMN_DT_NUM_COUNTERS) {
  617. i = __ffs(hw->dtcs_used);
  618. delta = arm_cmn_read_cc(cmn->dtc + i);
  619. local64_add(delta, &event->count);
  620. return;
  621. }
  622. new = arm_cmn_read_dtm(cmn, hw, false);
  623. prev = local64_xchg(&event->hw.prev_count, new);
  624. delta = new - prev;
  625. local_irq_save(flags);
  626. for (i = 0; hw->dtcs_used & (1U << i); i++) {
  627. new = arm_cmn_read_counter(cmn->dtc + i, hw->dtc_idx);
  628. delta += new << 16;
  629. }
  630. local_irq_restore(flags);
  631. local64_add(delta, &event->count);
  632. }
  633. static void arm_cmn_event_start(struct perf_event *event, int flags)
  634. {
  635. struct arm_cmn *cmn = to_cmn(event->pmu);
  636. struct arm_cmn_hw_event *hw = to_cmn_hw(event);
  637. struct arm_cmn_node *dn;
  638. enum cmn_node_type type = CMN_EVENT_TYPE(event);
  639. int i;
  640. if (type == CMN_TYPE_DTC) {
  641. i = __ffs(hw->dtcs_used);
  642. writeq_relaxed(CMN_CC_INIT, cmn->dtc[i].base + CMN_DT_PMCCNTR);
  643. cmn->dtc[i].cc_active = true;
  644. } else if (type == CMN_TYPE_WP) {
  645. int wp_idx = arm_cmn_wp_idx(event);
  646. u64 val = CMN_EVENT_WP_VAL(event);
  647. u64 mask = CMN_EVENT_WP_MASK(event);
  648. for_each_hw_dn(hw, dn, i) {
  649. writeq_relaxed(val, dn->pmu_base + CMN_DTM_WPn_VAL(wp_idx));
  650. writeq_relaxed(mask, dn->pmu_base + CMN_DTM_WPn_MASK(wp_idx));
  651. }
  652. } else for_each_hw_dn(hw, dn, i) {
  653. int dtm_idx = arm_cmn_get_index(hw->dtm_idx, i);
  654. dn->event[dtm_idx] = CMN_EVENT_EVENTID(event);
  655. writel_relaxed(le32_to_cpu(dn->event_sel), dn->pmu_base + CMN_PMU_EVENT_SEL);
  656. }
  657. }
  658. static void arm_cmn_event_stop(struct perf_event *event, int flags)
  659. {
  660. struct arm_cmn *cmn = to_cmn(event->pmu);
  661. struct arm_cmn_hw_event *hw = to_cmn_hw(event);
  662. struct arm_cmn_node *dn;
  663. enum cmn_node_type type = CMN_EVENT_TYPE(event);
  664. int i;
  665. if (type == CMN_TYPE_DTC) {
  666. i = __ffs(hw->dtcs_used);
  667. cmn->dtc[i].cc_active = false;
  668. } else if (type == CMN_TYPE_WP) {
  669. int wp_idx = arm_cmn_wp_idx(event);
  670. for_each_hw_dn(hw, dn, i) {
  671. writeq_relaxed(0, dn->pmu_base + CMN_DTM_WPn_MASK(wp_idx));
  672. writeq_relaxed(~0ULL, dn->pmu_base + CMN_DTM_WPn_VAL(wp_idx));
  673. }
  674. } else for_each_hw_dn(hw, dn, i) {
  675. int dtm_idx = arm_cmn_get_index(hw->dtm_idx, i);
  676. dn->event[dtm_idx] = 0;
  677. writel_relaxed(le32_to_cpu(dn->event_sel), dn->pmu_base + CMN_PMU_EVENT_SEL);
  678. }
  679. arm_cmn_event_read(event);
  680. }
  681. struct arm_cmn_val {
  682. u8 dtm_count[CMN_MAX_XPS];
  683. u8 occupid[CMN_MAX_XPS];
  684. u8 wp[CMN_MAX_XPS][4];
  685. int dtc_count;
  686. bool cycles;
  687. };
  688. static void arm_cmn_val_add_event(struct arm_cmn_val *val, struct perf_event *event)
  689. {
  690. struct arm_cmn_hw_event *hw = to_cmn_hw(event);
  691. struct arm_cmn_node *dn;
  692. enum cmn_node_type type;
  693. int i;
  694. u8 occupid;
  695. if (is_software_event(event))
  696. return;
  697. type = CMN_EVENT_TYPE(event);
  698. if (type == CMN_TYPE_DTC) {
  699. val->cycles = true;
  700. return;
  701. }
  702. val->dtc_count++;
  703. if (arm_cmn_is_occup_event(type, CMN_EVENT_EVENTID(event)))
  704. occupid = CMN_EVENT_OCCUPID(event) + 1;
  705. else
  706. occupid = 0;
  707. for_each_hw_dn(hw, dn, i) {
  708. int wp_idx, xp = arm_cmn_node_to_xp(dn)->logid;
  709. val->dtm_count[xp]++;
  710. val->occupid[xp] = occupid;
  711. if (type != CMN_TYPE_WP)
  712. continue;
  713. wp_idx = arm_cmn_wp_idx(event);
  714. val->wp[xp][wp_idx] = CMN_EVENT_WP_COMBINE(event) + 1;
  715. }
  716. }
  717. static int arm_cmn_validate_group(struct perf_event *event)
  718. {
  719. struct arm_cmn_hw_event *hw = to_cmn_hw(event);
  720. struct arm_cmn_node *dn;
  721. struct perf_event *sibling, *leader = event->group_leader;
  722. enum cmn_node_type type;
  723. struct arm_cmn_val val;
  724. int i;
  725. u8 occupid;
  726. if (leader == event)
  727. return 0;
  728. if (event->pmu != leader->pmu && !is_software_event(leader))
  729. return -EINVAL;
  730. memset(&val, 0, sizeof(val));
  731. arm_cmn_val_add_event(&val, leader);
  732. for_each_sibling_event(sibling, leader)
  733. arm_cmn_val_add_event(&val, sibling);
  734. type = CMN_EVENT_TYPE(event);
  735. if (type == CMN_TYPE_DTC)
  736. return val.cycles ? -EINVAL : 0;
  737. if (val.dtc_count == CMN_DT_NUM_COUNTERS)
  738. return -EINVAL;
  739. if (arm_cmn_is_occup_event(type, CMN_EVENT_EVENTID(event)))
  740. occupid = CMN_EVENT_OCCUPID(event) + 1;
  741. else
  742. occupid = 0;
  743. for_each_hw_dn(hw, dn, i) {
  744. int wp_idx, wp_cmb, xp = arm_cmn_node_to_xp(dn)->logid;
  745. if (val.dtm_count[xp] == CMN_DTM_NUM_COUNTERS)
  746. return -EINVAL;
  747. if (occupid && val.occupid[xp] && occupid != val.occupid[xp])
  748. return -EINVAL;
  749. if (type != CMN_TYPE_WP)
  750. continue;
  751. wp_idx = arm_cmn_wp_idx(event);
  752. if (val.wp[xp][wp_idx])
  753. return -EINVAL;
  754. wp_cmb = val.wp[xp][wp_idx ^ 1];
  755. if (wp_cmb && wp_cmb != CMN_EVENT_WP_COMBINE(event) + 1)
  756. return -EINVAL;
  757. }
  758. return 0;
  759. }
  760. static int arm_cmn_event_init(struct perf_event *event)
  761. {
  762. struct arm_cmn *cmn = to_cmn(event->pmu);
  763. struct arm_cmn_hw_event *hw = to_cmn_hw(event);
  764. enum cmn_node_type type;
  765. unsigned int i;
  766. bool bynodeid;
  767. u16 nodeid, eventid;
  768. if (event->attr.type != event->pmu->type)
  769. return -ENOENT;
  770. if (is_sampling_event(event) || event->attach_state & PERF_ATTACH_TASK)
  771. return -EINVAL;
  772. event->cpu = cmn->cpu;
  773. if (event->cpu < 0)
  774. return -EINVAL;
  775. type = CMN_EVENT_TYPE(event);
  776. /* DTC events (i.e. cycles) already have everything they need */
  777. if (type == CMN_TYPE_DTC)
  778. return 0;
  779. /* For watchpoints we need the actual XP node here */
  780. if (type == CMN_TYPE_WP) {
  781. type = CMN_TYPE_XP;
  782. /* ...and we need a "real" direction */
  783. eventid = CMN_EVENT_EVENTID(event);
  784. if (eventid != CMN_WP_UP && eventid != CMN_WP_DOWN)
  785. return -EINVAL;
  786. }
  787. bynodeid = CMN_EVENT_BYNODEID(event);
  788. nodeid = CMN_EVENT_NODEID(event);
  789. hw->dn = arm_cmn_node(cmn, type);
  790. for (i = hw->dn - cmn->dns; i < cmn->num_dns && cmn->dns[i].type == type; i++) {
  791. if (!bynodeid) {
  792. hw->num_dns++;
  793. } else if (cmn->dns[i].id != nodeid) {
  794. hw->dn++;
  795. } else {
  796. hw->num_dns = 1;
  797. break;
  798. }
  799. }
  800. if (!hw->num_dns) {
  801. int bits = arm_cmn_xyidbits(cmn);
  802. dev_dbg(cmn->dev, "invalid node 0x%x (%d,%d,%d,%d) type 0x%x\n",
  803. nodeid, CMN_NODEID_X(nodeid, bits), CMN_NODEID_Y(nodeid, bits),
  804. CMN_NODEID_PID(nodeid), CMN_NODEID_DEVID(nodeid), type);
  805. return -EINVAL;
  806. }
  807. /*
  808. * By assuming events count in all DTC domains, we cunningly avoid
  809. * needing to know anything about how XPs are assigned to domains.
  810. */
  811. hw->dtcs_used = (1U << cmn->num_dtcs) - 1;
  812. return arm_cmn_validate_group(event);
  813. }
  814. static void arm_cmn_event_clear(struct arm_cmn *cmn, struct perf_event *event,
  815. int i)
  816. {
  817. struct arm_cmn_hw_event *hw = to_cmn_hw(event);
  818. enum cmn_node_type type = CMN_EVENT_TYPE(event);
  819. while (i--) {
  820. struct arm_cmn_node *xp = arm_cmn_node_to_xp(hw->dn + i);
  821. unsigned int dtm_idx = arm_cmn_get_index(hw->dtm_idx, i);
  822. if (type == CMN_TYPE_WP)
  823. hw->dn[i].wp_event[arm_cmn_wp_idx(event)] = -1;
  824. if (arm_cmn_is_occup_event(type, CMN_EVENT_EVENTID(event)))
  825. hw->dn[i].occupid_count--;
  826. xp->pmu_config_low &= ~CMN__PMEVCNT_PAIRED(dtm_idx);
  827. writel_relaxed(xp->pmu_config_low, xp->pmu_base + CMN_DTM_PMU_CONFIG);
  828. }
  829. memset(hw->dtm_idx, 0, sizeof(hw->dtm_idx));
  830. for (i = 0; hw->dtcs_used & (1U << i); i++)
  831. cmn->dtc[i].counters[hw->dtc_idx] = NULL;
  832. }
  833. static int arm_cmn_event_add(struct perf_event *event, int flags)
  834. {
  835. struct arm_cmn *cmn = to_cmn(event->pmu);
  836. struct arm_cmn_hw_event *hw = to_cmn_hw(event);
  837. struct arm_cmn_dtc *dtc = &cmn->dtc[0];
  838. struct arm_cmn_node *dn;
  839. enum cmn_node_type type = CMN_EVENT_TYPE(event);
  840. unsigned int i, dtc_idx, input_sel;
  841. if (type == CMN_TYPE_DTC) {
  842. i = 0;
  843. while (cmn->dtc[i].cycles)
  844. if (++i == cmn->num_dtcs)
  845. return -ENOSPC;
  846. cmn->dtc[i].cycles = event;
  847. hw->dtc_idx = CMN_DT_NUM_COUNTERS;
  848. hw->dtcs_used = 1U << i;
  849. if (flags & PERF_EF_START)
  850. arm_cmn_event_start(event, 0);
  851. return 0;
  852. }
  853. /* Grab a free global counter first... */
  854. dtc_idx = 0;
  855. while (dtc->counters[dtc_idx])
  856. if (++dtc_idx == CMN_DT_NUM_COUNTERS)
  857. return -ENOSPC;
  858. hw->dtc_idx = dtc_idx;
  859. /* ...then the local counters to feed it. */
  860. for_each_hw_dn(hw, dn, i) {
  861. struct arm_cmn_node *xp = arm_cmn_node_to_xp(dn);
  862. unsigned int dtm_idx, shift;
  863. u64 reg;
  864. dtm_idx = 0;
  865. while (xp->pmu_config_low & CMN__PMEVCNT_PAIRED(dtm_idx))
  866. if (++dtm_idx == CMN_DTM_NUM_COUNTERS)
  867. goto free_dtms;
  868. if (type == CMN_TYPE_XP) {
  869. input_sel = CMN__PMEVCNT0_INPUT_SEL_XP + dtm_idx;
  870. } else if (type == CMN_TYPE_WP) {
  871. int tmp, wp_idx = arm_cmn_wp_idx(event);
  872. u32 cfg = arm_cmn_wp_config(event);
  873. if (dn->wp_event[wp_idx] >= 0)
  874. goto free_dtms;
  875. tmp = dn->wp_event[wp_idx ^ 1];
  876. if (tmp >= 0 && CMN_EVENT_WP_COMBINE(event) !=
  877. CMN_EVENT_WP_COMBINE(dtc->counters[tmp]))
  878. goto free_dtms;
  879. input_sel = CMN__PMEVCNT0_INPUT_SEL_WP + wp_idx;
  880. dn->wp_event[wp_idx] = dtc_idx;
  881. writel_relaxed(cfg, dn->pmu_base + CMN_DTM_WPn_CONFIG(wp_idx));
  882. } else {
  883. unsigned int port = CMN_NODEID_PID(dn->id);
  884. unsigned int dev = CMN_NODEID_DEVID(dn->id);
  885. input_sel = CMN__PMEVCNT0_INPUT_SEL_DEV + dtm_idx +
  886. (port << 4) + (dev << 2);
  887. if (arm_cmn_is_occup_event(type, CMN_EVENT_EVENTID(event))) {
  888. int occupid = CMN_EVENT_OCCUPID(event);
  889. if (dn->occupid_count == 0) {
  890. dn->occupid_val = occupid;
  891. writel_relaxed(occupid,
  892. dn->pmu_base + CMN_PMU_EVENT_SEL + 4);
  893. } else if (dn->occupid_val != occupid) {
  894. goto free_dtms;
  895. }
  896. dn->occupid_count++;
  897. }
  898. }
  899. arm_cmn_set_index(hw->dtm_idx, i, dtm_idx);
  900. xp->input_sel[dtm_idx] = input_sel;
  901. shift = CMN__PMEVCNTn_GLOBAL_NUM_SHIFT(dtm_idx);
  902. xp->pmu_config_low &= ~(CMN__PMEVCNT0_GLOBAL_NUM << shift);
  903. xp->pmu_config_low |= FIELD_PREP(CMN__PMEVCNT0_GLOBAL_NUM, dtc_idx) << shift;
  904. xp->pmu_config_low |= CMN__PMEVCNT_PAIRED(dtm_idx);
  905. reg = (u64)le32_to_cpu(xp->pmu_config_high) << 32 | xp->pmu_config_low;
  906. writeq_relaxed(reg, xp->pmu_base + CMN_DTM_PMU_CONFIG);
  907. }
  908. /* Go go go! */
  909. arm_cmn_init_counter(event);
  910. if (flags & PERF_EF_START)
  911. arm_cmn_event_start(event, 0);
  912. return 0;
  913. free_dtms:
  914. arm_cmn_event_clear(cmn, event, i);
  915. return -ENOSPC;
  916. }
  917. static void arm_cmn_event_del(struct perf_event *event, int flags)
  918. {
  919. struct arm_cmn *cmn = to_cmn(event->pmu);
  920. struct arm_cmn_hw_event *hw = to_cmn_hw(event);
  921. enum cmn_node_type type = CMN_EVENT_TYPE(event);
  922. arm_cmn_event_stop(event, PERF_EF_UPDATE);
  923. if (type == CMN_TYPE_DTC)
  924. cmn->dtc[__ffs(hw->dtcs_used)].cycles = NULL;
  925. else
  926. arm_cmn_event_clear(cmn, event, hw->num_dns);
  927. }
  928. /*
  929. * We stop the PMU for both add and read, to avoid skew across DTM counters.
  930. * In theory we could use snapshots to read without stopping, but then it
  931. * becomes a lot trickier to deal with overlow and racing against interrupts,
  932. * plus it seems they don't work properly on some hardware anyway :(
  933. */
  934. static void arm_cmn_start_txn(struct pmu *pmu, unsigned int flags)
  935. {
  936. arm_cmn_set_state(to_cmn(pmu), CMN_STATE_TXN);
  937. }
  938. static void arm_cmn_end_txn(struct pmu *pmu)
  939. {
  940. arm_cmn_clear_state(to_cmn(pmu), CMN_STATE_TXN);
  941. }
  942. static int arm_cmn_commit_txn(struct pmu *pmu)
  943. {
  944. arm_cmn_end_txn(pmu);
  945. return 0;
  946. }
  947. static int arm_cmn_pmu_offline_cpu(unsigned int cpu, struct hlist_node *node)
  948. {
  949. struct arm_cmn *cmn;
  950. unsigned int i, target;
  951. cmn = hlist_entry_safe(node, struct arm_cmn, cpuhp_node);
  952. if (cpu != cmn->cpu)
  953. return 0;
  954. target = cpumask_any_but(cpu_online_mask, cpu);
  955. if (target >= nr_cpu_ids)
  956. return 0;
  957. perf_pmu_migrate_context(&cmn->pmu, cpu, target);
  958. for (i = 0; i < cmn->num_dtcs; i++)
  959. irq_set_affinity_hint(cmn->dtc[i].irq, cpumask_of(target));
  960. cmn->cpu = target;
  961. return 0;
  962. }
  963. static irqreturn_t arm_cmn_handle_irq(int irq, void *dev_id)
  964. {
  965. struct arm_cmn_dtc *dtc = dev_id;
  966. irqreturn_t ret = IRQ_NONE;
  967. for (;;) {
  968. u32 status = readl_relaxed(dtc->base + CMN_DT_PMOVSR);
  969. u64 delta;
  970. int i;
  971. for (i = 0; i < CMN_DTM_NUM_COUNTERS; i++) {
  972. if (status & (1U << i)) {
  973. ret = IRQ_HANDLED;
  974. if (WARN_ON(!dtc->counters[i]))
  975. continue;
  976. delta = (u64)arm_cmn_read_counter(dtc, i) << 16;
  977. local64_add(delta, &dtc->counters[i]->count);
  978. }
  979. }
  980. if (status & (1U << CMN_DT_NUM_COUNTERS)) {
  981. ret = IRQ_HANDLED;
  982. if (dtc->cc_active && !WARN_ON(!dtc->cycles)) {
  983. delta = arm_cmn_read_cc(dtc);
  984. local64_add(delta, &dtc->cycles->count);
  985. }
  986. }
  987. writel_relaxed(status, dtc->base + CMN_DT_PMOVSR_CLR);
  988. if (!dtc->irq_friend)
  989. return ret;
  990. dtc += dtc->irq_friend;
  991. }
  992. }
  993. /* We can reasonably accommodate DTCs of the same CMN sharing IRQs */
  994. static int arm_cmn_init_irqs(struct arm_cmn *cmn)
  995. {
  996. int i, j, irq, err;
  997. for (i = 0; i < cmn->num_dtcs; i++) {
  998. irq = cmn->dtc[i].irq;
  999. for (j = i; j--; ) {
  1000. if (cmn->dtc[j].irq == irq) {
  1001. cmn->dtc[j].irq_friend = i - j;
  1002. goto next;
  1003. }
  1004. }
  1005. err = devm_request_irq(cmn->dev, irq, arm_cmn_handle_irq,
  1006. IRQF_NOBALANCING | IRQF_NO_THREAD,
  1007. dev_name(cmn->dev), &cmn->dtc[i]);
  1008. if (err)
  1009. return err;
  1010. err = irq_set_affinity_hint(irq, cpumask_of(cmn->cpu));
  1011. if (err)
  1012. return err;
  1013. next:
  1014. ; /* isn't C great? */
  1015. }
  1016. return 0;
  1017. }
  1018. static void arm_cmn_init_dtm(struct arm_cmn_node *xp)
  1019. {
  1020. int i;
  1021. for (i = 0; i < 4; i++) {
  1022. xp->wp_event[i] = -1;
  1023. writeq_relaxed(0, xp->pmu_base + CMN_DTM_WPn_MASK(i));
  1024. writeq_relaxed(~0ULL, xp->pmu_base + CMN_DTM_WPn_VAL(i));
  1025. }
  1026. xp->pmu_config_low = CMN_DTM_PMU_CONFIG_PMU_EN;
  1027. xp->dtc = -1;
  1028. }
  1029. static int arm_cmn_init_dtc(struct arm_cmn *cmn, struct arm_cmn_node *dn, int idx)
  1030. {
  1031. struct arm_cmn_dtc *dtc = cmn->dtc + idx;
  1032. struct arm_cmn_node *xp;
  1033. dtc->base = dn->pmu_base - CMN_PMU_OFFSET;
  1034. dtc->irq = platform_get_irq(to_platform_device(cmn->dev), idx);
  1035. if (dtc->irq < 0)
  1036. return dtc->irq;
  1037. writel_relaxed(0, dtc->base + CMN_DT_PMCR);
  1038. writel_relaxed(0x1ff, dtc->base + CMN_DT_PMOVSR_CLR);
  1039. writel_relaxed(CMN_DT_PMCR_OVFL_INTR_EN, dtc->base + CMN_DT_PMCR);
  1040. /* We do at least know that a DTC's XP must be in that DTC's domain */
  1041. xp = arm_cmn_node_to_xp(dn);
  1042. xp->dtc = idx;
  1043. return 0;
  1044. }
  1045. static int arm_cmn_node_cmp(const void *a, const void *b)
  1046. {
  1047. const struct arm_cmn_node *dna = a, *dnb = b;
  1048. int cmp;
  1049. cmp = dna->type - dnb->type;
  1050. if (!cmp)
  1051. cmp = dna->logid - dnb->logid;
  1052. return cmp;
  1053. }
  1054. static int arm_cmn_init_dtcs(struct arm_cmn *cmn)
  1055. {
  1056. struct arm_cmn_node *dn;
  1057. int dtc_idx = 0;
  1058. cmn->dtc = devm_kcalloc(cmn->dev, cmn->num_dtcs, sizeof(cmn->dtc[0]), GFP_KERNEL);
  1059. if (!cmn->dtc)
  1060. return -ENOMEM;
  1061. sort(cmn->dns, cmn->num_dns, sizeof(cmn->dns[0]), arm_cmn_node_cmp, NULL);
  1062. cmn->xps = arm_cmn_node(cmn, CMN_TYPE_XP);
  1063. for (dn = cmn->dns; dn < cmn->dns + cmn->num_dns; dn++) {
  1064. if (dn->type != CMN_TYPE_XP)
  1065. arm_cmn_init_node_to_xp(cmn, dn);
  1066. else if (cmn->num_dtcs == 1)
  1067. dn->dtc = 0;
  1068. if (dn->type == CMN_TYPE_DTC)
  1069. arm_cmn_init_dtc(cmn, dn, dtc_idx++);
  1070. /* To the PMU, RN-Ds don't add anything over RN-Is, so smoosh them together */
  1071. if (dn->type == CMN_TYPE_RND)
  1072. dn->type = CMN_TYPE_RNI;
  1073. }
  1074. writel_relaxed(CMN_DT_DTC_CTL_DT_EN, cmn->dtc[0].base + CMN_DT_DTC_CTL);
  1075. return 0;
  1076. }
  1077. static void arm_cmn_init_node_info(struct arm_cmn *cmn, u32 offset, struct arm_cmn_node *node)
  1078. {
  1079. int level;
  1080. u64 reg = readq_relaxed(cmn->base + offset + CMN_NODE_INFO);
  1081. node->type = FIELD_GET(CMN_NI_NODE_TYPE, reg);
  1082. node->id = FIELD_GET(CMN_NI_NODE_ID, reg);
  1083. node->logid = FIELD_GET(CMN_NI_LOGICAL_ID, reg);
  1084. node->pmu_base = cmn->base + offset + CMN_PMU_OFFSET;
  1085. if (node->type == CMN_TYPE_CFG)
  1086. level = 0;
  1087. else if (node->type == CMN_TYPE_XP)
  1088. level = 1;
  1089. else
  1090. level = 2;
  1091. dev_dbg(cmn->dev, "node%*c%#06hx%*ctype:%-#6x id:%-4hd off:%#x\n",
  1092. (level * 2) + 1, ' ', node->id, 5 - (level * 2), ' ',
  1093. node->type, node->logid, offset);
  1094. }
  1095. static int arm_cmn_discover(struct arm_cmn *cmn, unsigned int rgn_offset)
  1096. {
  1097. void __iomem *cfg_region;
  1098. struct arm_cmn_node cfg, *dn;
  1099. u16 child_count, child_poff;
  1100. u32 xp_offset[CMN_MAX_XPS];
  1101. u64 reg;
  1102. int i, j;
  1103. cfg_region = cmn->base + rgn_offset;
  1104. reg = readl_relaxed(cfg_region + CMN_CFGM_PERIPH_ID_2);
  1105. cmn->rev = FIELD_GET(CMN_CFGM_PID2_REVISION, reg);
  1106. dev_dbg(cmn->dev, "periph_id_2 revision: %d\n", cmn->rev);
  1107. arm_cmn_init_node_info(cmn, rgn_offset, &cfg);
  1108. if (cfg.type != CMN_TYPE_CFG)
  1109. return -ENODEV;
  1110. reg = readq_relaxed(cfg_region + CMN_CHILD_INFO);
  1111. child_count = FIELD_GET(CMN_CI_CHILD_COUNT, reg);
  1112. child_poff = FIELD_GET(CMN_CI_CHILD_PTR_OFFSET, reg);
  1113. cmn->num_xps = child_count;
  1114. cmn->num_dns = cmn->num_xps;
  1115. /* Pass 1: visit the XPs, enumerate their children */
  1116. for (i = 0; i < cmn->num_xps; i++) {
  1117. reg = readq_relaxed(cfg_region + child_poff + i * 8);
  1118. xp_offset[i] = reg & CMN_CHILD_NODE_ADDR;
  1119. reg = readq_relaxed(cmn->base + xp_offset[i] + CMN_CHILD_INFO);
  1120. cmn->num_dns += FIELD_GET(CMN_CI_CHILD_COUNT, reg);
  1121. }
  1122. /* Cheeky +1 to help terminate pointer-based iteration */
  1123. cmn->dns = devm_kcalloc(cmn->dev, cmn->num_dns + 1,
  1124. sizeof(*cmn->dns), GFP_KERNEL);
  1125. if (!cmn->dns)
  1126. return -ENOMEM;
  1127. /* Pass 2: now we can actually populate the nodes */
  1128. dn = cmn->dns;
  1129. for (i = 0; i < cmn->num_xps; i++) {
  1130. void __iomem *xp_region = cmn->base + xp_offset[i];
  1131. struct arm_cmn_node *xp = dn++;
  1132. arm_cmn_init_node_info(cmn, xp_offset[i], xp);
  1133. arm_cmn_init_dtm(xp);
  1134. /*
  1135. * Thanks to the order in which XP logical IDs seem to be
  1136. * assigned, we can handily infer the mesh X dimension by
  1137. * looking out for the XP at (0,1) without needing to know
  1138. * the exact node ID format, which we can later derive.
  1139. */
  1140. if (xp->id == (1 << 3))
  1141. cmn->mesh_x = xp->logid;
  1142. reg = readq_relaxed(xp_region + CMN_CHILD_INFO);
  1143. child_count = FIELD_GET(CMN_CI_CHILD_COUNT, reg);
  1144. child_poff = FIELD_GET(CMN_CI_CHILD_PTR_OFFSET, reg);
  1145. for (j = 0; j < child_count; j++) {
  1146. reg = readq_relaxed(xp_region + child_poff + j * 8);
  1147. /*
  1148. * Don't even try to touch anything external, since in general
  1149. * we haven't a clue how to power up arbitrary CHI requesters.
  1150. * As of CMN-600r1 these could only be RN-SAMs or CXLAs,
  1151. * neither of which have any PMU events anyway.
  1152. * (Actually, CXLAs do seem to have grown some events in r1p2,
  1153. * but they don't go to regular XP DTMs, and they depend on
  1154. * secure configuration which we can't easily deal with)
  1155. */
  1156. if (reg & CMN_CHILD_NODE_EXTERNAL) {
  1157. dev_dbg(cmn->dev, "ignoring external node %llx\n", reg);
  1158. continue;
  1159. }
  1160. arm_cmn_init_node_info(cmn, reg & CMN_CHILD_NODE_ADDR, dn);
  1161. switch (dn->type) {
  1162. case CMN_TYPE_DTC:
  1163. cmn->num_dtcs++;
  1164. dn++;
  1165. break;
  1166. /* These guys have PMU events */
  1167. case CMN_TYPE_DVM:
  1168. case CMN_TYPE_HNI:
  1169. case CMN_TYPE_HNF:
  1170. case CMN_TYPE_SBSX:
  1171. case CMN_TYPE_RNI:
  1172. case CMN_TYPE_RND:
  1173. case CMN_TYPE_CXRA:
  1174. case CMN_TYPE_CXHA:
  1175. dn++;
  1176. break;
  1177. /* Nothing to see here */
  1178. case CMN_TYPE_RNSAM:
  1179. case CMN_TYPE_CXLA:
  1180. break;
  1181. /* Something has gone horribly wrong */
  1182. default:
  1183. dev_err(cmn->dev, "invalid device node type: 0x%x\n", dn->type);
  1184. return -ENODEV;
  1185. }
  1186. }
  1187. }
  1188. /* Correct for any nodes we skipped */
  1189. cmn->num_dns = dn - cmn->dns;
  1190. /*
  1191. * If mesh_x wasn't set during discovery then we never saw
  1192. * an XP at (0,1), thus we must have an Nx1 configuration.
  1193. */
  1194. if (!cmn->mesh_x)
  1195. cmn->mesh_x = cmn->num_xps;
  1196. cmn->mesh_y = cmn->num_xps / cmn->mesh_x;
  1197. dev_dbg(cmn->dev, "mesh %dx%d, ID width %d\n",
  1198. cmn->mesh_x, cmn->mesh_y, arm_cmn_xyidbits(cmn));
  1199. return 0;
  1200. }
  1201. static int arm_cmn_acpi_probe(struct platform_device *pdev, struct arm_cmn *cmn)
  1202. {
  1203. struct resource *cfg, *root;
  1204. cfg = platform_get_resource(pdev, IORESOURCE_MEM, 0);
  1205. if (!cfg)
  1206. return -EINVAL;
  1207. root = platform_get_resource(pdev, IORESOURCE_MEM, 1);
  1208. if (!root)
  1209. return -EINVAL;
  1210. if (!resource_contains(cfg, root))
  1211. swap(cfg, root);
  1212. /*
  1213. * Note that devm_ioremap_resource() is dumb and won't let the platform
  1214. * device claim cfg when the ACPI companion device has already claimed
  1215. * root within it. But since they *are* already both claimed in the
  1216. * appropriate name, we don't really need to do it again here anyway.
  1217. */
  1218. cmn->base = devm_ioremap(cmn->dev, cfg->start, resource_size(cfg));
  1219. if (!cmn->base)
  1220. return -ENOMEM;
  1221. return root->start - cfg->start;
  1222. }
  1223. static int arm_cmn_of_probe(struct platform_device *pdev, struct arm_cmn *cmn)
  1224. {
  1225. struct device_node *np = pdev->dev.of_node;
  1226. u32 rootnode;
  1227. int ret;
  1228. cmn->base = devm_platform_ioremap_resource(pdev, 0);
  1229. if (IS_ERR(cmn->base))
  1230. return PTR_ERR(cmn->base);
  1231. ret = of_property_read_u32(np, "arm,root-node", &rootnode);
  1232. if (ret)
  1233. return ret;
  1234. return rootnode;
  1235. }
  1236. static int arm_cmn_probe(struct platform_device *pdev)
  1237. {
  1238. struct arm_cmn *cmn;
  1239. const char *name;
  1240. static atomic_t id;
  1241. int err, rootnode;
  1242. cmn = devm_kzalloc(&pdev->dev, sizeof(*cmn), GFP_KERNEL);
  1243. if (!cmn)
  1244. return -ENOMEM;
  1245. cmn->dev = &pdev->dev;
  1246. platform_set_drvdata(pdev, cmn);
  1247. if (has_acpi_companion(cmn->dev))
  1248. rootnode = arm_cmn_acpi_probe(pdev, cmn);
  1249. else
  1250. rootnode = arm_cmn_of_probe(pdev, cmn);
  1251. if (rootnode < 0)
  1252. return rootnode;
  1253. err = arm_cmn_discover(cmn, rootnode);
  1254. if (err)
  1255. return err;
  1256. err = arm_cmn_init_dtcs(cmn);
  1257. if (err)
  1258. return err;
  1259. err = arm_cmn_init_irqs(cmn);
  1260. if (err)
  1261. return err;
  1262. cmn->cpu = raw_smp_processor_id();
  1263. cmn->pmu = (struct pmu) {
  1264. .module = THIS_MODULE,
  1265. .attr_groups = arm_cmn_attr_groups,
  1266. .capabilities = PERF_PMU_CAP_NO_EXCLUDE,
  1267. .task_ctx_nr = perf_invalid_context,
  1268. .pmu_enable = arm_cmn_pmu_enable,
  1269. .pmu_disable = arm_cmn_pmu_disable,
  1270. .event_init = arm_cmn_event_init,
  1271. .add = arm_cmn_event_add,
  1272. .del = arm_cmn_event_del,
  1273. .start = arm_cmn_event_start,
  1274. .stop = arm_cmn_event_stop,
  1275. .read = arm_cmn_event_read,
  1276. .start_txn = arm_cmn_start_txn,
  1277. .commit_txn = arm_cmn_commit_txn,
  1278. .cancel_txn = arm_cmn_end_txn,
  1279. };
  1280. name = devm_kasprintf(cmn->dev, GFP_KERNEL, "arm_cmn_%d", atomic_fetch_inc(&id));
  1281. if (!name)
  1282. return -ENOMEM;
  1283. err = cpuhp_state_add_instance(arm_cmn_hp_state, &cmn->cpuhp_node);
  1284. if (err)
  1285. return err;
  1286. err = perf_pmu_register(&cmn->pmu, name, -1);
  1287. if (err)
  1288. cpuhp_state_remove_instance(arm_cmn_hp_state, &cmn->cpuhp_node);
  1289. return err;
  1290. }
  1291. static int arm_cmn_remove(struct platform_device *pdev)
  1292. {
  1293. struct arm_cmn *cmn = platform_get_drvdata(pdev);
  1294. int i;
  1295. writel_relaxed(0, cmn->dtc[0].base + CMN_DT_DTC_CTL);
  1296. perf_pmu_unregister(&cmn->pmu);
  1297. cpuhp_state_remove_instance(arm_cmn_hp_state, &cmn->cpuhp_node);
  1298. for (i = 0; i < cmn->num_dtcs; i++)
  1299. irq_set_affinity_hint(cmn->dtc[i].irq, NULL);
  1300. return 0;
  1301. }
  1302. #ifdef CONFIG_OF
  1303. static const struct of_device_id arm_cmn_of_match[] = {
  1304. { .compatible = "arm,cmn-600", },
  1305. {}
  1306. };
  1307. MODULE_DEVICE_TABLE(of, arm_cmn_of_match);
  1308. #endif
  1309. #ifdef CONFIG_ACPI
  1310. static const struct acpi_device_id arm_cmn_acpi_match[] = {
  1311. { "ARMHC600", },
  1312. {}
  1313. };
  1314. MODULE_DEVICE_TABLE(acpi, arm_cmn_acpi_match);
  1315. #endif
  1316. static struct platform_driver arm_cmn_driver = {
  1317. .driver = {
  1318. .name = "arm-cmn",
  1319. .of_match_table = of_match_ptr(arm_cmn_of_match),
  1320. .acpi_match_table = ACPI_PTR(arm_cmn_acpi_match),
  1321. },
  1322. .probe = arm_cmn_probe,
  1323. .remove = arm_cmn_remove,
  1324. };
  1325. static int __init arm_cmn_init(void)
  1326. {
  1327. int ret;
  1328. ret = cpuhp_setup_state_multi(CPUHP_AP_ONLINE_DYN,
  1329. "perf/arm/cmn:online", NULL,
  1330. arm_cmn_pmu_offline_cpu);
  1331. if (ret < 0)
  1332. return ret;
  1333. arm_cmn_hp_state = ret;
  1334. ret = platform_driver_register(&arm_cmn_driver);
  1335. if (ret)
  1336. cpuhp_remove_multi_state(arm_cmn_hp_state);
  1337. return ret;
  1338. }
  1339. static void __exit arm_cmn_exit(void)
  1340. {
  1341. platform_driver_unregister(&arm_cmn_driver);
  1342. cpuhp_remove_multi_state(arm_cmn_hp_state);
  1343. }
  1344. module_init(arm_cmn_init);
  1345. module_exit(arm_cmn_exit);
  1346. MODULE_AUTHOR("Robin Murphy <robin.murphy@arm.com>");
  1347. MODULE_DESCRIPTION("Arm CMN-600 PMU driver");
  1348. MODULE_LICENSE("GPL v2");