arm-cci.c 48 KB

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  1. // SPDX-License-Identifier: GPL-2.0
  2. // CCI Cache Coherent Interconnect PMU driver
  3. // Copyright (C) 2013-2018 Arm Ltd.
  4. // Author: Punit Agrawal <punit.agrawal@arm.com>, Suzuki Poulose <suzuki.poulose@arm.com>
  5. #include <linux/arm-cci.h>
  6. #include <linux/io.h>
  7. #include <linux/interrupt.h>
  8. #include <linux/module.h>
  9. #include <linux/of_address.h>
  10. #include <linux/of_device.h>
  11. #include <linux/of_irq.h>
  12. #include <linux/of_platform.h>
  13. #include <linux/perf_event.h>
  14. #include <linux/platform_device.h>
  15. #include <linux/slab.h>
  16. #include <linux/spinlock.h>
  17. #define DRIVER_NAME "ARM-CCI PMU"
  18. #define CCI_PMCR 0x0100
  19. #define CCI_PID2 0x0fe8
  20. #define CCI_PMCR_CEN 0x00000001
  21. #define CCI_PMCR_NCNT_MASK 0x0000f800
  22. #define CCI_PMCR_NCNT_SHIFT 11
  23. #define CCI_PID2_REV_MASK 0xf0
  24. #define CCI_PID2_REV_SHIFT 4
  25. #define CCI_PMU_EVT_SEL 0x000
  26. #define CCI_PMU_CNTR 0x004
  27. #define CCI_PMU_CNTR_CTRL 0x008
  28. #define CCI_PMU_OVRFLW 0x00c
  29. #define CCI_PMU_OVRFLW_FLAG 1
  30. #define CCI_PMU_CNTR_SIZE(model) ((model)->cntr_size)
  31. #define CCI_PMU_CNTR_BASE(model, idx) ((idx) * CCI_PMU_CNTR_SIZE(model))
  32. #define CCI_PMU_CNTR_MASK ((1ULL << 32) -1)
  33. #define CCI_PMU_CNTR_LAST(cci_pmu) (cci_pmu->num_cntrs - 1)
  34. #define CCI_PMU_MAX_HW_CNTRS(model) \
  35. ((model)->num_hw_cntrs + (model)->fixed_hw_cntrs)
  36. /* Types of interfaces that can generate events */
  37. enum {
  38. CCI_IF_SLAVE,
  39. CCI_IF_MASTER,
  40. #ifdef CONFIG_ARM_CCI5xx_PMU
  41. CCI_IF_GLOBAL,
  42. #endif
  43. CCI_IF_MAX,
  44. };
  45. #define NUM_HW_CNTRS_CII_4XX 4
  46. #define NUM_HW_CNTRS_CII_5XX 8
  47. #define NUM_HW_CNTRS_MAX NUM_HW_CNTRS_CII_5XX
  48. #define FIXED_HW_CNTRS_CII_4XX 1
  49. #define FIXED_HW_CNTRS_CII_5XX 0
  50. #define FIXED_HW_CNTRS_MAX FIXED_HW_CNTRS_CII_4XX
  51. #define HW_CNTRS_MAX (NUM_HW_CNTRS_MAX + FIXED_HW_CNTRS_MAX)
  52. struct event_range {
  53. u32 min;
  54. u32 max;
  55. };
  56. struct cci_pmu_hw_events {
  57. struct perf_event **events;
  58. unsigned long *used_mask;
  59. raw_spinlock_t pmu_lock;
  60. };
  61. struct cci_pmu;
  62. /*
  63. * struct cci_pmu_model:
  64. * @fixed_hw_cntrs - Number of fixed event counters
  65. * @num_hw_cntrs - Maximum number of programmable event counters
  66. * @cntr_size - Size of an event counter mapping
  67. */
  68. struct cci_pmu_model {
  69. char *name;
  70. u32 fixed_hw_cntrs;
  71. u32 num_hw_cntrs;
  72. u32 cntr_size;
  73. struct attribute **format_attrs;
  74. struct attribute **event_attrs;
  75. struct event_range event_ranges[CCI_IF_MAX];
  76. int (*validate_hw_event)(struct cci_pmu *, unsigned long);
  77. int (*get_event_idx)(struct cci_pmu *, struct cci_pmu_hw_events *, unsigned long);
  78. void (*write_counters)(struct cci_pmu *, unsigned long *);
  79. };
  80. static struct cci_pmu_model cci_pmu_models[];
  81. struct cci_pmu {
  82. void __iomem *base;
  83. void __iomem *ctrl_base;
  84. struct pmu pmu;
  85. int cpu;
  86. int nr_irqs;
  87. int *irqs;
  88. unsigned long active_irqs;
  89. const struct cci_pmu_model *model;
  90. struct cci_pmu_hw_events hw_events;
  91. struct platform_device *plat_device;
  92. int num_cntrs;
  93. atomic_t active_events;
  94. struct mutex reserve_mutex;
  95. };
  96. #define to_cci_pmu(c) (container_of(c, struct cci_pmu, pmu))
  97. static struct cci_pmu *g_cci_pmu;
  98. enum cci_models {
  99. #ifdef CONFIG_ARM_CCI400_PMU
  100. CCI400_R0,
  101. CCI400_R1,
  102. #endif
  103. #ifdef CONFIG_ARM_CCI5xx_PMU
  104. CCI500_R0,
  105. CCI550_R0,
  106. #endif
  107. CCI_MODEL_MAX
  108. };
  109. static void pmu_write_counters(struct cci_pmu *cci_pmu,
  110. unsigned long *mask);
  111. static ssize_t __maybe_unused cci_pmu_format_show(struct device *dev,
  112. struct device_attribute *attr, char *buf);
  113. static ssize_t __maybe_unused cci_pmu_event_show(struct device *dev,
  114. struct device_attribute *attr, char *buf);
  115. #define CCI_EXT_ATTR_ENTRY(_name, _func, _config) \
  116. &((struct dev_ext_attribute[]) { \
  117. { __ATTR(_name, S_IRUGO, _func, NULL), (void *)_config } \
  118. })[0].attr.attr
  119. #define CCI_FORMAT_EXT_ATTR_ENTRY(_name, _config) \
  120. CCI_EXT_ATTR_ENTRY(_name, cci_pmu_format_show, (char *)_config)
  121. #define CCI_EVENT_EXT_ATTR_ENTRY(_name, _config) \
  122. CCI_EXT_ATTR_ENTRY(_name, cci_pmu_event_show, (unsigned long)_config)
  123. /* CCI400 PMU Specific definitions */
  124. #ifdef CONFIG_ARM_CCI400_PMU
  125. /* Port ids */
  126. #define CCI400_PORT_S0 0
  127. #define CCI400_PORT_S1 1
  128. #define CCI400_PORT_S2 2
  129. #define CCI400_PORT_S3 3
  130. #define CCI400_PORT_S4 4
  131. #define CCI400_PORT_M0 5
  132. #define CCI400_PORT_M1 6
  133. #define CCI400_PORT_M2 7
  134. #define CCI400_R1_PX 5
  135. /*
  136. * Instead of an event id to monitor CCI cycles, a dedicated counter is
  137. * provided. Use 0xff to represent CCI cycles and hope that no future revisions
  138. * make use of this event in hardware.
  139. */
  140. enum cci400_perf_events {
  141. CCI400_PMU_CYCLES = 0xff
  142. };
  143. #define CCI400_PMU_CYCLE_CNTR_IDX 0
  144. #define CCI400_PMU_CNTR0_IDX 1
  145. /*
  146. * CCI PMU event id is an 8-bit value made of two parts - bits 7:5 for one of 8
  147. * ports and bits 4:0 are event codes. There are different event codes
  148. * associated with each port type.
  149. *
  150. * Additionally, the range of events associated with the port types changed
  151. * between Rev0 and Rev1.
  152. *
  153. * The constants below define the range of valid codes for each port type for
  154. * the different revisions and are used to validate the event to be monitored.
  155. */
  156. #define CCI400_PMU_EVENT_MASK 0xffUL
  157. #define CCI400_PMU_EVENT_SOURCE_SHIFT 5
  158. #define CCI400_PMU_EVENT_SOURCE_MASK 0x7
  159. #define CCI400_PMU_EVENT_CODE_SHIFT 0
  160. #define CCI400_PMU_EVENT_CODE_MASK 0x1f
  161. #define CCI400_PMU_EVENT_SOURCE(event) \
  162. ((event >> CCI400_PMU_EVENT_SOURCE_SHIFT) & \
  163. CCI400_PMU_EVENT_SOURCE_MASK)
  164. #define CCI400_PMU_EVENT_CODE(event) \
  165. ((event >> CCI400_PMU_EVENT_CODE_SHIFT) & CCI400_PMU_EVENT_CODE_MASK)
  166. #define CCI400_R0_SLAVE_PORT_MIN_EV 0x00
  167. #define CCI400_R0_SLAVE_PORT_MAX_EV 0x13
  168. #define CCI400_R0_MASTER_PORT_MIN_EV 0x14
  169. #define CCI400_R0_MASTER_PORT_MAX_EV 0x1a
  170. #define CCI400_R1_SLAVE_PORT_MIN_EV 0x00
  171. #define CCI400_R1_SLAVE_PORT_MAX_EV 0x14
  172. #define CCI400_R1_MASTER_PORT_MIN_EV 0x00
  173. #define CCI400_R1_MASTER_PORT_MAX_EV 0x11
  174. #define CCI400_CYCLE_EVENT_EXT_ATTR_ENTRY(_name, _config) \
  175. CCI_EXT_ATTR_ENTRY(_name, cci400_pmu_cycle_event_show, \
  176. (unsigned long)_config)
  177. static ssize_t cci400_pmu_cycle_event_show(struct device *dev,
  178. struct device_attribute *attr, char *buf);
  179. static struct attribute *cci400_pmu_format_attrs[] = {
  180. CCI_FORMAT_EXT_ATTR_ENTRY(event, "config:0-4"),
  181. CCI_FORMAT_EXT_ATTR_ENTRY(source, "config:5-7"),
  182. NULL
  183. };
  184. static struct attribute *cci400_r0_pmu_event_attrs[] = {
  185. /* Slave events */
  186. CCI_EVENT_EXT_ATTR_ENTRY(si_rrq_hs_any, 0x0),
  187. CCI_EVENT_EXT_ATTR_ENTRY(si_rrq_hs_device, 0x01),
  188. CCI_EVENT_EXT_ATTR_ENTRY(si_rrq_hs_normal_or_nonshareable, 0x2),
  189. CCI_EVENT_EXT_ATTR_ENTRY(si_rrq_hs_inner_or_outershareable, 0x3),
  190. CCI_EVENT_EXT_ATTR_ENTRY(si_rrq_hs_cache_maintenance, 0x4),
  191. CCI_EVENT_EXT_ATTR_ENTRY(si_rrq_hs_mem_barrier, 0x5),
  192. CCI_EVENT_EXT_ATTR_ENTRY(si_rrq_hs_sync_barrier, 0x6),
  193. CCI_EVENT_EXT_ATTR_ENTRY(si_rrq_hs_dvm_msg, 0x7),
  194. CCI_EVENT_EXT_ATTR_ENTRY(si_rrq_hs_dvm_msg_sync, 0x8),
  195. CCI_EVENT_EXT_ATTR_ENTRY(si_rrq_stall_tt_full, 0x9),
  196. CCI_EVENT_EXT_ATTR_ENTRY(si_r_data_last_hs_snoop, 0xA),
  197. CCI_EVENT_EXT_ATTR_ENTRY(si_r_data_stall_rvalids_h_rready_l, 0xB),
  198. CCI_EVENT_EXT_ATTR_ENTRY(si_wrq_hs_any, 0xC),
  199. CCI_EVENT_EXT_ATTR_ENTRY(si_wrq_hs_device, 0xD),
  200. CCI_EVENT_EXT_ATTR_ENTRY(si_wrq_hs_normal_or_nonshareable, 0xE),
  201. CCI_EVENT_EXT_ATTR_ENTRY(si_wrq_hs_inner_or_outershare_wback_wclean, 0xF),
  202. CCI_EVENT_EXT_ATTR_ENTRY(si_wrq_hs_write_unique, 0x10),
  203. CCI_EVENT_EXT_ATTR_ENTRY(si_wrq_hs_write_line_unique, 0x11),
  204. CCI_EVENT_EXT_ATTR_ENTRY(si_wrq_hs_evict, 0x12),
  205. CCI_EVENT_EXT_ATTR_ENTRY(si_wrq_stall_tt_full, 0x13),
  206. /* Master events */
  207. CCI_EVENT_EXT_ATTR_ENTRY(mi_retry_speculative_fetch, 0x14),
  208. CCI_EVENT_EXT_ATTR_ENTRY(mi_rrq_stall_addr_hazard, 0x15),
  209. CCI_EVENT_EXT_ATTR_ENTRY(mi_rrq_stall_id_hazard, 0x16),
  210. CCI_EVENT_EXT_ATTR_ENTRY(mi_rrq_stall_tt_full, 0x17),
  211. CCI_EVENT_EXT_ATTR_ENTRY(mi_rrq_stall_barrier_hazard, 0x18),
  212. CCI_EVENT_EXT_ATTR_ENTRY(mi_wrq_stall_barrier_hazard, 0x19),
  213. CCI_EVENT_EXT_ATTR_ENTRY(mi_wrq_stall_tt_full, 0x1A),
  214. /* Special event for cycles counter */
  215. CCI400_CYCLE_EVENT_EXT_ATTR_ENTRY(cycles, 0xff),
  216. NULL
  217. };
  218. static struct attribute *cci400_r1_pmu_event_attrs[] = {
  219. /* Slave events */
  220. CCI_EVENT_EXT_ATTR_ENTRY(si_rrq_hs_any, 0x0),
  221. CCI_EVENT_EXT_ATTR_ENTRY(si_rrq_hs_device, 0x01),
  222. CCI_EVENT_EXT_ATTR_ENTRY(si_rrq_hs_normal_or_nonshareable, 0x2),
  223. CCI_EVENT_EXT_ATTR_ENTRY(si_rrq_hs_inner_or_outershareable, 0x3),
  224. CCI_EVENT_EXT_ATTR_ENTRY(si_rrq_hs_cache_maintenance, 0x4),
  225. CCI_EVENT_EXT_ATTR_ENTRY(si_rrq_hs_mem_barrier, 0x5),
  226. CCI_EVENT_EXT_ATTR_ENTRY(si_rrq_hs_sync_barrier, 0x6),
  227. CCI_EVENT_EXT_ATTR_ENTRY(si_rrq_hs_dvm_msg, 0x7),
  228. CCI_EVENT_EXT_ATTR_ENTRY(si_rrq_hs_dvm_msg_sync, 0x8),
  229. CCI_EVENT_EXT_ATTR_ENTRY(si_rrq_stall_tt_full, 0x9),
  230. CCI_EVENT_EXT_ATTR_ENTRY(si_r_data_last_hs_snoop, 0xA),
  231. CCI_EVENT_EXT_ATTR_ENTRY(si_r_data_stall_rvalids_h_rready_l, 0xB),
  232. CCI_EVENT_EXT_ATTR_ENTRY(si_wrq_hs_any, 0xC),
  233. CCI_EVENT_EXT_ATTR_ENTRY(si_wrq_hs_device, 0xD),
  234. CCI_EVENT_EXT_ATTR_ENTRY(si_wrq_hs_normal_or_nonshareable, 0xE),
  235. CCI_EVENT_EXT_ATTR_ENTRY(si_wrq_hs_inner_or_outershare_wback_wclean, 0xF),
  236. CCI_EVENT_EXT_ATTR_ENTRY(si_wrq_hs_write_unique, 0x10),
  237. CCI_EVENT_EXT_ATTR_ENTRY(si_wrq_hs_write_line_unique, 0x11),
  238. CCI_EVENT_EXT_ATTR_ENTRY(si_wrq_hs_evict, 0x12),
  239. CCI_EVENT_EXT_ATTR_ENTRY(si_wrq_stall_tt_full, 0x13),
  240. CCI_EVENT_EXT_ATTR_ENTRY(si_rrq_stall_slave_id_hazard, 0x14),
  241. /* Master events */
  242. CCI_EVENT_EXT_ATTR_ENTRY(mi_retry_speculative_fetch, 0x0),
  243. CCI_EVENT_EXT_ATTR_ENTRY(mi_stall_cycle_addr_hazard, 0x1),
  244. CCI_EVENT_EXT_ATTR_ENTRY(mi_rrq_stall_master_id_hazard, 0x2),
  245. CCI_EVENT_EXT_ATTR_ENTRY(mi_rrq_stall_hi_prio_rtq_full, 0x3),
  246. CCI_EVENT_EXT_ATTR_ENTRY(mi_rrq_stall_barrier_hazard, 0x4),
  247. CCI_EVENT_EXT_ATTR_ENTRY(mi_wrq_stall_barrier_hazard, 0x5),
  248. CCI_EVENT_EXT_ATTR_ENTRY(mi_wrq_stall_wtq_full, 0x6),
  249. CCI_EVENT_EXT_ATTR_ENTRY(mi_rrq_stall_low_prio_rtq_full, 0x7),
  250. CCI_EVENT_EXT_ATTR_ENTRY(mi_rrq_stall_mid_prio_rtq_full, 0x8),
  251. CCI_EVENT_EXT_ATTR_ENTRY(mi_rrq_stall_qvn_vn0, 0x9),
  252. CCI_EVENT_EXT_ATTR_ENTRY(mi_rrq_stall_qvn_vn1, 0xA),
  253. CCI_EVENT_EXT_ATTR_ENTRY(mi_rrq_stall_qvn_vn2, 0xB),
  254. CCI_EVENT_EXT_ATTR_ENTRY(mi_rrq_stall_qvn_vn3, 0xC),
  255. CCI_EVENT_EXT_ATTR_ENTRY(mi_wrq_stall_qvn_vn0, 0xD),
  256. CCI_EVENT_EXT_ATTR_ENTRY(mi_wrq_stall_qvn_vn1, 0xE),
  257. CCI_EVENT_EXT_ATTR_ENTRY(mi_wrq_stall_qvn_vn2, 0xF),
  258. CCI_EVENT_EXT_ATTR_ENTRY(mi_wrq_stall_qvn_vn3, 0x10),
  259. CCI_EVENT_EXT_ATTR_ENTRY(mi_wrq_unique_or_line_unique_addr_hazard, 0x11),
  260. /* Special event for cycles counter */
  261. CCI400_CYCLE_EVENT_EXT_ATTR_ENTRY(cycles, 0xff),
  262. NULL
  263. };
  264. static ssize_t cci400_pmu_cycle_event_show(struct device *dev,
  265. struct device_attribute *attr, char *buf)
  266. {
  267. struct dev_ext_attribute *eattr = container_of(attr,
  268. struct dev_ext_attribute, attr);
  269. return snprintf(buf, PAGE_SIZE, "config=0x%lx\n", (unsigned long)eattr->var);
  270. }
  271. static int cci400_get_event_idx(struct cci_pmu *cci_pmu,
  272. struct cci_pmu_hw_events *hw,
  273. unsigned long cci_event)
  274. {
  275. int idx;
  276. /* cycles event idx is fixed */
  277. if (cci_event == CCI400_PMU_CYCLES) {
  278. if (test_and_set_bit(CCI400_PMU_CYCLE_CNTR_IDX, hw->used_mask))
  279. return -EAGAIN;
  280. return CCI400_PMU_CYCLE_CNTR_IDX;
  281. }
  282. for (idx = CCI400_PMU_CNTR0_IDX; idx <= CCI_PMU_CNTR_LAST(cci_pmu); ++idx)
  283. if (!test_and_set_bit(idx, hw->used_mask))
  284. return idx;
  285. /* No counters available */
  286. return -EAGAIN;
  287. }
  288. static int cci400_validate_hw_event(struct cci_pmu *cci_pmu, unsigned long hw_event)
  289. {
  290. u8 ev_source = CCI400_PMU_EVENT_SOURCE(hw_event);
  291. u8 ev_code = CCI400_PMU_EVENT_CODE(hw_event);
  292. int if_type;
  293. if (hw_event & ~CCI400_PMU_EVENT_MASK)
  294. return -ENOENT;
  295. if (hw_event == CCI400_PMU_CYCLES)
  296. return hw_event;
  297. switch (ev_source) {
  298. case CCI400_PORT_S0:
  299. case CCI400_PORT_S1:
  300. case CCI400_PORT_S2:
  301. case CCI400_PORT_S3:
  302. case CCI400_PORT_S4:
  303. /* Slave Interface */
  304. if_type = CCI_IF_SLAVE;
  305. break;
  306. case CCI400_PORT_M0:
  307. case CCI400_PORT_M1:
  308. case CCI400_PORT_M2:
  309. /* Master Interface */
  310. if_type = CCI_IF_MASTER;
  311. break;
  312. default:
  313. return -ENOENT;
  314. }
  315. if (ev_code >= cci_pmu->model->event_ranges[if_type].min &&
  316. ev_code <= cci_pmu->model->event_ranges[if_type].max)
  317. return hw_event;
  318. return -ENOENT;
  319. }
  320. static int probe_cci400_revision(struct cci_pmu *cci_pmu)
  321. {
  322. int rev;
  323. rev = readl_relaxed(cci_pmu->ctrl_base + CCI_PID2) & CCI_PID2_REV_MASK;
  324. rev >>= CCI_PID2_REV_SHIFT;
  325. if (rev < CCI400_R1_PX)
  326. return CCI400_R0;
  327. else
  328. return CCI400_R1;
  329. }
  330. static const struct cci_pmu_model *probe_cci_model(struct cci_pmu *cci_pmu)
  331. {
  332. if (platform_has_secure_cci_access())
  333. return &cci_pmu_models[probe_cci400_revision(cci_pmu)];
  334. return NULL;
  335. }
  336. #else /* !CONFIG_ARM_CCI400_PMU */
  337. static inline struct cci_pmu_model *probe_cci_model(struct cci_pmu *cci_pmu)
  338. {
  339. return NULL;
  340. }
  341. #endif /* CONFIG_ARM_CCI400_PMU */
  342. #ifdef CONFIG_ARM_CCI5xx_PMU
  343. /*
  344. * CCI5xx PMU event id is an 9-bit value made of two parts.
  345. * bits [8:5] - Source for the event
  346. * bits [4:0] - Event code (specific to type of interface)
  347. *
  348. *
  349. */
  350. /* Port ids */
  351. #define CCI5xx_PORT_S0 0x0
  352. #define CCI5xx_PORT_S1 0x1
  353. #define CCI5xx_PORT_S2 0x2
  354. #define CCI5xx_PORT_S3 0x3
  355. #define CCI5xx_PORT_S4 0x4
  356. #define CCI5xx_PORT_S5 0x5
  357. #define CCI5xx_PORT_S6 0x6
  358. #define CCI5xx_PORT_M0 0x8
  359. #define CCI5xx_PORT_M1 0x9
  360. #define CCI5xx_PORT_M2 0xa
  361. #define CCI5xx_PORT_M3 0xb
  362. #define CCI5xx_PORT_M4 0xc
  363. #define CCI5xx_PORT_M5 0xd
  364. #define CCI5xx_PORT_M6 0xe
  365. #define CCI5xx_PORT_GLOBAL 0xf
  366. #define CCI5xx_PMU_EVENT_MASK 0x1ffUL
  367. #define CCI5xx_PMU_EVENT_SOURCE_SHIFT 0x5
  368. #define CCI5xx_PMU_EVENT_SOURCE_MASK 0xf
  369. #define CCI5xx_PMU_EVENT_CODE_SHIFT 0x0
  370. #define CCI5xx_PMU_EVENT_CODE_MASK 0x1f
  371. #define CCI5xx_PMU_EVENT_SOURCE(event) \
  372. ((event >> CCI5xx_PMU_EVENT_SOURCE_SHIFT) & CCI5xx_PMU_EVENT_SOURCE_MASK)
  373. #define CCI5xx_PMU_EVENT_CODE(event) \
  374. ((event >> CCI5xx_PMU_EVENT_CODE_SHIFT) & CCI5xx_PMU_EVENT_CODE_MASK)
  375. #define CCI5xx_SLAVE_PORT_MIN_EV 0x00
  376. #define CCI5xx_SLAVE_PORT_MAX_EV 0x1f
  377. #define CCI5xx_MASTER_PORT_MIN_EV 0x00
  378. #define CCI5xx_MASTER_PORT_MAX_EV 0x06
  379. #define CCI5xx_GLOBAL_PORT_MIN_EV 0x00
  380. #define CCI5xx_GLOBAL_PORT_MAX_EV 0x0f
  381. #define CCI5xx_GLOBAL_EVENT_EXT_ATTR_ENTRY(_name, _config) \
  382. CCI_EXT_ATTR_ENTRY(_name, cci5xx_pmu_global_event_show, \
  383. (unsigned long) _config)
  384. static ssize_t cci5xx_pmu_global_event_show(struct device *dev,
  385. struct device_attribute *attr, char *buf);
  386. static struct attribute *cci5xx_pmu_format_attrs[] = {
  387. CCI_FORMAT_EXT_ATTR_ENTRY(event, "config:0-4"),
  388. CCI_FORMAT_EXT_ATTR_ENTRY(source, "config:5-8"),
  389. NULL,
  390. };
  391. static struct attribute *cci5xx_pmu_event_attrs[] = {
  392. /* Slave events */
  393. CCI_EVENT_EXT_ATTR_ENTRY(si_rrq_hs_arvalid, 0x0),
  394. CCI_EVENT_EXT_ATTR_ENTRY(si_rrq_dev, 0x1),
  395. CCI_EVENT_EXT_ATTR_ENTRY(si_rrq_hs_nonshareable, 0x2),
  396. CCI_EVENT_EXT_ATTR_ENTRY(si_rrq_hs_shareable_non_alloc, 0x3),
  397. CCI_EVENT_EXT_ATTR_ENTRY(si_rrq_hs_shareable_alloc, 0x4),
  398. CCI_EVENT_EXT_ATTR_ENTRY(si_rrq_hs_invalidate, 0x5),
  399. CCI_EVENT_EXT_ATTR_ENTRY(si_rrq_hs_cache_maint, 0x6),
  400. CCI_EVENT_EXT_ATTR_ENTRY(si_rrq_hs_dvm_msg, 0x7),
  401. CCI_EVENT_EXT_ATTR_ENTRY(si_rrq_hs_rval, 0x8),
  402. CCI_EVENT_EXT_ATTR_ENTRY(si_rrq_hs_rlast_snoop, 0x9),
  403. CCI_EVENT_EXT_ATTR_ENTRY(si_wrq_hs_awalid, 0xA),
  404. CCI_EVENT_EXT_ATTR_ENTRY(si_wrq_dev, 0xB),
  405. CCI_EVENT_EXT_ATTR_ENTRY(si_wrq_non_shareable, 0xC),
  406. CCI_EVENT_EXT_ATTR_ENTRY(si_wrq_share_wb, 0xD),
  407. CCI_EVENT_EXT_ATTR_ENTRY(si_wrq_share_wlu, 0xE),
  408. CCI_EVENT_EXT_ATTR_ENTRY(si_wrq_share_wunique, 0xF),
  409. CCI_EVENT_EXT_ATTR_ENTRY(si_wrq_evict, 0x10),
  410. CCI_EVENT_EXT_ATTR_ENTRY(si_wrq_wrevict, 0x11),
  411. CCI_EVENT_EXT_ATTR_ENTRY(si_w_data_beat, 0x12),
  412. CCI_EVENT_EXT_ATTR_ENTRY(si_srq_acvalid, 0x13),
  413. CCI_EVENT_EXT_ATTR_ENTRY(si_srq_read, 0x14),
  414. CCI_EVENT_EXT_ATTR_ENTRY(si_srq_clean, 0x15),
  415. CCI_EVENT_EXT_ATTR_ENTRY(si_srq_data_transfer_low, 0x16),
  416. CCI_EVENT_EXT_ATTR_ENTRY(si_rrq_stall_arvalid, 0x17),
  417. CCI_EVENT_EXT_ATTR_ENTRY(si_r_data_stall, 0x18),
  418. CCI_EVENT_EXT_ATTR_ENTRY(si_wrq_stall, 0x19),
  419. CCI_EVENT_EXT_ATTR_ENTRY(si_w_data_stall, 0x1A),
  420. CCI_EVENT_EXT_ATTR_ENTRY(si_w_resp_stall, 0x1B),
  421. CCI_EVENT_EXT_ATTR_ENTRY(si_srq_stall, 0x1C),
  422. CCI_EVENT_EXT_ATTR_ENTRY(si_s_data_stall, 0x1D),
  423. CCI_EVENT_EXT_ATTR_ENTRY(si_rq_stall_ot_limit, 0x1E),
  424. CCI_EVENT_EXT_ATTR_ENTRY(si_r_stall_arbit, 0x1F),
  425. /* Master events */
  426. CCI_EVENT_EXT_ATTR_ENTRY(mi_r_data_beat_any, 0x0),
  427. CCI_EVENT_EXT_ATTR_ENTRY(mi_w_data_beat_any, 0x1),
  428. CCI_EVENT_EXT_ATTR_ENTRY(mi_rrq_stall, 0x2),
  429. CCI_EVENT_EXT_ATTR_ENTRY(mi_r_data_stall, 0x3),
  430. CCI_EVENT_EXT_ATTR_ENTRY(mi_wrq_stall, 0x4),
  431. CCI_EVENT_EXT_ATTR_ENTRY(mi_w_data_stall, 0x5),
  432. CCI_EVENT_EXT_ATTR_ENTRY(mi_w_resp_stall, 0x6),
  433. /* Global events */
  434. CCI5xx_GLOBAL_EVENT_EXT_ATTR_ENTRY(cci_snoop_access_filter_bank_0_1, 0x0),
  435. CCI5xx_GLOBAL_EVENT_EXT_ATTR_ENTRY(cci_snoop_access_filter_bank_2_3, 0x1),
  436. CCI5xx_GLOBAL_EVENT_EXT_ATTR_ENTRY(cci_snoop_access_filter_bank_4_5, 0x2),
  437. CCI5xx_GLOBAL_EVENT_EXT_ATTR_ENTRY(cci_snoop_access_filter_bank_6_7, 0x3),
  438. CCI5xx_GLOBAL_EVENT_EXT_ATTR_ENTRY(cci_snoop_access_miss_filter_bank_0_1, 0x4),
  439. CCI5xx_GLOBAL_EVENT_EXT_ATTR_ENTRY(cci_snoop_access_miss_filter_bank_2_3, 0x5),
  440. CCI5xx_GLOBAL_EVENT_EXT_ATTR_ENTRY(cci_snoop_access_miss_filter_bank_4_5, 0x6),
  441. CCI5xx_GLOBAL_EVENT_EXT_ATTR_ENTRY(cci_snoop_access_miss_filter_bank_6_7, 0x7),
  442. CCI5xx_GLOBAL_EVENT_EXT_ATTR_ENTRY(cci_snoop_back_invalidation, 0x8),
  443. CCI5xx_GLOBAL_EVENT_EXT_ATTR_ENTRY(cci_snoop_stall_alloc_busy, 0x9),
  444. CCI5xx_GLOBAL_EVENT_EXT_ATTR_ENTRY(cci_snoop_stall_tt_full, 0xA),
  445. CCI5xx_GLOBAL_EVENT_EXT_ATTR_ENTRY(cci_wrq, 0xB),
  446. CCI5xx_GLOBAL_EVENT_EXT_ATTR_ENTRY(cci_snoop_cd_hs, 0xC),
  447. CCI5xx_GLOBAL_EVENT_EXT_ATTR_ENTRY(cci_rq_stall_addr_hazard, 0xD),
  448. CCI5xx_GLOBAL_EVENT_EXT_ATTR_ENTRY(cci_snoop_rq_stall_tt_full, 0xE),
  449. CCI5xx_GLOBAL_EVENT_EXT_ATTR_ENTRY(cci_snoop_rq_tzmp1_prot, 0xF),
  450. NULL
  451. };
  452. static ssize_t cci5xx_pmu_global_event_show(struct device *dev,
  453. struct device_attribute *attr, char *buf)
  454. {
  455. struct dev_ext_attribute *eattr = container_of(attr,
  456. struct dev_ext_attribute, attr);
  457. /* Global events have single fixed source code */
  458. return snprintf(buf, PAGE_SIZE, "event=0x%lx,source=0x%x\n",
  459. (unsigned long)eattr->var, CCI5xx_PORT_GLOBAL);
  460. }
  461. /*
  462. * CCI500 provides 8 independent event counters that can count
  463. * any of the events available.
  464. * CCI500 PMU event source ids
  465. * 0x0-0x6 - Slave interfaces
  466. * 0x8-0xD - Master interfaces
  467. * 0xf - Global Events
  468. * 0x7,0xe - Reserved
  469. */
  470. static int cci500_validate_hw_event(struct cci_pmu *cci_pmu,
  471. unsigned long hw_event)
  472. {
  473. u32 ev_source = CCI5xx_PMU_EVENT_SOURCE(hw_event);
  474. u32 ev_code = CCI5xx_PMU_EVENT_CODE(hw_event);
  475. int if_type;
  476. if (hw_event & ~CCI5xx_PMU_EVENT_MASK)
  477. return -ENOENT;
  478. switch (ev_source) {
  479. case CCI5xx_PORT_S0:
  480. case CCI5xx_PORT_S1:
  481. case CCI5xx_PORT_S2:
  482. case CCI5xx_PORT_S3:
  483. case CCI5xx_PORT_S4:
  484. case CCI5xx_PORT_S5:
  485. case CCI5xx_PORT_S6:
  486. if_type = CCI_IF_SLAVE;
  487. break;
  488. case CCI5xx_PORT_M0:
  489. case CCI5xx_PORT_M1:
  490. case CCI5xx_PORT_M2:
  491. case CCI5xx_PORT_M3:
  492. case CCI5xx_PORT_M4:
  493. case CCI5xx_PORT_M5:
  494. if_type = CCI_IF_MASTER;
  495. break;
  496. case CCI5xx_PORT_GLOBAL:
  497. if_type = CCI_IF_GLOBAL;
  498. break;
  499. default:
  500. return -ENOENT;
  501. }
  502. if (ev_code >= cci_pmu->model->event_ranges[if_type].min &&
  503. ev_code <= cci_pmu->model->event_ranges[if_type].max)
  504. return hw_event;
  505. return -ENOENT;
  506. }
  507. /*
  508. * CCI550 provides 8 independent event counters that can count
  509. * any of the events available.
  510. * CCI550 PMU event source ids
  511. * 0x0-0x6 - Slave interfaces
  512. * 0x8-0xe - Master interfaces
  513. * 0xf - Global Events
  514. * 0x7 - Reserved
  515. */
  516. static int cci550_validate_hw_event(struct cci_pmu *cci_pmu,
  517. unsigned long hw_event)
  518. {
  519. u32 ev_source = CCI5xx_PMU_EVENT_SOURCE(hw_event);
  520. u32 ev_code = CCI5xx_PMU_EVENT_CODE(hw_event);
  521. int if_type;
  522. if (hw_event & ~CCI5xx_PMU_EVENT_MASK)
  523. return -ENOENT;
  524. switch (ev_source) {
  525. case CCI5xx_PORT_S0:
  526. case CCI5xx_PORT_S1:
  527. case CCI5xx_PORT_S2:
  528. case CCI5xx_PORT_S3:
  529. case CCI5xx_PORT_S4:
  530. case CCI5xx_PORT_S5:
  531. case CCI5xx_PORT_S6:
  532. if_type = CCI_IF_SLAVE;
  533. break;
  534. case CCI5xx_PORT_M0:
  535. case CCI5xx_PORT_M1:
  536. case CCI5xx_PORT_M2:
  537. case CCI5xx_PORT_M3:
  538. case CCI5xx_PORT_M4:
  539. case CCI5xx_PORT_M5:
  540. case CCI5xx_PORT_M6:
  541. if_type = CCI_IF_MASTER;
  542. break;
  543. case CCI5xx_PORT_GLOBAL:
  544. if_type = CCI_IF_GLOBAL;
  545. break;
  546. default:
  547. return -ENOENT;
  548. }
  549. if (ev_code >= cci_pmu->model->event_ranges[if_type].min &&
  550. ev_code <= cci_pmu->model->event_ranges[if_type].max)
  551. return hw_event;
  552. return -ENOENT;
  553. }
  554. #endif /* CONFIG_ARM_CCI5xx_PMU */
  555. /*
  556. * Program the CCI PMU counters which have PERF_HES_ARCH set
  557. * with the event period and mark them ready before we enable
  558. * PMU.
  559. */
  560. static void cci_pmu_sync_counters(struct cci_pmu *cci_pmu)
  561. {
  562. int i;
  563. struct cci_pmu_hw_events *cci_hw = &cci_pmu->hw_events;
  564. DECLARE_BITMAP(mask, HW_CNTRS_MAX);
  565. bitmap_zero(mask, cci_pmu->num_cntrs);
  566. for_each_set_bit(i, cci_pmu->hw_events.used_mask, cci_pmu->num_cntrs) {
  567. struct perf_event *event = cci_hw->events[i];
  568. if (WARN_ON(!event))
  569. continue;
  570. /* Leave the events which are not counting */
  571. if (event->hw.state & PERF_HES_STOPPED)
  572. continue;
  573. if (event->hw.state & PERF_HES_ARCH) {
  574. set_bit(i, mask);
  575. event->hw.state &= ~PERF_HES_ARCH;
  576. }
  577. }
  578. pmu_write_counters(cci_pmu, mask);
  579. }
  580. /* Should be called with cci_pmu->hw_events->pmu_lock held */
  581. static void __cci_pmu_enable_nosync(struct cci_pmu *cci_pmu)
  582. {
  583. u32 val;
  584. /* Enable all the PMU counters. */
  585. val = readl_relaxed(cci_pmu->ctrl_base + CCI_PMCR) | CCI_PMCR_CEN;
  586. writel(val, cci_pmu->ctrl_base + CCI_PMCR);
  587. }
  588. /* Should be called with cci_pmu->hw_events->pmu_lock held */
  589. static void __cci_pmu_enable_sync(struct cci_pmu *cci_pmu)
  590. {
  591. cci_pmu_sync_counters(cci_pmu);
  592. __cci_pmu_enable_nosync(cci_pmu);
  593. }
  594. /* Should be called with cci_pmu->hw_events->pmu_lock held */
  595. static void __cci_pmu_disable(struct cci_pmu *cci_pmu)
  596. {
  597. u32 val;
  598. /* Disable all the PMU counters. */
  599. val = readl_relaxed(cci_pmu->ctrl_base + CCI_PMCR) & ~CCI_PMCR_CEN;
  600. writel(val, cci_pmu->ctrl_base + CCI_PMCR);
  601. }
  602. static ssize_t cci_pmu_format_show(struct device *dev,
  603. struct device_attribute *attr, char *buf)
  604. {
  605. struct dev_ext_attribute *eattr = container_of(attr,
  606. struct dev_ext_attribute, attr);
  607. return snprintf(buf, PAGE_SIZE, "%s\n", (char *)eattr->var);
  608. }
  609. static ssize_t cci_pmu_event_show(struct device *dev,
  610. struct device_attribute *attr, char *buf)
  611. {
  612. struct dev_ext_attribute *eattr = container_of(attr,
  613. struct dev_ext_attribute, attr);
  614. /* source parameter is mandatory for normal PMU events */
  615. return snprintf(buf, PAGE_SIZE, "source=?,event=0x%lx\n",
  616. (unsigned long)eattr->var);
  617. }
  618. static int pmu_is_valid_counter(struct cci_pmu *cci_pmu, int idx)
  619. {
  620. return 0 <= idx && idx <= CCI_PMU_CNTR_LAST(cci_pmu);
  621. }
  622. static u32 pmu_read_register(struct cci_pmu *cci_pmu, int idx, unsigned int offset)
  623. {
  624. return readl_relaxed(cci_pmu->base +
  625. CCI_PMU_CNTR_BASE(cci_pmu->model, idx) + offset);
  626. }
  627. static void pmu_write_register(struct cci_pmu *cci_pmu, u32 value,
  628. int idx, unsigned int offset)
  629. {
  630. writel_relaxed(value, cci_pmu->base +
  631. CCI_PMU_CNTR_BASE(cci_pmu->model, idx) + offset);
  632. }
  633. static void pmu_disable_counter(struct cci_pmu *cci_pmu, int idx)
  634. {
  635. pmu_write_register(cci_pmu, 0, idx, CCI_PMU_CNTR_CTRL);
  636. }
  637. static void pmu_enable_counter(struct cci_pmu *cci_pmu, int idx)
  638. {
  639. pmu_write_register(cci_pmu, 1, idx, CCI_PMU_CNTR_CTRL);
  640. }
  641. static bool __maybe_unused
  642. pmu_counter_is_enabled(struct cci_pmu *cci_pmu, int idx)
  643. {
  644. return (pmu_read_register(cci_pmu, idx, CCI_PMU_CNTR_CTRL) & 0x1) != 0;
  645. }
  646. static void pmu_set_event(struct cci_pmu *cci_pmu, int idx, unsigned long event)
  647. {
  648. pmu_write_register(cci_pmu, event, idx, CCI_PMU_EVT_SEL);
  649. }
  650. /*
  651. * For all counters on the CCI-PMU, disable any 'enabled' counters,
  652. * saving the changed counters in the mask, so that we can restore
  653. * it later using pmu_restore_counters. The mask is private to the
  654. * caller. We cannot rely on the used_mask maintained by the CCI_PMU
  655. * as it only tells us if the counter is assigned to perf_event or not.
  656. * The state of the perf_event cannot be locked by the PMU layer, hence
  657. * we check the individual counter status (which can be locked by
  658. * cci_pm->hw_events->pmu_lock).
  659. *
  660. * @mask should be initialised to empty by the caller.
  661. */
  662. static void __maybe_unused
  663. pmu_save_counters(struct cci_pmu *cci_pmu, unsigned long *mask)
  664. {
  665. int i;
  666. for (i = 0; i < cci_pmu->num_cntrs; i++) {
  667. if (pmu_counter_is_enabled(cci_pmu, i)) {
  668. set_bit(i, mask);
  669. pmu_disable_counter(cci_pmu, i);
  670. }
  671. }
  672. }
  673. /*
  674. * Restore the status of the counters. Reversal of the pmu_save_counters().
  675. * For each counter set in the mask, enable the counter back.
  676. */
  677. static void __maybe_unused
  678. pmu_restore_counters(struct cci_pmu *cci_pmu, unsigned long *mask)
  679. {
  680. int i;
  681. for_each_set_bit(i, mask, cci_pmu->num_cntrs)
  682. pmu_enable_counter(cci_pmu, i);
  683. }
  684. /*
  685. * Returns the number of programmable counters actually implemented
  686. * by the cci
  687. */
  688. static u32 pmu_get_max_counters(struct cci_pmu *cci_pmu)
  689. {
  690. return (readl_relaxed(cci_pmu->ctrl_base + CCI_PMCR) &
  691. CCI_PMCR_NCNT_MASK) >> CCI_PMCR_NCNT_SHIFT;
  692. }
  693. static int pmu_get_event_idx(struct cci_pmu_hw_events *hw, struct perf_event *event)
  694. {
  695. struct cci_pmu *cci_pmu = to_cci_pmu(event->pmu);
  696. unsigned long cci_event = event->hw.config_base;
  697. int idx;
  698. if (cci_pmu->model->get_event_idx)
  699. return cci_pmu->model->get_event_idx(cci_pmu, hw, cci_event);
  700. /* Generic code to find an unused idx from the mask */
  701. for(idx = 0; idx <= CCI_PMU_CNTR_LAST(cci_pmu); idx++)
  702. if (!test_and_set_bit(idx, hw->used_mask))
  703. return idx;
  704. /* No counters available */
  705. return -EAGAIN;
  706. }
  707. static int pmu_map_event(struct perf_event *event)
  708. {
  709. struct cci_pmu *cci_pmu = to_cci_pmu(event->pmu);
  710. if (event->attr.type < PERF_TYPE_MAX ||
  711. !cci_pmu->model->validate_hw_event)
  712. return -ENOENT;
  713. return cci_pmu->model->validate_hw_event(cci_pmu, event->attr.config);
  714. }
  715. static int pmu_request_irq(struct cci_pmu *cci_pmu, irq_handler_t handler)
  716. {
  717. int i;
  718. struct platform_device *pmu_device = cci_pmu->plat_device;
  719. if (unlikely(!pmu_device))
  720. return -ENODEV;
  721. if (cci_pmu->nr_irqs < 1) {
  722. dev_err(&pmu_device->dev, "no irqs for CCI PMUs defined\n");
  723. return -ENODEV;
  724. }
  725. /*
  726. * Register all available CCI PMU interrupts. In the interrupt handler
  727. * we iterate over the counters checking for interrupt source (the
  728. * overflowing counter) and clear it.
  729. *
  730. * This should allow handling of non-unique interrupt for the counters.
  731. */
  732. for (i = 0; i < cci_pmu->nr_irqs; i++) {
  733. int err = request_irq(cci_pmu->irqs[i], handler, IRQF_SHARED,
  734. "arm-cci-pmu", cci_pmu);
  735. if (err) {
  736. dev_err(&pmu_device->dev, "unable to request IRQ%d for ARM CCI PMU counters\n",
  737. cci_pmu->irqs[i]);
  738. return err;
  739. }
  740. set_bit(i, &cci_pmu->active_irqs);
  741. }
  742. return 0;
  743. }
  744. static void pmu_free_irq(struct cci_pmu *cci_pmu)
  745. {
  746. int i;
  747. for (i = 0; i < cci_pmu->nr_irqs; i++) {
  748. if (!test_and_clear_bit(i, &cci_pmu->active_irqs))
  749. continue;
  750. free_irq(cci_pmu->irqs[i], cci_pmu);
  751. }
  752. }
  753. static u32 pmu_read_counter(struct perf_event *event)
  754. {
  755. struct cci_pmu *cci_pmu = to_cci_pmu(event->pmu);
  756. struct hw_perf_event *hw_counter = &event->hw;
  757. int idx = hw_counter->idx;
  758. u32 value;
  759. if (unlikely(!pmu_is_valid_counter(cci_pmu, idx))) {
  760. dev_err(&cci_pmu->plat_device->dev, "Invalid CCI PMU counter %d\n", idx);
  761. return 0;
  762. }
  763. value = pmu_read_register(cci_pmu, idx, CCI_PMU_CNTR);
  764. return value;
  765. }
  766. static void pmu_write_counter(struct cci_pmu *cci_pmu, u32 value, int idx)
  767. {
  768. pmu_write_register(cci_pmu, value, idx, CCI_PMU_CNTR);
  769. }
  770. static void __pmu_write_counters(struct cci_pmu *cci_pmu, unsigned long *mask)
  771. {
  772. int i;
  773. struct cci_pmu_hw_events *cci_hw = &cci_pmu->hw_events;
  774. for_each_set_bit(i, mask, cci_pmu->num_cntrs) {
  775. struct perf_event *event = cci_hw->events[i];
  776. if (WARN_ON(!event))
  777. continue;
  778. pmu_write_counter(cci_pmu, local64_read(&event->hw.prev_count), i);
  779. }
  780. }
  781. static void pmu_write_counters(struct cci_pmu *cci_pmu, unsigned long *mask)
  782. {
  783. if (cci_pmu->model->write_counters)
  784. cci_pmu->model->write_counters(cci_pmu, mask);
  785. else
  786. __pmu_write_counters(cci_pmu, mask);
  787. }
  788. #ifdef CONFIG_ARM_CCI5xx_PMU
  789. /*
  790. * CCI-500/CCI-550 has advanced power saving policies, which could gate the
  791. * clocks to the PMU counters, which makes the writes to them ineffective.
  792. * The only way to write to those counters is when the global counters
  793. * are enabled and the particular counter is enabled.
  794. *
  795. * So we do the following :
  796. *
  797. * 1) Disable all the PMU counters, saving their current state
  798. * 2) Enable the global PMU profiling, now that all counters are
  799. * disabled.
  800. *
  801. * For each counter to be programmed, repeat steps 3-7:
  802. *
  803. * 3) Write an invalid event code to the event control register for the
  804. counter, so that the counters are not modified.
  805. * 4) Enable the counter control for the counter.
  806. * 5) Set the counter value
  807. * 6) Disable the counter
  808. * 7) Restore the event in the target counter
  809. *
  810. * 8) Disable the global PMU.
  811. * 9) Restore the status of the rest of the counters.
  812. *
  813. * We choose an event which for CCI-5xx is guaranteed not to count.
  814. * We use the highest possible event code (0x1f) for the master interface 0.
  815. */
  816. #define CCI5xx_INVALID_EVENT ((CCI5xx_PORT_M0 << CCI5xx_PMU_EVENT_SOURCE_SHIFT) | \
  817. (CCI5xx_PMU_EVENT_CODE_MASK << CCI5xx_PMU_EVENT_CODE_SHIFT))
  818. static void cci5xx_pmu_write_counters(struct cci_pmu *cci_pmu, unsigned long *mask)
  819. {
  820. int i;
  821. DECLARE_BITMAP(saved_mask, HW_CNTRS_MAX);
  822. bitmap_zero(saved_mask, cci_pmu->num_cntrs);
  823. pmu_save_counters(cci_pmu, saved_mask);
  824. /*
  825. * Now that all the counters are disabled, we can safely turn the PMU on,
  826. * without syncing the status of the counters
  827. */
  828. __cci_pmu_enable_nosync(cci_pmu);
  829. for_each_set_bit(i, mask, cci_pmu->num_cntrs) {
  830. struct perf_event *event = cci_pmu->hw_events.events[i];
  831. if (WARN_ON(!event))
  832. continue;
  833. pmu_set_event(cci_pmu, i, CCI5xx_INVALID_EVENT);
  834. pmu_enable_counter(cci_pmu, i);
  835. pmu_write_counter(cci_pmu, local64_read(&event->hw.prev_count), i);
  836. pmu_disable_counter(cci_pmu, i);
  837. pmu_set_event(cci_pmu, i, event->hw.config_base);
  838. }
  839. __cci_pmu_disable(cci_pmu);
  840. pmu_restore_counters(cci_pmu, saved_mask);
  841. }
  842. #endif /* CONFIG_ARM_CCI5xx_PMU */
  843. static u64 pmu_event_update(struct perf_event *event)
  844. {
  845. struct hw_perf_event *hwc = &event->hw;
  846. u64 delta, prev_raw_count, new_raw_count;
  847. do {
  848. prev_raw_count = local64_read(&hwc->prev_count);
  849. new_raw_count = pmu_read_counter(event);
  850. } while (local64_cmpxchg(&hwc->prev_count, prev_raw_count,
  851. new_raw_count) != prev_raw_count);
  852. delta = (new_raw_count - prev_raw_count) & CCI_PMU_CNTR_MASK;
  853. local64_add(delta, &event->count);
  854. return new_raw_count;
  855. }
  856. static void pmu_read(struct perf_event *event)
  857. {
  858. pmu_event_update(event);
  859. }
  860. static void pmu_event_set_period(struct perf_event *event)
  861. {
  862. struct hw_perf_event *hwc = &event->hw;
  863. /*
  864. * The CCI PMU counters have a period of 2^32. To account for the
  865. * possiblity of extreme interrupt latency we program for a period of
  866. * half that. Hopefully we can handle the interrupt before another 2^31
  867. * events occur and the counter overtakes its previous value.
  868. */
  869. u64 val = 1ULL << 31;
  870. local64_set(&hwc->prev_count, val);
  871. /*
  872. * CCI PMU uses PERF_HES_ARCH to keep track of the counters, whose
  873. * values needs to be sync-ed with the s/w state before the PMU is
  874. * enabled.
  875. * Mark this counter for sync.
  876. */
  877. hwc->state |= PERF_HES_ARCH;
  878. }
  879. static irqreturn_t pmu_handle_irq(int irq_num, void *dev)
  880. {
  881. unsigned long flags;
  882. struct cci_pmu *cci_pmu = dev;
  883. struct cci_pmu_hw_events *events = &cci_pmu->hw_events;
  884. int idx, handled = IRQ_NONE;
  885. raw_spin_lock_irqsave(&events->pmu_lock, flags);
  886. /* Disable the PMU while we walk through the counters */
  887. __cci_pmu_disable(cci_pmu);
  888. /*
  889. * Iterate over counters and update the corresponding perf events.
  890. * This should work regardless of whether we have per-counter overflow
  891. * interrupt or a combined overflow interrupt.
  892. */
  893. for (idx = 0; idx <= CCI_PMU_CNTR_LAST(cci_pmu); idx++) {
  894. struct perf_event *event = events->events[idx];
  895. if (!event)
  896. continue;
  897. /* Did this counter overflow? */
  898. if (!(pmu_read_register(cci_pmu, idx, CCI_PMU_OVRFLW) &
  899. CCI_PMU_OVRFLW_FLAG))
  900. continue;
  901. pmu_write_register(cci_pmu, CCI_PMU_OVRFLW_FLAG, idx,
  902. CCI_PMU_OVRFLW);
  903. pmu_event_update(event);
  904. pmu_event_set_period(event);
  905. handled = IRQ_HANDLED;
  906. }
  907. /* Enable the PMU and sync possibly overflowed counters */
  908. __cci_pmu_enable_sync(cci_pmu);
  909. raw_spin_unlock_irqrestore(&events->pmu_lock, flags);
  910. return IRQ_RETVAL(handled);
  911. }
  912. static int cci_pmu_get_hw(struct cci_pmu *cci_pmu)
  913. {
  914. int ret = pmu_request_irq(cci_pmu, pmu_handle_irq);
  915. if (ret) {
  916. pmu_free_irq(cci_pmu);
  917. return ret;
  918. }
  919. return 0;
  920. }
  921. static void cci_pmu_put_hw(struct cci_pmu *cci_pmu)
  922. {
  923. pmu_free_irq(cci_pmu);
  924. }
  925. static void hw_perf_event_destroy(struct perf_event *event)
  926. {
  927. struct cci_pmu *cci_pmu = to_cci_pmu(event->pmu);
  928. atomic_t *active_events = &cci_pmu->active_events;
  929. struct mutex *reserve_mutex = &cci_pmu->reserve_mutex;
  930. if (atomic_dec_and_mutex_lock(active_events, reserve_mutex)) {
  931. cci_pmu_put_hw(cci_pmu);
  932. mutex_unlock(reserve_mutex);
  933. }
  934. }
  935. static void cci_pmu_enable(struct pmu *pmu)
  936. {
  937. struct cci_pmu *cci_pmu = to_cci_pmu(pmu);
  938. struct cci_pmu_hw_events *hw_events = &cci_pmu->hw_events;
  939. int enabled = bitmap_weight(hw_events->used_mask, cci_pmu->num_cntrs);
  940. unsigned long flags;
  941. if (!enabled)
  942. return;
  943. raw_spin_lock_irqsave(&hw_events->pmu_lock, flags);
  944. __cci_pmu_enable_sync(cci_pmu);
  945. raw_spin_unlock_irqrestore(&hw_events->pmu_lock, flags);
  946. }
  947. static void cci_pmu_disable(struct pmu *pmu)
  948. {
  949. struct cci_pmu *cci_pmu = to_cci_pmu(pmu);
  950. struct cci_pmu_hw_events *hw_events = &cci_pmu->hw_events;
  951. unsigned long flags;
  952. raw_spin_lock_irqsave(&hw_events->pmu_lock, flags);
  953. __cci_pmu_disable(cci_pmu);
  954. raw_spin_unlock_irqrestore(&hw_events->pmu_lock, flags);
  955. }
  956. /*
  957. * Check if the idx represents a non-programmable counter.
  958. * All the fixed event counters are mapped before the programmable
  959. * counters.
  960. */
  961. static bool pmu_fixed_hw_idx(struct cci_pmu *cci_pmu, int idx)
  962. {
  963. return (idx >= 0) && (idx < cci_pmu->model->fixed_hw_cntrs);
  964. }
  965. static void cci_pmu_start(struct perf_event *event, int pmu_flags)
  966. {
  967. struct cci_pmu *cci_pmu = to_cci_pmu(event->pmu);
  968. struct cci_pmu_hw_events *hw_events = &cci_pmu->hw_events;
  969. struct hw_perf_event *hwc = &event->hw;
  970. int idx = hwc->idx;
  971. unsigned long flags;
  972. /*
  973. * To handle interrupt latency, we always reprogram the period
  974. * regardlesss of PERF_EF_RELOAD.
  975. */
  976. if (pmu_flags & PERF_EF_RELOAD)
  977. WARN_ON_ONCE(!(hwc->state & PERF_HES_UPTODATE));
  978. hwc->state = 0;
  979. if (unlikely(!pmu_is_valid_counter(cci_pmu, idx))) {
  980. dev_err(&cci_pmu->plat_device->dev, "Invalid CCI PMU counter %d\n", idx);
  981. return;
  982. }
  983. raw_spin_lock_irqsave(&hw_events->pmu_lock, flags);
  984. /* Configure the counter unless you are counting a fixed event */
  985. if (!pmu_fixed_hw_idx(cci_pmu, idx))
  986. pmu_set_event(cci_pmu, idx, hwc->config_base);
  987. pmu_event_set_period(event);
  988. pmu_enable_counter(cci_pmu, idx);
  989. raw_spin_unlock_irqrestore(&hw_events->pmu_lock, flags);
  990. }
  991. static void cci_pmu_stop(struct perf_event *event, int pmu_flags)
  992. {
  993. struct cci_pmu *cci_pmu = to_cci_pmu(event->pmu);
  994. struct hw_perf_event *hwc = &event->hw;
  995. int idx = hwc->idx;
  996. if (hwc->state & PERF_HES_STOPPED)
  997. return;
  998. if (unlikely(!pmu_is_valid_counter(cci_pmu, idx))) {
  999. dev_err(&cci_pmu->plat_device->dev, "Invalid CCI PMU counter %d\n", idx);
  1000. return;
  1001. }
  1002. /*
  1003. * We always reprogram the counter, so ignore PERF_EF_UPDATE. See
  1004. * cci_pmu_start()
  1005. */
  1006. pmu_disable_counter(cci_pmu, idx);
  1007. pmu_event_update(event);
  1008. hwc->state |= PERF_HES_STOPPED | PERF_HES_UPTODATE;
  1009. }
  1010. static int cci_pmu_add(struct perf_event *event, int flags)
  1011. {
  1012. struct cci_pmu *cci_pmu = to_cci_pmu(event->pmu);
  1013. struct cci_pmu_hw_events *hw_events = &cci_pmu->hw_events;
  1014. struct hw_perf_event *hwc = &event->hw;
  1015. int idx;
  1016. /* If we don't have a space for the counter then finish early. */
  1017. idx = pmu_get_event_idx(hw_events, event);
  1018. if (idx < 0)
  1019. return idx;
  1020. event->hw.idx = idx;
  1021. hw_events->events[idx] = event;
  1022. hwc->state = PERF_HES_STOPPED | PERF_HES_UPTODATE;
  1023. if (flags & PERF_EF_START)
  1024. cci_pmu_start(event, PERF_EF_RELOAD);
  1025. /* Propagate our changes to the userspace mapping. */
  1026. perf_event_update_userpage(event);
  1027. return 0;
  1028. }
  1029. static void cci_pmu_del(struct perf_event *event, int flags)
  1030. {
  1031. struct cci_pmu *cci_pmu = to_cci_pmu(event->pmu);
  1032. struct cci_pmu_hw_events *hw_events = &cci_pmu->hw_events;
  1033. struct hw_perf_event *hwc = &event->hw;
  1034. int idx = hwc->idx;
  1035. cci_pmu_stop(event, PERF_EF_UPDATE);
  1036. hw_events->events[idx] = NULL;
  1037. clear_bit(idx, hw_events->used_mask);
  1038. perf_event_update_userpage(event);
  1039. }
  1040. static int validate_event(struct pmu *cci_pmu,
  1041. struct cci_pmu_hw_events *hw_events,
  1042. struct perf_event *event)
  1043. {
  1044. if (is_software_event(event))
  1045. return 1;
  1046. /*
  1047. * Reject groups spanning multiple HW PMUs (e.g. CPU + CCI). The
  1048. * core perf code won't check that the pmu->ctx == leader->ctx
  1049. * until after pmu->event_init(event).
  1050. */
  1051. if (event->pmu != cci_pmu)
  1052. return 0;
  1053. if (event->state < PERF_EVENT_STATE_OFF)
  1054. return 1;
  1055. if (event->state == PERF_EVENT_STATE_OFF && !event->attr.enable_on_exec)
  1056. return 1;
  1057. return pmu_get_event_idx(hw_events, event) >= 0;
  1058. }
  1059. static int validate_group(struct perf_event *event)
  1060. {
  1061. struct perf_event *sibling, *leader = event->group_leader;
  1062. struct cci_pmu *cci_pmu = to_cci_pmu(event->pmu);
  1063. unsigned long mask[BITS_TO_LONGS(HW_CNTRS_MAX)];
  1064. struct cci_pmu_hw_events fake_pmu = {
  1065. /*
  1066. * Initialise the fake PMU. We only need to populate the
  1067. * used_mask for the purposes of validation.
  1068. */
  1069. .used_mask = mask,
  1070. };
  1071. memset(mask, 0, BITS_TO_LONGS(cci_pmu->num_cntrs) * sizeof(unsigned long));
  1072. if (!validate_event(event->pmu, &fake_pmu, leader))
  1073. return -EINVAL;
  1074. for_each_sibling_event(sibling, leader) {
  1075. if (!validate_event(event->pmu, &fake_pmu, sibling))
  1076. return -EINVAL;
  1077. }
  1078. if (!validate_event(event->pmu, &fake_pmu, event))
  1079. return -EINVAL;
  1080. return 0;
  1081. }
  1082. static int __hw_perf_event_init(struct perf_event *event)
  1083. {
  1084. struct hw_perf_event *hwc = &event->hw;
  1085. int mapping;
  1086. mapping = pmu_map_event(event);
  1087. if (mapping < 0) {
  1088. pr_debug("event %x:%llx not supported\n", event->attr.type,
  1089. event->attr.config);
  1090. return mapping;
  1091. }
  1092. /*
  1093. * We don't assign an index until we actually place the event onto
  1094. * hardware. Use -1 to signify that we haven't decided where to put it
  1095. * yet.
  1096. */
  1097. hwc->idx = -1;
  1098. hwc->config_base = 0;
  1099. hwc->config = 0;
  1100. hwc->event_base = 0;
  1101. /*
  1102. * Store the event encoding into the config_base field.
  1103. */
  1104. hwc->config_base |= (unsigned long)mapping;
  1105. if (event->group_leader != event) {
  1106. if (validate_group(event) != 0)
  1107. return -EINVAL;
  1108. }
  1109. return 0;
  1110. }
  1111. static int cci_pmu_event_init(struct perf_event *event)
  1112. {
  1113. struct cci_pmu *cci_pmu = to_cci_pmu(event->pmu);
  1114. atomic_t *active_events = &cci_pmu->active_events;
  1115. int err = 0;
  1116. if (event->attr.type != event->pmu->type)
  1117. return -ENOENT;
  1118. /* Shared by all CPUs, no meaningful state to sample */
  1119. if (is_sampling_event(event) || event->attach_state & PERF_ATTACH_TASK)
  1120. return -EOPNOTSUPP;
  1121. /*
  1122. * Following the example set by other "uncore" PMUs, we accept any CPU
  1123. * and rewrite its affinity dynamically rather than having perf core
  1124. * handle cpu == -1 and pid == -1 for this case.
  1125. *
  1126. * The perf core will pin online CPUs for the duration of this call and
  1127. * the event being installed into its context, so the PMU's CPU can't
  1128. * change under our feet.
  1129. */
  1130. if (event->cpu < 0)
  1131. return -EINVAL;
  1132. event->cpu = cci_pmu->cpu;
  1133. event->destroy = hw_perf_event_destroy;
  1134. if (!atomic_inc_not_zero(active_events)) {
  1135. mutex_lock(&cci_pmu->reserve_mutex);
  1136. if (atomic_read(active_events) == 0)
  1137. err = cci_pmu_get_hw(cci_pmu);
  1138. if (!err)
  1139. atomic_inc(active_events);
  1140. mutex_unlock(&cci_pmu->reserve_mutex);
  1141. }
  1142. if (err)
  1143. return err;
  1144. err = __hw_perf_event_init(event);
  1145. if (err)
  1146. hw_perf_event_destroy(event);
  1147. return err;
  1148. }
  1149. static ssize_t pmu_cpumask_attr_show(struct device *dev,
  1150. struct device_attribute *attr, char *buf)
  1151. {
  1152. struct pmu *pmu = dev_get_drvdata(dev);
  1153. struct cci_pmu *cci_pmu = to_cci_pmu(pmu);
  1154. return cpumap_print_to_pagebuf(true, buf, cpumask_of(cci_pmu->cpu));
  1155. }
  1156. static struct device_attribute pmu_cpumask_attr =
  1157. __ATTR(cpumask, S_IRUGO, pmu_cpumask_attr_show, NULL);
  1158. static struct attribute *pmu_attrs[] = {
  1159. &pmu_cpumask_attr.attr,
  1160. NULL,
  1161. };
  1162. static struct attribute_group pmu_attr_group = {
  1163. .attrs = pmu_attrs,
  1164. };
  1165. static struct attribute_group pmu_format_attr_group = {
  1166. .name = "format",
  1167. .attrs = NULL, /* Filled in cci_pmu_init_attrs */
  1168. };
  1169. static struct attribute_group pmu_event_attr_group = {
  1170. .name = "events",
  1171. .attrs = NULL, /* Filled in cci_pmu_init_attrs */
  1172. };
  1173. static const struct attribute_group *pmu_attr_groups[] = {
  1174. &pmu_attr_group,
  1175. &pmu_format_attr_group,
  1176. &pmu_event_attr_group,
  1177. NULL
  1178. };
  1179. static int cci_pmu_init(struct cci_pmu *cci_pmu, struct platform_device *pdev)
  1180. {
  1181. const struct cci_pmu_model *model = cci_pmu->model;
  1182. char *name = model->name;
  1183. u32 num_cntrs;
  1184. if (WARN_ON(model->num_hw_cntrs > NUM_HW_CNTRS_MAX))
  1185. return -EINVAL;
  1186. if (WARN_ON(model->fixed_hw_cntrs > FIXED_HW_CNTRS_MAX))
  1187. return -EINVAL;
  1188. pmu_event_attr_group.attrs = model->event_attrs;
  1189. pmu_format_attr_group.attrs = model->format_attrs;
  1190. cci_pmu->pmu = (struct pmu) {
  1191. .module = THIS_MODULE,
  1192. .name = cci_pmu->model->name,
  1193. .task_ctx_nr = perf_invalid_context,
  1194. .pmu_enable = cci_pmu_enable,
  1195. .pmu_disable = cci_pmu_disable,
  1196. .event_init = cci_pmu_event_init,
  1197. .add = cci_pmu_add,
  1198. .del = cci_pmu_del,
  1199. .start = cci_pmu_start,
  1200. .stop = cci_pmu_stop,
  1201. .read = pmu_read,
  1202. .attr_groups = pmu_attr_groups,
  1203. .capabilities = PERF_PMU_CAP_NO_EXCLUDE,
  1204. };
  1205. cci_pmu->plat_device = pdev;
  1206. num_cntrs = pmu_get_max_counters(cci_pmu);
  1207. if (num_cntrs > cci_pmu->model->num_hw_cntrs) {
  1208. dev_warn(&pdev->dev,
  1209. "PMU implements more counters(%d) than supported by"
  1210. " the model(%d), truncated.",
  1211. num_cntrs, cci_pmu->model->num_hw_cntrs);
  1212. num_cntrs = cci_pmu->model->num_hw_cntrs;
  1213. }
  1214. cci_pmu->num_cntrs = num_cntrs + cci_pmu->model->fixed_hw_cntrs;
  1215. return perf_pmu_register(&cci_pmu->pmu, name, -1);
  1216. }
  1217. static int cci_pmu_offline_cpu(unsigned int cpu)
  1218. {
  1219. int target;
  1220. if (!g_cci_pmu || cpu != g_cci_pmu->cpu)
  1221. return 0;
  1222. target = cpumask_any_but(cpu_online_mask, cpu);
  1223. if (target >= nr_cpu_ids)
  1224. return 0;
  1225. perf_pmu_migrate_context(&g_cci_pmu->pmu, cpu, target);
  1226. g_cci_pmu->cpu = target;
  1227. return 0;
  1228. }
  1229. static __maybe_unused struct cci_pmu_model cci_pmu_models[] = {
  1230. #ifdef CONFIG_ARM_CCI400_PMU
  1231. [CCI400_R0] = {
  1232. .name = "CCI_400",
  1233. .fixed_hw_cntrs = FIXED_HW_CNTRS_CII_4XX, /* Cycle counter */
  1234. .num_hw_cntrs = NUM_HW_CNTRS_CII_4XX,
  1235. .cntr_size = SZ_4K,
  1236. .format_attrs = cci400_pmu_format_attrs,
  1237. .event_attrs = cci400_r0_pmu_event_attrs,
  1238. .event_ranges = {
  1239. [CCI_IF_SLAVE] = {
  1240. CCI400_R0_SLAVE_PORT_MIN_EV,
  1241. CCI400_R0_SLAVE_PORT_MAX_EV,
  1242. },
  1243. [CCI_IF_MASTER] = {
  1244. CCI400_R0_MASTER_PORT_MIN_EV,
  1245. CCI400_R0_MASTER_PORT_MAX_EV,
  1246. },
  1247. },
  1248. .validate_hw_event = cci400_validate_hw_event,
  1249. .get_event_idx = cci400_get_event_idx,
  1250. },
  1251. [CCI400_R1] = {
  1252. .name = "CCI_400_r1",
  1253. .fixed_hw_cntrs = FIXED_HW_CNTRS_CII_4XX, /* Cycle counter */
  1254. .num_hw_cntrs = NUM_HW_CNTRS_CII_4XX,
  1255. .cntr_size = SZ_4K,
  1256. .format_attrs = cci400_pmu_format_attrs,
  1257. .event_attrs = cci400_r1_pmu_event_attrs,
  1258. .event_ranges = {
  1259. [CCI_IF_SLAVE] = {
  1260. CCI400_R1_SLAVE_PORT_MIN_EV,
  1261. CCI400_R1_SLAVE_PORT_MAX_EV,
  1262. },
  1263. [CCI_IF_MASTER] = {
  1264. CCI400_R1_MASTER_PORT_MIN_EV,
  1265. CCI400_R1_MASTER_PORT_MAX_EV,
  1266. },
  1267. },
  1268. .validate_hw_event = cci400_validate_hw_event,
  1269. .get_event_idx = cci400_get_event_idx,
  1270. },
  1271. #endif
  1272. #ifdef CONFIG_ARM_CCI5xx_PMU
  1273. [CCI500_R0] = {
  1274. .name = "CCI_500",
  1275. .fixed_hw_cntrs = FIXED_HW_CNTRS_CII_5XX,
  1276. .num_hw_cntrs = NUM_HW_CNTRS_CII_5XX,
  1277. .cntr_size = SZ_64K,
  1278. .format_attrs = cci5xx_pmu_format_attrs,
  1279. .event_attrs = cci5xx_pmu_event_attrs,
  1280. .event_ranges = {
  1281. [CCI_IF_SLAVE] = {
  1282. CCI5xx_SLAVE_PORT_MIN_EV,
  1283. CCI5xx_SLAVE_PORT_MAX_EV,
  1284. },
  1285. [CCI_IF_MASTER] = {
  1286. CCI5xx_MASTER_PORT_MIN_EV,
  1287. CCI5xx_MASTER_PORT_MAX_EV,
  1288. },
  1289. [CCI_IF_GLOBAL] = {
  1290. CCI5xx_GLOBAL_PORT_MIN_EV,
  1291. CCI5xx_GLOBAL_PORT_MAX_EV,
  1292. },
  1293. },
  1294. .validate_hw_event = cci500_validate_hw_event,
  1295. .write_counters = cci5xx_pmu_write_counters,
  1296. },
  1297. [CCI550_R0] = {
  1298. .name = "CCI_550",
  1299. .fixed_hw_cntrs = FIXED_HW_CNTRS_CII_5XX,
  1300. .num_hw_cntrs = NUM_HW_CNTRS_CII_5XX,
  1301. .cntr_size = SZ_64K,
  1302. .format_attrs = cci5xx_pmu_format_attrs,
  1303. .event_attrs = cci5xx_pmu_event_attrs,
  1304. .event_ranges = {
  1305. [CCI_IF_SLAVE] = {
  1306. CCI5xx_SLAVE_PORT_MIN_EV,
  1307. CCI5xx_SLAVE_PORT_MAX_EV,
  1308. },
  1309. [CCI_IF_MASTER] = {
  1310. CCI5xx_MASTER_PORT_MIN_EV,
  1311. CCI5xx_MASTER_PORT_MAX_EV,
  1312. },
  1313. [CCI_IF_GLOBAL] = {
  1314. CCI5xx_GLOBAL_PORT_MIN_EV,
  1315. CCI5xx_GLOBAL_PORT_MAX_EV,
  1316. },
  1317. },
  1318. .validate_hw_event = cci550_validate_hw_event,
  1319. .write_counters = cci5xx_pmu_write_counters,
  1320. },
  1321. #endif
  1322. };
  1323. static const struct of_device_id arm_cci_pmu_matches[] = {
  1324. #ifdef CONFIG_ARM_CCI400_PMU
  1325. {
  1326. .compatible = "arm,cci-400-pmu",
  1327. .data = NULL,
  1328. },
  1329. {
  1330. .compatible = "arm,cci-400-pmu,r0",
  1331. .data = &cci_pmu_models[CCI400_R0],
  1332. },
  1333. {
  1334. .compatible = "arm,cci-400-pmu,r1",
  1335. .data = &cci_pmu_models[CCI400_R1],
  1336. },
  1337. #endif
  1338. #ifdef CONFIG_ARM_CCI5xx_PMU
  1339. {
  1340. .compatible = "arm,cci-500-pmu,r0",
  1341. .data = &cci_pmu_models[CCI500_R0],
  1342. },
  1343. {
  1344. .compatible = "arm,cci-550-pmu,r0",
  1345. .data = &cci_pmu_models[CCI550_R0],
  1346. },
  1347. #endif
  1348. {},
  1349. };
  1350. MODULE_DEVICE_TABLE(of, arm_cci_pmu_matches);
  1351. static bool is_duplicate_irq(int irq, int *irqs, int nr_irqs)
  1352. {
  1353. int i;
  1354. for (i = 0; i < nr_irqs; i++)
  1355. if (irq == irqs[i])
  1356. return true;
  1357. return false;
  1358. }
  1359. static struct cci_pmu *cci_pmu_alloc(struct device *dev)
  1360. {
  1361. struct cci_pmu *cci_pmu;
  1362. const struct cci_pmu_model *model;
  1363. /*
  1364. * All allocations are devm_* hence we don't have to free
  1365. * them explicitly on an error, as it would end up in driver
  1366. * detach.
  1367. */
  1368. cci_pmu = devm_kzalloc(dev, sizeof(*cci_pmu), GFP_KERNEL);
  1369. if (!cci_pmu)
  1370. return ERR_PTR(-ENOMEM);
  1371. cci_pmu->ctrl_base = *(void __iomem **)dev->platform_data;
  1372. model = of_device_get_match_data(dev);
  1373. if (!model) {
  1374. dev_warn(dev,
  1375. "DEPRECATED compatible property, requires secure access to CCI registers");
  1376. model = probe_cci_model(cci_pmu);
  1377. }
  1378. if (!model) {
  1379. dev_warn(dev, "CCI PMU version not supported\n");
  1380. return ERR_PTR(-ENODEV);
  1381. }
  1382. cci_pmu->model = model;
  1383. cci_pmu->irqs = devm_kcalloc(dev, CCI_PMU_MAX_HW_CNTRS(model),
  1384. sizeof(*cci_pmu->irqs), GFP_KERNEL);
  1385. if (!cci_pmu->irqs)
  1386. return ERR_PTR(-ENOMEM);
  1387. cci_pmu->hw_events.events = devm_kcalloc(dev,
  1388. CCI_PMU_MAX_HW_CNTRS(model),
  1389. sizeof(*cci_pmu->hw_events.events),
  1390. GFP_KERNEL);
  1391. if (!cci_pmu->hw_events.events)
  1392. return ERR_PTR(-ENOMEM);
  1393. cci_pmu->hw_events.used_mask = devm_kcalloc(dev,
  1394. BITS_TO_LONGS(CCI_PMU_MAX_HW_CNTRS(model)),
  1395. sizeof(*cci_pmu->hw_events.used_mask),
  1396. GFP_KERNEL);
  1397. if (!cci_pmu->hw_events.used_mask)
  1398. return ERR_PTR(-ENOMEM);
  1399. return cci_pmu;
  1400. }
  1401. static int cci_pmu_probe(struct platform_device *pdev)
  1402. {
  1403. struct cci_pmu *cci_pmu;
  1404. int i, ret, irq;
  1405. cci_pmu = cci_pmu_alloc(&pdev->dev);
  1406. if (IS_ERR(cci_pmu))
  1407. return PTR_ERR(cci_pmu);
  1408. cci_pmu->base = devm_platform_ioremap_resource(pdev, 0);
  1409. if (IS_ERR(cci_pmu->base))
  1410. return -ENOMEM;
  1411. /*
  1412. * CCI PMU has one overflow interrupt per counter; but some may be tied
  1413. * together to a common interrupt.
  1414. */
  1415. cci_pmu->nr_irqs = 0;
  1416. for (i = 0; i < CCI_PMU_MAX_HW_CNTRS(cci_pmu->model); i++) {
  1417. irq = platform_get_irq(pdev, i);
  1418. if (irq < 0)
  1419. break;
  1420. if (is_duplicate_irq(irq, cci_pmu->irqs, cci_pmu->nr_irqs))
  1421. continue;
  1422. cci_pmu->irqs[cci_pmu->nr_irqs++] = irq;
  1423. }
  1424. /*
  1425. * Ensure that the device tree has as many interrupts as the number
  1426. * of counters.
  1427. */
  1428. if (i < CCI_PMU_MAX_HW_CNTRS(cci_pmu->model)) {
  1429. dev_warn(&pdev->dev, "In-correct number of interrupts: %d, should be %d\n",
  1430. i, CCI_PMU_MAX_HW_CNTRS(cci_pmu->model));
  1431. return -EINVAL;
  1432. }
  1433. raw_spin_lock_init(&cci_pmu->hw_events.pmu_lock);
  1434. mutex_init(&cci_pmu->reserve_mutex);
  1435. atomic_set(&cci_pmu->active_events, 0);
  1436. cci_pmu->cpu = raw_smp_processor_id();
  1437. g_cci_pmu = cci_pmu;
  1438. cpuhp_setup_state_nocalls(CPUHP_AP_PERF_ARM_CCI_ONLINE,
  1439. "perf/arm/cci:online", NULL,
  1440. cci_pmu_offline_cpu);
  1441. ret = cci_pmu_init(cci_pmu, pdev);
  1442. if (ret)
  1443. goto error_pmu_init;
  1444. pr_info("ARM %s PMU driver probed", cci_pmu->model->name);
  1445. return 0;
  1446. error_pmu_init:
  1447. cpuhp_remove_state(CPUHP_AP_PERF_ARM_CCI_ONLINE);
  1448. g_cci_pmu = NULL;
  1449. return ret;
  1450. }
  1451. static int cci_pmu_remove(struct platform_device *pdev)
  1452. {
  1453. if (!g_cci_pmu)
  1454. return 0;
  1455. cpuhp_remove_state(CPUHP_AP_PERF_ARM_CCI_ONLINE);
  1456. perf_pmu_unregister(&g_cci_pmu->pmu);
  1457. g_cci_pmu = NULL;
  1458. return 0;
  1459. }
  1460. static struct platform_driver cci_pmu_driver = {
  1461. .driver = {
  1462. .name = DRIVER_NAME,
  1463. .of_match_table = arm_cci_pmu_matches,
  1464. .suppress_bind_attrs = true,
  1465. },
  1466. .probe = cci_pmu_probe,
  1467. .remove = cci_pmu_remove,
  1468. };
  1469. module_platform_driver(cci_pmu_driver);
  1470. MODULE_LICENSE("GPL v2");
  1471. MODULE_DESCRIPTION("ARM CCI PMU support");