topic.h 5.9 KB

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  1. /*
  2. * topic.h 1.8 1999/08/28 04:01:47
  3. *
  4. * The contents of this file are subject to the Mozilla Public License
  5. * Version 1.1 (the "License"); you may not use this file except in
  6. * compliance with the License. You may obtain a copy of the License
  7. * at http://www.mozilla.org/MPL/
  8. *
  9. * Software distributed under the License is distributed on an "AS IS"
  10. * basis, WITHOUT WARRANTY OF ANY KIND, either express or implied. See
  11. * the License for the specific language governing rights and
  12. * limitations under the License.
  13. *
  14. * The initial developer of the original code is David A. Hinds
  15. * <dahinds@users.sourceforge.net>. Portions created by David A. Hinds
  16. * are Copyright (C) 1999 David A. Hinds. All Rights Reserved.
  17. *
  18. * Alternatively, the contents of this file may be used under the
  19. * terms of the GNU General Public License version 2 (the "GPL"), in which
  20. * case the provisions of the GPL are applicable instead of the
  21. * above. If you wish to allow the use of your version of this file
  22. * only under the terms of the GPL and not to allow others to use
  23. * your version of this file under the MPL, indicate your decision by
  24. * deleting the provisions above and replace them with the notice and
  25. * other provisions required by the GPL. If you do not delete the
  26. * provisions above, a recipient may use your version of this file
  27. * under either the MPL or the GPL.
  28. * topic.h $Release$ 1999/08/28 04:01:47
  29. */
  30. #ifndef _LINUX_TOPIC_H
  31. #define _LINUX_TOPIC_H
  32. /* Register definitions for Toshiba ToPIC95/97/100 controllers */
  33. #define TOPIC_SOCKET_CONTROL 0x0090 /* 32 bit */
  34. #define TOPIC_SCR_IRQSEL 0x00000001
  35. #define TOPIC_SLOT_CONTROL 0x00a0 /* 8 bit */
  36. #define TOPIC_SLOT_SLOTON 0x80
  37. #define TOPIC_SLOT_SLOTEN 0x40
  38. #define TOPIC_SLOT_ID_LOCK 0x20
  39. #define TOPIC_SLOT_ID_WP 0x10
  40. #define TOPIC_SLOT_PORT_MASK 0x0c
  41. #define TOPIC_SLOT_PORT_SHIFT 2
  42. #define TOPIC_SLOT_OFS_MASK 0x03
  43. #define TOPIC_CARD_CONTROL 0x00a1 /* 8 bit */
  44. #define TOPIC_CCR_INTB 0x20
  45. #define TOPIC_CCR_INTA 0x10
  46. #define TOPIC_CCR_CLOCK 0x0c
  47. #define TOPIC_CCR_PCICLK 0x0c
  48. #define TOPIC_CCR_PCICLK_2 0x08
  49. #define TOPIC_CCR_CCLK 0x04
  50. #define TOPIC97_INT_CONTROL 0x00a1 /* 8 bit */
  51. #define TOPIC97_ICR_INTB 0x20
  52. #define TOPIC97_ICR_INTA 0x10
  53. #define TOPIC97_ICR_STSIRQNP 0x04
  54. #define TOPIC97_ICR_IRQNP 0x02
  55. #define TOPIC97_ICR_IRQSEL 0x01
  56. #define TOPIC_CARD_DETECT 0x00a3 /* 8 bit */
  57. #define TOPIC_CDR_MODE_PC32 0x80
  58. #define TOPIC_CDR_VS1 0x04
  59. #define TOPIC_CDR_VS2 0x02
  60. #define TOPIC_CDR_SW_DETECT 0x01
  61. #define TOPIC_REGISTER_CONTROL 0x00a4 /* 32 bit */
  62. #define TOPIC_RCR_RESUME_RESET 0x80000000
  63. #define TOPIC_RCR_REMOVE_RESET 0x40000000
  64. #define TOPIC97_RCR_CLKRUN_ENA 0x20000000
  65. #define TOPIC97_RCR_TESTMODE 0x10000000
  66. #define TOPIC97_RCR_IOPLUP 0x08000000
  67. #define TOPIC_RCR_BUFOFF_PWROFF 0x02000000
  68. #define TOPIC_RCR_BUFOFF_SIGOFF 0x01000000
  69. #define TOPIC97_RCR_CB_DEV_MASK 0x0000f800
  70. #define TOPIC97_RCR_CB_DEV_SHIFT 11
  71. #define TOPIC97_RCR_RI_DISABLE 0x00000004
  72. #define TOPIC97_RCR_CAUDIO_OFF 0x00000002
  73. #define TOPIC_RCR_CAUDIO_INVERT 0x00000001
  74. #define TOPIC97_MISC1 0x00ad /* 8bit */
  75. #define TOPIC97_MISC1_CLOCKRUN_ENABLE 0x80
  76. #define TOPIC97_MISC1_CLOCKRUN_MODE 0x40
  77. #define TOPIC97_MISC1_DETECT_REQ_ENA 0x10
  78. #define TOPIC97_MISC1_SCK_CLEAR_DIS 0x04
  79. #define TOPIC97_MISC1_R2_LOW_ENABLE 0x10
  80. #define TOPIC97_MISC2 0x00ae /* 8 bit */
  81. #define TOPIC97_MISC2_SPWRCLK_MASK 0x70
  82. #define TOPIC97_MISC2_SPWRMOD 0x08
  83. #define TOPIC97_MISC2_SPWR_ENABLE 0x04
  84. #define TOPIC97_MISC2_ZV_MODE 0x02
  85. #define TOPIC97_MISC2_ZV_ENABLE 0x01
  86. #define TOPIC97_ZOOM_VIDEO_CONTROL 0x009c /* 8 bit */
  87. #define TOPIC97_ZV_CONTROL_ENABLE 0x01
  88. #define TOPIC97_AUDIO_VIDEO_SWITCH 0x003c /* 8 bit */
  89. #define TOPIC97_AVS_AUDIO_CONTROL 0x02
  90. #define TOPIC97_AVS_VIDEO_CONTROL 0x01
  91. #define TOPIC_EXCA_IF_CONTROL 0x3e /* 8 bit */
  92. #define TOPIC_EXCA_IFC_33V_ENA 0x01
  93. #define TOPIC_PCI_CFG_PPBCN 0x3e /* 16-bit */
  94. #define TOPIC_PCI_CFG_PPBCN_WBEN 0x0400
  95. static void topic97_zoom_video(struct pcmcia_socket *sock, int onoff)
  96. {
  97. struct yenta_socket *socket = container_of(sock, struct yenta_socket, socket);
  98. u8 reg_zv, reg;
  99. reg_zv = config_readb(socket, TOPIC97_ZOOM_VIDEO_CONTROL);
  100. if (onoff) {
  101. reg_zv |= TOPIC97_ZV_CONTROL_ENABLE;
  102. config_writeb(socket, TOPIC97_ZOOM_VIDEO_CONTROL, reg_zv);
  103. reg = config_readb(socket, TOPIC97_AUDIO_VIDEO_SWITCH);
  104. reg |= TOPIC97_AVS_AUDIO_CONTROL | TOPIC97_AVS_VIDEO_CONTROL;
  105. config_writeb(socket, TOPIC97_AUDIO_VIDEO_SWITCH, reg);
  106. } else {
  107. reg_zv &= ~TOPIC97_ZV_CONTROL_ENABLE;
  108. config_writeb(socket, TOPIC97_ZOOM_VIDEO_CONTROL, reg_zv);
  109. reg = config_readb(socket, TOPIC97_AUDIO_VIDEO_SWITCH);
  110. reg &= ~(TOPIC97_AVS_AUDIO_CONTROL | TOPIC97_AVS_VIDEO_CONTROL);
  111. config_writeb(socket, TOPIC97_AUDIO_VIDEO_SWITCH, reg);
  112. }
  113. }
  114. static int topic97_override(struct yenta_socket *socket)
  115. {
  116. /* ToPIC97/100 support ZV */
  117. socket->socket.zoom_video = topic97_zoom_video;
  118. return 0;
  119. }
  120. static int topic95_override(struct yenta_socket *socket)
  121. {
  122. u8 fctrl;
  123. u16 ppbcn;
  124. /* enable 3.3V support for 16bit cards */
  125. fctrl = exca_readb(socket, TOPIC_EXCA_IF_CONTROL);
  126. exca_writeb(socket, TOPIC_EXCA_IF_CONTROL, fctrl | TOPIC_EXCA_IFC_33V_ENA);
  127. /* tell yenta to use exca registers to power 16bit cards */
  128. socket->flags |= YENTA_16BIT_POWER_EXCA | YENTA_16BIT_POWER_DF;
  129. /* Disable write buffers to prevent lockups under load with numerous
  130. Cardbus cards, observed on Tecra 500CDT and reported elsewhere on the
  131. net. This is not a power-on default according to the datasheet
  132. but some BIOSes seem to set it. */
  133. if (pci_read_config_word(socket->dev, TOPIC_PCI_CFG_PPBCN, &ppbcn) == 0
  134. && socket->dev->revision <= 7
  135. && (ppbcn & TOPIC_PCI_CFG_PPBCN_WBEN)) {
  136. ppbcn &= ~TOPIC_PCI_CFG_PPBCN_WBEN;
  137. pci_write_config_word(socket->dev, TOPIC_PCI_CFG_PPBCN, ppbcn);
  138. dev_info(&socket->dev->dev, "Disabled ToPIC95 Cardbus write buffers.\n");
  139. }
  140. return 0;
  141. }
  142. #endif /* _LINUX_TOPIC_H */