ti113x.h 28 KB

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  1. /*
  2. * ti113x.h 1.16 1999/10/25 20:03:34
  3. *
  4. * The contents of this file are subject to the Mozilla Public License
  5. * Version 1.1 (the "License"); you may not use this file except in
  6. * compliance with the License. You may obtain a copy of the License
  7. * at http://www.mozilla.org/MPL/
  8. *
  9. * Software distributed under the License is distributed on an "AS IS"
  10. * basis, WITHOUT WARRANTY OF ANY KIND, either express or implied. See
  11. * the License for the specific language governing rights and
  12. * limitations under the License.
  13. *
  14. * The initial developer of the original code is David A. Hinds
  15. * <dahinds@users.sourceforge.net>. Portions created by David A. Hinds
  16. * are Copyright (C) 1999 David A. Hinds. All Rights Reserved.
  17. *
  18. * Alternatively, the contents of this file may be used under the
  19. * terms of the GNU General Public License version 2 (the "GPL"), in which
  20. * case the provisions of the GPL are applicable instead of the
  21. * above. If you wish to allow the use of your version of this file
  22. * only under the terms of the GPL and not to allow others to use
  23. * your version of this file under the MPL, indicate your decision by
  24. * deleting the provisions above and replace them with the notice and
  25. * other provisions required by the GPL. If you do not delete the
  26. * provisions above, a recipient may use your version of this file
  27. * under either the MPL or the GPL.
  28. */
  29. #ifndef _LINUX_TI113X_H
  30. #define _LINUX_TI113X_H
  31. /* Register definitions for TI 113X PCI-to-CardBus bridges */
  32. /* System Control Register */
  33. #define TI113X_SYSTEM_CONTROL 0x0080 /* 32 bit */
  34. #define TI113X_SCR_SMIROUTE 0x04000000
  35. #define TI113X_SCR_SMISTATUS 0x02000000
  36. #define TI113X_SCR_SMIENB 0x01000000
  37. #define TI113X_SCR_VCCPROT 0x00200000
  38. #define TI113X_SCR_REDUCEZV 0x00100000
  39. #define TI113X_SCR_CDREQEN 0x00080000
  40. #define TI113X_SCR_CDMACHAN 0x00070000
  41. #define TI113X_SCR_SOCACTIVE 0x00002000
  42. #define TI113X_SCR_PWRSTREAM 0x00000800
  43. #define TI113X_SCR_DELAYUP 0x00000400
  44. #define TI113X_SCR_DELAYDOWN 0x00000200
  45. #define TI113X_SCR_INTERROGATE 0x00000100
  46. #define TI113X_SCR_CLKRUN_SEL 0x00000080
  47. #define TI113X_SCR_PWRSAVINGS 0x00000040
  48. #define TI113X_SCR_SUBSYSRW 0x00000020
  49. #define TI113X_SCR_CB_DPAR 0x00000010
  50. #define TI113X_SCR_CDMA_EN 0x00000008
  51. #define TI113X_SCR_ASYNC_IRQ 0x00000004
  52. #define TI113X_SCR_KEEPCLK 0x00000002
  53. #define TI113X_SCR_CLKRUN_ENA 0x00000001
  54. #define TI122X_SCR_SER_STEP 0xc0000000
  55. #define TI122X_SCR_INTRTIE 0x20000000
  56. #define TIXX21_SCR_TIEALL 0x10000000
  57. #define TI122X_SCR_CBRSVD 0x00400000
  58. #define TI122X_SCR_MRBURSTDN 0x00008000
  59. #define TI122X_SCR_MRBURSTUP 0x00004000
  60. #define TI122X_SCR_RIMUX 0x00000001
  61. /* Multimedia Control Register */
  62. #define TI1250_MULTIMEDIA_CTL 0x0084 /* 8 bit */
  63. #define TI1250_MMC_ZVOUTEN 0x80
  64. #define TI1250_MMC_PORTSEL 0x40
  65. #define TI1250_MMC_ZVEN1 0x02
  66. #define TI1250_MMC_ZVEN0 0x01
  67. #define TI1250_GENERAL_STATUS 0x0085 /* 8 bit */
  68. #define TI1250_GPIO0_CONTROL 0x0088 /* 8 bit */
  69. #define TI1250_GPIO1_CONTROL 0x0089 /* 8 bit */
  70. #define TI1250_GPIO2_CONTROL 0x008a /* 8 bit */
  71. #define TI1250_GPIO3_CONTROL 0x008b /* 8 bit */
  72. #define TI1250_GPIO_MODE_MASK 0xc0
  73. /* IRQMUX/MFUNC Register */
  74. #define TI122X_MFUNC 0x008c /* 32 bit */
  75. #define TI122X_MFUNC0_MASK 0x0000000f
  76. #define TI122X_MFUNC1_MASK 0x000000f0
  77. #define TI122X_MFUNC2_MASK 0x00000f00
  78. #define TI122X_MFUNC3_MASK 0x0000f000
  79. #define TI122X_MFUNC4_MASK 0x000f0000
  80. #define TI122X_MFUNC5_MASK 0x00f00000
  81. #define TI122X_MFUNC6_MASK 0x0f000000
  82. #define TI122X_MFUNC0_INTA 0x00000002
  83. #define TI125X_MFUNC0_INTB 0x00000001
  84. #define TI122X_MFUNC1_INTB 0x00000020
  85. #define TI122X_MFUNC3_IRQSER 0x00001000
  86. /* Retry Status Register */
  87. #define TI113X_RETRY_STATUS 0x0090 /* 8 bit */
  88. #define TI113X_RSR_PCIRETRY 0x80
  89. #define TI113X_RSR_CBRETRY 0x40
  90. #define TI113X_RSR_TEXP_CBB 0x20
  91. #define TI113X_RSR_MEXP_CBB 0x10
  92. #define TI113X_RSR_TEXP_CBA 0x08
  93. #define TI113X_RSR_MEXP_CBA 0x04
  94. #define TI113X_RSR_TEXP_PCI 0x02
  95. #define TI113X_RSR_MEXP_PCI 0x01
  96. /* Card Control Register */
  97. #define TI113X_CARD_CONTROL 0x0091 /* 8 bit */
  98. #define TI113X_CCR_RIENB 0x80
  99. #define TI113X_CCR_ZVENABLE 0x40
  100. #define TI113X_CCR_PCI_IRQ_ENA 0x20
  101. #define TI113X_CCR_PCI_IREQ 0x10
  102. #define TI113X_CCR_PCI_CSC 0x08
  103. #define TI113X_CCR_SPKROUTEN 0x02
  104. #define TI113X_CCR_IFG 0x01
  105. #define TI1220_CCR_PORT_SEL 0x20
  106. #define TI122X_CCR_AUD2MUX 0x04
  107. /* Device Control Register */
  108. #define TI113X_DEVICE_CONTROL 0x0092 /* 8 bit */
  109. #define TI113X_DCR_5V_FORCE 0x40
  110. #define TI113X_DCR_3V_FORCE 0x20
  111. #define TI113X_DCR_IMODE_MASK 0x06
  112. #define TI113X_DCR_IMODE_ISA 0x02
  113. #define TI113X_DCR_IMODE_SERIAL 0x04
  114. #define TI12XX_DCR_IMODE_PCI_ONLY 0x00
  115. #define TI12XX_DCR_IMODE_ALL_SERIAL 0x06
  116. /* Buffer Control Register */
  117. #define TI113X_BUFFER_CONTROL 0x0093 /* 8 bit */
  118. #define TI113X_BCR_CB_READ_DEPTH 0x08
  119. #define TI113X_BCR_CB_WRITE_DEPTH 0x04
  120. #define TI113X_BCR_PCI_READ_DEPTH 0x02
  121. #define TI113X_BCR_PCI_WRITE_DEPTH 0x01
  122. /* Diagnostic Register */
  123. #define TI1250_DIAGNOSTIC 0x0093 /* 8 bit */
  124. #define TI1250_DIAG_TRUE_VALUE 0x80
  125. #define TI1250_DIAG_PCI_IREQ 0x40
  126. #define TI1250_DIAG_PCI_CSC 0x20
  127. #define TI1250_DIAG_ASYNC_CSC 0x01
  128. /* DMA Registers */
  129. #define TI113X_DMA_0 0x0094 /* 32 bit */
  130. #define TI113X_DMA_1 0x0098 /* 32 bit */
  131. /* ExCA IO offset registers */
  132. #define TI113X_IO_OFFSET(map) (0x36+((map)<<1))
  133. /* EnE test register */
  134. #define ENE_TEST_C9 0xc9 /* 8bit */
  135. #define ENE_TEST_C9_TLTENABLE 0x02
  136. #define ENE_TEST_C9_PFENABLE_F0 0x04
  137. #define ENE_TEST_C9_PFENABLE_F1 0x08
  138. #define ENE_TEST_C9_PFENABLE (ENE_TEST_C9_PFENABLE_F0 | ENE_TEST_C9_PFENABLE_F1)
  139. #define ENE_TEST_C9_WPDISALBLE_F0 0x40
  140. #define ENE_TEST_C9_WPDISALBLE_F1 0x80
  141. #define ENE_TEST_C9_WPDISALBLE (ENE_TEST_C9_WPDISALBLE_F0 | ENE_TEST_C9_WPDISALBLE_F1)
  142. /*
  143. * Texas Instruments CardBus controller overrides.
  144. */
  145. #define ti_sysctl(socket) ((socket)->private[0])
  146. #define ti_cardctl(socket) ((socket)->private[1])
  147. #define ti_devctl(socket) ((socket)->private[2])
  148. #define ti_diag(socket) ((socket)->private[3])
  149. #define ti_mfunc(socket) ((socket)->private[4])
  150. #define ene_test_c9(socket) ((socket)->private[5])
  151. /*
  152. * These are the TI specific power management handlers.
  153. */
  154. static void ti_save_state(struct yenta_socket *socket)
  155. {
  156. ti_sysctl(socket) = config_readl(socket, TI113X_SYSTEM_CONTROL);
  157. ti_mfunc(socket) = config_readl(socket, TI122X_MFUNC);
  158. ti_cardctl(socket) = config_readb(socket, TI113X_CARD_CONTROL);
  159. ti_devctl(socket) = config_readb(socket, TI113X_DEVICE_CONTROL);
  160. ti_diag(socket) = config_readb(socket, TI1250_DIAGNOSTIC);
  161. if (socket->dev->vendor == PCI_VENDOR_ID_ENE)
  162. ene_test_c9(socket) = config_readb(socket, ENE_TEST_C9);
  163. }
  164. static void ti_restore_state(struct yenta_socket *socket)
  165. {
  166. config_writel(socket, TI113X_SYSTEM_CONTROL, ti_sysctl(socket));
  167. config_writel(socket, TI122X_MFUNC, ti_mfunc(socket));
  168. config_writeb(socket, TI113X_CARD_CONTROL, ti_cardctl(socket));
  169. config_writeb(socket, TI113X_DEVICE_CONTROL, ti_devctl(socket));
  170. config_writeb(socket, TI1250_DIAGNOSTIC, ti_diag(socket));
  171. if (socket->dev->vendor == PCI_VENDOR_ID_ENE)
  172. config_writeb(socket, ENE_TEST_C9, ene_test_c9(socket));
  173. }
  174. /*
  175. * Zoom video control for TI122x/113x chips
  176. */
  177. static void ti_zoom_video(struct pcmcia_socket *sock, int onoff)
  178. {
  179. u8 reg;
  180. struct yenta_socket *socket = container_of(sock, struct yenta_socket, socket);
  181. /* If we don't have a Zoom Video switch this is harmless,
  182. we just tristate the unused (ZV) lines */
  183. reg = config_readb(socket, TI113X_CARD_CONTROL);
  184. if (onoff)
  185. /* Zoom zoom, we will all go together, zoom zoom, zoom zoom */
  186. reg |= TI113X_CCR_ZVENABLE;
  187. else
  188. reg &= ~TI113X_CCR_ZVENABLE;
  189. config_writeb(socket, TI113X_CARD_CONTROL, reg);
  190. }
  191. /*
  192. * The 145x series can also use this. They have an additional
  193. * ZV autodetect mode we don't use but don't actually need.
  194. * FIXME: manual says its in func0 and func1 but disagrees with
  195. * itself about this - do we need to force func0, if so we need
  196. * to know a lot more about socket pairings in pcmcia_socket than
  197. * we do now.. uggh.
  198. */
  199. static void ti1250_zoom_video(struct pcmcia_socket *sock, int onoff)
  200. {
  201. struct yenta_socket *socket = container_of(sock, struct yenta_socket, socket);
  202. int shift = 0;
  203. u8 reg;
  204. ti_zoom_video(sock, onoff);
  205. reg = config_readb(socket, TI1250_MULTIMEDIA_CTL);
  206. reg |= TI1250_MMC_ZVOUTEN; /* ZV bus enable */
  207. if(PCI_FUNC(socket->dev->devfn)==1)
  208. shift = 1;
  209. if(onoff)
  210. {
  211. reg &= ~(1<<6); /* Clear select bit */
  212. reg |= shift<<6; /* Favour our socket */
  213. reg |= 1<<shift; /* Socket zoom video on */
  214. }
  215. else
  216. {
  217. reg &= ~(1<<6); /* Clear select bit */
  218. reg |= (1^shift)<<6; /* Favour other socket */
  219. reg &= ~(1<<shift); /* Socket zoon video off */
  220. }
  221. config_writeb(socket, TI1250_MULTIMEDIA_CTL, reg);
  222. }
  223. static void ti_set_zv(struct yenta_socket *socket)
  224. {
  225. if(socket->dev->vendor == PCI_VENDOR_ID_TI)
  226. {
  227. switch(socket->dev->device)
  228. {
  229. /* There may be more .. */
  230. case PCI_DEVICE_ID_TI_1220:
  231. case PCI_DEVICE_ID_TI_1221:
  232. case PCI_DEVICE_ID_TI_1225:
  233. case PCI_DEVICE_ID_TI_4510:
  234. socket->socket.zoom_video = ti_zoom_video;
  235. break;
  236. case PCI_DEVICE_ID_TI_1250:
  237. case PCI_DEVICE_ID_TI_1251A:
  238. case PCI_DEVICE_ID_TI_1251B:
  239. case PCI_DEVICE_ID_TI_1450:
  240. socket->socket.zoom_video = ti1250_zoom_video;
  241. }
  242. }
  243. }
  244. /*
  245. * Generic TI init - TI has an extension for the
  246. * INTCTL register that sets the PCI CSC interrupt.
  247. * Make sure we set it correctly at open and init
  248. * time
  249. * - override: disable the PCI CSC interrupt. This makes
  250. * it possible to use the CSC interrupt to probe the
  251. * ISA interrupts.
  252. * - init: set the interrupt to match our PCI state.
  253. * This makes us correctly get PCI CSC interrupt
  254. * events.
  255. */
  256. static int ti_init(struct yenta_socket *socket)
  257. {
  258. u8 new, reg = exca_readb(socket, I365_INTCTL);
  259. new = reg & ~I365_INTR_ENA;
  260. if (socket->dev->irq)
  261. new |= I365_INTR_ENA;
  262. if (new != reg)
  263. exca_writeb(socket, I365_INTCTL, new);
  264. return 0;
  265. }
  266. static int ti_override(struct yenta_socket *socket)
  267. {
  268. u8 new, reg = exca_readb(socket, I365_INTCTL);
  269. new = reg & ~I365_INTR_ENA;
  270. if (new != reg)
  271. exca_writeb(socket, I365_INTCTL, new);
  272. ti_set_zv(socket);
  273. return 0;
  274. }
  275. static void ti113x_use_isa_irq(struct yenta_socket *socket)
  276. {
  277. int isa_irq = -1;
  278. u8 intctl;
  279. u32 isa_irq_mask = 0;
  280. if (!isa_probe)
  281. return;
  282. /* get a free isa int */
  283. isa_irq_mask = yenta_probe_irq(socket, isa_interrupts);
  284. if (!isa_irq_mask)
  285. return; /* no useable isa irq found */
  286. /* choose highest available */
  287. for (; isa_irq_mask; isa_irq++)
  288. isa_irq_mask >>= 1;
  289. socket->cb_irq = isa_irq;
  290. exca_writeb(socket, I365_CSCINT, (isa_irq << 4));
  291. intctl = exca_readb(socket, I365_INTCTL);
  292. intctl &= ~(I365_INTR_ENA | I365_IRQ_MASK); /* CSC Enable */
  293. exca_writeb(socket, I365_INTCTL, intctl);
  294. dev_info(&socket->dev->dev,
  295. "Yenta TI113x: using isa irq %d for CardBus\n", isa_irq);
  296. }
  297. static int ti113x_override(struct yenta_socket *socket)
  298. {
  299. u8 cardctl;
  300. cardctl = config_readb(socket, TI113X_CARD_CONTROL);
  301. cardctl &= ~(TI113X_CCR_PCI_IRQ_ENA | TI113X_CCR_PCI_IREQ | TI113X_CCR_PCI_CSC);
  302. if (socket->dev->irq)
  303. cardctl |= TI113X_CCR_PCI_IRQ_ENA | TI113X_CCR_PCI_CSC | TI113X_CCR_PCI_IREQ;
  304. else
  305. ti113x_use_isa_irq(socket);
  306. config_writeb(socket, TI113X_CARD_CONTROL, cardctl);
  307. return ti_override(socket);
  308. }
  309. /* irqrouting for func0, probes PCI interrupt and ISA interrupts */
  310. static void ti12xx_irqroute_func0(struct yenta_socket *socket)
  311. {
  312. u32 mfunc, mfunc_old, devctl;
  313. u8 gpio3, gpio3_old;
  314. int pci_irq_status;
  315. mfunc = mfunc_old = config_readl(socket, TI122X_MFUNC);
  316. devctl = config_readb(socket, TI113X_DEVICE_CONTROL);
  317. dev_info(&socket->dev->dev, "TI: mfunc 0x%08x, devctl 0x%02x\n",
  318. mfunc, devctl);
  319. /* make sure PCI interrupts are enabled before probing */
  320. ti_init(socket);
  321. /* test PCI interrupts first. only try fixing if return value is 0! */
  322. pci_irq_status = yenta_probe_cb_irq(socket);
  323. if (pci_irq_status)
  324. goto out;
  325. /*
  326. * We're here which means PCI interrupts are _not_ delivered. try to
  327. * find the right setting (all serial or parallel)
  328. */
  329. dev_info(&socket->dev->dev,
  330. "TI: probing PCI interrupt failed, trying to fix\n");
  331. /* for serial PCI make sure MFUNC3 is set to IRQSER */
  332. if ((devctl & TI113X_DCR_IMODE_MASK) == TI12XX_DCR_IMODE_ALL_SERIAL) {
  333. switch (socket->dev->device) {
  334. case PCI_DEVICE_ID_TI_1250:
  335. case PCI_DEVICE_ID_TI_1251A:
  336. case PCI_DEVICE_ID_TI_1251B:
  337. case PCI_DEVICE_ID_TI_1450:
  338. case PCI_DEVICE_ID_TI_1451A:
  339. case PCI_DEVICE_ID_TI_4450:
  340. case PCI_DEVICE_ID_TI_4451:
  341. /* these chips have no IRQSER setting in MFUNC3 */
  342. break;
  343. default:
  344. mfunc = (mfunc & ~TI122X_MFUNC3_MASK) | TI122X_MFUNC3_IRQSER;
  345. /* write down if changed, probe */
  346. if (mfunc != mfunc_old) {
  347. config_writel(socket, TI122X_MFUNC, mfunc);
  348. pci_irq_status = yenta_probe_cb_irq(socket);
  349. if (pci_irq_status == 1) {
  350. dev_info(&socket->dev->dev,
  351. "TI: all-serial interrupts ok\n");
  352. mfunc_old = mfunc;
  353. goto out;
  354. }
  355. /* not working, back to old value */
  356. mfunc = mfunc_old;
  357. config_writel(socket, TI122X_MFUNC, mfunc);
  358. if (pci_irq_status == -1)
  359. goto out;
  360. }
  361. }
  362. /* serial PCI interrupts not working fall back to parallel */
  363. dev_info(&socket->dev->dev,
  364. "TI: falling back to parallel PCI interrupts\n");
  365. devctl &= ~TI113X_DCR_IMODE_MASK;
  366. devctl |= TI113X_DCR_IMODE_SERIAL; /* serial ISA could be right */
  367. config_writeb(socket, TI113X_DEVICE_CONTROL, devctl);
  368. }
  369. /* parallel PCI interrupts: route INTA */
  370. switch (socket->dev->device) {
  371. case PCI_DEVICE_ID_TI_1250:
  372. case PCI_DEVICE_ID_TI_1251A:
  373. case PCI_DEVICE_ID_TI_1251B:
  374. case PCI_DEVICE_ID_TI_1450:
  375. /* make sure GPIO3 is set to INTA */
  376. gpio3 = gpio3_old = config_readb(socket, TI1250_GPIO3_CONTROL);
  377. gpio3 &= ~TI1250_GPIO_MODE_MASK;
  378. if (gpio3 != gpio3_old)
  379. config_writeb(socket, TI1250_GPIO3_CONTROL, gpio3);
  380. break;
  381. default:
  382. gpio3 = gpio3_old = 0;
  383. mfunc = (mfunc & ~TI122X_MFUNC0_MASK) | TI122X_MFUNC0_INTA;
  384. if (mfunc != mfunc_old)
  385. config_writel(socket, TI122X_MFUNC, mfunc);
  386. }
  387. /* time to probe again */
  388. pci_irq_status = yenta_probe_cb_irq(socket);
  389. if (pci_irq_status == 1) {
  390. mfunc_old = mfunc;
  391. dev_info(&socket->dev->dev, "TI: parallel PCI interrupts ok\n");
  392. } else {
  393. /* not working, back to old value */
  394. mfunc = mfunc_old;
  395. config_writel(socket, TI122X_MFUNC, mfunc);
  396. if (gpio3 != gpio3_old)
  397. config_writeb(socket, TI1250_GPIO3_CONTROL, gpio3_old);
  398. }
  399. out:
  400. if (pci_irq_status < 1) {
  401. socket->cb_irq = 0;
  402. dev_info(&socket->dev->dev,
  403. "Yenta TI: no PCI interrupts. Fish. Please report.\n");
  404. }
  405. }
  406. /* changes the irq of func1 to match that of func0 */
  407. static int ti12xx_align_irqs(struct yenta_socket *socket, int *old_irq)
  408. {
  409. struct pci_dev *func0;
  410. /* find func0 device */
  411. func0 = pci_get_slot(socket->dev->bus, socket->dev->devfn & ~0x07);
  412. if (!func0)
  413. return 0;
  414. if (old_irq)
  415. *old_irq = socket->cb_irq;
  416. socket->cb_irq = socket->dev->irq = func0->irq;
  417. pci_dev_put(func0);
  418. return 1;
  419. }
  420. /*
  421. * ties INTA and INTB together. also changes the devices irq to that of
  422. * the function 0 device. call from func1 only.
  423. * returns 1 if INTRTIE changed, 0 otherwise.
  424. */
  425. static int ti12xx_tie_interrupts(struct yenta_socket *socket, int *old_irq)
  426. {
  427. u32 sysctl;
  428. int ret;
  429. sysctl = config_readl(socket, TI113X_SYSTEM_CONTROL);
  430. if (sysctl & TI122X_SCR_INTRTIE)
  431. return 0;
  432. /* align */
  433. ret = ti12xx_align_irqs(socket, old_irq);
  434. if (!ret)
  435. return 0;
  436. /* tie */
  437. sysctl |= TI122X_SCR_INTRTIE;
  438. config_writel(socket, TI113X_SYSTEM_CONTROL, sysctl);
  439. return 1;
  440. }
  441. /* undo what ti12xx_tie_interrupts() did */
  442. static void ti12xx_untie_interrupts(struct yenta_socket *socket, int old_irq)
  443. {
  444. u32 sysctl = config_readl(socket, TI113X_SYSTEM_CONTROL);
  445. sysctl &= ~TI122X_SCR_INTRTIE;
  446. config_writel(socket, TI113X_SYSTEM_CONTROL, sysctl);
  447. socket->cb_irq = socket->dev->irq = old_irq;
  448. }
  449. /*
  450. * irqrouting for func1, plays with INTB routing
  451. * only touches MFUNC for INTB routing. all other bits are taken
  452. * care of in func0 already.
  453. */
  454. static void ti12xx_irqroute_func1(struct yenta_socket *socket)
  455. {
  456. u32 mfunc, mfunc_old, devctl, sysctl;
  457. int pci_irq_status;
  458. mfunc = mfunc_old = config_readl(socket, TI122X_MFUNC);
  459. devctl = config_readb(socket, TI113X_DEVICE_CONTROL);
  460. dev_info(&socket->dev->dev, "TI: mfunc 0x%08x, devctl 0x%02x\n",
  461. mfunc, devctl);
  462. /* if IRQs are configured as tied, align irq of func1 with func0 */
  463. sysctl = config_readl(socket, TI113X_SYSTEM_CONTROL);
  464. if (sysctl & TI122X_SCR_INTRTIE)
  465. ti12xx_align_irqs(socket, NULL);
  466. /* make sure PCI interrupts are enabled before probing */
  467. ti_init(socket);
  468. /* test PCI interrupts first. only try fixing if return value is 0! */
  469. pci_irq_status = yenta_probe_cb_irq(socket);
  470. if (pci_irq_status)
  471. goto out;
  472. /*
  473. * We're here which means PCI interrupts are _not_ delivered. try to
  474. * find the right setting
  475. */
  476. dev_info(&socket->dev->dev,
  477. "TI: probing PCI interrupt failed, trying to fix\n");
  478. /* if all serial: set INTRTIE, probe again */
  479. if ((devctl & TI113X_DCR_IMODE_MASK) == TI12XX_DCR_IMODE_ALL_SERIAL) {
  480. int old_irq;
  481. if (ti12xx_tie_interrupts(socket, &old_irq)) {
  482. pci_irq_status = yenta_probe_cb_irq(socket);
  483. if (pci_irq_status == 1) {
  484. dev_info(&socket->dev->dev,
  485. "TI: all-serial interrupts, tied ok\n");
  486. goto out;
  487. }
  488. ti12xx_untie_interrupts(socket, old_irq);
  489. }
  490. }
  491. /* parallel PCI: route INTB, probe again */
  492. else {
  493. int old_irq;
  494. switch (socket->dev->device) {
  495. case PCI_DEVICE_ID_TI_1250:
  496. /* the 1250 has one pin for IRQSER/INTB depending on devctl */
  497. break;
  498. case PCI_DEVICE_ID_TI_1251A:
  499. case PCI_DEVICE_ID_TI_1251B:
  500. case PCI_DEVICE_ID_TI_1450:
  501. /*
  502. * those have a pin for IRQSER/INTB plus INTB in MFUNC0
  503. * we alread probed the shared pin, now go for MFUNC0
  504. */
  505. mfunc = (mfunc & ~TI122X_MFUNC0_MASK) | TI125X_MFUNC0_INTB;
  506. break;
  507. default:
  508. mfunc = (mfunc & ~TI122X_MFUNC1_MASK) | TI122X_MFUNC1_INTB;
  509. break;
  510. }
  511. /* write, probe */
  512. if (mfunc != mfunc_old) {
  513. config_writel(socket, TI122X_MFUNC, mfunc);
  514. pci_irq_status = yenta_probe_cb_irq(socket);
  515. if (pci_irq_status == 1) {
  516. dev_info(&socket->dev->dev,
  517. "TI: parallel PCI interrupts ok\n");
  518. goto out;
  519. }
  520. mfunc = mfunc_old;
  521. config_writel(socket, TI122X_MFUNC, mfunc);
  522. if (pci_irq_status == -1)
  523. goto out;
  524. }
  525. /* still nothing: set INTRTIE */
  526. if (ti12xx_tie_interrupts(socket, &old_irq)) {
  527. pci_irq_status = yenta_probe_cb_irq(socket);
  528. if (pci_irq_status == 1) {
  529. dev_info(&socket->dev->dev,
  530. "TI: parallel PCI interrupts, tied ok\n");
  531. goto out;
  532. }
  533. ti12xx_untie_interrupts(socket, old_irq);
  534. }
  535. }
  536. out:
  537. if (pci_irq_status < 1) {
  538. socket->cb_irq = 0;
  539. dev_info(&socket->dev->dev,
  540. "TI: no PCI interrupts. Fish. Please report.\n");
  541. }
  542. }
  543. /* Returns true value if the second slot of a two-slot controller is empty */
  544. static int ti12xx_2nd_slot_empty(struct yenta_socket *socket)
  545. {
  546. struct pci_dev *func;
  547. struct yenta_socket *slot2;
  548. int devfn;
  549. unsigned int state;
  550. int ret = 1;
  551. u32 sysctl;
  552. /* catch the two-slot controllers */
  553. switch (socket->dev->device) {
  554. case PCI_DEVICE_ID_TI_1220:
  555. case PCI_DEVICE_ID_TI_1221:
  556. case PCI_DEVICE_ID_TI_1225:
  557. case PCI_DEVICE_ID_TI_1251A:
  558. case PCI_DEVICE_ID_TI_1251B:
  559. case PCI_DEVICE_ID_TI_1420:
  560. case PCI_DEVICE_ID_TI_1450:
  561. case PCI_DEVICE_ID_TI_1451A:
  562. case PCI_DEVICE_ID_TI_1520:
  563. case PCI_DEVICE_ID_TI_1620:
  564. case PCI_DEVICE_ID_TI_4520:
  565. case PCI_DEVICE_ID_TI_4450:
  566. case PCI_DEVICE_ID_TI_4451:
  567. /*
  568. * there are way more, but they need to be added in yenta_socket.c
  569. * and pci_ids.h first anyway.
  570. */
  571. break;
  572. case PCI_DEVICE_ID_TI_XX12:
  573. case PCI_DEVICE_ID_TI_X515:
  574. case PCI_DEVICE_ID_TI_X420:
  575. case PCI_DEVICE_ID_TI_X620:
  576. case PCI_DEVICE_ID_TI_XX21_XX11:
  577. case PCI_DEVICE_ID_TI_7410:
  578. case PCI_DEVICE_ID_TI_7610:
  579. /*
  580. * those are either single or dual slot CB with additional functions
  581. * like 1394, smartcard reader, etc. check the TIEALL flag for them
  582. * the TIEALL flag binds the IRQ of all functions together.
  583. * we catch the single slot variants later.
  584. */
  585. sysctl = config_readl(socket, TI113X_SYSTEM_CONTROL);
  586. if (sysctl & TIXX21_SCR_TIEALL)
  587. return 0;
  588. break;
  589. /* single-slot controllers have the 2nd slot empty always :) */
  590. default:
  591. return 1;
  592. }
  593. /* get other slot */
  594. devfn = socket->dev->devfn & ~0x07;
  595. func = pci_get_slot(socket->dev->bus,
  596. (socket->dev->devfn & 0x07) ? devfn : devfn | 0x01);
  597. if (!func)
  598. return 1;
  599. /*
  600. * check that the device id of both slots match. this is needed for the
  601. * XX21 and the XX11 controller that share the same device id for single
  602. * and dual slot controllers. return '2nd slot empty'. we already checked
  603. * if the interrupt is tied to another function.
  604. */
  605. if (socket->dev->device != func->device)
  606. goto out;
  607. slot2 = pci_get_drvdata(func);
  608. if (!slot2)
  609. goto out;
  610. /* check state */
  611. yenta_get_status(&slot2->socket, &state);
  612. if (state & SS_DETECT) {
  613. ret = 0;
  614. goto out;
  615. }
  616. out:
  617. pci_dev_put(func);
  618. return ret;
  619. }
  620. /*
  621. * TI specifiy parts for the power hook.
  622. *
  623. * some TI's with some CB's produces interrupt storm on power on. it has been
  624. * seen with atheros wlan cards on TI1225 and TI1410. solution is simply to
  625. * disable any CB interrupts during this time.
  626. */
  627. static int ti12xx_power_hook(struct pcmcia_socket *sock, int operation)
  628. {
  629. struct yenta_socket *socket = container_of(sock, struct yenta_socket, socket);
  630. u32 mfunc, devctl, sysctl;
  631. u8 gpio3;
  632. /* only POWER_PRE and POWER_POST are interesting */
  633. if ((operation != HOOK_POWER_PRE) && (operation != HOOK_POWER_POST))
  634. return 0;
  635. devctl = config_readb(socket, TI113X_DEVICE_CONTROL);
  636. sysctl = config_readl(socket, TI113X_SYSTEM_CONTROL);
  637. mfunc = config_readl(socket, TI122X_MFUNC);
  638. /*
  639. * all serial/tied: only disable when modparm set. always doing it
  640. * would mean a regression for working setups 'cos it disables the
  641. * interrupts for both both slots on 2-slot controllers
  642. * (and users of single slot controllers where it's save have to
  643. * live with setting the modparm, most don't have to anyway)
  644. */
  645. if (((devctl & TI113X_DCR_IMODE_MASK) == TI12XX_DCR_IMODE_ALL_SERIAL) &&
  646. (pwr_irqs_off || ti12xx_2nd_slot_empty(socket))) {
  647. switch (socket->dev->device) {
  648. case PCI_DEVICE_ID_TI_1250:
  649. case PCI_DEVICE_ID_TI_1251A:
  650. case PCI_DEVICE_ID_TI_1251B:
  651. case PCI_DEVICE_ID_TI_1450:
  652. case PCI_DEVICE_ID_TI_1451A:
  653. case PCI_DEVICE_ID_TI_4450:
  654. case PCI_DEVICE_ID_TI_4451:
  655. /* these chips have no IRQSER setting in MFUNC3 */
  656. break;
  657. default:
  658. if (operation == HOOK_POWER_PRE)
  659. mfunc = (mfunc & ~TI122X_MFUNC3_MASK);
  660. else
  661. mfunc = (mfunc & ~TI122X_MFUNC3_MASK) | TI122X_MFUNC3_IRQSER;
  662. }
  663. return 0;
  664. }
  665. /* do the job differently for func0/1 */
  666. if ((PCI_FUNC(socket->dev->devfn) == 0) ||
  667. ((sysctl & TI122X_SCR_INTRTIE) &&
  668. (pwr_irqs_off || ti12xx_2nd_slot_empty(socket)))) {
  669. /* some bridges are different */
  670. switch (socket->dev->device) {
  671. case PCI_DEVICE_ID_TI_1250:
  672. case PCI_DEVICE_ID_TI_1251A:
  673. case PCI_DEVICE_ID_TI_1251B:
  674. case PCI_DEVICE_ID_TI_1450:
  675. /* those oldies use gpio3 for INTA */
  676. gpio3 = config_readb(socket, TI1250_GPIO3_CONTROL);
  677. if (operation == HOOK_POWER_PRE)
  678. gpio3 = (gpio3 & ~TI1250_GPIO_MODE_MASK) | 0x40;
  679. else
  680. gpio3 &= ~TI1250_GPIO_MODE_MASK;
  681. config_writeb(socket, TI1250_GPIO3_CONTROL, gpio3);
  682. break;
  683. default:
  684. /* all new bridges are the same */
  685. if (operation == HOOK_POWER_PRE)
  686. mfunc &= ~TI122X_MFUNC0_MASK;
  687. else
  688. mfunc |= TI122X_MFUNC0_INTA;
  689. config_writel(socket, TI122X_MFUNC, mfunc);
  690. }
  691. } else {
  692. switch (socket->dev->device) {
  693. case PCI_DEVICE_ID_TI_1251A:
  694. case PCI_DEVICE_ID_TI_1251B:
  695. case PCI_DEVICE_ID_TI_1450:
  696. /* those have INTA elsewhere and INTB in MFUNC0 */
  697. if (operation == HOOK_POWER_PRE)
  698. mfunc &= ~TI122X_MFUNC0_MASK;
  699. else
  700. mfunc |= TI125X_MFUNC0_INTB;
  701. config_writel(socket, TI122X_MFUNC, mfunc);
  702. break;
  703. default:
  704. /* all new bridges are the same */
  705. if (operation == HOOK_POWER_PRE)
  706. mfunc &= ~TI122X_MFUNC1_MASK;
  707. else
  708. mfunc |= TI122X_MFUNC1_INTB;
  709. config_writel(socket, TI122X_MFUNC, mfunc);
  710. }
  711. }
  712. return 0;
  713. }
  714. static int ti12xx_override(struct yenta_socket *socket)
  715. {
  716. u32 val, val_orig;
  717. /* make sure that memory burst is active */
  718. val_orig = val = config_readl(socket, TI113X_SYSTEM_CONTROL);
  719. if (disable_clkrun && PCI_FUNC(socket->dev->devfn) == 0) {
  720. dev_info(&socket->dev->dev, "Disabling CLKRUN feature\n");
  721. val |= TI113X_SCR_KEEPCLK;
  722. }
  723. if (!(val & TI122X_SCR_MRBURSTUP)) {
  724. dev_info(&socket->dev->dev,
  725. "Enabling burst memory read transactions\n");
  726. val |= TI122X_SCR_MRBURSTUP;
  727. }
  728. if (val_orig != val)
  729. config_writel(socket, TI113X_SYSTEM_CONTROL, val);
  730. /*
  731. * Yenta expects controllers to use CSCINT to route
  732. * CSC interrupts to PCI rather than INTVAL.
  733. */
  734. val = config_readb(socket, TI1250_DIAGNOSTIC);
  735. dev_info(&socket->dev->dev, "Using %s to route CSC interrupts to PCI\n",
  736. (val & TI1250_DIAG_PCI_CSC) ? "CSCINT" : "INTVAL");
  737. dev_info(&socket->dev->dev, "Routing CardBus interrupts to %s\n",
  738. (val & TI1250_DIAG_PCI_IREQ) ? "PCI" : "ISA");
  739. /* do irqrouting, depending on function */
  740. if (PCI_FUNC(socket->dev->devfn) == 0)
  741. ti12xx_irqroute_func0(socket);
  742. else
  743. ti12xx_irqroute_func1(socket);
  744. /* install power hook */
  745. socket->socket.power_hook = ti12xx_power_hook;
  746. return ti_override(socket);
  747. }
  748. static int ti1250_override(struct yenta_socket *socket)
  749. {
  750. u8 old, diag;
  751. old = config_readb(socket, TI1250_DIAGNOSTIC);
  752. diag = old & ~(TI1250_DIAG_PCI_CSC | TI1250_DIAG_PCI_IREQ);
  753. if (socket->cb_irq)
  754. diag |= TI1250_DIAG_PCI_CSC | TI1250_DIAG_PCI_IREQ;
  755. if (diag != old) {
  756. dev_info(&socket->dev->dev,
  757. "adjusting diagnostic: %02x -> %02x\n",
  758. old, diag);
  759. config_writeb(socket, TI1250_DIAGNOSTIC, diag);
  760. }
  761. return ti12xx_override(socket);
  762. }
  763. /**
  764. * EnE specific part. EnE bridges are register compatible with TI bridges but
  765. * have their own test registers and more important their own little problems.
  766. * Some fixup code to make everybody happy (TM).
  767. */
  768. #ifdef CONFIG_YENTA_ENE_TUNE
  769. /*
  770. * set/clear various test bits:
  771. * Defaults to clear the bit.
  772. * - mask (u8) defines what bits to change
  773. * - bits (u8) is the values to change them to
  774. * -> it's
  775. * current = (current & ~mask) | bits
  776. */
  777. /* pci ids of devices that wants to have the bit set */
  778. #define DEVID(_vend,_dev,_subvend,_subdev,mask,bits) { \
  779. .vendor = _vend, \
  780. .device = _dev, \
  781. .subvendor = _subvend, \
  782. .subdevice = _subdev, \
  783. .driver_data = ((mask) << 8 | (bits)), \
  784. }
  785. static struct pci_device_id ene_tune_tbl[] = {
  786. /* Echo Audio products based on motorola DSP56301 and DSP56361 */
  787. DEVID(PCI_VENDOR_ID_MOTOROLA, 0x1801, 0xECC0, PCI_ANY_ID,
  788. ENE_TEST_C9_TLTENABLE | ENE_TEST_C9_PFENABLE, ENE_TEST_C9_TLTENABLE),
  789. DEVID(PCI_VENDOR_ID_MOTOROLA, 0x3410, 0xECC0, PCI_ANY_ID,
  790. ENE_TEST_C9_TLTENABLE | ENE_TEST_C9_PFENABLE, ENE_TEST_C9_TLTENABLE),
  791. {}
  792. };
  793. static void ene_tune_bridge(struct pcmcia_socket *sock, struct pci_bus *bus)
  794. {
  795. struct yenta_socket *socket = container_of(sock, struct yenta_socket, socket);
  796. struct pci_dev *dev;
  797. struct pci_device_id *id = NULL;
  798. u8 test_c9, old_c9, mask, bits;
  799. list_for_each_entry(dev, &bus->devices, bus_list) {
  800. id = (struct pci_device_id *) pci_match_id(ene_tune_tbl, dev);
  801. if (id)
  802. break;
  803. }
  804. test_c9 = old_c9 = config_readb(socket, ENE_TEST_C9);
  805. if (id) {
  806. mask = (id->driver_data >> 8) & 0xFF;
  807. bits = id->driver_data & 0xFF;
  808. test_c9 = (test_c9 & ~mask) | bits;
  809. }
  810. else
  811. /* default to clear TLTEnable bit, old behaviour */
  812. test_c9 &= ~ENE_TEST_C9_TLTENABLE;
  813. dev_info(&socket->dev->dev,
  814. "EnE: changing testregister 0xC9, %02x -> %02x\n",
  815. old_c9, test_c9);
  816. config_writeb(socket, ENE_TEST_C9, test_c9);
  817. }
  818. static int ene_override(struct yenta_socket *socket)
  819. {
  820. /* install tune_bridge() function */
  821. socket->socket.tune_bridge = ene_tune_bridge;
  822. return ti1250_override(socket);
  823. }
  824. #else
  825. # define ene_override ti1250_override
  826. #endif /* !CONFIG_YENTA_ENE_TUNE */
  827. #endif /* _LINUX_TI113X_H */