pxa2xx_base.c 10 KB

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  1. // SPDX-License-Identifier: GPL-2.0-only
  2. /*======================================================================
  3. Device driver for the PCMCIA control functionality of PXA2xx
  4. microprocessors.
  5. (c) Ian Molton (spyro@f2s.com) 2003
  6. (c) Stefan Eletzhofer (stefan.eletzhofer@inquant.de) 2003,4
  7. derived from sa11xx_base.c
  8. Portions created by John G. Dorsey are
  9. Copyright (C) 1999 John G. Dorsey.
  10. ======================================================================*/
  11. #include <linux/module.h>
  12. #include <linux/slab.h>
  13. #include <linux/init.h>
  14. #include <linux/cpufreq.h>
  15. #include <linux/ioport.h>
  16. #include <linux/kernel.h>
  17. #include <linux/spinlock.h>
  18. #include <linux/platform_device.h>
  19. #include <mach/hardware.h>
  20. #include <mach/smemc.h>
  21. #include <asm/io.h>
  22. #include <asm/irq.h>
  23. #include <mach/pxa2xx-regs.h>
  24. #include <asm/mach-types.h>
  25. #include <pcmcia/ss.h>
  26. #include <pcmcia/cistpl.h>
  27. #include "soc_common.h"
  28. #include "pxa2xx_base.h"
  29. /*
  30. * Personal Computer Memory Card International Association (PCMCIA) sockets
  31. */
  32. #define PCMCIAPrtSp 0x04000000 /* PCMCIA Partition Space [byte] */
  33. #define PCMCIASp (4*PCMCIAPrtSp) /* PCMCIA Space [byte] */
  34. #define PCMCIAIOSp PCMCIAPrtSp /* PCMCIA I/O Space [byte] */
  35. #define PCMCIAAttrSp PCMCIAPrtSp /* PCMCIA Attribute Space [byte] */
  36. #define PCMCIAMemSp PCMCIAPrtSp /* PCMCIA Memory Space [byte] */
  37. #define PCMCIA0Sp PCMCIASp /* PCMCIA 0 Space [byte] */
  38. #define PCMCIA0IOSp PCMCIAIOSp /* PCMCIA 0 I/O Space [byte] */
  39. #define PCMCIA0AttrSp PCMCIAAttrSp /* PCMCIA 0 Attribute Space [byte] */
  40. #define PCMCIA0MemSp PCMCIAMemSp /* PCMCIA 0 Memory Space [byte] */
  41. #define PCMCIA1Sp PCMCIASp /* PCMCIA 1 Space [byte] */
  42. #define PCMCIA1IOSp PCMCIAIOSp /* PCMCIA 1 I/O Space [byte] */
  43. #define PCMCIA1AttrSp PCMCIAAttrSp /* PCMCIA 1 Attribute Space [byte] */
  44. #define PCMCIA1MemSp PCMCIAMemSp /* PCMCIA 1 Memory Space [byte] */
  45. #define _PCMCIA(Nb) /* PCMCIA [0..1] */ \
  46. (0x20000000 + (Nb) * PCMCIASp)
  47. #define _PCMCIAIO(Nb) _PCMCIA(Nb) /* PCMCIA I/O [0..1] */
  48. #define _PCMCIAAttr(Nb) /* PCMCIA Attribute [0..1] */ \
  49. (_PCMCIA(Nb) + 2 * PCMCIAPrtSp)
  50. #define _PCMCIAMem(Nb) /* PCMCIA Memory [0..1] */ \
  51. (_PCMCIA(Nb) + 3 * PCMCIAPrtSp)
  52. #define _PCMCIA0 _PCMCIA(0) /* PCMCIA 0 */
  53. #define _PCMCIA0IO _PCMCIAIO(0) /* PCMCIA 0 I/O */
  54. #define _PCMCIA0Attr _PCMCIAAttr(0) /* PCMCIA 0 Attribute */
  55. #define _PCMCIA0Mem _PCMCIAMem(0) /* PCMCIA 0 Memory */
  56. #define _PCMCIA1 _PCMCIA(1) /* PCMCIA 1 */
  57. #define _PCMCIA1IO _PCMCIAIO(1) /* PCMCIA 1 I/O */
  58. #define _PCMCIA1Attr _PCMCIAAttr(1) /* PCMCIA 1 Attribute */
  59. #define _PCMCIA1Mem _PCMCIAMem(1) /* PCMCIA 1 Memory */
  60. #define MCXX_SETUP_MASK (0x7f)
  61. #define MCXX_ASST_MASK (0x1f)
  62. #define MCXX_HOLD_MASK (0x3f)
  63. #define MCXX_SETUP_SHIFT (0)
  64. #define MCXX_ASST_SHIFT (7)
  65. #define MCXX_HOLD_SHIFT (14)
  66. static inline u_int pxa2xx_mcxx_hold(u_int pcmcia_cycle_ns,
  67. u_int mem_clk_10khz)
  68. {
  69. u_int code = pcmcia_cycle_ns * mem_clk_10khz;
  70. return (code / 300000) + ((code % 300000) ? 1 : 0) - 1;
  71. }
  72. static inline u_int pxa2xx_mcxx_asst(u_int pcmcia_cycle_ns,
  73. u_int mem_clk_10khz)
  74. {
  75. u_int code = pcmcia_cycle_ns * mem_clk_10khz;
  76. return (code / 300000) + ((code % 300000) ? 1 : 0) + 1;
  77. }
  78. static inline u_int pxa2xx_mcxx_setup(u_int pcmcia_cycle_ns,
  79. u_int mem_clk_10khz)
  80. {
  81. u_int code = pcmcia_cycle_ns * mem_clk_10khz;
  82. return (code / 100000) + ((code % 100000) ? 1 : 0) - 1;
  83. }
  84. /* This function returns the (approximate) command assertion period, in
  85. * nanoseconds, for a given CPU clock frequency and MCXX_ASST value:
  86. */
  87. static inline u_int pxa2xx_pcmcia_cmd_time(u_int mem_clk_10khz,
  88. u_int pcmcia_mcxx_asst)
  89. {
  90. return (300000 * (pcmcia_mcxx_asst + 1) / mem_clk_10khz);
  91. }
  92. static int pxa2xx_pcmcia_set_mcmem( int sock, int speed, int clock )
  93. {
  94. uint32_t val;
  95. val = ((pxa2xx_mcxx_setup(speed, clock)
  96. & MCXX_SETUP_MASK) << MCXX_SETUP_SHIFT)
  97. | ((pxa2xx_mcxx_asst(speed, clock)
  98. & MCXX_ASST_MASK) << MCXX_ASST_SHIFT)
  99. | ((pxa2xx_mcxx_hold(speed, clock)
  100. & MCXX_HOLD_MASK) << MCXX_HOLD_SHIFT);
  101. __raw_writel(val, MCMEM(sock));
  102. return 0;
  103. }
  104. static int pxa2xx_pcmcia_set_mcio( int sock, int speed, int clock )
  105. {
  106. uint32_t val;
  107. val = ((pxa2xx_mcxx_setup(speed, clock)
  108. & MCXX_SETUP_MASK) << MCXX_SETUP_SHIFT)
  109. | ((pxa2xx_mcxx_asst(speed, clock)
  110. & MCXX_ASST_MASK) << MCXX_ASST_SHIFT)
  111. | ((pxa2xx_mcxx_hold(speed, clock)
  112. & MCXX_HOLD_MASK) << MCXX_HOLD_SHIFT);
  113. __raw_writel(val, MCIO(sock));
  114. return 0;
  115. }
  116. static int pxa2xx_pcmcia_set_mcatt( int sock, int speed, int clock )
  117. {
  118. uint32_t val;
  119. val = ((pxa2xx_mcxx_setup(speed, clock)
  120. & MCXX_SETUP_MASK) << MCXX_SETUP_SHIFT)
  121. | ((pxa2xx_mcxx_asst(speed, clock)
  122. & MCXX_ASST_MASK) << MCXX_ASST_SHIFT)
  123. | ((pxa2xx_mcxx_hold(speed, clock)
  124. & MCXX_HOLD_MASK) << MCXX_HOLD_SHIFT);
  125. __raw_writel(val, MCATT(sock));
  126. return 0;
  127. }
  128. static int pxa2xx_pcmcia_set_mcxx(struct soc_pcmcia_socket *skt, unsigned int clk)
  129. {
  130. struct soc_pcmcia_timing timing;
  131. int sock = skt->nr;
  132. soc_common_pcmcia_get_timing(skt, &timing);
  133. pxa2xx_pcmcia_set_mcmem(sock, timing.mem, clk);
  134. pxa2xx_pcmcia_set_mcatt(sock, timing.attr, clk);
  135. pxa2xx_pcmcia_set_mcio(sock, timing.io, clk);
  136. return 0;
  137. }
  138. static int pxa2xx_pcmcia_set_timing(struct soc_pcmcia_socket *skt)
  139. {
  140. unsigned long clk = clk_get_rate(skt->clk);
  141. return pxa2xx_pcmcia_set_mcxx(skt, clk / 10000);
  142. }
  143. #ifdef CONFIG_CPU_FREQ
  144. static int
  145. pxa2xx_pcmcia_frequency_change(struct soc_pcmcia_socket *skt,
  146. unsigned long val,
  147. struct cpufreq_freqs *freqs)
  148. {
  149. switch (val) {
  150. case CPUFREQ_PRECHANGE:
  151. if (freqs->new > freqs->old) {
  152. debug(skt, 2, "new frequency %u.%uMHz > %u.%uMHz, "
  153. "pre-updating\n",
  154. freqs->new / 1000, (freqs->new / 100) % 10,
  155. freqs->old / 1000, (freqs->old / 100) % 10);
  156. pxa2xx_pcmcia_set_timing(skt);
  157. }
  158. break;
  159. case CPUFREQ_POSTCHANGE:
  160. if (freqs->new < freqs->old) {
  161. debug(skt, 2, "new frequency %u.%uMHz < %u.%uMHz, "
  162. "post-updating\n",
  163. freqs->new / 1000, (freqs->new / 100) % 10,
  164. freqs->old / 1000, (freqs->old / 100) % 10);
  165. pxa2xx_pcmcia_set_timing(skt);
  166. }
  167. break;
  168. }
  169. return 0;
  170. }
  171. #endif
  172. void pxa2xx_configure_sockets(struct device *dev, struct pcmcia_low_level *ops)
  173. {
  174. /*
  175. * We have at least one socket, so set MECR:CIT
  176. * (Card Is There)
  177. */
  178. uint32_t mecr = MECR_CIT;
  179. /* Set MECR:NOS (Number Of Sockets) */
  180. if ((ops->first + ops->nr) > 1 ||
  181. machine_is_viper() || machine_is_arcom_zeus())
  182. mecr |= MECR_NOS;
  183. __raw_writel(mecr, MECR);
  184. }
  185. EXPORT_SYMBOL(pxa2xx_configure_sockets);
  186. static const char *skt_names[] = {
  187. "PCMCIA socket 0",
  188. "PCMCIA socket 1",
  189. };
  190. #define SKT_DEV_INFO_SIZE(n) \
  191. (sizeof(struct skt_dev_info) + (n)*sizeof(struct soc_pcmcia_socket))
  192. int pxa2xx_drv_pcmcia_add_one(struct soc_pcmcia_socket *skt)
  193. {
  194. skt->res_skt.start = _PCMCIA(skt->nr);
  195. skt->res_skt.end = _PCMCIA(skt->nr) + PCMCIASp - 1;
  196. skt->res_skt.name = skt_names[skt->nr];
  197. skt->res_skt.flags = IORESOURCE_MEM;
  198. skt->res_io.start = _PCMCIAIO(skt->nr);
  199. skt->res_io.end = _PCMCIAIO(skt->nr) + PCMCIAIOSp - 1;
  200. skt->res_io.name = "io";
  201. skt->res_io.flags = IORESOURCE_MEM | IORESOURCE_BUSY;
  202. skt->res_mem.start = _PCMCIAMem(skt->nr);
  203. skt->res_mem.end = _PCMCIAMem(skt->nr) + PCMCIAMemSp - 1;
  204. skt->res_mem.name = "memory";
  205. skt->res_mem.flags = IORESOURCE_MEM;
  206. skt->res_attr.start = _PCMCIAAttr(skt->nr);
  207. skt->res_attr.end = _PCMCIAAttr(skt->nr) + PCMCIAAttrSp - 1;
  208. skt->res_attr.name = "attribute";
  209. skt->res_attr.flags = IORESOURCE_MEM;
  210. return soc_pcmcia_add_one(skt);
  211. }
  212. EXPORT_SYMBOL(pxa2xx_drv_pcmcia_add_one);
  213. void pxa2xx_drv_pcmcia_ops(struct pcmcia_low_level *ops)
  214. {
  215. /* Provide our PXA2xx specific timing routines. */
  216. ops->set_timing = pxa2xx_pcmcia_set_timing;
  217. #ifdef CONFIG_CPU_FREQ
  218. ops->frequency_change = pxa2xx_pcmcia_frequency_change;
  219. #endif
  220. }
  221. EXPORT_SYMBOL(pxa2xx_drv_pcmcia_ops);
  222. static int pxa2xx_drv_pcmcia_probe(struct platform_device *dev)
  223. {
  224. int i, ret = 0;
  225. struct pcmcia_low_level *ops;
  226. struct skt_dev_info *sinfo;
  227. struct soc_pcmcia_socket *skt;
  228. struct clk *clk;
  229. ops = (struct pcmcia_low_level *)dev->dev.platform_data;
  230. if (!ops) {
  231. ret = -ENODEV;
  232. goto err0;
  233. }
  234. if (cpu_is_pxa320() && ops->nr > 1) {
  235. dev_err(&dev->dev, "pxa320 supports only one pcmcia slot");
  236. ret = -EINVAL;
  237. goto err0;
  238. }
  239. clk = devm_clk_get(&dev->dev, NULL);
  240. if (IS_ERR(clk))
  241. return -ENODEV;
  242. pxa2xx_drv_pcmcia_ops(ops);
  243. sinfo = devm_kzalloc(&dev->dev, SKT_DEV_INFO_SIZE(ops->nr),
  244. GFP_KERNEL);
  245. if (!sinfo)
  246. return -ENOMEM;
  247. sinfo->nskt = ops->nr;
  248. /* Initialize processor specific parameters */
  249. for (i = 0; i < ops->nr; i++) {
  250. skt = &sinfo->skt[i];
  251. skt->nr = ops->first + i;
  252. skt->clk = clk;
  253. soc_pcmcia_init_one(skt, ops, &dev->dev);
  254. ret = pxa2xx_drv_pcmcia_add_one(skt);
  255. if (ret)
  256. goto err1;
  257. }
  258. pxa2xx_configure_sockets(&dev->dev, ops);
  259. dev_set_drvdata(&dev->dev, sinfo);
  260. return 0;
  261. err1:
  262. while (--i >= 0)
  263. soc_pcmcia_remove_one(&sinfo->skt[i]);
  264. err0:
  265. return ret;
  266. }
  267. static int pxa2xx_drv_pcmcia_remove(struct platform_device *dev)
  268. {
  269. struct skt_dev_info *sinfo = platform_get_drvdata(dev);
  270. int i;
  271. for (i = 0; i < sinfo->nskt; i++)
  272. soc_pcmcia_remove_one(&sinfo->skt[i]);
  273. return 0;
  274. }
  275. static int pxa2xx_drv_pcmcia_resume(struct device *dev)
  276. {
  277. struct pcmcia_low_level *ops = (struct pcmcia_low_level *)dev->platform_data;
  278. pxa2xx_configure_sockets(dev, ops);
  279. return 0;
  280. }
  281. static const struct dev_pm_ops pxa2xx_drv_pcmcia_pm_ops = {
  282. .resume = pxa2xx_drv_pcmcia_resume,
  283. };
  284. static struct platform_driver pxa2xx_pcmcia_driver = {
  285. .probe = pxa2xx_drv_pcmcia_probe,
  286. .remove = pxa2xx_drv_pcmcia_remove,
  287. .driver = {
  288. .name = "pxa2xx-pcmcia",
  289. .pm = &pxa2xx_drv_pcmcia_pm_ops,
  290. },
  291. };
  292. static int __init pxa2xx_pcmcia_init(void)
  293. {
  294. return platform_driver_register(&pxa2xx_pcmcia_driver);
  295. }
  296. static void __exit pxa2xx_pcmcia_exit(void)
  297. {
  298. platform_driver_unregister(&pxa2xx_pcmcia_driver);
  299. }
  300. fs_initcall(pxa2xx_pcmcia_init);
  301. module_exit(pxa2xx_pcmcia_exit);
  302. MODULE_AUTHOR("Stefan Eletzhofer <stefan.eletzhofer@inquant.de> and Ian Molton <spyro@f2s.com>");
  303. MODULE_DESCRIPTION("Linux PCMCIA Card Services: PXA2xx core socket driver");
  304. MODULE_LICENSE("GPL");
  305. MODULE_ALIAS("platform:pxa2xx-pcmcia");