i82365.h 4.9 KB

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  1. /*
  2. * i82365.h 1.15 1999/10/25 20:03:34
  3. *
  4. * The contents of this file are subject to the Mozilla Public License
  5. * Version 1.1 (the "License"); you may not use this file except in
  6. * compliance with the License. You may obtain a copy of the License
  7. * at http://www.mozilla.org/MPL/
  8. *
  9. * Software distributed under the License is distributed on an "AS IS"
  10. * basis, WITHOUT WARRANTY OF ANY KIND, either express or implied. See
  11. * the License for the specific language governing rights and
  12. * limitations under the License.
  13. *
  14. * The initial developer of the original code is David A. Hinds
  15. * <dahinds@users.sourceforge.net>. Portions created by David A. Hinds
  16. * are Copyright (C) 1999 David A. Hinds. All Rights Reserved.
  17. *
  18. * Alternatively, the contents of this file may be used under the
  19. * terms of the GNU General Public License version 2 (the "GPL"), in which
  20. * case the provisions of the GPL are applicable instead of the
  21. * above. If you wish to allow the use of your version of this file
  22. * only under the terms of the GPL and not to allow others to use
  23. * your version of this file under the MPL, indicate your decision by
  24. * deleting the provisions above and replace them with the notice and
  25. * other provisions required by the GPL. If you do not delete the
  26. * provisions above, a recipient may use your version of this file
  27. * under either the MPL or the GPL.
  28. */
  29. #ifndef _LINUX_I82365_H
  30. #define _LINUX_I82365_H
  31. /* register definitions for the Intel 82365SL PCMCIA controller */
  32. /* Offsets for PCIC registers */
  33. #define I365_IDENT 0x00 /* Identification and revision */
  34. #define I365_STATUS 0x01 /* Interface status */
  35. #define I365_POWER 0x02 /* Power and RESETDRV control */
  36. #define I365_INTCTL 0x03 /* Interrupt and general control */
  37. #define I365_CSC 0x04 /* Card status change */
  38. #define I365_CSCINT 0x05 /* Card status change interrupt control */
  39. #define I365_ADDRWIN 0x06 /* Address window enable */
  40. #define I365_IOCTL 0x07 /* I/O control */
  41. #define I365_GENCTL 0x16 /* Card detect and general control */
  42. #define I365_GBLCTL 0x1E /* Global control register */
  43. /* Offsets for I/O and memory window registers */
  44. #define I365_IO(map) (0x08+((map)<<2))
  45. #define I365_MEM(map) (0x10+((map)<<3))
  46. #define I365_W_START 0
  47. #define I365_W_STOP 2
  48. #define I365_W_OFF 4
  49. /* Flags for I365_STATUS */
  50. #define I365_CS_BVD1 0x01
  51. #define I365_CS_STSCHG 0x01
  52. #define I365_CS_BVD2 0x02
  53. #define I365_CS_SPKR 0x02
  54. #define I365_CS_DETECT 0x0C
  55. #define I365_CS_WRPROT 0x10
  56. #define I365_CS_READY 0x20 /* Inverted */
  57. #define I365_CS_POWERON 0x40
  58. #define I365_CS_GPI 0x80
  59. /* Flags for I365_POWER */
  60. #define I365_PWR_OFF 0x00 /* Turn off the socket */
  61. #define I365_PWR_OUT 0x80 /* Output enable */
  62. #define I365_PWR_NORESET 0x40 /* Disable RESETDRV on resume */
  63. #define I365_PWR_AUTO 0x20 /* Auto pwr switch enable */
  64. #define I365_VCC_MASK 0x18 /* Mask for turning off Vcc */
  65. /* There are different layouts for B-step and DF-step chips: the B
  66. step has independent Vpp1/Vpp2 control, and the DF step has only
  67. Vpp1 control, plus 3V control */
  68. #define I365_VCC_5V 0x10 /* Vcc = 5.0v */
  69. #define I365_VCC_3V 0x18 /* Vcc = 3.3v */
  70. #define I365_VPP2_MASK 0x0c /* Mask for turning off Vpp2 */
  71. #define I365_VPP2_5V 0x04 /* Vpp2 = 5.0v */
  72. #define I365_VPP2_12V 0x08 /* Vpp2 = 12.0v */
  73. #define I365_VPP1_MASK 0x03 /* Mask for turning off Vpp1 */
  74. #define I365_VPP1_5V 0x01 /* Vpp1 = 5.0v */
  75. #define I365_VPP1_12V 0x02 /* Vpp1 = 12.0v */
  76. /* Flags for I365_INTCTL */
  77. #define I365_RING_ENA 0x80
  78. #define I365_PC_RESET 0x40
  79. #define I365_PC_IOCARD 0x20
  80. #define I365_INTR_ENA 0x10
  81. #define I365_IRQ_MASK 0x0F
  82. /* Flags for I365_CSC and I365_CSCINT*/
  83. #define I365_CSC_BVD1 0x01
  84. #define I365_CSC_STSCHG 0x01
  85. #define I365_CSC_BVD2 0x02
  86. #define I365_CSC_READY 0x04
  87. #define I365_CSC_DETECT 0x08
  88. #define I365_CSC_ANY 0x0F
  89. #define I365_CSC_GPI 0x10
  90. #define I365_CSC_IRQ_MASK 0xF0
  91. /* Flags for I365_ADDRWIN */
  92. #define I365_ENA_IO(map) (0x40 << (map))
  93. #define I365_ENA_MEM(map) (0x01 << (map))
  94. /* Flags for I365_IOCTL */
  95. #define I365_IOCTL_MASK(map) (0x0F << (map<<2))
  96. #define I365_IOCTL_WAIT(map) (0x08 << (map<<2))
  97. #define I365_IOCTL_0WS(map) (0x04 << (map<<2))
  98. #define I365_IOCTL_IOCS16(map) (0x02 << (map<<2))
  99. #define I365_IOCTL_16BIT(map) (0x01 << (map<<2))
  100. /* Flags for I365_GENCTL */
  101. #define I365_CTL_16DELAY 0x01
  102. #define I365_CTL_RESET 0x02
  103. #define I365_CTL_GPI_ENA 0x04
  104. #define I365_CTL_GPI_CTL 0x08
  105. #define I365_CTL_RESUME 0x10
  106. #define I365_CTL_SW_IRQ 0x20
  107. /* Flags for I365_GBLCTL */
  108. #define I365_GBL_PWRDOWN 0x01
  109. #define I365_GBL_CSC_LEV 0x02
  110. #define I365_GBL_WRBACK 0x04
  111. #define I365_GBL_IRQ_0_LEV 0x08
  112. #define I365_GBL_IRQ_1_LEV 0x10
  113. /* Flags for memory window registers */
  114. #define I365_MEM_16BIT 0x8000 /* In memory start high byte */
  115. #define I365_MEM_0WS 0x4000
  116. #define I365_MEM_WS1 0x8000 /* In memory stop high byte */
  117. #define I365_MEM_WS0 0x4000
  118. #define I365_MEM_WRPROT 0x8000 /* In offset high byte */
  119. #define I365_MEM_REG 0x4000
  120. #define I365_REG(slot, reg) (((slot) << 6) + reg)
  121. #endif /* _LINUX_I82365_H */