i82092.c 15 KB

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  1. // SPDX-License-Identifier: GPL-2.0-only
  2. /*
  3. * Driver for Intel I82092AA PCI-PCMCIA bridge.
  4. *
  5. * (C) 2001 Red Hat, Inc.
  6. *
  7. * Author: Arjan Van De Ven <arjanv@redhat.com>
  8. * Loosly based on i82365.c from the pcmcia-cs package
  9. */
  10. #include <linux/kernel.h>
  11. #include <linux/module.h>
  12. #include <linux/pci.h>
  13. #include <linux/init.h>
  14. #include <linux/workqueue.h>
  15. #include <linux/interrupt.h>
  16. #include <linux/device.h>
  17. #include <pcmcia/ss.h>
  18. #include <linux/io.h>
  19. #include "i82092aa.h"
  20. #include "i82365.h"
  21. MODULE_LICENSE("GPL");
  22. /* PCI core routines */
  23. static const struct pci_device_id i82092aa_pci_ids[] = {
  24. { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82092AA_0) },
  25. { }
  26. };
  27. MODULE_DEVICE_TABLE(pci, i82092aa_pci_ids);
  28. static struct pci_driver i82092aa_pci_driver = {
  29. .name = "i82092aa",
  30. .id_table = i82092aa_pci_ids,
  31. .probe = i82092aa_pci_probe,
  32. .remove = i82092aa_pci_remove,
  33. };
  34. /* the pccard structure and its functions */
  35. static struct pccard_operations i82092aa_operations = {
  36. .init = i82092aa_init,
  37. .get_status = i82092aa_get_status,
  38. .set_socket = i82092aa_set_socket,
  39. .set_io_map = i82092aa_set_io_map,
  40. .set_mem_map = i82092aa_set_mem_map,
  41. };
  42. /* The card can do up to 4 sockets, allocate a structure for each of them */
  43. struct socket_info {
  44. int number;
  45. int card_state;
  46. /* 0 = no socket,
  47. * 1 = empty socket,
  48. * 2 = card but not initialized,
  49. * 3 = operational card
  50. */
  51. unsigned int io_base; /* base io address of the socket */
  52. struct pcmcia_socket socket;
  53. struct pci_dev *dev; /* The PCI device for the socket */
  54. };
  55. #define MAX_SOCKETS 4
  56. static struct socket_info sockets[MAX_SOCKETS];
  57. static int socket_count; /* shortcut */
  58. static int i82092aa_pci_probe(struct pci_dev *dev,
  59. const struct pci_device_id *id)
  60. {
  61. unsigned char configbyte;
  62. int i, ret;
  63. ret = pci_enable_device(dev);
  64. if (ret)
  65. return ret;
  66. /* PCI Configuration Control */
  67. pci_read_config_byte(dev, 0x40, &configbyte);
  68. switch (configbyte&6) {
  69. case 0:
  70. socket_count = 2;
  71. break;
  72. case 2:
  73. socket_count = 1;
  74. break;
  75. case 4:
  76. case 6:
  77. socket_count = 4;
  78. break;
  79. default:
  80. dev_err(&dev->dev,
  81. "Oops, you did something we didn't think of.\n");
  82. ret = -EIO;
  83. goto err_out_disable;
  84. }
  85. dev_info(&dev->dev, "configured as a %d socket device.\n",
  86. socket_count);
  87. if (!request_region(pci_resource_start(dev, 0), 2, "i82092aa")) {
  88. ret = -EBUSY;
  89. goto err_out_disable;
  90. }
  91. for (i = 0; i < socket_count; i++) {
  92. sockets[i].card_state = 1; /* 1 = present but empty */
  93. sockets[i].io_base = pci_resource_start(dev, 0);
  94. sockets[i].dev = dev;
  95. sockets[i].socket.features |= SS_CAP_PCCARD;
  96. sockets[i].socket.map_size = 0x1000;
  97. sockets[i].socket.irq_mask = 0;
  98. sockets[i].socket.pci_irq = dev->irq;
  99. sockets[i].socket.cb_dev = dev;
  100. sockets[i].socket.owner = THIS_MODULE;
  101. sockets[i].number = i;
  102. if (card_present(i)) {
  103. sockets[i].card_state = 3;
  104. dev_dbg(&dev->dev, "slot %i is occupied\n", i);
  105. } else {
  106. dev_dbg(&dev->dev, "slot %i is vacant\n", i);
  107. }
  108. }
  109. /* Now, specifiy that all interrupts are to be done as PCI interrupts
  110. * bitmask, one bit per event, 1 = PCI interrupt, 0 = ISA interrupt
  111. */
  112. configbyte = 0xFF;
  113. /* PCI Interrupt Routing Register */
  114. pci_write_config_byte(dev, 0x50, configbyte);
  115. /* Register the interrupt handler */
  116. dev_dbg(&dev->dev, "Requesting interrupt %i\n", dev->irq);
  117. ret = request_irq(dev->irq, i82092aa_interrupt, IRQF_SHARED,
  118. "i82092aa", i82092aa_interrupt);
  119. if (ret) {
  120. dev_err(&dev->dev, "Failed to register IRQ %d, aborting\n",
  121. dev->irq);
  122. goto err_out_free_res;
  123. }
  124. for (i = 0; i < socket_count; i++) {
  125. sockets[i].socket.dev.parent = &dev->dev;
  126. sockets[i].socket.ops = &i82092aa_operations;
  127. sockets[i].socket.resource_ops = &pccard_nonstatic_ops;
  128. ret = pcmcia_register_socket(&sockets[i].socket);
  129. if (ret)
  130. goto err_out_free_sockets;
  131. }
  132. return 0;
  133. err_out_free_sockets:
  134. if (i) {
  135. for (i--; i >= 0; i--)
  136. pcmcia_unregister_socket(&sockets[i].socket);
  137. }
  138. free_irq(dev->irq, i82092aa_interrupt);
  139. err_out_free_res:
  140. release_region(pci_resource_start(dev, 0), 2);
  141. err_out_disable:
  142. pci_disable_device(dev);
  143. return ret;
  144. }
  145. static void i82092aa_pci_remove(struct pci_dev *dev)
  146. {
  147. int i;
  148. free_irq(dev->irq, i82092aa_interrupt);
  149. for (i = 0; i < socket_count; i++)
  150. pcmcia_unregister_socket(&sockets[i].socket);
  151. }
  152. static DEFINE_SPINLOCK(port_lock);
  153. /* basic value read/write functions */
  154. static unsigned char indirect_read(int socket, unsigned short reg)
  155. {
  156. unsigned short int port;
  157. unsigned char val;
  158. unsigned long flags;
  159. spin_lock_irqsave(&port_lock, flags);
  160. reg += socket * 0x40;
  161. port = sockets[socket].io_base;
  162. outb(reg, port);
  163. val = inb(port+1);
  164. spin_unlock_irqrestore(&port_lock, flags);
  165. return val;
  166. }
  167. static void indirect_write(int socket, unsigned short reg, unsigned char value)
  168. {
  169. unsigned short int port;
  170. unsigned long flags;
  171. spin_lock_irqsave(&port_lock, flags);
  172. reg = reg + socket * 0x40;
  173. port = sockets[socket].io_base;
  174. outb(reg, port);
  175. outb(value, port+1);
  176. spin_unlock_irqrestore(&port_lock, flags);
  177. }
  178. static void indirect_setbit(int socket, unsigned short reg, unsigned char mask)
  179. {
  180. unsigned short int port;
  181. unsigned char val;
  182. unsigned long flags;
  183. spin_lock_irqsave(&port_lock, flags);
  184. reg = reg + socket * 0x40;
  185. port = sockets[socket].io_base;
  186. outb(reg, port);
  187. val = inb(port+1);
  188. val |= mask;
  189. outb(reg, port);
  190. outb(val, port+1);
  191. spin_unlock_irqrestore(&port_lock, flags);
  192. }
  193. static void indirect_resetbit(int socket,
  194. unsigned short reg, unsigned char mask)
  195. {
  196. unsigned short int port;
  197. unsigned char val;
  198. unsigned long flags;
  199. spin_lock_irqsave(&port_lock, flags);
  200. reg = reg + socket * 0x40;
  201. port = sockets[socket].io_base;
  202. outb(reg, port);
  203. val = inb(port+1);
  204. val &= ~mask;
  205. outb(reg, port);
  206. outb(val, port+1);
  207. spin_unlock_irqrestore(&port_lock, flags);
  208. }
  209. static void indirect_write16(int socket,
  210. unsigned short reg, unsigned short value)
  211. {
  212. unsigned short int port;
  213. unsigned char val;
  214. unsigned long flags;
  215. spin_lock_irqsave(&port_lock, flags);
  216. reg = reg + socket * 0x40;
  217. port = sockets[socket].io_base;
  218. outb(reg, port);
  219. val = value & 255;
  220. outb(val, port+1);
  221. reg++;
  222. outb(reg, port);
  223. val = value>>8;
  224. outb(val, port+1);
  225. spin_unlock_irqrestore(&port_lock, flags);
  226. }
  227. /* simple helper functions */
  228. /* External clock time, in nanoseconds. 120 ns = 8.33 MHz */
  229. static int cycle_time = 120;
  230. static int to_cycles(int ns)
  231. {
  232. if (cycle_time != 0)
  233. return ns/cycle_time;
  234. else
  235. return 0;
  236. }
  237. /* Interrupt handler functionality */
  238. static irqreturn_t i82092aa_interrupt(int irq, void *dev)
  239. {
  240. int i;
  241. int loopcount = 0;
  242. int handled = 0;
  243. unsigned int events, active = 0;
  244. while (1) {
  245. loopcount++;
  246. if (loopcount > 20) {
  247. pr_err("i82092aa: infinite eventloop in interrupt\n");
  248. break;
  249. }
  250. active = 0;
  251. for (i = 0; i < socket_count; i++) {
  252. int csc;
  253. /* Inactive socket, should not happen */
  254. if (sockets[i].card_state == 0)
  255. continue;
  256. /* card status change register */
  257. csc = indirect_read(i, I365_CSC);
  258. if (csc == 0) /* no events on this socket */
  259. continue;
  260. handled = 1;
  261. events = 0;
  262. if (csc & I365_CSC_DETECT) {
  263. events |= SS_DETECT;
  264. dev_info(&sockets[i].dev->dev,
  265. "Card detected in socket %i!\n", i);
  266. }
  267. if (indirect_read(i, I365_INTCTL) & I365_PC_IOCARD) {
  268. /* For IO/CARDS, bit 0 means "read the card" */
  269. if (csc & I365_CSC_STSCHG)
  270. events |= SS_STSCHG;
  271. } else {
  272. /* Check for battery/ready events */
  273. if (csc & I365_CSC_BVD1)
  274. events |= SS_BATDEAD;
  275. if (csc & I365_CSC_BVD2)
  276. events |= SS_BATWARN;
  277. if (csc & I365_CSC_READY)
  278. events |= SS_READY;
  279. }
  280. if (events)
  281. pcmcia_parse_events(&sockets[i].socket, events);
  282. active |= events;
  283. }
  284. if (active == 0) /* no more events to handle */
  285. break;
  286. }
  287. return IRQ_RETVAL(handled);
  288. }
  289. /* socket functions */
  290. static int card_present(int socketno)
  291. {
  292. unsigned int val;
  293. if ((socketno < 0) || (socketno >= MAX_SOCKETS))
  294. return 0;
  295. if (sockets[socketno].io_base == 0)
  296. return 0;
  297. val = indirect_read(socketno, 1); /* Interface status register */
  298. if ((val&12) == 12)
  299. return 1;
  300. return 0;
  301. }
  302. static void set_bridge_state(int sock)
  303. {
  304. indirect_write(sock, I365_GBLCTL, 0x00);
  305. indirect_write(sock, I365_GENCTL, 0x00);
  306. indirect_setbit(sock, I365_INTCTL, 0x08);
  307. }
  308. static int i82092aa_init(struct pcmcia_socket *sock)
  309. {
  310. int i;
  311. struct resource res = { .start = 0, .end = 0x0fff };
  312. pccard_io_map io = { 0, 0, 0, 0, 1 };
  313. pccard_mem_map mem = { .res = &res, };
  314. for (i = 0; i < 2; i++) {
  315. io.map = i;
  316. i82092aa_set_io_map(sock, &io);
  317. }
  318. for (i = 0; i < 5; i++) {
  319. mem.map = i;
  320. i82092aa_set_mem_map(sock, &mem);
  321. }
  322. return 0;
  323. }
  324. static int i82092aa_get_status(struct pcmcia_socket *socket, u_int *value)
  325. {
  326. unsigned int sock = container_of(socket,
  327. struct socket_info, socket)->number;
  328. unsigned int status;
  329. /* Interface Status Register */
  330. status = indirect_read(sock, I365_STATUS);
  331. *value = 0;
  332. if ((status & I365_CS_DETECT) == I365_CS_DETECT)
  333. *value |= SS_DETECT;
  334. /* IO cards have a different meaning of bits 0,1 */
  335. /* Also notice the inverse-logic on the bits */
  336. if (indirect_read(sock, I365_INTCTL) & I365_PC_IOCARD) {
  337. /* IO card */
  338. if (!(status & I365_CS_STSCHG))
  339. *value |= SS_STSCHG;
  340. } else { /* non I/O card */
  341. if (!(status & I365_CS_BVD1))
  342. *value |= SS_BATDEAD;
  343. if (!(status & I365_CS_BVD2))
  344. *value |= SS_BATWARN;
  345. }
  346. if (status & I365_CS_WRPROT)
  347. (*value) |= SS_WRPROT; /* card is write protected */
  348. if (status & I365_CS_READY)
  349. (*value) |= SS_READY; /* card is not busy */
  350. if (status & I365_CS_POWERON)
  351. (*value) |= SS_POWERON; /* power is applied to the card */
  352. return 0;
  353. }
  354. static int i82092aa_set_socket(struct pcmcia_socket *socket,
  355. socket_state_t *state)
  356. {
  357. struct socket_info *sock_info = container_of(socket, struct socket_info,
  358. socket);
  359. unsigned int sock = sock_info->number;
  360. unsigned char reg;
  361. /* First, set the global controller options */
  362. set_bridge_state(sock);
  363. /* Values for the IGENC register */
  364. reg = 0;
  365. /* The reset bit has "inverse" logic */
  366. if (!(state->flags & SS_RESET))
  367. reg = reg | I365_PC_RESET;
  368. if (state->flags & SS_IOCARD)
  369. reg = reg | I365_PC_IOCARD;
  370. /* IGENC, Interrupt and General Control Register */
  371. indirect_write(sock, I365_INTCTL, reg);
  372. /* Power registers */
  373. reg = I365_PWR_NORESET; /* default: disable resetdrv on resume */
  374. if (state->flags & SS_PWR_AUTO) {
  375. dev_info(&sock_info->dev->dev, "Auto power\n");
  376. reg |= I365_PWR_AUTO; /* automatic power mngmnt */
  377. }
  378. if (state->flags & SS_OUTPUT_ENA) {
  379. dev_info(&sock_info->dev->dev, "Power Enabled\n");
  380. reg |= I365_PWR_OUT; /* enable power */
  381. }
  382. switch (state->Vcc) {
  383. case 0:
  384. break;
  385. case 50:
  386. dev_info(&sock_info->dev->dev,
  387. "setting voltage to Vcc to 5V on socket %i\n",
  388. sock);
  389. reg |= I365_VCC_5V;
  390. break;
  391. default:
  392. dev_err(&sock_info->dev->dev,
  393. "%s called with invalid VCC power value: %i",
  394. __func__, state->Vcc);
  395. return -EINVAL;
  396. }
  397. switch (state->Vpp) {
  398. case 0:
  399. dev_info(&sock_info->dev->dev,
  400. "not setting Vpp on socket %i\n", sock);
  401. break;
  402. case 50:
  403. dev_info(&sock_info->dev->dev,
  404. "setting Vpp to 5.0 for socket %i\n", sock);
  405. reg |= I365_VPP1_5V | I365_VPP2_5V;
  406. break;
  407. case 120:
  408. dev_info(&sock_info->dev->dev, "setting Vpp to 12.0\n");
  409. reg |= I365_VPP1_12V | I365_VPP2_12V;
  410. break;
  411. default:
  412. dev_err(&sock_info->dev->dev,
  413. "%s called with invalid VPP power value: %i",
  414. __func__, state->Vcc);
  415. return -EINVAL;
  416. }
  417. if (reg != indirect_read(sock, I365_POWER)) /* only write if changed */
  418. indirect_write(sock, I365_POWER, reg);
  419. /* Enable specific interrupt events */
  420. reg = 0x00;
  421. if (state->csc_mask & SS_DETECT)
  422. reg |= I365_CSC_DETECT;
  423. if (state->flags & SS_IOCARD) {
  424. if (state->csc_mask & SS_STSCHG)
  425. reg |= I365_CSC_STSCHG;
  426. } else {
  427. if (state->csc_mask & SS_BATDEAD)
  428. reg |= I365_CSC_BVD1;
  429. if (state->csc_mask & SS_BATWARN)
  430. reg |= I365_CSC_BVD2;
  431. if (state->csc_mask & SS_READY)
  432. reg |= I365_CSC_READY;
  433. }
  434. /* now write the value and clear the (probably bogus) pending stuff
  435. * by doing a dummy read
  436. */
  437. indirect_write(sock, I365_CSCINT, reg);
  438. (void)indirect_read(sock, I365_CSC);
  439. return 0;
  440. }
  441. static int i82092aa_set_io_map(struct pcmcia_socket *socket,
  442. struct pccard_io_map *io)
  443. {
  444. struct socket_info *sock_info = container_of(socket, struct socket_info,
  445. socket);
  446. unsigned int sock = sock_info->number;
  447. unsigned char map, ioctl;
  448. map = io->map;
  449. /* Check error conditions */
  450. if (map > 1)
  451. return -EINVAL;
  452. if ((io->start > 0xffff) || (io->stop > 0xffff)
  453. || (io->stop < io->start))
  454. return -EINVAL;
  455. /* Turn off the window before changing anything */
  456. if (indirect_read(sock, I365_ADDRWIN) & I365_ENA_IO(map))
  457. indirect_resetbit(sock, I365_ADDRWIN, I365_ENA_IO(map));
  458. /* write the new values */
  459. indirect_write16(sock, I365_IO(map)+I365_W_START, io->start);
  460. indirect_write16(sock, I365_IO(map)+I365_W_STOP, io->stop);
  461. ioctl = indirect_read(sock, I365_IOCTL) & ~I365_IOCTL_MASK(map);
  462. if (io->flags & (MAP_16BIT|MAP_AUTOSZ))
  463. ioctl |= I365_IOCTL_16BIT(map);
  464. indirect_write(sock, I365_IOCTL, ioctl);
  465. /* Turn the window back on if needed */
  466. if (io->flags & MAP_ACTIVE)
  467. indirect_setbit(sock, I365_ADDRWIN, I365_ENA_IO(map));
  468. return 0;
  469. }
  470. static int i82092aa_set_mem_map(struct pcmcia_socket *socket,
  471. struct pccard_mem_map *mem)
  472. {
  473. struct socket_info *sock_info = container_of(socket, struct socket_info,
  474. socket);
  475. unsigned int sock = sock_info->number;
  476. struct pci_bus_region region;
  477. unsigned short base, i;
  478. unsigned char map;
  479. pcibios_resource_to_bus(sock_info->dev->bus, &region, mem->res);
  480. map = mem->map;
  481. if (map > 4)
  482. return -EINVAL;
  483. if ((mem->card_start > 0x3ffffff) || (region.start > region.end) ||
  484. (mem->speed > 1000)) {
  485. dev_err(&sock_info->dev->dev,
  486. "invalid mem map for socket %i: %llx to %llx with a start of %x\n",
  487. sock,
  488. (unsigned long long)region.start,
  489. (unsigned long long)region.end,
  490. mem->card_start);
  491. return -EINVAL;
  492. }
  493. /* Turn off the window before changing anything */
  494. if (indirect_read(sock, I365_ADDRWIN) & I365_ENA_MEM(map))
  495. indirect_resetbit(sock, I365_ADDRWIN, I365_ENA_MEM(map));
  496. /* write the start address */
  497. base = I365_MEM(map);
  498. i = (region.start >> 12) & 0x0fff;
  499. if (mem->flags & MAP_16BIT)
  500. i |= I365_MEM_16BIT;
  501. if (mem->flags & MAP_0WS)
  502. i |= I365_MEM_0WS;
  503. indirect_write16(sock, base+I365_W_START, i);
  504. /* write the stop address */
  505. i = (region.end >> 12) & 0x0fff;
  506. switch (to_cycles(mem->speed)) {
  507. case 0:
  508. break;
  509. case 1:
  510. i |= I365_MEM_WS0;
  511. break;
  512. case 2:
  513. i |= I365_MEM_WS1;
  514. break;
  515. default:
  516. i |= I365_MEM_WS1 | I365_MEM_WS0;
  517. break;
  518. }
  519. indirect_write16(sock, base+I365_W_STOP, i);
  520. /* card start */
  521. i = ((mem->card_start - region.start) >> 12) & 0x3fff;
  522. if (mem->flags & MAP_WRPROT)
  523. i |= I365_MEM_WRPROT;
  524. if (mem->flags & MAP_ATTRIB)
  525. i |= I365_MEM_REG;
  526. indirect_write16(sock, base+I365_W_OFF, i);
  527. /* Enable the window if necessary */
  528. if (mem->flags & MAP_ACTIVE)
  529. indirect_setbit(sock, I365_ADDRWIN, I365_ENA_MEM(map));
  530. return 0;
  531. }
  532. static int i82092aa_module_init(void)
  533. {
  534. return pci_register_driver(&i82092aa_pci_driver);
  535. }
  536. static void i82092aa_module_exit(void)
  537. {
  538. pci_unregister_driver(&i82092aa_pci_driver);
  539. if (sockets[0].io_base > 0)
  540. release_region(sockets[0].io_base, 2);
  541. }
  542. module_init(i82092aa_module_init);
  543. module_exit(i82092aa_module_exit);