vpd.c 16 KB

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  1. // SPDX-License-Identifier: GPL-2.0
  2. /*
  3. * PCI VPD support
  4. *
  5. * Copyright (C) 2010 Broadcom Corporation.
  6. */
  7. #include <linux/pci.h>
  8. #include <linux/delay.h>
  9. #include <linux/export.h>
  10. #include <linux/sched/signal.h>
  11. #include "pci.h"
  12. /* VPD access through PCI 2.2+ VPD capability */
  13. struct pci_vpd_ops {
  14. ssize_t (*read)(struct pci_dev *dev, loff_t pos, size_t count, void *buf);
  15. ssize_t (*write)(struct pci_dev *dev, loff_t pos, size_t count, const void *buf);
  16. int (*set_size)(struct pci_dev *dev, size_t len);
  17. };
  18. struct pci_vpd {
  19. const struct pci_vpd_ops *ops;
  20. struct bin_attribute *attr; /* Descriptor for sysfs VPD entry */
  21. struct mutex lock;
  22. unsigned int len;
  23. u16 flag;
  24. u8 cap;
  25. unsigned int busy:1;
  26. unsigned int valid:1;
  27. };
  28. /**
  29. * pci_read_vpd - Read one entry from Vital Product Data
  30. * @dev: pci device struct
  31. * @pos: offset in vpd space
  32. * @count: number of bytes to read
  33. * @buf: pointer to where to store result
  34. */
  35. ssize_t pci_read_vpd(struct pci_dev *dev, loff_t pos, size_t count, void *buf)
  36. {
  37. if (!dev->vpd || !dev->vpd->ops)
  38. return -ENODEV;
  39. return dev->vpd->ops->read(dev, pos, count, buf);
  40. }
  41. EXPORT_SYMBOL(pci_read_vpd);
  42. /**
  43. * pci_write_vpd - Write entry to Vital Product Data
  44. * @dev: pci device struct
  45. * @pos: offset in vpd space
  46. * @count: number of bytes to write
  47. * @buf: buffer containing write data
  48. */
  49. ssize_t pci_write_vpd(struct pci_dev *dev, loff_t pos, size_t count, const void *buf)
  50. {
  51. if (!dev->vpd || !dev->vpd->ops)
  52. return -ENODEV;
  53. return dev->vpd->ops->write(dev, pos, count, buf);
  54. }
  55. EXPORT_SYMBOL(pci_write_vpd);
  56. /**
  57. * pci_set_vpd_size - Set size of Vital Product Data space
  58. * @dev: pci device struct
  59. * @len: size of vpd space
  60. */
  61. int pci_set_vpd_size(struct pci_dev *dev, size_t len)
  62. {
  63. if (!dev->vpd || !dev->vpd->ops)
  64. return -ENODEV;
  65. return dev->vpd->ops->set_size(dev, len);
  66. }
  67. EXPORT_SYMBOL(pci_set_vpd_size);
  68. #define PCI_VPD_MAX_SIZE (PCI_VPD_ADDR_MASK + 1)
  69. /**
  70. * pci_vpd_size - determine actual size of Vital Product Data
  71. * @dev: pci device struct
  72. * @old_size: current assumed size, also maximum allowed size
  73. */
  74. static size_t pci_vpd_size(struct pci_dev *dev, size_t old_size)
  75. {
  76. size_t off = 0;
  77. unsigned char header[1+2]; /* 1 byte tag, 2 bytes length */
  78. while (off < old_size &&
  79. pci_read_vpd(dev, off, 1, header) == 1) {
  80. unsigned char tag;
  81. if (header[0] & PCI_VPD_LRDT) {
  82. /* Large Resource Data Type Tag */
  83. tag = pci_vpd_lrdt_tag(header);
  84. /* Only read length from known tag items */
  85. if ((tag == PCI_VPD_LTIN_ID_STRING) ||
  86. (tag == PCI_VPD_LTIN_RO_DATA) ||
  87. (tag == PCI_VPD_LTIN_RW_DATA)) {
  88. if (pci_read_vpd(dev, off+1, 2,
  89. &header[1]) != 2) {
  90. pci_warn(dev, "invalid large VPD tag %02x size at offset %zu",
  91. tag, off + 1);
  92. return 0;
  93. }
  94. off += PCI_VPD_LRDT_TAG_SIZE +
  95. pci_vpd_lrdt_size(header);
  96. }
  97. } else {
  98. /* Short Resource Data Type Tag */
  99. off += PCI_VPD_SRDT_TAG_SIZE +
  100. pci_vpd_srdt_size(header);
  101. tag = pci_vpd_srdt_tag(header);
  102. }
  103. if (tag == PCI_VPD_STIN_END) /* End tag descriptor */
  104. return off;
  105. if ((tag != PCI_VPD_LTIN_ID_STRING) &&
  106. (tag != PCI_VPD_LTIN_RO_DATA) &&
  107. (tag != PCI_VPD_LTIN_RW_DATA)) {
  108. pci_warn(dev, "invalid %s VPD tag %02x at offset %zu",
  109. (header[0] & PCI_VPD_LRDT) ? "large" : "short",
  110. tag, off);
  111. return 0;
  112. }
  113. }
  114. return 0;
  115. }
  116. /*
  117. * Wait for last operation to complete.
  118. * This code has to spin since there is no other notification from the PCI
  119. * hardware. Since the VPD is often implemented by serial attachment to an
  120. * EEPROM, it may take many milliseconds to complete.
  121. *
  122. * Returns 0 on success, negative values indicate error.
  123. */
  124. static int pci_vpd_wait(struct pci_dev *dev)
  125. {
  126. struct pci_vpd *vpd = dev->vpd;
  127. unsigned long timeout = jiffies + msecs_to_jiffies(125);
  128. unsigned long max_sleep = 16;
  129. u16 status;
  130. int ret;
  131. if (!vpd->busy)
  132. return 0;
  133. do {
  134. ret = pci_user_read_config_word(dev, vpd->cap + PCI_VPD_ADDR,
  135. &status);
  136. if (ret < 0)
  137. return ret;
  138. if ((status & PCI_VPD_ADDR_F) == vpd->flag) {
  139. vpd->busy = 0;
  140. return 0;
  141. }
  142. if (fatal_signal_pending(current))
  143. return -EINTR;
  144. if (time_after(jiffies, timeout))
  145. break;
  146. usleep_range(10, max_sleep);
  147. if (max_sleep < 1024)
  148. max_sleep *= 2;
  149. } while (true);
  150. pci_warn(dev, "VPD access failed. This is likely a firmware bug on this device. Contact the card vendor for a firmware update\n");
  151. return -ETIMEDOUT;
  152. }
  153. static ssize_t pci_vpd_read(struct pci_dev *dev, loff_t pos, size_t count,
  154. void *arg)
  155. {
  156. struct pci_vpd *vpd = dev->vpd;
  157. int ret;
  158. loff_t end = pos + count;
  159. u8 *buf = arg;
  160. if (pos < 0)
  161. return -EINVAL;
  162. if (!vpd->valid) {
  163. vpd->valid = 1;
  164. vpd->len = pci_vpd_size(dev, vpd->len);
  165. }
  166. if (vpd->len == 0)
  167. return -EIO;
  168. if (pos > vpd->len)
  169. return 0;
  170. if (end > vpd->len) {
  171. end = vpd->len;
  172. count = end - pos;
  173. }
  174. if (mutex_lock_killable(&vpd->lock))
  175. return -EINTR;
  176. ret = pci_vpd_wait(dev);
  177. if (ret < 0)
  178. goto out;
  179. while (pos < end) {
  180. u32 val;
  181. unsigned int i, skip;
  182. ret = pci_user_write_config_word(dev, vpd->cap + PCI_VPD_ADDR,
  183. pos & ~3);
  184. if (ret < 0)
  185. break;
  186. vpd->busy = 1;
  187. vpd->flag = PCI_VPD_ADDR_F;
  188. ret = pci_vpd_wait(dev);
  189. if (ret < 0)
  190. break;
  191. ret = pci_user_read_config_dword(dev, vpd->cap + PCI_VPD_DATA, &val);
  192. if (ret < 0)
  193. break;
  194. skip = pos & 3;
  195. for (i = 0; i < sizeof(u32); i++) {
  196. if (i >= skip) {
  197. *buf++ = val;
  198. if (++pos == end)
  199. break;
  200. }
  201. val >>= 8;
  202. }
  203. }
  204. out:
  205. mutex_unlock(&vpd->lock);
  206. return ret ? ret : count;
  207. }
  208. static ssize_t pci_vpd_write(struct pci_dev *dev, loff_t pos, size_t count,
  209. const void *arg)
  210. {
  211. struct pci_vpd *vpd = dev->vpd;
  212. const u8 *buf = arg;
  213. loff_t end = pos + count;
  214. int ret = 0;
  215. if (pos < 0 || (pos & 3) || (count & 3))
  216. return -EINVAL;
  217. if (!vpd->valid) {
  218. vpd->valid = 1;
  219. vpd->len = pci_vpd_size(dev, vpd->len);
  220. }
  221. if (vpd->len == 0)
  222. return -EIO;
  223. if (end > vpd->len)
  224. return -EINVAL;
  225. if (mutex_lock_killable(&vpd->lock))
  226. return -EINTR;
  227. ret = pci_vpd_wait(dev);
  228. if (ret < 0)
  229. goto out;
  230. while (pos < end) {
  231. u32 val;
  232. val = *buf++;
  233. val |= *buf++ << 8;
  234. val |= *buf++ << 16;
  235. val |= *buf++ << 24;
  236. ret = pci_user_write_config_dword(dev, vpd->cap + PCI_VPD_DATA, val);
  237. if (ret < 0)
  238. break;
  239. ret = pci_user_write_config_word(dev, vpd->cap + PCI_VPD_ADDR,
  240. pos | PCI_VPD_ADDR_F);
  241. if (ret < 0)
  242. break;
  243. vpd->busy = 1;
  244. vpd->flag = 0;
  245. ret = pci_vpd_wait(dev);
  246. if (ret < 0)
  247. break;
  248. pos += sizeof(u32);
  249. }
  250. out:
  251. mutex_unlock(&vpd->lock);
  252. return ret ? ret : count;
  253. }
  254. static int pci_vpd_set_size(struct pci_dev *dev, size_t len)
  255. {
  256. struct pci_vpd *vpd = dev->vpd;
  257. if (len == 0 || len > PCI_VPD_MAX_SIZE)
  258. return -EIO;
  259. vpd->valid = 1;
  260. vpd->len = len;
  261. return 0;
  262. }
  263. static const struct pci_vpd_ops pci_vpd_ops = {
  264. .read = pci_vpd_read,
  265. .write = pci_vpd_write,
  266. .set_size = pci_vpd_set_size,
  267. };
  268. static ssize_t pci_vpd_f0_read(struct pci_dev *dev, loff_t pos, size_t count,
  269. void *arg)
  270. {
  271. struct pci_dev *tdev = pci_get_slot(dev->bus,
  272. PCI_DEVFN(PCI_SLOT(dev->devfn), 0));
  273. ssize_t ret;
  274. if (!tdev)
  275. return -ENODEV;
  276. ret = pci_read_vpd(tdev, pos, count, arg);
  277. pci_dev_put(tdev);
  278. return ret;
  279. }
  280. static ssize_t pci_vpd_f0_write(struct pci_dev *dev, loff_t pos, size_t count,
  281. const void *arg)
  282. {
  283. struct pci_dev *tdev = pci_get_slot(dev->bus,
  284. PCI_DEVFN(PCI_SLOT(dev->devfn), 0));
  285. ssize_t ret;
  286. if (!tdev)
  287. return -ENODEV;
  288. ret = pci_write_vpd(tdev, pos, count, arg);
  289. pci_dev_put(tdev);
  290. return ret;
  291. }
  292. static int pci_vpd_f0_set_size(struct pci_dev *dev, size_t len)
  293. {
  294. struct pci_dev *tdev = pci_get_slot(dev->bus,
  295. PCI_DEVFN(PCI_SLOT(dev->devfn), 0));
  296. int ret;
  297. if (!tdev)
  298. return -ENODEV;
  299. ret = pci_set_vpd_size(tdev, len);
  300. pci_dev_put(tdev);
  301. return ret;
  302. }
  303. static const struct pci_vpd_ops pci_vpd_f0_ops = {
  304. .read = pci_vpd_f0_read,
  305. .write = pci_vpd_f0_write,
  306. .set_size = pci_vpd_f0_set_size,
  307. };
  308. int pci_vpd_init(struct pci_dev *dev)
  309. {
  310. struct pci_vpd *vpd;
  311. u8 cap;
  312. cap = pci_find_capability(dev, PCI_CAP_ID_VPD);
  313. if (!cap)
  314. return -ENODEV;
  315. vpd = kzalloc(sizeof(*vpd), GFP_ATOMIC);
  316. if (!vpd)
  317. return -ENOMEM;
  318. vpd->len = PCI_VPD_MAX_SIZE;
  319. if (dev->dev_flags & PCI_DEV_FLAGS_VPD_REF_F0)
  320. vpd->ops = &pci_vpd_f0_ops;
  321. else
  322. vpd->ops = &pci_vpd_ops;
  323. mutex_init(&vpd->lock);
  324. vpd->cap = cap;
  325. vpd->busy = 0;
  326. vpd->valid = 0;
  327. dev->vpd = vpd;
  328. return 0;
  329. }
  330. void pci_vpd_release(struct pci_dev *dev)
  331. {
  332. kfree(dev->vpd);
  333. }
  334. static ssize_t read_vpd_attr(struct file *filp, struct kobject *kobj,
  335. struct bin_attribute *bin_attr, char *buf,
  336. loff_t off, size_t count)
  337. {
  338. struct pci_dev *dev = to_pci_dev(kobj_to_dev(kobj));
  339. if (bin_attr->size > 0) {
  340. if (off > bin_attr->size)
  341. count = 0;
  342. else if (count > bin_attr->size - off)
  343. count = bin_attr->size - off;
  344. }
  345. return pci_read_vpd(dev, off, count, buf);
  346. }
  347. static ssize_t write_vpd_attr(struct file *filp, struct kobject *kobj,
  348. struct bin_attribute *bin_attr, char *buf,
  349. loff_t off, size_t count)
  350. {
  351. struct pci_dev *dev = to_pci_dev(kobj_to_dev(kobj));
  352. if (bin_attr->size > 0) {
  353. if (off > bin_attr->size)
  354. count = 0;
  355. else if (count > bin_attr->size - off)
  356. count = bin_attr->size - off;
  357. }
  358. return pci_write_vpd(dev, off, count, buf);
  359. }
  360. void pcie_vpd_create_sysfs_dev_files(struct pci_dev *dev)
  361. {
  362. int retval;
  363. struct bin_attribute *attr;
  364. if (!dev->vpd)
  365. return;
  366. attr = kzalloc(sizeof(*attr), GFP_ATOMIC);
  367. if (!attr)
  368. return;
  369. sysfs_bin_attr_init(attr);
  370. attr->size = 0;
  371. attr->attr.name = "vpd";
  372. attr->attr.mode = S_IRUSR | S_IWUSR;
  373. attr->read = read_vpd_attr;
  374. attr->write = write_vpd_attr;
  375. retval = sysfs_create_bin_file(&dev->dev.kobj, attr);
  376. if (retval) {
  377. kfree(attr);
  378. return;
  379. }
  380. dev->vpd->attr = attr;
  381. }
  382. void pcie_vpd_remove_sysfs_dev_files(struct pci_dev *dev)
  383. {
  384. if (dev->vpd && dev->vpd->attr) {
  385. sysfs_remove_bin_file(&dev->dev.kobj, dev->vpd->attr);
  386. kfree(dev->vpd->attr);
  387. }
  388. }
  389. int pci_vpd_find_tag(const u8 *buf, unsigned int off, unsigned int len, u8 rdt)
  390. {
  391. int i;
  392. for (i = off; i < len; ) {
  393. u8 val = buf[i];
  394. if (val & PCI_VPD_LRDT) {
  395. /* Don't return success of the tag isn't complete */
  396. if (i + PCI_VPD_LRDT_TAG_SIZE > len)
  397. break;
  398. if (val == rdt)
  399. return i;
  400. i += PCI_VPD_LRDT_TAG_SIZE +
  401. pci_vpd_lrdt_size(&buf[i]);
  402. } else {
  403. u8 tag = val & ~PCI_VPD_SRDT_LEN_MASK;
  404. if (tag == rdt)
  405. return i;
  406. if (tag == PCI_VPD_SRDT_END)
  407. break;
  408. i += PCI_VPD_SRDT_TAG_SIZE +
  409. pci_vpd_srdt_size(&buf[i]);
  410. }
  411. }
  412. return -ENOENT;
  413. }
  414. EXPORT_SYMBOL_GPL(pci_vpd_find_tag);
  415. int pci_vpd_find_info_keyword(const u8 *buf, unsigned int off,
  416. unsigned int len, const char *kw)
  417. {
  418. int i;
  419. for (i = off; i + PCI_VPD_INFO_FLD_HDR_SIZE <= off + len;) {
  420. if (buf[i + 0] == kw[0] &&
  421. buf[i + 1] == kw[1])
  422. return i;
  423. i += PCI_VPD_INFO_FLD_HDR_SIZE +
  424. pci_vpd_info_field_size(&buf[i]);
  425. }
  426. return -ENOENT;
  427. }
  428. EXPORT_SYMBOL_GPL(pci_vpd_find_info_keyword);
  429. #ifdef CONFIG_PCI_QUIRKS
  430. /*
  431. * Quirk non-zero PCI functions to route VPD access through function 0 for
  432. * devices that share VPD resources between functions. The functions are
  433. * expected to be identical devices.
  434. */
  435. static void quirk_f0_vpd_link(struct pci_dev *dev)
  436. {
  437. struct pci_dev *f0;
  438. if (!PCI_FUNC(dev->devfn))
  439. return;
  440. f0 = pci_get_slot(dev->bus, PCI_DEVFN(PCI_SLOT(dev->devfn), 0));
  441. if (!f0)
  442. return;
  443. if (f0->vpd && dev->class == f0->class &&
  444. dev->vendor == f0->vendor && dev->device == f0->device)
  445. dev->dev_flags |= PCI_DEV_FLAGS_VPD_REF_F0;
  446. pci_dev_put(f0);
  447. }
  448. DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_INTEL, PCI_ANY_ID,
  449. PCI_CLASS_NETWORK_ETHERNET, 8, quirk_f0_vpd_link);
  450. /*
  451. * If a device follows the VPD format spec, the PCI core will not read or
  452. * write past the VPD End Tag. But some vendors do not follow the VPD
  453. * format spec, so we can't tell how much data is safe to access. Devices
  454. * may behave unpredictably if we access too much. Blacklist these devices
  455. * so we don't touch VPD at all.
  456. */
  457. static void quirk_blacklist_vpd(struct pci_dev *dev)
  458. {
  459. if (dev->vpd) {
  460. dev->vpd->len = 0;
  461. pci_warn(dev, FW_BUG "disabling VPD access (can't determine size of non-standard VPD format)\n");
  462. }
  463. }
  464. DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_LSI_LOGIC, 0x0060, quirk_blacklist_vpd);
  465. DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_LSI_LOGIC, 0x007c, quirk_blacklist_vpd);
  466. DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_LSI_LOGIC, 0x0413, quirk_blacklist_vpd);
  467. DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_LSI_LOGIC, 0x0078, quirk_blacklist_vpd);
  468. DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_LSI_LOGIC, 0x0079, quirk_blacklist_vpd);
  469. DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_LSI_LOGIC, 0x0073, quirk_blacklist_vpd);
  470. DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_LSI_LOGIC, 0x0071, quirk_blacklist_vpd);
  471. DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_LSI_LOGIC, 0x005b, quirk_blacklist_vpd);
  472. DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_LSI_LOGIC, 0x002f, quirk_blacklist_vpd);
  473. DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_LSI_LOGIC, 0x005d, quirk_blacklist_vpd);
  474. DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_LSI_LOGIC, 0x005f, quirk_blacklist_vpd);
  475. DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATTANSIC, PCI_ANY_ID,
  476. quirk_blacklist_vpd);
  477. /*
  478. * The Amazon Annapurna Labs 0x0031 device id is reused for other non Root Port
  479. * device types, so the quirk is registered for the PCI_CLASS_BRIDGE_PCI class.
  480. */
  481. DECLARE_PCI_FIXUP_CLASS_FINAL(PCI_VENDOR_ID_AMAZON_ANNAPURNA_LABS, 0x0031,
  482. PCI_CLASS_BRIDGE_PCI, 8, quirk_blacklist_vpd);
  483. /*
  484. * For Broadcom 5706, 5708, 5709 rev. A nics, any read beyond the
  485. * VPD end tag will hang the device. This problem was initially
  486. * observed when a vpd entry was created in sysfs
  487. * ('/sys/bus/pci/devices/<id>/vpd'). A read to this sysfs entry
  488. * will dump 32k of data. Reading a full 32k will cause an access
  489. * beyond the VPD end tag causing the device to hang. Once the device
  490. * is hung, the bnx2 driver will not be able to reset the device.
  491. * We believe that it is legal to read beyond the end tag and
  492. * therefore the solution is to limit the read/write length.
  493. */
  494. static void quirk_brcm_570x_limit_vpd(struct pci_dev *dev)
  495. {
  496. /*
  497. * Only disable the VPD capability for 5706, 5706S, 5708,
  498. * 5708S and 5709 rev. A
  499. */
  500. if ((dev->device == PCI_DEVICE_ID_NX2_5706) ||
  501. (dev->device == PCI_DEVICE_ID_NX2_5706S) ||
  502. (dev->device == PCI_DEVICE_ID_NX2_5708) ||
  503. (dev->device == PCI_DEVICE_ID_NX2_5708S) ||
  504. ((dev->device == PCI_DEVICE_ID_NX2_5709) &&
  505. (dev->revision & 0xf0) == 0x0)) {
  506. if (dev->vpd)
  507. dev->vpd->len = 0x80;
  508. }
  509. }
  510. DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_BROADCOM,
  511. PCI_DEVICE_ID_NX2_5706,
  512. quirk_brcm_570x_limit_vpd);
  513. DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_BROADCOM,
  514. PCI_DEVICE_ID_NX2_5706S,
  515. quirk_brcm_570x_limit_vpd);
  516. DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_BROADCOM,
  517. PCI_DEVICE_ID_NX2_5708,
  518. quirk_brcm_570x_limit_vpd);
  519. DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_BROADCOM,
  520. PCI_DEVICE_ID_NX2_5708S,
  521. quirk_brcm_570x_limit_vpd);
  522. DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_BROADCOM,
  523. PCI_DEVICE_ID_NX2_5709,
  524. quirk_brcm_570x_limit_vpd);
  525. DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_BROADCOM,
  526. PCI_DEVICE_ID_NX2_5709S,
  527. quirk_brcm_570x_limit_vpd);
  528. static void quirk_chelsio_extend_vpd(struct pci_dev *dev)
  529. {
  530. int chip = (dev->device & 0xf000) >> 12;
  531. int func = (dev->device & 0x0f00) >> 8;
  532. int prod = (dev->device & 0x00ff) >> 0;
  533. /*
  534. * If this is a T3-based adapter, there's a 1KB VPD area at offset
  535. * 0xc00 which contains the preferred VPD values. If this is a T4 or
  536. * later based adapter, the special VPD is at offset 0x400 for the
  537. * Physical Functions (the SR-IOV Virtual Functions have no VPD
  538. * Capabilities). The PCI VPD Access core routines will normally
  539. * compute the size of the VPD by parsing the VPD Data Structure at
  540. * offset 0x000. This will result in silent failures when attempting
  541. * to accesses these other VPD areas which are beyond those computed
  542. * limits.
  543. */
  544. if (chip == 0x0 && prod >= 0x20)
  545. pci_set_vpd_size(dev, 8192);
  546. else if (chip >= 0x4 && func < 0x8)
  547. pci_set_vpd_size(dev, 2048);
  548. }
  549. DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_CHELSIO, PCI_ANY_ID,
  550. quirk_chelsio_extend_vpd);
  551. #endif