setup-res.c 13 KB

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  1. // SPDX-License-Identifier: GPL-2.0
  2. /*
  3. * Support routines for initializing a PCI subsystem
  4. *
  5. * Extruded from code written by
  6. * Dave Rusling (david.rusling@reo.mts.dec.com)
  7. * David Mosberger (davidm@cs.arizona.edu)
  8. * David Miller (davem@redhat.com)
  9. *
  10. * Fixed for multiple PCI buses, 1999 Andrea Arcangeli <andrea@suse.de>
  11. *
  12. * Nov 2000, Ivan Kokshaysky <ink@jurassic.park.msu.ru>
  13. * Resource sorting
  14. */
  15. #include <linux/kernel.h>
  16. #include <linux/export.h>
  17. #include <linux/pci.h>
  18. #include <linux/errno.h>
  19. #include <linux/ioport.h>
  20. #include <linux/cache.h>
  21. #include <linux/slab.h>
  22. #include "pci.h"
  23. static void pci_std_update_resource(struct pci_dev *dev, int resno)
  24. {
  25. struct pci_bus_region region;
  26. bool disable;
  27. u16 cmd;
  28. u32 new, check, mask;
  29. int reg;
  30. struct resource *res = dev->resource + resno;
  31. /* Per SR-IOV spec 3.4.1.11, VF BARs are RO zero */
  32. if (dev->is_virtfn)
  33. return;
  34. /*
  35. * Ignore resources for unimplemented BARs and unused resource slots
  36. * for 64 bit BARs.
  37. */
  38. if (!res->flags)
  39. return;
  40. if (res->flags & IORESOURCE_UNSET)
  41. return;
  42. /*
  43. * Ignore non-moveable resources. This might be legacy resources for
  44. * which no functional BAR register exists or another important
  45. * system resource we shouldn't move around.
  46. */
  47. if (res->flags & IORESOURCE_PCI_FIXED)
  48. return;
  49. pcibios_resource_to_bus(dev->bus, &region, res);
  50. new = region.start;
  51. if (res->flags & IORESOURCE_IO) {
  52. mask = (u32)PCI_BASE_ADDRESS_IO_MASK;
  53. new |= res->flags & ~PCI_BASE_ADDRESS_IO_MASK;
  54. } else if (resno == PCI_ROM_RESOURCE) {
  55. mask = PCI_ROM_ADDRESS_MASK;
  56. } else {
  57. mask = (u32)PCI_BASE_ADDRESS_MEM_MASK;
  58. new |= res->flags & ~PCI_BASE_ADDRESS_MEM_MASK;
  59. }
  60. if (resno < PCI_ROM_RESOURCE) {
  61. reg = PCI_BASE_ADDRESS_0 + 4 * resno;
  62. } else if (resno == PCI_ROM_RESOURCE) {
  63. /*
  64. * Apparently some Matrox devices have ROM BARs that read
  65. * as zero when disabled, so don't update ROM BARs unless
  66. * they're enabled. See
  67. * https://lore.kernel.org/r/43147B3D.1030309@vc.cvut.cz/
  68. */
  69. if (!(res->flags & IORESOURCE_ROM_ENABLE))
  70. return;
  71. reg = dev->rom_base_reg;
  72. new |= PCI_ROM_ADDRESS_ENABLE;
  73. } else
  74. return;
  75. /*
  76. * We can't update a 64-bit BAR atomically, so when possible,
  77. * disable decoding so that a half-updated BAR won't conflict
  78. * with another device.
  79. */
  80. disable = (res->flags & IORESOURCE_MEM_64) && !dev->mmio_always_on;
  81. if (disable) {
  82. pci_read_config_word(dev, PCI_COMMAND, &cmd);
  83. pci_write_config_word(dev, PCI_COMMAND,
  84. cmd & ~PCI_COMMAND_MEMORY);
  85. }
  86. pci_write_config_dword(dev, reg, new);
  87. pci_read_config_dword(dev, reg, &check);
  88. if ((new ^ check) & mask) {
  89. pci_err(dev, "BAR %d: error updating (%#08x != %#08x)\n",
  90. resno, new, check);
  91. }
  92. if (res->flags & IORESOURCE_MEM_64) {
  93. new = region.start >> 16 >> 16;
  94. pci_write_config_dword(dev, reg + 4, new);
  95. pci_read_config_dword(dev, reg + 4, &check);
  96. if (check != new) {
  97. pci_err(dev, "BAR %d: error updating (high %#08x != %#08x)\n",
  98. resno, new, check);
  99. }
  100. }
  101. if (disable)
  102. pci_write_config_word(dev, PCI_COMMAND, cmd);
  103. }
  104. void pci_update_resource(struct pci_dev *dev, int resno)
  105. {
  106. if (resno <= PCI_ROM_RESOURCE)
  107. pci_std_update_resource(dev, resno);
  108. #ifdef CONFIG_PCI_IOV
  109. else if (resno >= PCI_IOV_RESOURCES && resno <= PCI_IOV_RESOURCE_END)
  110. pci_iov_update_resource(dev, resno);
  111. #endif
  112. }
  113. int pci_claim_resource(struct pci_dev *dev, int resource)
  114. {
  115. struct resource *res = &dev->resource[resource];
  116. struct resource *root, *conflict;
  117. if (res->flags & IORESOURCE_UNSET) {
  118. pci_info(dev, "can't claim BAR %d %pR: no address assigned\n",
  119. resource, res);
  120. return -EINVAL;
  121. }
  122. /*
  123. * If we have a shadow copy in RAM, the PCI device doesn't respond
  124. * to the shadow range, so we don't need to claim it, and upstream
  125. * bridges don't need to route the range to the device.
  126. */
  127. if (res->flags & IORESOURCE_ROM_SHADOW)
  128. return 0;
  129. root = pci_find_parent_resource(dev, res);
  130. if (!root) {
  131. pci_info(dev, "can't claim BAR %d %pR: no compatible bridge window\n",
  132. resource, res);
  133. res->flags |= IORESOURCE_UNSET;
  134. return -EINVAL;
  135. }
  136. conflict = request_resource_conflict(root, res);
  137. if (conflict) {
  138. pci_info(dev, "can't claim BAR %d %pR: address conflict with %s %pR\n",
  139. resource, res, conflict->name, conflict);
  140. res->flags |= IORESOURCE_UNSET;
  141. return -EBUSY;
  142. }
  143. return 0;
  144. }
  145. EXPORT_SYMBOL(pci_claim_resource);
  146. void pci_disable_bridge_window(struct pci_dev *dev)
  147. {
  148. /* MMIO Base/Limit */
  149. pci_write_config_dword(dev, PCI_MEMORY_BASE, 0x0000fff0);
  150. /* Prefetchable MMIO Base/Limit */
  151. pci_write_config_dword(dev, PCI_PREF_LIMIT_UPPER32, 0);
  152. pci_write_config_dword(dev, PCI_PREF_MEMORY_BASE, 0x0000fff0);
  153. pci_write_config_dword(dev, PCI_PREF_BASE_UPPER32, 0xffffffff);
  154. }
  155. /*
  156. * Generic function that returns a value indicating that the device's
  157. * original BIOS BAR address was not saved and so is not available for
  158. * reinstatement.
  159. *
  160. * Can be over-ridden by architecture specific code that implements
  161. * reinstatement functionality rather than leaving it disabled when
  162. * normal allocation attempts fail.
  163. */
  164. resource_size_t __weak pcibios_retrieve_fw_addr(struct pci_dev *dev, int idx)
  165. {
  166. return 0;
  167. }
  168. static int pci_revert_fw_address(struct resource *res, struct pci_dev *dev,
  169. int resno, resource_size_t size)
  170. {
  171. struct resource *root, *conflict;
  172. resource_size_t fw_addr, start, end;
  173. fw_addr = pcibios_retrieve_fw_addr(dev, resno);
  174. if (!fw_addr)
  175. return -ENOMEM;
  176. start = res->start;
  177. end = res->end;
  178. res->start = fw_addr;
  179. res->end = res->start + size - 1;
  180. res->flags &= ~IORESOURCE_UNSET;
  181. root = pci_find_parent_resource(dev, res);
  182. if (!root) {
  183. if (res->flags & IORESOURCE_IO)
  184. root = &ioport_resource;
  185. else
  186. root = &iomem_resource;
  187. }
  188. pci_info(dev, "BAR %d: trying firmware assignment %pR\n",
  189. resno, res);
  190. conflict = request_resource_conflict(root, res);
  191. if (conflict) {
  192. pci_info(dev, "BAR %d: %pR conflicts with %s %pR\n",
  193. resno, res, conflict->name, conflict);
  194. res->start = start;
  195. res->end = end;
  196. res->flags |= IORESOURCE_UNSET;
  197. return -EBUSY;
  198. }
  199. return 0;
  200. }
  201. /*
  202. * We don't have to worry about legacy ISA devices, so nothing to do here.
  203. * This is marked as __weak because multiple architectures define it; it should
  204. * eventually go away.
  205. */
  206. resource_size_t __weak pcibios_align_resource(void *data,
  207. const struct resource *res,
  208. resource_size_t size,
  209. resource_size_t align)
  210. {
  211. return res->start;
  212. }
  213. static int __pci_assign_resource(struct pci_bus *bus, struct pci_dev *dev,
  214. int resno, resource_size_t size, resource_size_t align)
  215. {
  216. struct resource *res = dev->resource + resno;
  217. resource_size_t min;
  218. int ret;
  219. min = (res->flags & IORESOURCE_IO) ? PCIBIOS_MIN_IO : PCIBIOS_MIN_MEM;
  220. /*
  221. * First, try exact prefetching match. Even if a 64-bit
  222. * prefetchable bridge window is below 4GB, we can't put a 32-bit
  223. * prefetchable resource in it because pbus_size_mem() assumes a
  224. * 64-bit window will contain no 32-bit resources. If we assign
  225. * things differently than they were sized, not everything will fit.
  226. */
  227. ret = pci_bus_alloc_resource(bus, res, size, align, min,
  228. IORESOURCE_PREFETCH | IORESOURCE_MEM_64,
  229. pcibios_align_resource, dev);
  230. if (ret == 0)
  231. return 0;
  232. /*
  233. * If the prefetchable window is only 32 bits wide, we can put
  234. * 64-bit prefetchable resources in it.
  235. */
  236. if ((res->flags & (IORESOURCE_PREFETCH | IORESOURCE_MEM_64)) ==
  237. (IORESOURCE_PREFETCH | IORESOURCE_MEM_64)) {
  238. ret = pci_bus_alloc_resource(bus, res, size, align, min,
  239. IORESOURCE_PREFETCH,
  240. pcibios_align_resource, dev);
  241. if (ret == 0)
  242. return 0;
  243. }
  244. /*
  245. * If we didn't find a better match, we can put any memory resource
  246. * in a non-prefetchable window. If this resource is 32 bits and
  247. * non-prefetchable, the first call already tried the only possibility
  248. * so we don't need to try again.
  249. */
  250. if (res->flags & (IORESOURCE_PREFETCH | IORESOURCE_MEM_64))
  251. ret = pci_bus_alloc_resource(bus, res, size, align, min, 0,
  252. pcibios_align_resource, dev);
  253. return ret;
  254. }
  255. static int _pci_assign_resource(struct pci_dev *dev, int resno,
  256. resource_size_t size, resource_size_t min_align)
  257. {
  258. struct pci_bus *bus;
  259. int ret;
  260. bus = dev->bus;
  261. while ((ret = __pci_assign_resource(bus, dev, resno, size, min_align))) {
  262. if (!bus->parent || !bus->self->transparent)
  263. break;
  264. bus = bus->parent;
  265. }
  266. return ret;
  267. }
  268. int pci_assign_resource(struct pci_dev *dev, int resno)
  269. {
  270. struct resource *res = dev->resource + resno;
  271. resource_size_t align, size;
  272. int ret;
  273. if (res->flags & IORESOURCE_PCI_FIXED)
  274. return 0;
  275. res->flags |= IORESOURCE_UNSET;
  276. align = pci_resource_alignment(dev, res);
  277. if (!align) {
  278. pci_info(dev, "BAR %d: can't assign %pR (bogus alignment)\n",
  279. resno, res);
  280. return -EINVAL;
  281. }
  282. size = resource_size(res);
  283. ret = _pci_assign_resource(dev, resno, size, align);
  284. /*
  285. * If we failed to assign anything, let's try the address
  286. * where firmware left it. That at least has a chance of
  287. * working, which is better than just leaving it disabled.
  288. */
  289. if (ret < 0) {
  290. pci_info(dev, "BAR %d: no space for %pR\n", resno, res);
  291. ret = pci_revert_fw_address(res, dev, resno, size);
  292. }
  293. if (ret < 0) {
  294. pci_info(dev, "BAR %d: failed to assign %pR\n", resno, res);
  295. return ret;
  296. }
  297. res->flags &= ~IORESOURCE_UNSET;
  298. res->flags &= ~IORESOURCE_STARTALIGN;
  299. pci_info(dev, "BAR %d: assigned %pR\n", resno, res);
  300. if (resno < PCI_BRIDGE_RESOURCES)
  301. pci_update_resource(dev, resno);
  302. return 0;
  303. }
  304. EXPORT_SYMBOL(pci_assign_resource);
  305. int pci_reassign_resource(struct pci_dev *dev, int resno, resource_size_t addsize,
  306. resource_size_t min_align)
  307. {
  308. struct resource *res = dev->resource + resno;
  309. unsigned long flags;
  310. resource_size_t new_size;
  311. int ret;
  312. if (res->flags & IORESOURCE_PCI_FIXED)
  313. return 0;
  314. flags = res->flags;
  315. res->flags |= IORESOURCE_UNSET;
  316. if (!res->parent) {
  317. pci_info(dev, "BAR %d: can't reassign an unassigned resource %pR\n",
  318. resno, res);
  319. return -EINVAL;
  320. }
  321. /* already aligned with min_align */
  322. new_size = resource_size(res) + addsize;
  323. ret = _pci_assign_resource(dev, resno, new_size, min_align);
  324. if (ret) {
  325. res->flags = flags;
  326. pci_info(dev, "BAR %d: %pR (failed to expand by %#llx)\n",
  327. resno, res, (unsigned long long) addsize);
  328. return ret;
  329. }
  330. res->flags &= ~IORESOURCE_UNSET;
  331. res->flags &= ~IORESOURCE_STARTALIGN;
  332. pci_info(dev, "BAR %d: reassigned %pR (expanded by %#llx)\n",
  333. resno, res, (unsigned long long) addsize);
  334. if (resno < PCI_BRIDGE_RESOURCES)
  335. pci_update_resource(dev, resno);
  336. return 0;
  337. }
  338. void pci_release_resource(struct pci_dev *dev, int resno)
  339. {
  340. struct resource *res = dev->resource + resno;
  341. pci_info(dev, "BAR %d: releasing %pR\n", resno, res);
  342. if (!res->parent)
  343. return;
  344. release_resource(res);
  345. res->end = resource_size(res) - 1;
  346. res->start = 0;
  347. res->flags |= IORESOURCE_UNSET;
  348. }
  349. EXPORT_SYMBOL(pci_release_resource);
  350. int pci_resize_resource(struct pci_dev *dev, int resno, int size)
  351. {
  352. struct resource *res = dev->resource + resno;
  353. struct pci_host_bridge *host;
  354. int old, ret;
  355. u32 sizes;
  356. u16 cmd;
  357. /* Check if we must preserve the firmware's resource assignment */
  358. host = pci_find_host_bridge(dev->bus);
  359. if (host->preserve_config)
  360. return -ENOTSUPP;
  361. /* Make sure the resource isn't assigned before resizing it. */
  362. if (!(res->flags & IORESOURCE_UNSET))
  363. return -EBUSY;
  364. pci_read_config_word(dev, PCI_COMMAND, &cmd);
  365. if (cmd & PCI_COMMAND_MEMORY)
  366. return -EBUSY;
  367. sizes = pci_rebar_get_possible_sizes(dev, resno);
  368. if (!sizes)
  369. return -ENOTSUPP;
  370. if (!(sizes & BIT(size)))
  371. return -EINVAL;
  372. old = pci_rebar_get_current_size(dev, resno);
  373. if (old < 0)
  374. return old;
  375. ret = pci_rebar_set_size(dev, resno, size);
  376. if (ret)
  377. return ret;
  378. res->end = res->start + pci_rebar_size_to_bytes(size) - 1;
  379. /* Check if the new config works by trying to assign everything. */
  380. if (dev->bus->self) {
  381. ret = pci_reassign_bridge_resources(dev->bus->self, res->flags);
  382. if (ret)
  383. goto error_resize;
  384. }
  385. return 0;
  386. error_resize:
  387. pci_rebar_set_size(dev, resno, old);
  388. res->end = res->start + pci_rebar_size_to_bytes(old) - 1;
  389. return ret;
  390. }
  391. EXPORT_SYMBOL(pci_resize_resource);
  392. int pci_enable_resources(struct pci_dev *dev, int mask)
  393. {
  394. u16 cmd, old_cmd;
  395. int i;
  396. struct resource *r;
  397. pci_read_config_word(dev, PCI_COMMAND, &cmd);
  398. old_cmd = cmd;
  399. for (i = 0; i < PCI_NUM_RESOURCES; i++) {
  400. if (!(mask & (1 << i)))
  401. continue;
  402. r = &dev->resource[i];
  403. if (!(r->flags & (IORESOURCE_IO | IORESOURCE_MEM)))
  404. continue;
  405. if ((i == PCI_ROM_RESOURCE) &&
  406. (!(r->flags & IORESOURCE_ROM_ENABLE)))
  407. continue;
  408. if (r->flags & IORESOURCE_UNSET) {
  409. pci_err(dev, "can't enable device: BAR %d %pR not assigned\n",
  410. i, r);
  411. return -EINVAL;
  412. }
  413. if (!r->parent) {
  414. pci_err(dev, "can't enable device: BAR %d %pR not claimed\n",
  415. i, r);
  416. return -EINVAL;
  417. }
  418. if (r->flags & IORESOURCE_IO)
  419. cmd |= PCI_COMMAND_IO;
  420. if (r->flags & IORESOURCE_MEM)
  421. cmd |= PCI_COMMAND_MEMORY;
  422. }
  423. if (cmd != old_cmd) {
  424. pci_info(dev, "enabling device (%04x -> %04x)\n", old_cmd, cmd);
  425. pci_write_config_word(dev, PCI_COMMAND, cmd);
  426. }
  427. return 0;
  428. }