setup-bus.c 59 KB

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  1. // SPDX-License-Identifier: GPL-2.0
  2. /*
  3. * Support routines for initializing a PCI subsystem
  4. *
  5. * Extruded from code written by
  6. * Dave Rusling (david.rusling@reo.mts.dec.com)
  7. * David Mosberger (davidm@cs.arizona.edu)
  8. * David Miller (davem@redhat.com)
  9. *
  10. * Nov 2000, Ivan Kokshaysky <ink@jurassic.park.msu.ru>
  11. * PCI-PCI bridges cleanup, sorted resource allocation.
  12. * Feb 2002, Ivan Kokshaysky <ink@jurassic.park.msu.ru>
  13. * Converted to allocation in 3 passes, which gives
  14. * tighter packing. Prefetchable range support.
  15. */
  16. #include <linux/init.h>
  17. #include <linux/kernel.h>
  18. #include <linux/module.h>
  19. #include <linux/pci.h>
  20. #include <linux/errno.h>
  21. #include <linux/ioport.h>
  22. #include <linux/cache.h>
  23. #include <linux/slab.h>
  24. #include <linux/acpi.h>
  25. #include "pci.h"
  26. unsigned int pci_flags;
  27. EXPORT_SYMBOL_GPL(pci_flags);
  28. struct pci_dev_resource {
  29. struct list_head list;
  30. struct resource *res;
  31. struct pci_dev *dev;
  32. resource_size_t start;
  33. resource_size_t end;
  34. resource_size_t add_size;
  35. resource_size_t min_align;
  36. unsigned long flags;
  37. };
  38. static void free_list(struct list_head *head)
  39. {
  40. struct pci_dev_resource *dev_res, *tmp;
  41. list_for_each_entry_safe(dev_res, tmp, head, list) {
  42. list_del(&dev_res->list);
  43. kfree(dev_res);
  44. }
  45. }
  46. /**
  47. * add_to_list() - Add a new resource tracker to the list
  48. * @head: Head of the list
  49. * @dev: Device to which the resource belongs
  50. * @res: Resource to be tracked
  51. * @add_size: Additional size to be optionally added to the resource
  52. * @min_align: Minimum memory window alignment
  53. */
  54. static int add_to_list(struct list_head *head, struct pci_dev *dev,
  55. struct resource *res, resource_size_t add_size,
  56. resource_size_t min_align)
  57. {
  58. struct pci_dev_resource *tmp;
  59. tmp = kzalloc(sizeof(*tmp), GFP_KERNEL);
  60. if (!tmp)
  61. return -ENOMEM;
  62. tmp->res = res;
  63. tmp->dev = dev;
  64. tmp->start = res->start;
  65. tmp->end = res->end;
  66. tmp->flags = res->flags;
  67. tmp->add_size = add_size;
  68. tmp->min_align = min_align;
  69. list_add(&tmp->list, head);
  70. return 0;
  71. }
  72. static void remove_from_list(struct list_head *head, struct resource *res)
  73. {
  74. struct pci_dev_resource *dev_res, *tmp;
  75. list_for_each_entry_safe(dev_res, tmp, head, list) {
  76. if (dev_res->res == res) {
  77. list_del(&dev_res->list);
  78. kfree(dev_res);
  79. break;
  80. }
  81. }
  82. }
  83. static struct pci_dev_resource *res_to_dev_res(struct list_head *head,
  84. struct resource *res)
  85. {
  86. struct pci_dev_resource *dev_res;
  87. list_for_each_entry(dev_res, head, list) {
  88. if (dev_res->res == res)
  89. return dev_res;
  90. }
  91. return NULL;
  92. }
  93. static resource_size_t get_res_add_size(struct list_head *head,
  94. struct resource *res)
  95. {
  96. struct pci_dev_resource *dev_res;
  97. dev_res = res_to_dev_res(head, res);
  98. return dev_res ? dev_res->add_size : 0;
  99. }
  100. static resource_size_t get_res_add_align(struct list_head *head,
  101. struct resource *res)
  102. {
  103. struct pci_dev_resource *dev_res;
  104. dev_res = res_to_dev_res(head, res);
  105. return dev_res ? dev_res->min_align : 0;
  106. }
  107. /* Sort resources by alignment */
  108. static void pdev_sort_resources(struct pci_dev *dev, struct list_head *head)
  109. {
  110. int i;
  111. for (i = 0; i < PCI_NUM_RESOURCES; i++) {
  112. struct resource *r;
  113. struct pci_dev_resource *dev_res, *tmp;
  114. resource_size_t r_align;
  115. struct list_head *n;
  116. r = &dev->resource[i];
  117. if (r->flags & IORESOURCE_PCI_FIXED)
  118. continue;
  119. if (!(r->flags) || r->parent)
  120. continue;
  121. r_align = pci_resource_alignment(dev, r);
  122. if (!r_align) {
  123. pci_warn(dev, "BAR %d: %pR has bogus alignment\n",
  124. i, r);
  125. continue;
  126. }
  127. tmp = kzalloc(sizeof(*tmp), GFP_KERNEL);
  128. if (!tmp)
  129. panic("%s: kzalloc() failed!\n", __func__);
  130. tmp->res = r;
  131. tmp->dev = dev;
  132. /* Fallback is smallest one or list is empty */
  133. n = head;
  134. list_for_each_entry(dev_res, head, list) {
  135. resource_size_t align;
  136. align = pci_resource_alignment(dev_res->dev,
  137. dev_res->res);
  138. if (r_align > align) {
  139. n = &dev_res->list;
  140. break;
  141. }
  142. }
  143. /* Insert it just before n */
  144. list_add_tail(&tmp->list, n);
  145. }
  146. }
  147. static void __dev_sort_resources(struct pci_dev *dev, struct list_head *head)
  148. {
  149. u16 class = dev->class >> 8;
  150. /* Don't touch classless devices or host bridges or IOAPICs */
  151. if (class == PCI_CLASS_NOT_DEFINED || class == PCI_CLASS_BRIDGE_HOST)
  152. return;
  153. /* Don't touch IOAPIC devices already enabled by firmware */
  154. if (class == PCI_CLASS_SYSTEM_PIC) {
  155. u16 command;
  156. pci_read_config_word(dev, PCI_COMMAND, &command);
  157. if (command & (PCI_COMMAND_IO | PCI_COMMAND_MEMORY))
  158. return;
  159. }
  160. pdev_sort_resources(dev, head);
  161. }
  162. static inline void reset_resource(struct resource *res)
  163. {
  164. res->start = 0;
  165. res->end = 0;
  166. res->flags = 0;
  167. }
  168. /**
  169. * reassign_resources_sorted() - Satisfy any additional resource requests
  170. *
  171. * @realloc_head: Head of the list tracking requests requiring
  172. * additional resources
  173. * @head: Head of the list tracking requests with allocated
  174. * resources
  175. *
  176. * Walk through each element of the realloc_head and try to procure additional
  177. * resources for the element, provided the element is in the head list.
  178. */
  179. static void reassign_resources_sorted(struct list_head *realloc_head,
  180. struct list_head *head)
  181. {
  182. struct resource *res;
  183. struct pci_dev_resource *add_res, *tmp;
  184. struct pci_dev_resource *dev_res;
  185. resource_size_t add_size, align;
  186. int idx;
  187. list_for_each_entry_safe(add_res, tmp, realloc_head, list) {
  188. bool found_match = false;
  189. res = add_res->res;
  190. /* Skip resource that has been reset */
  191. if (!res->flags)
  192. goto out;
  193. /* Skip this resource if not found in head list */
  194. list_for_each_entry(dev_res, head, list) {
  195. if (dev_res->res == res) {
  196. found_match = true;
  197. break;
  198. }
  199. }
  200. if (!found_match) /* Just skip */
  201. continue;
  202. idx = res - &add_res->dev->resource[0];
  203. add_size = add_res->add_size;
  204. align = add_res->min_align;
  205. if (!resource_size(res)) {
  206. res->start = align;
  207. res->end = res->start + add_size - 1;
  208. if (pci_assign_resource(add_res->dev, idx))
  209. reset_resource(res);
  210. } else {
  211. res->flags |= add_res->flags &
  212. (IORESOURCE_STARTALIGN|IORESOURCE_SIZEALIGN);
  213. if (pci_reassign_resource(add_res->dev, idx,
  214. add_size, align))
  215. pci_info(add_res->dev, "failed to add %llx res[%d]=%pR\n",
  216. (unsigned long long) add_size, idx,
  217. res);
  218. }
  219. out:
  220. list_del(&add_res->list);
  221. kfree(add_res);
  222. }
  223. }
  224. /**
  225. * assign_requested_resources_sorted() - Satisfy resource requests
  226. *
  227. * @head: Head of the list tracking requests for resources
  228. * @fail_head: Head of the list tracking requests that could not be
  229. * allocated
  230. *
  231. * Satisfy resource requests of each element in the list. Add requests that
  232. * could not be satisfied to the failed_list.
  233. */
  234. static void assign_requested_resources_sorted(struct list_head *head,
  235. struct list_head *fail_head)
  236. {
  237. struct resource *res;
  238. struct pci_dev_resource *dev_res;
  239. int idx;
  240. list_for_each_entry(dev_res, head, list) {
  241. res = dev_res->res;
  242. idx = res - &dev_res->dev->resource[0];
  243. if (resource_size(res) &&
  244. pci_assign_resource(dev_res->dev, idx)) {
  245. if (fail_head) {
  246. /*
  247. * If the failed resource is a ROM BAR and
  248. * it will be enabled later, don't add it
  249. * to the list.
  250. */
  251. if (!((idx == PCI_ROM_RESOURCE) &&
  252. (!(res->flags & IORESOURCE_ROM_ENABLE))))
  253. add_to_list(fail_head,
  254. dev_res->dev, res,
  255. 0 /* don't care */,
  256. 0 /* don't care */);
  257. }
  258. reset_resource(res);
  259. }
  260. }
  261. }
  262. static unsigned long pci_fail_res_type_mask(struct list_head *fail_head)
  263. {
  264. struct pci_dev_resource *fail_res;
  265. unsigned long mask = 0;
  266. /* Check failed type */
  267. list_for_each_entry(fail_res, fail_head, list)
  268. mask |= fail_res->flags;
  269. /*
  270. * One pref failed resource will set IORESOURCE_MEM, as we can
  271. * allocate pref in non-pref range. Will release all assigned
  272. * non-pref sibling resources according to that bit.
  273. */
  274. return mask & (IORESOURCE_IO | IORESOURCE_MEM | IORESOURCE_PREFETCH);
  275. }
  276. static bool pci_need_to_release(unsigned long mask, struct resource *res)
  277. {
  278. if (res->flags & IORESOURCE_IO)
  279. return !!(mask & IORESOURCE_IO);
  280. /* Check pref at first */
  281. if (res->flags & IORESOURCE_PREFETCH) {
  282. if (mask & IORESOURCE_PREFETCH)
  283. return true;
  284. /* Count pref if its parent is non-pref */
  285. else if ((mask & IORESOURCE_MEM) &&
  286. !(res->parent->flags & IORESOURCE_PREFETCH))
  287. return true;
  288. else
  289. return false;
  290. }
  291. if (res->flags & IORESOURCE_MEM)
  292. return !!(mask & IORESOURCE_MEM);
  293. return false; /* Should not get here */
  294. }
  295. static void __assign_resources_sorted(struct list_head *head,
  296. struct list_head *realloc_head,
  297. struct list_head *fail_head)
  298. {
  299. /*
  300. * Should not assign requested resources at first. They could be
  301. * adjacent, so later reassign can not reallocate them one by one in
  302. * parent resource window.
  303. *
  304. * Try to assign requested + add_size at beginning. If could do that,
  305. * could get out early. If could not do that, we still try to assign
  306. * requested at first, then try to reassign add_size for some resources.
  307. *
  308. * Separate three resource type checking if we need to release
  309. * assigned resource after requested + add_size try.
  310. *
  311. * 1. If IO port assignment fails, will release assigned IO
  312. * port.
  313. * 2. If pref MMIO assignment fails, release assigned pref
  314. * MMIO. If assigned pref MMIO's parent is non-pref MMIO
  315. * and non-pref MMIO assignment fails, will release that
  316. * assigned pref MMIO.
  317. * 3. If non-pref MMIO assignment fails or pref MMIO
  318. * assignment fails, will release assigned non-pref MMIO.
  319. */
  320. LIST_HEAD(save_head);
  321. LIST_HEAD(local_fail_head);
  322. struct pci_dev_resource *save_res;
  323. struct pci_dev_resource *dev_res, *tmp_res, *dev_res2;
  324. unsigned long fail_type;
  325. resource_size_t add_align, align;
  326. /* Check if optional add_size is there */
  327. if (!realloc_head || list_empty(realloc_head))
  328. goto requested_and_reassign;
  329. /* Save original start, end, flags etc at first */
  330. list_for_each_entry(dev_res, head, list) {
  331. if (add_to_list(&save_head, dev_res->dev, dev_res->res, 0, 0)) {
  332. free_list(&save_head);
  333. goto requested_and_reassign;
  334. }
  335. }
  336. /* Update res in head list with add_size in realloc_head list */
  337. list_for_each_entry_safe(dev_res, tmp_res, head, list) {
  338. dev_res->res->end += get_res_add_size(realloc_head,
  339. dev_res->res);
  340. /*
  341. * There are two kinds of additional resources in the list:
  342. * 1. bridge resource -- IORESOURCE_STARTALIGN
  343. * 2. SR-IOV resource -- IORESOURCE_SIZEALIGN
  344. * Here just fix the additional alignment for bridge
  345. */
  346. if (!(dev_res->res->flags & IORESOURCE_STARTALIGN))
  347. continue;
  348. add_align = get_res_add_align(realloc_head, dev_res->res);
  349. /*
  350. * The "head" list is sorted by alignment so resources with
  351. * bigger alignment will be assigned first. After we
  352. * change the alignment of a dev_res in "head" list, we
  353. * need to reorder the list by alignment to make it
  354. * consistent.
  355. */
  356. if (add_align > dev_res->res->start) {
  357. resource_size_t r_size = resource_size(dev_res->res);
  358. dev_res->res->start = add_align;
  359. dev_res->res->end = add_align + r_size - 1;
  360. list_for_each_entry(dev_res2, head, list) {
  361. align = pci_resource_alignment(dev_res2->dev,
  362. dev_res2->res);
  363. if (add_align > align) {
  364. list_move_tail(&dev_res->list,
  365. &dev_res2->list);
  366. break;
  367. }
  368. }
  369. }
  370. }
  371. /* Try updated head list with add_size added */
  372. assign_requested_resources_sorted(head, &local_fail_head);
  373. /* All assigned with add_size? */
  374. if (list_empty(&local_fail_head)) {
  375. /* Remove head list from realloc_head list */
  376. list_for_each_entry(dev_res, head, list)
  377. remove_from_list(realloc_head, dev_res->res);
  378. free_list(&save_head);
  379. free_list(head);
  380. return;
  381. }
  382. /* Check failed type */
  383. fail_type = pci_fail_res_type_mask(&local_fail_head);
  384. /* Remove not need to be released assigned res from head list etc */
  385. list_for_each_entry_safe(dev_res, tmp_res, head, list)
  386. if (dev_res->res->parent &&
  387. !pci_need_to_release(fail_type, dev_res->res)) {
  388. /* Remove it from realloc_head list */
  389. remove_from_list(realloc_head, dev_res->res);
  390. remove_from_list(&save_head, dev_res->res);
  391. list_del(&dev_res->list);
  392. kfree(dev_res);
  393. }
  394. free_list(&local_fail_head);
  395. /* Release assigned resource */
  396. list_for_each_entry(dev_res, head, list)
  397. if (dev_res->res->parent)
  398. release_resource(dev_res->res);
  399. /* Restore start/end/flags from saved list */
  400. list_for_each_entry(save_res, &save_head, list) {
  401. struct resource *res = save_res->res;
  402. res->start = save_res->start;
  403. res->end = save_res->end;
  404. res->flags = save_res->flags;
  405. }
  406. free_list(&save_head);
  407. requested_and_reassign:
  408. /* Satisfy the must-have resource requests */
  409. assign_requested_resources_sorted(head, fail_head);
  410. /* Try to satisfy any additional optional resource requests */
  411. if (realloc_head)
  412. reassign_resources_sorted(realloc_head, head);
  413. free_list(head);
  414. }
  415. static void pdev_assign_resources_sorted(struct pci_dev *dev,
  416. struct list_head *add_head,
  417. struct list_head *fail_head)
  418. {
  419. LIST_HEAD(head);
  420. __dev_sort_resources(dev, &head);
  421. __assign_resources_sorted(&head, add_head, fail_head);
  422. }
  423. static void pbus_assign_resources_sorted(const struct pci_bus *bus,
  424. struct list_head *realloc_head,
  425. struct list_head *fail_head)
  426. {
  427. struct pci_dev *dev;
  428. LIST_HEAD(head);
  429. list_for_each_entry(dev, &bus->devices, bus_list)
  430. __dev_sort_resources(dev, &head);
  431. __assign_resources_sorted(&head, realloc_head, fail_head);
  432. }
  433. void pci_setup_cardbus(struct pci_bus *bus)
  434. {
  435. struct pci_dev *bridge = bus->self;
  436. struct resource *res;
  437. struct pci_bus_region region;
  438. pci_info(bridge, "CardBus bridge to %pR\n",
  439. &bus->busn_res);
  440. res = bus->resource[0];
  441. pcibios_resource_to_bus(bridge->bus, &region, res);
  442. if (res->flags & IORESOURCE_IO) {
  443. /*
  444. * The IO resource is allocated a range twice as large as it
  445. * would normally need. This allows us to set both IO regs.
  446. */
  447. pci_info(bridge, " bridge window %pR\n", res);
  448. pci_write_config_dword(bridge, PCI_CB_IO_BASE_0,
  449. region.start);
  450. pci_write_config_dword(bridge, PCI_CB_IO_LIMIT_0,
  451. region.end);
  452. }
  453. res = bus->resource[1];
  454. pcibios_resource_to_bus(bridge->bus, &region, res);
  455. if (res->flags & IORESOURCE_IO) {
  456. pci_info(bridge, " bridge window %pR\n", res);
  457. pci_write_config_dword(bridge, PCI_CB_IO_BASE_1,
  458. region.start);
  459. pci_write_config_dword(bridge, PCI_CB_IO_LIMIT_1,
  460. region.end);
  461. }
  462. res = bus->resource[2];
  463. pcibios_resource_to_bus(bridge->bus, &region, res);
  464. if (res->flags & IORESOURCE_MEM) {
  465. pci_info(bridge, " bridge window %pR\n", res);
  466. pci_write_config_dword(bridge, PCI_CB_MEMORY_BASE_0,
  467. region.start);
  468. pci_write_config_dword(bridge, PCI_CB_MEMORY_LIMIT_0,
  469. region.end);
  470. }
  471. res = bus->resource[3];
  472. pcibios_resource_to_bus(bridge->bus, &region, res);
  473. if (res->flags & IORESOURCE_MEM) {
  474. pci_info(bridge, " bridge window %pR\n", res);
  475. pci_write_config_dword(bridge, PCI_CB_MEMORY_BASE_1,
  476. region.start);
  477. pci_write_config_dword(bridge, PCI_CB_MEMORY_LIMIT_1,
  478. region.end);
  479. }
  480. }
  481. EXPORT_SYMBOL(pci_setup_cardbus);
  482. /*
  483. * Initialize bridges with base/limit values we have collected. PCI-to-PCI
  484. * Bridge Architecture Specification rev. 1.1 (1998) requires that if there
  485. * are no I/O ports or memory behind the bridge, the corresponding range
  486. * must be turned off by writing base value greater than limit to the
  487. * bridge's base/limit registers.
  488. *
  489. * Note: care must be taken when updating I/O base/limit registers of
  490. * bridges which support 32-bit I/O. This update requires two config space
  491. * writes, so it's quite possible that an I/O window of the bridge will
  492. * have some undesirable address (e.g. 0) after the first write. Ditto
  493. * 64-bit prefetchable MMIO.
  494. */
  495. static void pci_setup_bridge_io(struct pci_dev *bridge)
  496. {
  497. struct resource *res;
  498. struct pci_bus_region region;
  499. unsigned long io_mask;
  500. u8 io_base_lo, io_limit_lo;
  501. u16 l;
  502. u32 io_upper16;
  503. io_mask = PCI_IO_RANGE_MASK;
  504. if (bridge->io_window_1k)
  505. io_mask = PCI_IO_1K_RANGE_MASK;
  506. /* Set up the top and bottom of the PCI I/O segment for this bus */
  507. res = &bridge->resource[PCI_BRIDGE_IO_WINDOW];
  508. pcibios_resource_to_bus(bridge->bus, &region, res);
  509. if (res->flags & IORESOURCE_IO) {
  510. pci_read_config_word(bridge, PCI_IO_BASE, &l);
  511. io_base_lo = (region.start >> 8) & io_mask;
  512. io_limit_lo = (region.end >> 8) & io_mask;
  513. l = ((u16) io_limit_lo << 8) | io_base_lo;
  514. /* Set up upper 16 bits of I/O base/limit */
  515. io_upper16 = (region.end & 0xffff0000) | (region.start >> 16);
  516. pci_info(bridge, " bridge window %pR\n", res);
  517. } else {
  518. /* Clear upper 16 bits of I/O base/limit */
  519. io_upper16 = 0;
  520. l = 0x00f0;
  521. }
  522. /* Temporarily disable the I/O range before updating PCI_IO_BASE */
  523. pci_write_config_dword(bridge, PCI_IO_BASE_UPPER16, 0x0000ffff);
  524. /* Update lower 16 bits of I/O base/limit */
  525. pci_write_config_word(bridge, PCI_IO_BASE, l);
  526. /* Update upper 16 bits of I/O base/limit */
  527. pci_write_config_dword(bridge, PCI_IO_BASE_UPPER16, io_upper16);
  528. }
  529. static void pci_setup_bridge_mmio(struct pci_dev *bridge)
  530. {
  531. struct resource *res;
  532. struct pci_bus_region region;
  533. u32 l;
  534. /* Set up the top and bottom of the PCI Memory segment for this bus */
  535. res = &bridge->resource[PCI_BRIDGE_MEM_WINDOW];
  536. pcibios_resource_to_bus(bridge->bus, &region, res);
  537. if (res->flags & IORESOURCE_MEM) {
  538. l = (region.start >> 16) & 0xfff0;
  539. l |= region.end & 0xfff00000;
  540. pci_info(bridge, " bridge window %pR\n", res);
  541. } else {
  542. l = 0x0000fff0;
  543. }
  544. pci_write_config_dword(bridge, PCI_MEMORY_BASE, l);
  545. }
  546. static void pci_setup_bridge_mmio_pref(struct pci_dev *bridge)
  547. {
  548. struct resource *res;
  549. struct pci_bus_region region;
  550. u32 l, bu, lu;
  551. /*
  552. * Clear out the upper 32 bits of PREF limit. If
  553. * PCI_PREF_BASE_UPPER32 was non-zero, this temporarily disables
  554. * PREF range, which is ok.
  555. */
  556. pci_write_config_dword(bridge, PCI_PREF_LIMIT_UPPER32, 0);
  557. /* Set up PREF base/limit */
  558. bu = lu = 0;
  559. res = &bridge->resource[PCI_BRIDGE_PREF_MEM_WINDOW];
  560. pcibios_resource_to_bus(bridge->bus, &region, res);
  561. if (res->flags & IORESOURCE_PREFETCH) {
  562. l = (region.start >> 16) & 0xfff0;
  563. l |= region.end & 0xfff00000;
  564. if (res->flags & IORESOURCE_MEM_64) {
  565. bu = upper_32_bits(region.start);
  566. lu = upper_32_bits(region.end);
  567. }
  568. pci_info(bridge, " bridge window %pR\n", res);
  569. } else {
  570. l = 0x0000fff0;
  571. }
  572. pci_write_config_dword(bridge, PCI_PREF_MEMORY_BASE, l);
  573. /* Set the upper 32 bits of PREF base & limit */
  574. pci_write_config_dword(bridge, PCI_PREF_BASE_UPPER32, bu);
  575. pci_write_config_dword(bridge, PCI_PREF_LIMIT_UPPER32, lu);
  576. }
  577. static void __pci_setup_bridge(struct pci_bus *bus, unsigned long type)
  578. {
  579. struct pci_dev *bridge = bus->self;
  580. pci_info(bridge, "PCI bridge to %pR\n",
  581. &bus->busn_res);
  582. if (type & IORESOURCE_IO)
  583. pci_setup_bridge_io(bridge);
  584. if (type & IORESOURCE_MEM)
  585. pci_setup_bridge_mmio(bridge);
  586. if (type & IORESOURCE_PREFETCH)
  587. pci_setup_bridge_mmio_pref(bridge);
  588. pci_write_config_word(bridge, PCI_BRIDGE_CONTROL, bus->bridge_ctl);
  589. }
  590. void __weak pcibios_setup_bridge(struct pci_bus *bus, unsigned long type)
  591. {
  592. }
  593. void pci_setup_bridge(struct pci_bus *bus)
  594. {
  595. unsigned long type = IORESOURCE_IO | IORESOURCE_MEM |
  596. IORESOURCE_PREFETCH;
  597. pcibios_setup_bridge(bus, type);
  598. __pci_setup_bridge(bus, type);
  599. }
  600. int pci_claim_bridge_resource(struct pci_dev *bridge, int i)
  601. {
  602. if (i < PCI_BRIDGE_RESOURCES || i > PCI_BRIDGE_RESOURCE_END)
  603. return 0;
  604. if (pci_claim_resource(bridge, i) == 0)
  605. return 0; /* Claimed the window */
  606. if ((bridge->class >> 8) != PCI_CLASS_BRIDGE_PCI)
  607. return 0;
  608. if (!pci_bus_clip_resource(bridge, i))
  609. return -EINVAL; /* Clipping didn't change anything */
  610. switch (i) {
  611. case PCI_BRIDGE_IO_WINDOW:
  612. pci_setup_bridge_io(bridge);
  613. break;
  614. case PCI_BRIDGE_MEM_WINDOW:
  615. pci_setup_bridge_mmio(bridge);
  616. break;
  617. case PCI_BRIDGE_PREF_MEM_WINDOW:
  618. pci_setup_bridge_mmio_pref(bridge);
  619. break;
  620. default:
  621. return -EINVAL;
  622. }
  623. if (pci_claim_resource(bridge, i) == 0)
  624. return 0; /* Claimed a smaller window */
  625. return -EINVAL;
  626. }
  627. /*
  628. * Check whether the bridge supports optional I/O and prefetchable memory
  629. * ranges. If not, the respective base/limit registers must be read-only
  630. * and read as 0.
  631. */
  632. static void pci_bridge_check_ranges(struct pci_bus *bus)
  633. {
  634. struct pci_dev *bridge = bus->self;
  635. struct resource *b_res;
  636. b_res = &bridge->resource[PCI_BRIDGE_MEM_WINDOW];
  637. b_res->flags |= IORESOURCE_MEM;
  638. if (bridge->io_window) {
  639. b_res = &bridge->resource[PCI_BRIDGE_IO_WINDOW];
  640. b_res->flags |= IORESOURCE_IO;
  641. }
  642. if (bridge->pref_window) {
  643. b_res = &bridge->resource[PCI_BRIDGE_PREF_MEM_WINDOW];
  644. b_res->flags |= IORESOURCE_MEM | IORESOURCE_PREFETCH;
  645. if (bridge->pref_64_window) {
  646. b_res->flags |= IORESOURCE_MEM_64 |
  647. PCI_PREF_RANGE_TYPE_64;
  648. }
  649. }
  650. }
  651. /*
  652. * Helper function for sizing routines. Assigned resources have non-NULL
  653. * parent resource.
  654. *
  655. * Return first unassigned resource of the correct type. If there is none,
  656. * return first assigned resource of the correct type. If none of the
  657. * above, return NULL.
  658. *
  659. * Returning an assigned resource of the correct type allows the caller to
  660. * distinguish between already assigned and no resource of the correct type.
  661. */
  662. static struct resource *find_bus_resource_of_type(struct pci_bus *bus,
  663. unsigned long type_mask,
  664. unsigned long type)
  665. {
  666. struct resource *r, *r_assigned = NULL;
  667. int i;
  668. pci_bus_for_each_resource(bus, r, i) {
  669. if (r == &ioport_resource || r == &iomem_resource)
  670. continue;
  671. if (r && (r->flags & type_mask) == type && !r->parent)
  672. return r;
  673. if (r && (r->flags & type_mask) == type && !r_assigned)
  674. r_assigned = r;
  675. }
  676. return r_assigned;
  677. }
  678. static resource_size_t calculate_iosize(resource_size_t size,
  679. resource_size_t min_size,
  680. resource_size_t size1,
  681. resource_size_t add_size,
  682. resource_size_t children_add_size,
  683. resource_size_t old_size,
  684. resource_size_t align)
  685. {
  686. if (size < min_size)
  687. size = min_size;
  688. if (old_size == 1)
  689. old_size = 0;
  690. /*
  691. * To be fixed in 2.5: we should have sort of HAVE_ISA flag in the
  692. * struct pci_bus.
  693. */
  694. #if defined(CONFIG_ISA) || defined(CONFIG_EISA)
  695. size = (size & 0xff) + ((size & ~0xffUL) << 2);
  696. #endif
  697. size = size + size1;
  698. if (size < old_size)
  699. size = old_size;
  700. size = ALIGN(max(size, add_size) + children_add_size, align);
  701. return size;
  702. }
  703. static resource_size_t calculate_memsize(resource_size_t size,
  704. resource_size_t min_size,
  705. resource_size_t add_size,
  706. resource_size_t children_add_size,
  707. resource_size_t old_size,
  708. resource_size_t align)
  709. {
  710. if (size < min_size)
  711. size = min_size;
  712. if (old_size == 1)
  713. old_size = 0;
  714. if (size < old_size)
  715. size = old_size;
  716. size = ALIGN(max(size, add_size) + children_add_size, align);
  717. return size;
  718. }
  719. resource_size_t __weak pcibios_window_alignment(struct pci_bus *bus,
  720. unsigned long type)
  721. {
  722. return 1;
  723. }
  724. #define PCI_P2P_DEFAULT_MEM_ALIGN 0x100000 /* 1MiB */
  725. #define PCI_P2P_DEFAULT_IO_ALIGN 0x1000 /* 4KiB */
  726. #define PCI_P2P_DEFAULT_IO_ALIGN_1K 0x400 /* 1KiB */
  727. static resource_size_t window_alignment(struct pci_bus *bus, unsigned long type)
  728. {
  729. resource_size_t align = 1, arch_align;
  730. if (type & IORESOURCE_MEM)
  731. align = PCI_P2P_DEFAULT_MEM_ALIGN;
  732. else if (type & IORESOURCE_IO) {
  733. /*
  734. * Per spec, I/O windows are 4K-aligned, but some bridges have
  735. * an extension to support 1K alignment.
  736. */
  737. if (bus->self && bus->self->io_window_1k)
  738. align = PCI_P2P_DEFAULT_IO_ALIGN_1K;
  739. else
  740. align = PCI_P2P_DEFAULT_IO_ALIGN;
  741. }
  742. arch_align = pcibios_window_alignment(bus, type);
  743. return max(align, arch_align);
  744. }
  745. /**
  746. * pbus_size_io() - Size the I/O window of a given bus
  747. *
  748. * @bus: The bus
  749. * @min_size: The minimum I/O window that must be allocated
  750. * @add_size: Additional optional I/O window
  751. * @realloc_head: Track the additional I/O window on this list
  752. *
  753. * Sizing the I/O windows of the PCI-PCI bridge is trivial, since these
  754. * windows have 1K or 4K granularity and the I/O ranges of non-bridge PCI
  755. * devices are limited to 256 bytes. We must be careful with the ISA
  756. * aliasing though.
  757. */
  758. static void pbus_size_io(struct pci_bus *bus, resource_size_t min_size,
  759. resource_size_t add_size,
  760. struct list_head *realloc_head)
  761. {
  762. struct pci_dev *dev;
  763. struct resource *b_res = find_bus_resource_of_type(bus, IORESOURCE_IO,
  764. IORESOURCE_IO);
  765. resource_size_t size = 0, size0 = 0, size1 = 0;
  766. resource_size_t children_add_size = 0;
  767. resource_size_t min_align, align;
  768. if (!b_res)
  769. return;
  770. /* If resource is already assigned, nothing more to do */
  771. if (b_res->parent)
  772. return;
  773. min_align = window_alignment(bus, IORESOURCE_IO);
  774. list_for_each_entry(dev, &bus->devices, bus_list) {
  775. int i;
  776. for (i = 0; i < PCI_NUM_RESOURCES; i++) {
  777. struct resource *r = &dev->resource[i];
  778. unsigned long r_size;
  779. if (r->parent || !(r->flags & IORESOURCE_IO))
  780. continue;
  781. r_size = resource_size(r);
  782. if (r_size < 0x400)
  783. /* Might be re-aligned for ISA */
  784. size += r_size;
  785. else
  786. size1 += r_size;
  787. align = pci_resource_alignment(dev, r);
  788. if (align > min_align)
  789. min_align = align;
  790. if (realloc_head)
  791. children_add_size += get_res_add_size(realloc_head, r);
  792. }
  793. }
  794. size0 = calculate_iosize(size, min_size, size1, 0, 0,
  795. resource_size(b_res), min_align);
  796. size1 = (!realloc_head || (realloc_head && !add_size && !children_add_size)) ? size0 :
  797. calculate_iosize(size, min_size, size1, add_size, children_add_size,
  798. resource_size(b_res), min_align);
  799. if (!size0 && !size1) {
  800. if (bus->self && (b_res->start || b_res->end))
  801. pci_info(bus->self, "disabling bridge window %pR to %pR (unused)\n",
  802. b_res, &bus->busn_res);
  803. b_res->flags = 0;
  804. return;
  805. }
  806. b_res->start = min_align;
  807. b_res->end = b_res->start + size0 - 1;
  808. b_res->flags |= IORESOURCE_STARTALIGN;
  809. if (bus->self && size1 > size0 && realloc_head) {
  810. add_to_list(realloc_head, bus->self, b_res, size1-size0,
  811. min_align);
  812. pci_info(bus->self, "bridge window %pR to %pR add_size %llx\n",
  813. b_res, &bus->busn_res,
  814. (unsigned long long) size1 - size0);
  815. }
  816. }
  817. static inline resource_size_t calculate_mem_align(resource_size_t *aligns,
  818. int max_order)
  819. {
  820. resource_size_t align = 0;
  821. resource_size_t min_align = 0;
  822. int order;
  823. for (order = 0; order <= max_order; order++) {
  824. resource_size_t align1 = 1;
  825. align1 <<= (order + 20);
  826. if (!align)
  827. min_align = align1;
  828. else if (ALIGN(align + min_align, min_align) < align1)
  829. min_align = align1 >> 1;
  830. align += aligns[order];
  831. }
  832. return min_align;
  833. }
  834. /**
  835. * pbus_size_mem() - Size the memory window of a given bus
  836. *
  837. * @bus: The bus
  838. * @mask: Mask the resource flag, then compare it with type
  839. * @type: The type of free resource from bridge
  840. * @type2: Second match type
  841. * @type3: Third match type
  842. * @min_size: The minimum memory window that must be allocated
  843. * @add_size: Additional optional memory window
  844. * @realloc_head: Track the additional memory window on this list
  845. *
  846. * Calculate the size of the bus and minimal alignment which guarantees
  847. * that all child resources fit in this size.
  848. *
  849. * Return -ENOSPC if there's no available bus resource of the desired
  850. * type. Otherwise, set the bus resource start/end to indicate the
  851. * required size, add things to realloc_head (if supplied), and return 0.
  852. */
  853. static int pbus_size_mem(struct pci_bus *bus, unsigned long mask,
  854. unsigned long type, unsigned long type2,
  855. unsigned long type3, resource_size_t min_size,
  856. resource_size_t add_size,
  857. struct list_head *realloc_head)
  858. {
  859. struct pci_dev *dev;
  860. resource_size_t min_align, align, size, size0, size1;
  861. resource_size_t aligns[18]; /* Alignments from 1MB to 128GB */
  862. int order, max_order;
  863. struct resource *b_res = find_bus_resource_of_type(bus,
  864. mask | IORESOURCE_PREFETCH, type);
  865. resource_size_t children_add_size = 0;
  866. resource_size_t children_add_align = 0;
  867. resource_size_t add_align = 0;
  868. if (!b_res)
  869. return -ENOSPC;
  870. /* If resource is already assigned, nothing more to do */
  871. if (b_res->parent)
  872. return 0;
  873. memset(aligns, 0, sizeof(aligns));
  874. max_order = 0;
  875. size = 0;
  876. list_for_each_entry(dev, &bus->devices, bus_list) {
  877. int i;
  878. for (i = 0; i < PCI_NUM_RESOURCES; i++) {
  879. struct resource *r = &dev->resource[i];
  880. resource_size_t r_size;
  881. if (r->parent || (r->flags & IORESOURCE_PCI_FIXED) ||
  882. ((r->flags & mask) != type &&
  883. (r->flags & mask) != type2 &&
  884. (r->flags & mask) != type3))
  885. continue;
  886. r_size = resource_size(r);
  887. #ifdef CONFIG_PCI_IOV
  888. /* Put SRIOV requested res to the optional list */
  889. if (realloc_head && i >= PCI_IOV_RESOURCES &&
  890. i <= PCI_IOV_RESOURCE_END) {
  891. add_align = max(pci_resource_alignment(dev, r), add_align);
  892. r->end = r->start - 1;
  893. add_to_list(realloc_head, dev, r, r_size, 0 /* Don't care */);
  894. children_add_size += r_size;
  895. continue;
  896. }
  897. #endif
  898. /*
  899. * aligns[0] is for 1MB (since bridge memory
  900. * windows are always at least 1MB aligned), so
  901. * keep "order" from being negative for smaller
  902. * resources.
  903. */
  904. align = pci_resource_alignment(dev, r);
  905. order = __ffs(align) - 20;
  906. if (order < 0)
  907. order = 0;
  908. if (order >= ARRAY_SIZE(aligns)) {
  909. pci_warn(dev, "disabling BAR %d: %pR (bad alignment %#llx)\n",
  910. i, r, (unsigned long long) align);
  911. r->flags = 0;
  912. continue;
  913. }
  914. size += max(r_size, align);
  915. /*
  916. * Exclude ranges with size > align from calculation of
  917. * the alignment.
  918. */
  919. if (r_size <= align)
  920. aligns[order] += align;
  921. if (order > max_order)
  922. max_order = order;
  923. if (realloc_head) {
  924. children_add_size += get_res_add_size(realloc_head, r);
  925. children_add_align = get_res_add_align(realloc_head, r);
  926. add_align = max(add_align, children_add_align);
  927. }
  928. }
  929. }
  930. min_align = calculate_mem_align(aligns, max_order);
  931. min_align = max(min_align, window_alignment(bus, b_res->flags));
  932. size0 = calculate_memsize(size, min_size, 0, 0, resource_size(b_res), min_align);
  933. add_align = max(min_align, add_align);
  934. size1 = (!realloc_head || (realloc_head && !add_size && !children_add_size)) ? size0 :
  935. calculate_memsize(size, min_size, add_size, children_add_size,
  936. resource_size(b_res), add_align);
  937. if (!size0 && !size1) {
  938. if (bus->self && (b_res->start || b_res->end))
  939. pci_info(bus->self, "disabling bridge window %pR to %pR (unused)\n",
  940. b_res, &bus->busn_res);
  941. b_res->flags = 0;
  942. return 0;
  943. }
  944. b_res->start = min_align;
  945. b_res->end = size0 + min_align - 1;
  946. b_res->flags |= IORESOURCE_STARTALIGN;
  947. if (bus->self && size1 > size0 && realloc_head) {
  948. add_to_list(realloc_head, bus->self, b_res, size1-size0, add_align);
  949. pci_info(bus->self, "bridge window %pR to %pR add_size %llx add_align %llx\n",
  950. b_res, &bus->busn_res,
  951. (unsigned long long) (size1 - size0),
  952. (unsigned long long) add_align);
  953. }
  954. return 0;
  955. }
  956. unsigned long pci_cardbus_resource_alignment(struct resource *res)
  957. {
  958. if (res->flags & IORESOURCE_IO)
  959. return pci_cardbus_io_size;
  960. if (res->flags & IORESOURCE_MEM)
  961. return pci_cardbus_mem_size;
  962. return 0;
  963. }
  964. static void pci_bus_size_cardbus(struct pci_bus *bus,
  965. struct list_head *realloc_head)
  966. {
  967. struct pci_dev *bridge = bus->self;
  968. struct resource *b_res;
  969. resource_size_t b_res_3_size = pci_cardbus_mem_size * 2;
  970. u16 ctrl;
  971. b_res = &bridge->resource[PCI_CB_BRIDGE_IO_0_WINDOW];
  972. if (b_res->parent)
  973. goto handle_b_res_1;
  974. /*
  975. * Reserve some resources for CardBus. We reserve a fixed amount
  976. * of bus space for CardBus bridges.
  977. */
  978. b_res->start = pci_cardbus_io_size;
  979. b_res->end = b_res->start + pci_cardbus_io_size - 1;
  980. b_res->flags |= IORESOURCE_IO | IORESOURCE_STARTALIGN;
  981. if (realloc_head) {
  982. b_res->end -= pci_cardbus_io_size;
  983. add_to_list(realloc_head, bridge, b_res, pci_cardbus_io_size,
  984. pci_cardbus_io_size);
  985. }
  986. handle_b_res_1:
  987. b_res = &bridge->resource[PCI_CB_BRIDGE_IO_1_WINDOW];
  988. if (b_res->parent)
  989. goto handle_b_res_2;
  990. b_res->start = pci_cardbus_io_size;
  991. b_res->end = b_res->start + pci_cardbus_io_size - 1;
  992. b_res->flags |= IORESOURCE_IO | IORESOURCE_STARTALIGN;
  993. if (realloc_head) {
  994. b_res->end -= pci_cardbus_io_size;
  995. add_to_list(realloc_head, bridge, b_res, pci_cardbus_io_size,
  996. pci_cardbus_io_size);
  997. }
  998. handle_b_res_2:
  999. /* MEM1 must not be pref MMIO */
  1000. pci_read_config_word(bridge, PCI_CB_BRIDGE_CONTROL, &ctrl);
  1001. if (ctrl & PCI_CB_BRIDGE_CTL_PREFETCH_MEM1) {
  1002. ctrl &= ~PCI_CB_BRIDGE_CTL_PREFETCH_MEM1;
  1003. pci_write_config_word(bridge, PCI_CB_BRIDGE_CONTROL, ctrl);
  1004. pci_read_config_word(bridge, PCI_CB_BRIDGE_CONTROL, &ctrl);
  1005. }
  1006. /* Check whether prefetchable memory is supported by this bridge. */
  1007. pci_read_config_word(bridge, PCI_CB_BRIDGE_CONTROL, &ctrl);
  1008. if (!(ctrl & PCI_CB_BRIDGE_CTL_PREFETCH_MEM0)) {
  1009. ctrl |= PCI_CB_BRIDGE_CTL_PREFETCH_MEM0;
  1010. pci_write_config_word(bridge, PCI_CB_BRIDGE_CONTROL, ctrl);
  1011. pci_read_config_word(bridge, PCI_CB_BRIDGE_CONTROL, &ctrl);
  1012. }
  1013. b_res = &bridge->resource[PCI_CB_BRIDGE_MEM_0_WINDOW];
  1014. if (b_res->parent)
  1015. goto handle_b_res_3;
  1016. /*
  1017. * If we have prefetchable memory support, allocate two regions.
  1018. * Otherwise, allocate one region of twice the size.
  1019. */
  1020. if (ctrl & PCI_CB_BRIDGE_CTL_PREFETCH_MEM0) {
  1021. b_res->start = pci_cardbus_mem_size;
  1022. b_res->end = b_res->start + pci_cardbus_mem_size - 1;
  1023. b_res->flags |= IORESOURCE_MEM | IORESOURCE_PREFETCH |
  1024. IORESOURCE_STARTALIGN;
  1025. if (realloc_head) {
  1026. b_res->end -= pci_cardbus_mem_size;
  1027. add_to_list(realloc_head, bridge, b_res,
  1028. pci_cardbus_mem_size, pci_cardbus_mem_size);
  1029. }
  1030. /* Reduce that to half */
  1031. b_res_3_size = pci_cardbus_mem_size;
  1032. }
  1033. handle_b_res_3:
  1034. b_res = &bridge->resource[PCI_CB_BRIDGE_MEM_1_WINDOW];
  1035. if (b_res->parent)
  1036. goto handle_done;
  1037. b_res->start = pci_cardbus_mem_size;
  1038. b_res->end = b_res->start + b_res_3_size - 1;
  1039. b_res->flags |= IORESOURCE_MEM | IORESOURCE_STARTALIGN;
  1040. if (realloc_head) {
  1041. b_res->end -= b_res_3_size;
  1042. add_to_list(realloc_head, bridge, b_res, b_res_3_size,
  1043. pci_cardbus_mem_size);
  1044. }
  1045. handle_done:
  1046. ;
  1047. }
  1048. void __pci_bus_size_bridges(struct pci_bus *bus, struct list_head *realloc_head)
  1049. {
  1050. struct pci_dev *dev;
  1051. unsigned long mask, prefmask, type2 = 0, type3 = 0;
  1052. resource_size_t additional_io_size = 0, additional_mmio_size = 0,
  1053. additional_mmio_pref_size = 0;
  1054. struct resource *pref;
  1055. struct pci_host_bridge *host;
  1056. int hdr_type, i, ret;
  1057. list_for_each_entry(dev, &bus->devices, bus_list) {
  1058. struct pci_bus *b = dev->subordinate;
  1059. if (!b)
  1060. continue;
  1061. switch (dev->hdr_type) {
  1062. case PCI_HEADER_TYPE_CARDBUS:
  1063. pci_bus_size_cardbus(b, realloc_head);
  1064. break;
  1065. case PCI_HEADER_TYPE_BRIDGE:
  1066. default:
  1067. __pci_bus_size_bridges(b, realloc_head);
  1068. break;
  1069. }
  1070. }
  1071. /* The root bus? */
  1072. if (pci_is_root_bus(bus)) {
  1073. host = to_pci_host_bridge(bus->bridge);
  1074. if (!host->size_windows)
  1075. return;
  1076. pci_bus_for_each_resource(bus, pref, i)
  1077. if (pref && (pref->flags & IORESOURCE_PREFETCH))
  1078. break;
  1079. hdr_type = -1; /* Intentionally invalid - not a PCI device. */
  1080. } else {
  1081. pref = &bus->self->resource[PCI_BRIDGE_PREF_MEM_WINDOW];
  1082. hdr_type = bus->self->hdr_type;
  1083. }
  1084. switch (hdr_type) {
  1085. case PCI_HEADER_TYPE_CARDBUS:
  1086. /* Don't size CardBuses yet */
  1087. break;
  1088. case PCI_HEADER_TYPE_BRIDGE:
  1089. pci_bridge_check_ranges(bus);
  1090. if (bus->self->is_hotplug_bridge) {
  1091. additional_io_size = pci_hotplug_io_size;
  1092. additional_mmio_size = pci_hotplug_mmio_size;
  1093. additional_mmio_pref_size = pci_hotplug_mmio_pref_size;
  1094. }
  1095. fallthrough;
  1096. default:
  1097. pbus_size_io(bus, realloc_head ? 0 : additional_io_size,
  1098. additional_io_size, realloc_head);
  1099. /*
  1100. * If there's a 64-bit prefetchable MMIO window, compute
  1101. * the size required to put all 64-bit prefetchable
  1102. * resources in it.
  1103. */
  1104. mask = IORESOURCE_MEM;
  1105. prefmask = IORESOURCE_MEM | IORESOURCE_PREFETCH;
  1106. if (pref && (pref->flags & IORESOURCE_MEM_64)) {
  1107. prefmask |= IORESOURCE_MEM_64;
  1108. ret = pbus_size_mem(bus, prefmask, prefmask,
  1109. prefmask, prefmask,
  1110. realloc_head ? 0 : additional_mmio_pref_size,
  1111. additional_mmio_pref_size, realloc_head);
  1112. /*
  1113. * If successful, all non-prefetchable resources
  1114. * and any 32-bit prefetchable resources will go in
  1115. * the non-prefetchable window.
  1116. */
  1117. if (ret == 0) {
  1118. mask = prefmask;
  1119. type2 = prefmask & ~IORESOURCE_MEM_64;
  1120. type3 = prefmask & ~IORESOURCE_PREFETCH;
  1121. }
  1122. }
  1123. /*
  1124. * If there is no 64-bit prefetchable window, compute the
  1125. * size required to put all prefetchable resources in the
  1126. * 32-bit prefetchable window (if there is one).
  1127. */
  1128. if (!type2) {
  1129. prefmask &= ~IORESOURCE_MEM_64;
  1130. ret = pbus_size_mem(bus, prefmask, prefmask,
  1131. prefmask, prefmask,
  1132. realloc_head ? 0 : additional_mmio_pref_size,
  1133. additional_mmio_pref_size, realloc_head);
  1134. /*
  1135. * If successful, only non-prefetchable resources
  1136. * will go in the non-prefetchable window.
  1137. */
  1138. if (ret == 0)
  1139. mask = prefmask;
  1140. else
  1141. additional_mmio_size += additional_mmio_pref_size;
  1142. type2 = type3 = IORESOURCE_MEM;
  1143. }
  1144. /*
  1145. * Compute the size required to put everything else in the
  1146. * non-prefetchable window. This includes:
  1147. *
  1148. * - all non-prefetchable resources
  1149. * - 32-bit prefetchable resources if there's a 64-bit
  1150. * prefetchable window or no prefetchable window at all
  1151. * - 64-bit prefetchable resources if there's no prefetchable
  1152. * window at all
  1153. *
  1154. * Note that the strategy in __pci_assign_resource() must match
  1155. * that used here. Specifically, we cannot put a 32-bit
  1156. * prefetchable resource in a 64-bit prefetchable window.
  1157. */
  1158. pbus_size_mem(bus, mask, IORESOURCE_MEM, type2, type3,
  1159. realloc_head ? 0 : additional_mmio_size,
  1160. additional_mmio_size, realloc_head);
  1161. break;
  1162. }
  1163. }
  1164. void pci_bus_size_bridges(struct pci_bus *bus)
  1165. {
  1166. __pci_bus_size_bridges(bus, NULL);
  1167. }
  1168. EXPORT_SYMBOL(pci_bus_size_bridges);
  1169. static void assign_fixed_resource_on_bus(struct pci_bus *b, struct resource *r)
  1170. {
  1171. int i;
  1172. struct resource *parent_r;
  1173. unsigned long mask = IORESOURCE_IO | IORESOURCE_MEM |
  1174. IORESOURCE_PREFETCH;
  1175. pci_bus_for_each_resource(b, parent_r, i) {
  1176. if (!parent_r)
  1177. continue;
  1178. if ((r->flags & mask) == (parent_r->flags & mask) &&
  1179. resource_contains(parent_r, r))
  1180. request_resource(parent_r, r);
  1181. }
  1182. }
  1183. /*
  1184. * Try to assign any resources marked as IORESOURCE_PCI_FIXED, as they are
  1185. * skipped by pbus_assign_resources_sorted().
  1186. */
  1187. static void pdev_assign_fixed_resources(struct pci_dev *dev)
  1188. {
  1189. int i;
  1190. for (i = 0; i < PCI_NUM_RESOURCES; i++) {
  1191. struct pci_bus *b;
  1192. struct resource *r = &dev->resource[i];
  1193. if (r->parent || !(r->flags & IORESOURCE_PCI_FIXED) ||
  1194. !(r->flags & (IORESOURCE_IO | IORESOURCE_MEM)))
  1195. continue;
  1196. b = dev->bus;
  1197. while (b && !r->parent) {
  1198. assign_fixed_resource_on_bus(b, r);
  1199. b = b->parent;
  1200. }
  1201. }
  1202. }
  1203. void __pci_bus_assign_resources(const struct pci_bus *bus,
  1204. struct list_head *realloc_head,
  1205. struct list_head *fail_head)
  1206. {
  1207. struct pci_bus *b;
  1208. struct pci_dev *dev;
  1209. pbus_assign_resources_sorted(bus, realloc_head, fail_head);
  1210. list_for_each_entry(dev, &bus->devices, bus_list) {
  1211. pdev_assign_fixed_resources(dev);
  1212. b = dev->subordinate;
  1213. if (!b)
  1214. continue;
  1215. __pci_bus_assign_resources(b, realloc_head, fail_head);
  1216. switch (dev->hdr_type) {
  1217. case PCI_HEADER_TYPE_BRIDGE:
  1218. if (!pci_is_enabled(dev))
  1219. pci_setup_bridge(b);
  1220. break;
  1221. case PCI_HEADER_TYPE_CARDBUS:
  1222. pci_setup_cardbus(b);
  1223. break;
  1224. default:
  1225. pci_info(dev, "not setting up bridge for bus %04x:%02x\n",
  1226. pci_domain_nr(b), b->number);
  1227. break;
  1228. }
  1229. }
  1230. }
  1231. void pci_bus_assign_resources(const struct pci_bus *bus)
  1232. {
  1233. __pci_bus_assign_resources(bus, NULL, NULL);
  1234. }
  1235. EXPORT_SYMBOL(pci_bus_assign_resources);
  1236. static void pci_claim_device_resources(struct pci_dev *dev)
  1237. {
  1238. int i;
  1239. for (i = 0; i < PCI_BRIDGE_RESOURCES; i++) {
  1240. struct resource *r = &dev->resource[i];
  1241. if (!r->flags || r->parent)
  1242. continue;
  1243. pci_claim_resource(dev, i);
  1244. }
  1245. }
  1246. static void pci_claim_bridge_resources(struct pci_dev *dev)
  1247. {
  1248. int i;
  1249. for (i = PCI_BRIDGE_RESOURCES; i < PCI_NUM_RESOURCES; i++) {
  1250. struct resource *r = &dev->resource[i];
  1251. if (!r->flags || r->parent)
  1252. continue;
  1253. pci_claim_bridge_resource(dev, i);
  1254. }
  1255. }
  1256. static void pci_bus_allocate_dev_resources(struct pci_bus *b)
  1257. {
  1258. struct pci_dev *dev;
  1259. struct pci_bus *child;
  1260. list_for_each_entry(dev, &b->devices, bus_list) {
  1261. pci_claim_device_resources(dev);
  1262. child = dev->subordinate;
  1263. if (child)
  1264. pci_bus_allocate_dev_resources(child);
  1265. }
  1266. }
  1267. static void pci_bus_allocate_resources(struct pci_bus *b)
  1268. {
  1269. struct pci_bus *child;
  1270. /*
  1271. * Carry out a depth-first search on the PCI bus tree to allocate
  1272. * bridge apertures. Read the programmed bridge bases and
  1273. * recursively claim the respective bridge resources.
  1274. */
  1275. if (b->self) {
  1276. pci_read_bridge_bases(b);
  1277. pci_claim_bridge_resources(b->self);
  1278. }
  1279. list_for_each_entry(child, &b->children, node)
  1280. pci_bus_allocate_resources(child);
  1281. }
  1282. void pci_bus_claim_resources(struct pci_bus *b)
  1283. {
  1284. pci_bus_allocate_resources(b);
  1285. pci_bus_allocate_dev_resources(b);
  1286. }
  1287. EXPORT_SYMBOL(pci_bus_claim_resources);
  1288. static void __pci_bridge_assign_resources(const struct pci_dev *bridge,
  1289. struct list_head *add_head,
  1290. struct list_head *fail_head)
  1291. {
  1292. struct pci_bus *b;
  1293. pdev_assign_resources_sorted((struct pci_dev *)bridge,
  1294. add_head, fail_head);
  1295. b = bridge->subordinate;
  1296. if (!b)
  1297. return;
  1298. __pci_bus_assign_resources(b, add_head, fail_head);
  1299. switch (bridge->class >> 8) {
  1300. case PCI_CLASS_BRIDGE_PCI:
  1301. pci_setup_bridge(b);
  1302. break;
  1303. case PCI_CLASS_BRIDGE_CARDBUS:
  1304. pci_setup_cardbus(b);
  1305. break;
  1306. default:
  1307. pci_info(bridge, "not setting up bridge for bus %04x:%02x\n",
  1308. pci_domain_nr(b), b->number);
  1309. break;
  1310. }
  1311. }
  1312. #define PCI_RES_TYPE_MASK \
  1313. (IORESOURCE_IO | IORESOURCE_MEM | IORESOURCE_PREFETCH |\
  1314. IORESOURCE_MEM_64)
  1315. static void pci_bridge_release_resources(struct pci_bus *bus,
  1316. unsigned long type)
  1317. {
  1318. struct pci_dev *dev = bus->self;
  1319. struct resource *r;
  1320. unsigned old_flags = 0;
  1321. struct resource *b_res;
  1322. int idx = 1;
  1323. b_res = &dev->resource[PCI_BRIDGE_RESOURCES];
  1324. /*
  1325. * 1. If IO port assignment fails, release bridge IO port.
  1326. * 2. If non pref MMIO assignment fails, release bridge nonpref MMIO.
  1327. * 3. If 64bit pref MMIO assignment fails, and bridge pref is 64bit,
  1328. * release bridge pref MMIO.
  1329. * 4. If pref MMIO assignment fails, and bridge pref is 32bit,
  1330. * release bridge pref MMIO.
  1331. * 5. If pref MMIO assignment fails, and bridge pref is not
  1332. * assigned, release bridge nonpref MMIO.
  1333. */
  1334. if (type & IORESOURCE_IO)
  1335. idx = 0;
  1336. else if (!(type & IORESOURCE_PREFETCH))
  1337. idx = 1;
  1338. else if ((type & IORESOURCE_MEM_64) &&
  1339. (b_res[2].flags & IORESOURCE_MEM_64))
  1340. idx = 2;
  1341. else if (!(b_res[2].flags & IORESOURCE_MEM_64) &&
  1342. (b_res[2].flags & IORESOURCE_PREFETCH))
  1343. idx = 2;
  1344. else
  1345. idx = 1;
  1346. r = &b_res[idx];
  1347. if (!r->parent)
  1348. return;
  1349. /* If there are children, release them all */
  1350. release_child_resources(r);
  1351. if (!release_resource(r)) {
  1352. type = old_flags = r->flags & PCI_RES_TYPE_MASK;
  1353. pci_info(dev, "resource %d %pR released\n",
  1354. PCI_BRIDGE_RESOURCES + idx, r);
  1355. /* Keep the old size */
  1356. r->end = resource_size(r) - 1;
  1357. r->start = 0;
  1358. r->flags = 0;
  1359. /* Avoiding touch the one without PREF */
  1360. if (type & IORESOURCE_PREFETCH)
  1361. type = IORESOURCE_PREFETCH;
  1362. __pci_setup_bridge(bus, type);
  1363. /* For next child res under same bridge */
  1364. r->flags = old_flags;
  1365. }
  1366. }
  1367. enum release_type {
  1368. leaf_only,
  1369. whole_subtree,
  1370. };
  1371. /*
  1372. * Try to release PCI bridge resources from leaf bridge, so we can allocate
  1373. * a larger window later.
  1374. */
  1375. static void pci_bus_release_bridge_resources(struct pci_bus *bus,
  1376. unsigned long type,
  1377. enum release_type rel_type)
  1378. {
  1379. struct pci_dev *dev;
  1380. bool is_leaf_bridge = true;
  1381. list_for_each_entry(dev, &bus->devices, bus_list) {
  1382. struct pci_bus *b = dev->subordinate;
  1383. if (!b)
  1384. continue;
  1385. is_leaf_bridge = false;
  1386. if ((dev->class >> 8) != PCI_CLASS_BRIDGE_PCI)
  1387. continue;
  1388. if (rel_type == whole_subtree)
  1389. pci_bus_release_bridge_resources(b, type,
  1390. whole_subtree);
  1391. }
  1392. if (pci_is_root_bus(bus))
  1393. return;
  1394. if ((bus->self->class >> 8) != PCI_CLASS_BRIDGE_PCI)
  1395. return;
  1396. if ((rel_type == whole_subtree) || is_leaf_bridge)
  1397. pci_bridge_release_resources(bus, type);
  1398. }
  1399. static void pci_bus_dump_res(struct pci_bus *bus)
  1400. {
  1401. struct resource *res;
  1402. int i;
  1403. pci_bus_for_each_resource(bus, res, i) {
  1404. if (!res || !res->end || !res->flags)
  1405. continue;
  1406. dev_info(&bus->dev, "resource %d %pR\n", i, res);
  1407. }
  1408. }
  1409. static void pci_bus_dump_resources(struct pci_bus *bus)
  1410. {
  1411. struct pci_bus *b;
  1412. struct pci_dev *dev;
  1413. pci_bus_dump_res(bus);
  1414. list_for_each_entry(dev, &bus->devices, bus_list) {
  1415. b = dev->subordinate;
  1416. if (!b)
  1417. continue;
  1418. pci_bus_dump_resources(b);
  1419. }
  1420. }
  1421. static int pci_bus_get_depth(struct pci_bus *bus)
  1422. {
  1423. int depth = 0;
  1424. struct pci_bus *child_bus;
  1425. list_for_each_entry(child_bus, &bus->children, node) {
  1426. int ret;
  1427. ret = pci_bus_get_depth(child_bus);
  1428. if (ret + 1 > depth)
  1429. depth = ret + 1;
  1430. }
  1431. return depth;
  1432. }
  1433. /*
  1434. * -1: undefined, will auto detect later
  1435. * 0: disabled by user
  1436. * 1: disabled by auto detect
  1437. * 2: enabled by user
  1438. * 3: enabled by auto detect
  1439. */
  1440. enum enable_type {
  1441. undefined = -1,
  1442. user_disabled,
  1443. auto_disabled,
  1444. user_enabled,
  1445. auto_enabled,
  1446. };
  1447. static enum enable_type pci_realloc_enable = undefined;
  1448. void __init pci_realloc_get_opt(char *str)
  1449. {
  1450. if (!strncmp(str, "off", 3))
  1451. pci_realloc_enable = user_disabled;
  1452. else if (!strncmp(str, "on", 2))
  1453. pci_realloc_enable = user_enabled;
  1454. }
  1455. static bool pci_realloc_enabled(enum enable_type enable)
  1456. {
  1457. return enable >= user_enabled;
  1458. }
  1459. #if defined(CONFIG_PCI_IOV) && defined(CONFIG_PCI_REALLOC_ENABLE_AUTO)
  1460. static int iov_resources_unassigned(struct pci_dev *dev, void *data)
  1461. {
  1462. int i;
  1463. bool *unassigned = data;
  1464. for (i = 0; i < PCI_SRIOV_NUM_BARS; i++) {
  1465. struct resource *r = &dev->resource[i + PCI_IOV_RESOURCES];
  1466. struct pci_bus_region region;
  1467. /* Not assigned or rejected by kernel? */
  1468. if (!r->flags)
  1469. continue;
  1470. pcibios_resource_to_bus(dev->bus, &region, r);
  1471. if (!region.start) {
  1472. *unassigned = true;
  1473. return 1; /* Return early from pci_walk_bus() */
  1474. }
  1475. }
  1476. return 0;
  1477. }
  1478. static enum enable_type pci_realloc_detect(struct pci_bus *bus,
  1479. enum enable_type enable_local)
  1480. {
  1481. bool unassigned = false;
  1482. struct pci_host_bridge *host;
  1483. if (enable_local != undefined)
  1484. return enable_local;
  1485. host = pci_find_host_bridge(bus);
  1486. if (host->preserve_config)
  1487. return auto_disabled;
  1488. pci_walk_bus(bus, iov_resources_unassigned, &unassigned);
  1489. if (unassigned)
  1490. return auto_enabled;
  1491. return enable_local;
  1492. }
  1493. #else
  1494. static enum enable_type pci_realloc_detect(struct pci_bus *bus,
  1495. enum enable_type enable_local)
  1496. {
  1497. return enable_local;
  1498. }
  1499. #endif
  1500. /*
  1501. * First try will not touch PCI bridge res.
  1502. * Second and later try will clear small leaf bridge res.
  1503. * Will stop till to the max depth if can not find good one.
  1504. */
  1505. void pci_assign_unassigned_root_bus_resources(struct pci_bus *bus)
  1506. {
  1507. LIST_HEAD(realloc_head);
  1508. /* List of resources that want additional resources */
  1509. struct list_head *add_list = NULL;
  1510. int tried_times = 0;
  1511. enum release_type rel_type = leaf_only;
  1512. LIST_HEAD(fail_head);
  1513. struct pci_dev_resource *fail_res;
  1514. int pci_try_num = 1;
  1515. enum enable_type enable_local;
  1516. /* Don't realloc if asked to do so */
  1517. enable_local = pci_realloc_detect(bus, pci_realloc_enable);
  1518. if (pci_realloc_enabled(enable_local)) {
  1519. int max_depth = pci_bus_get_depth(bus);
  1520. pci_try_num = max_depth + 1;
  1521. dev_info(&bus->dev, "max bus depth: %d pci_try_num: %d\n",
  1522. max_depth, pci_try_num);
  1523. }
  1524. again:
  1525. /*
  1526. * Last try will use add_list, otherwise will try good to have as must
  1527. * have, so can realloc parent bridge resource
  1528. */
  1529. if (tried_times + 1 == pci_try_num)
  1530. add_list = &realloc_head;
  1531. /*
  1532. * Depth first, calculate sizes and alignments of all subordinate buses.
  1533. */
  1534. __pci_bus_size_bridges(bus, add_list);
  1535. /* Depth last, allocate resources and update the hardware. */
  1536. __pci_bus_assign_resources(bus, add_list, &fail_head);
  1537. if (add_list)
  1538. BUG_ON(!list_empty(add_list));
  1539. tried_times++;
  1540. /* Any device complain? */
  1541. if (list_empty(&fail_head))
  1542. goto dump;
  1543. if (tried_times >= pci_try_num) {
  1544. if (enable_local == undefined)
  1545. dev_info(&bus->dev, "Some PCI device resources are unassigned, try booting with pci=realloc\n");
  1546. else if (enable_local == auto_enabled)
  1547. dev_info(&bus->dev, "Automatically enabled pci realloc, if you have problem, try booting with pci=realloc=off\n");
  1548. free_list(&fail_head);
  1549. goto dump;
  1550. }
  1551. dev_info(&bus->dev, "No. %d try to assign unassigned res\n",
  1552. tried_times + 1);
  1553. /* Third times and later will not check if it is leaf */
  1554. if ((tried_times + 1) > 2)
  1555. rel_type = whole_subtree;
  1556. /*
  1557. * Try to release leaf bridge's resources that doesn't fit resource of
  1558. * child device under that bridge.
  1559. */
  1560. list_for_each_entry(fail_res, &fail_head, list)
  1561. pci_bus_release_bridge_resources(fail_res->dev->bus,
  1562. fail_res->flags & PCI_RES_TYPE_MASK,
  1563. rel_type);
  1564. /* Restore size and flags */
  1565. list_for_each_entry(fail_res, &fail_head, list) {
  1566. struct resource *res = fail_res->res;
  1567. int idx;
  1568. res->start = fail_res->start;
  1569. res->end = fail_res->end;
  1570. res->flags = fail_res->flags;
  1571. if (pci_is_bridge(fail_res->dev)) {
  1572. idx = res - &fail_res->dev->resource[0];
  1573. if (idx >= PCI_BRIDGE_RESOURCES &&
  1574. idx <= PCI_BRIDGE_RESOURCE_END)
  1575. res->flags = 0;
  1576. }
  1577. }
  1578. free_list(&fail_head);
  1579. goto again;
  1580. dump:
  1581. /* Dump the resource on buses */
  1582. pci_bus_dump_resources(bus);
  1583. }
  1584. void __init pci_assign_unassigned_resources(void)
  1585. {
  1586. struct pci_bus *root_bus;
  1587. list_for_each_entry(root_bus, &pci_root_buses, node) {
  1588. pci_assign_unassigned_root_bus_resources(root_bus);
  1589. /* Make sure the root bridge has a companion ACPI device */
  1590. if (ACPI_HANDLE(root_bus->bridge))
  1591. acpi_ioapic_add(ACPI_HANDLE(root_bus->bridge));
  1592. }
  1593. }
  1594. static void adjust_bridge_window(struct pci_dev *bridge, struct resource *res,
  1595. struct list_head *add_list,
  1596. resource_size_t new_size)
  1597. {
  1598. resource_size_t add_size, size = resource_size(res);
  1599. if (res->parent)
  1600. return;
  1601. if (!new_size)
  1602. return;
  1603. if (new_size > size) {
  1604. add_size = new_size - size;
  1605. pci_dbg(bridge, "bridge window %pR extended by %pa\n", res,
  1606. &add_size);
  1607. } else if (new_size < size) {
  1608. add_size = size - new_size;
  1609. pci_dbg(bridge, "bridge window %pR shrunken by %pa\n", res,
  1610. &add_size);
  1611. }
  1612. res->end = res->start + new_size - 1;
  1613. remove_from_list(add_list, res);
  1614. }
  1615. static void pci_bus_distribute_available_resources(struct pci_bus *bus,
  1616. struct list_head *add_list,
  1617. struct resource io,
  1618. struct resource mmio,
  1619. struct resource mmio_pref)
  1620. {
  1621. unsigned int normal_bridges = 0, hotplug_bridges = 0;
  1622. struct resource *io_res, *mmio_res, *mmio_pref_res;
  1623. struct pci_dev *dev, *bridge = bus->self;
  1624. resource_size_t io_per_hp, mmio_per_hp, mmio_pref_per_hp, align;
  1625. io_res = &bridge->resource[PCI_BRIDGE_IO_WINDOW];
  1626. mmio_res = &bridge->resource[PCI_BRIDGE_MEM_WINDOW];
  1627. mmio_pref_res = &bridge->resource[PCI_BRIDGE_PREF_MEM_WINDOW];
  1628. /*
  1629. * The alignment of this bridge is yet to be considered, hence it must
  1630. * be done now before extending its bridge window.
  1631. */
  1632. align = pci_resource_alignment(bridge, io_res);
  1633. if (!io_res->parent && align)
  1634. io.start = min(ALIGN(io.start, align), io.end + 1);
  1635. align = pci_resource_alignment(bridge, mmio_res);
  1636. if (!mmio_res->parent && align)
  1637. mmio.start = min(ALIGN(mmio.start, align), mmio.end + 1);
  1638. align = pci_resource_alignment(bridge, mmio_pref_res);
  1639. if (!mmio_pref_res->parent && align)
  1640. mmio_pref.start = min(ALIGN(mmio_pref.start, align),
  1641. mmio_pref.end + 1);
  1642. /*
  1643. * Now that we have adjusted for alignment, update the bridge window
  1644. * resources to fill as much remaining resource space as possible.
  1645. */
  1646. adjust_bridge_window(bridge, io_res, add_list, resource_size(&io));
  1647. adjust_bridge_window(bridge, mmio_res, add_list, resource_size(&mmio));
  1648. adjust_bridge_window(bridge, mmio_pref_res, add_list,
  1649. resource_size(&mmio_pref));
  1650. /*
  1651. * Calculate how many hotplug bridges and normal bridges there
  1652. * are on this bus. We will distribute the additional available
  1653. * resources between hotplug bridges.
  1654. */
  1655. for_each_pci_bridge(dev, bus) {
  1656. if (dev->is_hotplug_bridge)
  1657. hotplug_bridges++;
  1658. else
  1659. normal_bridges++;
  1660. }
  1661. /*
  1662. * There is only one bridge on the bus so it gets all available
  1663. * resources which it can then distribute to the possible hotplug
  1664. * bridges below.
  1665. */
  1666. if (hotplug_bridges + normal_bridges == 1) {
  1667. dev = list_first_entry(&bus->devices, struct pci_dev, bus_list);
  1668. if (dev->subordinate)
  1669. pci_bus_distribute_available_resources(dev->subordinate,
  1670. add_list, io, mmio, mmio_pref);
  1671. return;
  1672. }
  1673. if (hotplug_bridges == 0)
  1674. return;
  1675. /*
  1676. * Calculate the total amount of extra resource space we can
  1677. * pass to bridges below this one. This is basically the
  1678. * extra space reduced by the minimal required space for the
  1679. * non-hotplug bridges.
  1680. */
  1681. for_each_pci_bridge(dev, bus) {
  1682. resource_size_t used_size;
  1683. struct resource *res;
  1684. if (dev->is_hotplug_bridge)
  1685. continue;
  1686. /*
  1687. * Reduce the available resource space by what the
  1688. * bridge and devices below it occupy.
  1689. */
  1690. res = &dev->resource[PCI_BRIDGE_IO_WINDOW];
  1691. align = pci_resource_alignment(dev, res);
  1692. align = align ? ALIGN(io.start, align) - io.start : 0;
  1693. used_size = align + resource_size(res);
  1694. if (!res->parent)
  1695. io.start = min(io.start + used_size, io.end + 1);
  1696. res = &dev->resource[PCI_BRIDGE_MEM_WINDOW];
  1697. align = pci_resource_alignment(dev, res);
  1698. align = align ? ALIGN(mmio.start, align) - mmio.start : 0;
  1699. used_size = align + resource_size(res);
  1700. if (!res->parent)
  1701. mmio.start = min(mmio.start + used_size, mmio.end + 1);
  1702. res = &dev->resource[PCI_BRIDGE_PREF_MEM_WINDOW];
  1703. align = pci_resource_alignment(dev, res);
  1704. align = align ? ALIGN(mmio_pref.start, align) -
  1705. mmio_pref.start : 0;
  1706. used_size = align + resource_size(res);
  1707. if (!res->parent)
  1708. mmio_pref.start = min(mmio_pref.start + used_size,
  1709. mmio_pref.end + 1);
  1710. }
  1711. io_per_hp = div64_ul(resource_size(&io), hotplug_bridges);
  1712. mmio_per_hp = div64_ul(resource_size(&mmio), hotplug_bridges);
  1713. mmio_pref_per_hp = div64_ul(resource_size(&mmio_pref),
  1714. hotplug_bridges);
  1715. /*
  1716. * Go over devices on this bus and distribute the remaining
  1717. * resource space between hotplug bridges.
  1718. */
  1719. for_each_pci_bridge(dev, bus) {
  1720. struct pci_bus *b;
  1721. b = dev->subordinate;
  1722. if (!b || !dev->is_hotplug_bridge)
  1723. continue;
  1724. /*
  1725. * Distribute available extra resources equally between
  1726. * hotplug-capable downstream ports taking alignment into
  1727. * account.
  1728. */
  1729. io.end = io.start + io_per_hp - 1;
  1730. mmio.end = mmio.start + mmio_per_hp - 1;
  1731. mmio_pref.end = mmio_pref.start + mmio_pref_per_hp - 1;
  1732. pci_bus_distribute_available_resources(b, add_list, io, mmio,
  1733. mmio_pref);
  1734. io.start += io_per_hp;
  1735. mmio.start += mmio_per_hp;
  1736. mmio_pref.start += mmio_pref_per_hp;
  1737. }
  1738. }
  1739. static void pci_bridge_distribute_available_resources(struct pci_dev *bridge,
  1740. struct list_head *add_list)
  1741. {
  1742. struct resource available_io, available_mmio, available_mmio_pref;
  1743. if (!bridge->is_hotplug_bridge)
  1744. return;
  1745. /* Take the initial extra resources from the hotplug port */
  1746. available_io = bridge->resource[PCI_BRIDGE_IO_WINDOW];
  1747. available_mmio = bridge->resource[PCI_BRIDGE_MEM_WINDOW];
  1748. available_mmio_pref = bridge->resource[PCI_BRIDGE_PREF_MEM_WINDOW];
  1749. pci_bus_distribute_available_resources(bridge->subordinate,
  1750. add_list, available_io,
  1751. available_mmio,
  1752. available_mmio_pref);
  1753. }
  1754. void pci_assign_unassigned_bridge_resources(struct pci_dev *bridge)
  1755. {
  1756. struct pci_bus *parent = bridge->subordinate;
  1757. /* List of resources that want additional resources */
  1758. LIST_HEAD(add_list);
  1759. int tried_times = 0;
  1760. LIST_HEAD(fail_head);
  1761. struct pci_dev_resource *fail_res;
  1762. int retval;
  1763. again:
  1764. __pci_bus_size_bridges(parent, &add_list);
  1765. /*
  1766. * Distribute remaining resources (if any) equally between hotplug
  1767. * bridges below. This makes it possible to extend the hierarchy
  1768. * later without running out of resources.
  1769. */
  1770. pci_bridge_distribute_available_resources(bridge, &add_list);
  1771. __pci_bridge_assign_resources(bridge, &add_list, &fail_head);
  1772. BUG_ON(!list_empty(&add_list));
  1773. tried_times++;
  1774. if (list_empty(&fail_head))
  1775. goto enable_all;
  1776. if (tried_times >= 2) {
  1777. /* Still fail, don't need to try more */
  1778. free_list(&fail_head);
  1779. goto enable_all;
  1780. }
  1781. printk(KERN_DEBUG "PCI: No. %d try to assign unassigned res\n",
  1782. tried_times + 1);
  1783. /*
  1784. * Try to release leaf bridge's resources that aren't big enough
  1785. * to contain child device resources.
  1786. */
  1787. list_for_each_entry(fail_res, &fail_head, list)
  1788. pci_bus_release_bridge_resources(fail_res->dev->bus,
  1789. fail_res->flags & PCI_RES_TYPE_MASK,
  1790. whole_subtree);
  1791. /* Restore size and flags */
  1792. list_for_each_entry(fail_res, &fail_head, list) {
  1793. struct resource *res = fail_res->res;
  1794. int idx;
  1795. res->start = fail_res->start;
  1796. res->end = fail_res->end;
  1797. res->flags = fail_res->flags;
  1798. if (pci_is_bridge(fail_res->dev)) {
  1799. idx = res - &fail_res->dev->resource[0];
  1800. if (idx >= PCI_BRIDGE_RESOURCES &&
  1801. idx <= PCI_BRIDGE_RESOURCE_END)
  1802. res->flags = 0;
  1803. }
  1804. }
  1805. free_list(&fail_head);
  1806. goto again;
  1807. enable_all:
  1808. retval = pci_reenable_device(bridge);
  1809. if (retval)
  1810. pci_err(bridge, "Error reenabling bridge (%d)\n", retval);
  1811. pci_set_master(bridge);
  1812. }
  1813. EXPORT_SYMBOL_GPL(pci_assign_unassigned_bridge_resources);
  1814. int pci_reassign_bridge_resources(struct pci_dev *bridge, unsigned long type)
  1815. {
  1816. struct pci_dev_resource *dev_res;
  1817. struct pci_dev *next;
  1818. LIST_HEAD(saved);
  1819. LIST_HEAD(added);
  1820. LIST_HEAD(failed);
  1821. unsigned int i;
  1822. int ret;
  1823. down_read(&pci_bus_sem);
  1824. /* Walk to the root hub, releasing bridge BARs when possible */
  1825. next = bridge;
  1826. do {
  1827. bridge = next;
  1828. for (i = PCI_BRIDGE_RESOURCES; i < PCI_BRIDGE_RESOURCE_END;
  1829. i++) {
  1830. struct resource *res = &bridge->resource[i];
  1831. if ((res->flags ^ type) & PCI_RES_TYPE_MASK)
  1832. continue;
  1833. /* Ignore BARs which are still in use */
  1834. if (res->child)
  1835. continue;
  1836. ret = add_to_list(&saved, bridge, res, 0, 0);
  1837. if (ret)
  1838. goto cleanup;
  1839. pci_info(bridge, "BAR %d: releasing %pR\n",
  1840. i, res);
  1841. if (res->parent)
  1842. release_resource(res);
  1843. res->start = 0;
  1844. res->end = 0;
  1845. break;
  1846. }
  1847. if (i == PCI_BRIDGE_RESOURCE_END)
  1848. break;
  1849. next = bridge->bus ? bridge->bus->self : NULL;
  1850. } while (next);
  1851. if (list_empty(&saved)) {
  1852. up_read(&pci_bus_sem);
  1853. return -ENOENT;
  1854. }
  1855. __pci_bus_size_bridges(bridge->subordinate, &added);
  1856. __pci_bridge_assign_resources(bridge, &added, &failed);
  1857. BUG_ON(!list_empty(&added));
  1858. if (!list_empty(&failed)) {
  1859. ret = -ENOSPC;
  1860. goto cleanup;
  1861. }
  1862. list_for_each_entry(dev_res, &saved, list) {
  1863. /* Skip the bridge we just assigned resources for */
  1864. if (bridge == dev_res->dev)
  1865. continue;
  1866. bridge = dev_res->dev;
  1867. pci_setup_bridge(bridge->subordinate);
  1868. }
  1869. free_list(&saved);
  1870. up_read(&pci_bus_sem);
  1871. return 0;
  1872. cleanup:
  1873. /* Restore size and flags */
  1874. list_for_each_entry(dev_res, &failed, list) {
  1875. struct resource *res = dev_res->res;
  1876. res->start = dev_res->start;
  1877. res->end = dev_res->end;
  1878. res->flags = dev_res->flags;
  1879. }
  1880. free_list(&failed);
  1881. /* Revert to the old configuration */
  1882. list_for_each_entry(dev_res, &saved, list) {
  1883. struct resource *res = dev_res->res;
  1884. bridge = dev_res->dev;
  1885. i = res - bridge->resource;
  1886. res->start = dev_res->start;
  1887. res->end = dev_res->end;
  1888. res->flags = dev_res->flags;
  1889. pci_claim_resource(bridge, i);
  1890. pci_setup_bridge(bridge->subordinate);
  1891. }
  1892. free_list(&saved);
  1893. up_read(&pci_bus_sem);
  1894. return ret;
  1895. }
  1896. void pci_assign_unassigned_bus_resources(struct pci_bus *bus)
  1897. {
  1898. struct pci_dev *dev;
  1899. /* List of resources that want additional resources */
  1900. LIST_HEAD(add_list);
  1901. down_read(&pci_bus_sem);
  1902. for_each_pci_bridge(dev, bus)
  1903. if (pci_has_subordinate(dev))
  1904. __pci_bus_size_bridges(dev->subordinate, &add_list);
  1905. up_read(&pci_bus_sem);
  1906. __pci_bus_assign_resources(bus, &add_list, NULL);
  1907. BUG_ON(!list_empty(&add_list));
  1908. }
  1909. EXPORT_SYMBOL_GPL(pci_assign_unassigned_bus_resources);