quirks.c 204 KB

1234567891011121314151617181920212223242526272829303132333435363738394041424344454647484950515253545556575859606162636465666768697071727374757677787980818283848586878889909192939495969798991001011021031041051061071081091101111121131141151161171181191201211221231241251261271281291301311321331341351361371381391401411421431441451461471481491501511521531541551561571581591601611621631641651661671681691701711721731741751761771781791801811821831841851861871881891901911921931941951961971981992002012022032042052062072082092102112122132142152162172182192202212222232242252262272282292302312322332342352362372382392402412422432442452462472482492502512522532542552562572582592602612622632642652662672682692702712722732742752762772782792802812822832842852862872882892902912922932942952962972982993003013023033043053063073083093103113123133143153163173183193203213223233243253263273283293303313323333343353363373383393403413423433443453463473483493503513523533543553563573583593603613623633643653663673683693703713723733743753763773783793803813823833843853863873883893903913923933943953963973983994004014024034044054064074084094104114124134144154164174184194204214224234244254264274284294304314324334344354364374384394404414424434444454464474484494504514524534544554564574584594604614624634644654664674684694704714724734744754764774784794804814824834844854864874884894904914924934944954964974984995005015025035045055065075085095105115125135145155165175185195205215225235245255265275285295305315325335345355365375385395405415425435445455465475485495505515525535545555565575585595605615625635645655665675685695705715725735745755765775785795805815825835845855865875885895905915925935945955965975985996006016026036046056066076086096106116126136146156166176186196206216226236246256266276286296306316326336346356366376386396406416426436446456466476486496506516526536546556566576586596606616626636646656666676686696706716726736746756766776786796806816826836846856866876886896906916926936946956966976986997007017027037047057067077087097107117127137147157167177187197207217227237247257267277287297307317327337347357367377387397407417427437447457467477487497507517527537547557567577587597607617627637647657667677687697707717727737747757767777787797807817827837847857867877887897907917927937947957967977987998008018028038048058068078088098108118128138148158168178188198208218228238248258268278288298308318328338348358368378388398408418428438448458468478488498508518528538548558568578588598608618628638648658668678688698708718728738748758768778788798808818828838848858868878888898908918928938948958968978988999009019029039049059069079089099109119129139149159169179189199209219229239249259269279289299309319329339349359369379389399409419429439449459469479489499509519529539549559569579589599609619629639649659669679689699709719729739749759769779789799809819829839849859869879889899909919929939949959969979989991000100110021003100410051006100710081009101010111012101310141015101610171018101910201021102210231024102510261027102810291030103110321033103410351036103710381039104010411042104310441045104610471048104910501051105210531054105510561057105810591060106110621063106410651066106710681069107010711072107310741075107610771078107910801081108210831084108510861087108810891090109110921093109410951096109710981099110011011102110311041105110611071108110911101111111211131114111511161117111811191120112111221123112411251126112711281129113011311132113311341135113611371138113911401141114211431144114511461147114811491150115111521153115411551156115711581159116011611162116311641165116611671168116911701171117211731174117511761177117811791180118111821183118411851186118711881189119011911192119311941195119611971198119912001201120212031204120512061207120812091210121112121213121412151216121712181219122012211222122312241225122612271228122912301231123212331234123512361237123812391240124112421243124412451246124712481249125012511252125312541255125612571258125912601261126212631264126512661267126812691270127112721273127412751276127712781279128012811282128312841285128612871288128912901291129212931294129512961297129812991300130113021303130413051306130713081309131013111312131313141315131613171318131913201321132213231324132513261327132813291330133113321333133413351336133713381339134013411342134313441345134613471348134913501351135213531354135513561357135813591360136113621363136413651366136713681369137013711372137313741375137613771378137913801381138213831384138513861387138813891390139113921393139413951396139713981399140014011402140314041405140614071408140914101411141214131414141514161417141814191420142114221423142414251426142714281429143014311432143314341435143614371438143914401441144214431444144514461447144814491450145114521453145414551456145714581459146014611462146314641465146614671468146914701471147214731474147514761477147814791480148114821483148414851486148714881489149014911492149314941495149614971498149915001501150215031504150515061507150815091510151115121513151415151516151715181519152015211522152315241525152615271528152915301531153215331534153515361537153815391540154115421543154415451546154715481549155015511552155315541555155615571558155915601561156215631564156515661567156815691570157115721573157415751576157715781579158015811582158315841585158615871588158915901591159215931594159515961597159815991600160116021603160416051606160716081609161016111612161316141615161616171618161916201621162216231624162516261627162816291630163116321633163416351636163716381639164016411642164316441645164616471648164916501651165216531654165516561657165816591660166116621663166416651666166716681669167016711672167316741675167616771678167916801681168216831684168516861687168816891690169116921693169416951696169716981699170017011702170317041705170617071708170917101711171217131714171517161717171817191720172117221723172417251726172717281729173017311732173317341735173617371738173917401741174217431744174517461747174817491750175117521753175417551756175717581759176017611762176317641765176617671768176917701771177217731774177517761777177817791780178117821783178417851786178717881789179017911792179317941795179617971798179918001801180218031804180518061807180818091810181118121813181418151816181718181819182018211822182318241825182618271828182918301831183218331834183518361837183818391840184118421843184418451846184718481849185018511852185318541855185618571858185918601861186218631864186518661867186818691870187118721873187418751876187718781879188018811882188318841885188618871888188918901891189218931894189518961897189818991900190119021903190419051906190719081909191019111912191319141915191619171918191919201921192219231924192519261927192819291930193119321933193419351936193719381939194019411942194319441945194619471948194919501951195219531954195519561957195819591960196119621963196419651966196719681969197019711972197319741975197619771978197919801981198219831984198519861987198819891990199119921993199419951996199719981999200020012002200320042005200620072008200920102011201220132014201520162017201820192020202120222023202420252026202720282029203020312032203320342035203620372038203920402041204220432044204520462047204820492050205120522053205420552056205720582059206020612062206320642065206620672068206920702071207220732074207520762077207820792080208120822083208420852086208720882089209020912092209320942095209620972098209921002101210221032104210521062107210821092110211121122113211421152116211721182119212021212122212321242125212621272128212921302131213221332134213521362137213821392140214121422143214421452146214721482149215021512152215321542155215621572158215921602161216221632164216521662167216821692170217121722173217421752176217721782179218021812182218321842185218621872188218921902191219221932194219521962197219821992200220122022203220422052206220722082209221022112212221322142215221622172218221922202221222222232224222522262227222822292230223122322233223422352236223722382239224022412242224322442245224622472248224922502251225222532254225522562257225822592260226122622263226422652266226722682269227022712272227322742275227622772278227922802281228222832284228522862287228822892290229122922293229422952296229722982299230023012302230323042305230623072308230923102311231223132314231523162317231823192320232123222323232423252326232723282329233023312332233323342335233623372338233923402341234223432344234523462347234823492350235123522353235423552356235723582359236023612362236323642365236623672368236923702371237223732374237523762377237823792380238123822383238423852386238723882389239023912392239323942395239623972398239924002401240224032404240524062407240824092410241124122413241424152416241724182419242024212422242324242425242624272428242924302431243224332434243524362437243824392440244124422443244424452446244724482449245024512452245324542455245624572458245924602461246224632464246524662467246824692470247124722473247424752476247724782479248024812482248324842485248624872488248924902491249224932494249524962497249824992500250125022503250425052506250725082509251025112512251325142515251625172518251925202521252225232524252525262527252825292530253125322533253425352536253725382539254025412542254325442545254625472548254925502551255225532554255525562557255825592560256125622563256425652566256725682569257025712572257325742575257625772578257925802581258225832584258525862587258825892590259125922593259425952596259725982599260026012602260326042605260626072608260926102611261226132614261526162617261826192620262126222623262426252626262726282629263026312632263326342635263626372638263926402641264226432644264526462647264826492650265126522653265426552656265726582659266026612662266326642665266626672668266926702671267226732674267526762677267826792680268126822683268426852686268726882689269026912692269326942695269626972698269927002701270227032704270527062707270827092710271127122713271427152716271727182719272027212722272327242725272627272728272927302731273227332734273527362737273827392740274127422743274427452746274727482749275027512752275327542755275627572758275927602761276227632764276527662767276827692770277127722773277427752776277727782779278027812782278327842785278627872788278927902791279227932794279527962797279827992800280128022803280428052806280728082809281028112812281328142815281628172818281928202821282228232824282528262827282828292830283128322833283428352836283728382839284028412842284328442845284628472848284928502851285228532854285528562857285828592860286128622863286428652866286728682869287028712872287328742875287628772878287928802881288228832884288528862887288828892890289128922893289428952896289728982899290029012902290329042905290629072908290929102911291229132914291529162917291829192920292129222923292429252926292729282929293029312932293329342935293629372938293929402941294229432944294529462947294829492950295129522953295429552956295729582959296029612962296329642965296629672968296929702971297229732974297529762977297829792980298129822983298429852986298729882989299029912992299329942995299629972998299930003001300230033004300530063007300830093010301130123013301430153016301730183019302030213022302330243025302630273028302930303031303230333034303530363037303830393040304130423043304430453046304730483049305030513052305330543055305630573058305930603061306230633064306530663067306830693070307130723073307430753076307730783079308030813082308330843085308630873088308930903091309230933094309530963097309830993100310131023103310431053106310731083109311031113112311331143115311631173118311931203121312231233124312531263127312831293130313131323133313431353136313731383139314031413142314331443145314631473148314931503151315231533154315531563157315831593160316131623163316431653166316731683169317031713172317331743175317631773178317931803181318231833184318531863187318831893190319131923193319431953196319731983199320032013202320332043205320632073208320932103211321232133214321532163217321832193220322132223223322432253226322732283229323032313232323332343235323632373238323932403241324232433244324532463247324832493250325132523253325432553256325732583259326032613262326332643265326632673268326932703271327232733274327532763277327832793280328132823283328432853286328732883289329032913292329332943295329632973298329933003301330233033304330533063307330833093310331133123313331433153316331733183319332033213322332333243325332633273328332933303331333233333334333533363337333833393340334133423343334433453346334733483349335033513352335333543355335633573358335933603361336233633364336533663367336833693370337133723373337433753376337733783379338033813382338333843385338633873388338933903391339233933394339533963397339833993400340134023403340434053406340734083409341034113412341334143415341634173418341934203421342234233424342534263427342834293430343134323433343434353436343734383439344034413442344334443445344634473448344934503451345234533454345534563457345834593460346134623463346434653466346734683469347034713472347334743475347634773478347934803481348234833484348534863487348834893490349134923493349434953496349734983499350035013502350335043505350635073508350935103511351235133514351535163517351835193520352135223523352435253526352735283529353035313532353335343535353635373538353935403541354235433544354535463547354835493550355135523553355435553556355735583559356035613562356335643565356635673568356935703571357235733574357535763577357835793580358135823583358435853586358735883589359035913592359335943595359635973598359936003601360236033604360536063607360836093610361136123613361436153616361736183619362036213622362336243625362636273628362936303631363236333634363536363637363836393640364136423643364436453646364736483649365036513652365336543655365636573658365936603661366236633664366536663667366836693670367136723673367436753676367736783679368036813682368336843685368636873688368936903691369236933694369536963697369836993700370137023703370437053706370737083709371037113712371337143715371637173718371937203721372237233724372537263727372837293730373137323733373437353736373737383739374037413742374337443745374637473748374937503751375237533754375537563757375837593760376137623763376437653766376737683769377037713772377337743775377637773778377937803781378237833784378537863787378837893790379137923793379437953796379737983799380038013802380338043805380638073808380938103811381238133814381538163817381838193820382138223823382438253826382738283829383038313832383338343835383638373838383938403841384238433844384538463847384838493850385138523853385438553856385738583859386038613862386338643865386638673868386938703871387238733874387538763877387838793880388138823883388438853886388738883889389038913892389338943895389638973898389939003901390239033904390539063907390839093910391139123913391439153916391739183919392039213922392339243925392639273928392939303931393239333934393539363937393839393940394139423943394439453946394739483949395039513952395339543955395639573958395939603961396239633964396539663967396839693970397139723973397439753976397739783979398039813982398339843985398639873988398939903991399239933994399539963997399839994000400140024003400440054006400740084009401040114012401340144015401640174018401940204021402240234024402540264027402840294030403140324033403440354036403740384039404040414042404340444045404640474048404940504051405240534054405540564057405840594060406140624063406440654066406740684069407040714072407340744075407640774078407940804081408240834084408540864087408840894090409140924093409440954096409740984099410041014102410341044105410641074108410941104111411241134114411541164117411841194120412141224123412441254126412741284129413041314132413341344135413641374138413941404141414241434144414541464147414841494150415141524153415441554156415741584159416041614162416341644165416641674168416941704171417241734174417541764177417841794180418141824183418441854186418741884189419041914192419341944195419641974198419942004201420242034204420542064207420842094210421142124213421442154216421742184219422042214222422342244225422642274228422942304231423242334234423542364237423842394240424142424243424442454246424742484249425042514252425342544255425642574258425942604261426242634264426542664267426842694270427142724273427442754276427742784279428042814282428342844285428642874288428942904291429242934294429542964297429842994300430143024303430443054306430743084309431043114312431343144315431643174318431943204321432243234324432543264327432843294330433143324333433443354336433743384339434043414342434343444345434643474348434943504351435243534354435543564357435843594360436143624363436443654366436743684369437043714372437343744375437643774378437943804381438243834384438543864387438843894390439143924393439443954396439743984399440044014402440344044405440644074408440944104411441244134414441544164417441844194420442144224423442444254426442744284429443044314432443344344435443644374438443944404441444244434444444544464447444844494450445144524453445444554456445744584459446044614462446344644465446644674468446944704471447244734474447544764477447844794480448144824483448444854486448744884489449044914492449344944495449644974498449945004501450245034504450545064507450845094510451145124513451445154516451745184519452045214522452345244525452645274528452945304531453245334534453545364537453845394540454145424543454445454546454745484549455045514552455345544555455645574558455945604561456245634564456545664567456845694570457145724573457445754576457745784579458045814582458345844585458645874588458945904591459245934594459545964597459845994600460146024603460446054606460746084609461046114612461346144615461646174618461946204621462246234624462546264627462846294630463146324633463446354636463746384639464046414642464346444645464646474648464946504651465246534654465546564657465846594660466146624663466446654666466746684669467046714672467346744675467646774678467946804681468246834684468546864687468846894690469146924693469446954696469746984699470047014702470347044705470647074708470947104711471247134714471547164717471847194720472147224723472447254726472747284729473047314732473347344735473647374738473947404741474247434744474547464747474847494750475147524753475447554756475747584759476047614762476347644765476647674768476947704771477247734774477547764777477847794780478147824783478447854786478747884789479047914792479347944795479647974798479948004801480248034804480548064807480848094810481148124813481448154816481748184819482048214822482348244825482648274828482948304831483248334834483548364837483848394840484148424843484448454846484748484849485048514852485348544855485648574858485948604861486248634864486548664867486848694870487148724873487448754876487748784879488048814882488348844885488648874888488948904891489248934894489548964897489848994900490149024903490449054906490749084909491049114912491349144915491649174918491949204921492249234924492549264927492849294930493149324933493449354936493749384939494049414942494349444945494649474948494949504951495249534954495549564957495849594960496149624963496449654966496749684969497049714972497349744975497649774978497949804981498249834984498549864987498849894990499149924993499449954996499749984999500050015002500350045005500650075008500950105011501250135014501550165017501850195020502150225023502450255026502750285029503050315032503350345035503650375038503950405041504250435044504550465047504850495050505150525053505450555056505750585059506050615062506350645065506650675068506950705071507250735074507550765077507850795080508150825083508450855086508750885089509050915092509350945095509650975098509951005101510251035104510551065107510851095110511151125113511451155116511751185119512051215122512351245125512651275128512951305131513251335134513551365137513851395140514151425143514451455146514751485149515051515152515351545155515651575158515951605161516251635164516551665167516851695170517151725173517451755176517751785179518051815182518351845185518651875188518951905191519251935194519551965197519851995200520152025203520452055206520752085209521052115212521352145215521652175218521952205221522252235224522552265227522852295230523152325233523452355236523752385239524052415242524352445245524652475248524952505251525252535254525552565257525852595260526152625263526452655266526752685269527052715272527352745275527652775278527952805281528252835284528552865287528852895290529152925293529452955296529752985299530053015302530353045305530653075308530953105311531253135314531553165317531853195320532153225323532453255326532753285329533053315332533353345335533653375338533953405341534253435344534553465347534853495350535153525353535453555356535753585359536053615362536353645365536653675368536953705371537253735374537553765377537853795380538153825383538453855386538753885389539053915392539353945395539653975398539954005401540254035404540554065407540854095410541154125413541454155416541754185419542054215422542354245425542654275428542954305431543254335434543554365437543854395440544154425443544454455446544754485449545054515452545354545455545654575458545954605461546254635464546554665467546854695470547154725473547454755476547754785479548054815482548354845485548654875488548954905491549254935494549554965497549854995500550155025503550455055506550755085509551055115512551355145515551655175518551955205521552255235524552555265527552855295530553155325533553455355536553755385539554055415542554355445545554655475548554955505551555255535554555555565557555855595560556155625563556455655566556755685569557055715572557355745575557655775578557955805581558255835584558555865587558855895590559155925593559455955596559755985599560056015602560356045605560656075608560956105611561256135614561556165617561856195620562156225623562456255626562756285629563056315632563356345635563656375638563956405641564256435644564556465647564856495650565156525653565456555656565756585659566056615662566356645665566656675668566956705671567256735674567556765677567856795680568156825683568456855686568756885689569056915692569356945695569656975698569957005701570257035704570557065707570857095710571157125713571457155716571757185719572057215722572357245725572657275728572957305731573257335734573557365737573857395740574157425743574457455746574757485749575057515752575357545755575657575758575957605761576257635764576557665767576857695770577157725773577457755776577757785779
  1. // SPDX-License-Identifier: GPL-2.0
  2. /*
  3. * This file contains work-arounds for many known PCI hardware bugs.
  4. * Devices present only on certain architectures (host bridges et cetera)
  5. * should be handled in arch-specific code.
  6. *
  7. * Note: any quirks for hotpluggable devices must _NOT_ be declared __init.
  8. *
  9. * Copyright (c) 1999 Martin Mares <mj@ucw.cz>
  10. *
  11. * Init/reset quirks for USB host controllers should be in the USB quirks
  12. * file, where their drivers can use them.
  13. */
  14. #include <linux/types.h>
  15. #include <linux/kernel.h>
  16. #include <linux/export.h>
  17. #include <linux/pci.h>
  18. #include <linux/init.h>
  19. #include <linux/delay.h>
  20. #include <linux/acpi.h>
  21. #include <linux/dmi.h>
  22. #include <linux/ioport.h>
  23. #include <linux/sched.h>
  24. #include <linux/ktime.h>
  25. #include <linux/mm.h>
  26. #include <linux/nvme.h>
  27. #include <linux/platform_data/x86/apple.h>
  28. #include <linux/pm_runtime.h>
  29. #include <linux/suspend.h>
  30. #include <linux/switchtec.h>
  31. #include <asm/dma.h> /* isa_dma_bridge_buggy */
  32. #include "pci.h"
  33. static ktime_t fixup_debug_start(struct pci_dev *dev,
  34. void (*fn)(struct pci_dev *dev))
  35. {
  36. if (initcall_debug)
  37. pci_info(dev, "calling %pS @ %i\n", fn, task_pid_nr(current));
  38. return ktime_get();
  39. }
  40. static void fixup_debug_report(struct pci_dev *dev, ktime_t calltime,
  41. void (*fn)(struct pci_dev *dev))
  42. {
  43. ktime_t delta, rettime;
  44. unsigned long long duration;
  45. rettime = ktime_get();
  46. delta = ktime_sub(rettime, calltime);
  47. duration = (unsigned long long) ktime_to_ns(delta) >> 10;
  48. if (initcall_debug || duration > 10000)
  49. pci_info(dev, "%pS took %lld usecs\n", fn, duration);
  50. }
  51. static void pci_do_fixups(struct pci_dev *dev, struct pci_fixup *f,
  52. struct pci_fixup *end)
  53. {
  54. ktime_t calltime;
  55. for (; f < end; f++)
  56. if ((f->class == (u32) (dev->class >> f->class_shift) ||
  57. f->class == (u32) PCI_ANY_ID) &&
  58. (f->vendor == dev->vendor ||
  59. f->vendor == (u16) PCI_ANY_ID) &&
  60. (f->device == dev->device ||
  61. f->device == (u16) PCI_ANY_ID)) {
  62. void (*hook)(struct pci_dev *dev);
  63. #ifdef CONFIG_HAVE_ARCH_PREL32_RELOCATIONS
  64. hook = offset_to_ptr(&f->hook_offset);
  65. #else
  66. hook = f->hook;
  67. #endif
  68. calltime = fixup_debug_start(dev, hook);
  69. hook(dev);
  70. fixup_debug_report(dev, calltime, hook);
  71. }
  72. }
  73. extern struct pci_fixup __start_pci_fixups_early[];
  74. extern struct pci_fixup __end_pci_fixups_early[];
  75. extern struct pci_fixup __start_pci_fixups_header[];
  76. extern struct pci_fixup __end_pci_fixups_header[];
  77. extern struct pci_fixup __start_pci_fixups_final[];
  78. extern struct pci_fixup __end_pci_fixups_final[];
  79. extern struct pci_fixup __start_pci_fixups_enable[];
  80. extern struct pci_fixup __end_pci_fixups_enable[];
  81. extern struct pci_fixup __start_pci_fixups_resume[];
  82. extern struct pci_fixup __end_pci_fixups_resume[];
  83. extern struct pci_fixup __start_pci_fixups_resume_early[];
  84. extern struct pci_fixup __end_pci_fixups_resume_early[];
  85. extern struct pci_fixup __start_pci_fixups_suspend[];
  86. extern struct pci_fixup __end_pci_fixups_suspend[];
  87. extern struct pci_fixup __start_pci_fixups_suspend_late[];
  88. extern struct pci_fixup __end_pci_fixups_suspend_late[];
  89. static bool pci_apply_fixup_final_quirks;
  90. void pci_fixup_device(enum pci_fixup_pass pass, struct pci_dev *dev)
  91. {
  92. struct pci_fixup *start, *end;
  93. switch (pass) {
  94. case pci_fixup_early:
  95. start = __start_pci_fixups_early;
  96. end = __end_pci_fixups_early;
  97. break;
  98. case pci_fixup_header:
  99. start = __start_pci_fixups_header;
  100. end = __end_pci_fixups_header;
  101. break;
  102. case pci_fixup_final:
  103. if (!pci_apply_fixup_final_quirks)
  104. return;
  105. start = __start_pci_fixups_final;
  106. end = __end_pci_fixups_final;
  107. break;
  108. case pci_fixup_enable:
  109. start = __start_pci_fixups_enable;
  110. end = __end_pci_fixups_enable;
  111. break;
  112. case pci_fixup_resume:
  113. start = __start_pci_fixups_resume;
  114. end = __end_pci_fixups_resume;
  115. break;
  116. case pci_fixup_resume_early:
  117. start = __start_pci_fixups_resume_early;
  118. end = __end_pci_fixups_resume_early;
  119. break;
  120. case pci_fixup_suspend:
  121. start = __start_pci_fixups_suspend;
  122. end = __end_pci_fixups_suspend;
  123. break;
  124. case pci_fixup_suspend_late:
  125. start = __start_pci_fixups_suspend_late;
  126. end = __end_pci_fixups_suspend_late;
  127. break;
  128. default:
  129. /* stupid compiler warning, you would think with an enum... */
  130. return;
  131. }
  132. pci_do_fixups(dev, start, end);
  133. }
  134. EXPORT_SYMBOL(pci_fixup_device);
  135. static int __init pci_apply_final_quirks(void)
  136. {
  137. struct pci_dev *dev = NULL;
  138. u8 cls = 0;
  139. u8 tmp;
  140. if (pci_cache_line_size)
  141. pr_info("PCI: CLS %u bytes\n", pci_cache_line_size << 2);
  142. pci_apply_fixup_final_quirks = true;
  143. for_each_pci_dev(dev) {
  144. pci_fixup_device(pci_fixup_final, dev);
  145. /*
  146. * If arch hasn't set it explicitly yet, use the CLS
  147. * value shared by all PCI devices. If there's a
  148. * mismatch, fall back to the default value.
  149. */
  150. if (!pci_cache_line_size) {
  151. pci_read_config_byte(dev, PCI_CACHE_LINE_SIZE, &tmp);
  152. if (!cls)
  153. cls = tmp;
  154. if (!tmp || cls == tmp)
  155. continue;
  156. pci_info(dev, "CLS mismatch (%u != %u), using %u bytes\n",
  157. cls << 2, tmp << 2,
  158. pci_dfl_cache_line_size << 2);
  159. pci_cache_line_size = pci_dfl_cache_line_size;
  160. }
  161. }
  162. if (!pci_cache_line_size) {
  163. pr_info("PCI: CLS %u bytes, default %u\n", cls << 2,
  164. pci_dfl_cache_line_size << 2);
  165. pci_cache_line_size = cls ? cls : pci_dfl_cache_line_size;
  166. }
  167. return 0;
  168. }
  169. fs_initcall_sync(pci_apply_final_quirks);
  170. /*
  171. * Decoding should be disabled for a PCI device during BAR sizing to avoid
  172. * conflict. But doing so may cause problems on host bridge and perhaps other
  173. * key system devices. For devices that need to have mmio decoding always-on,
  174. * we need to set the dev->mmio_always_on bit.
  175. */
  176. static void quirk_mmio_always_on(struct pci_dev *dev)
  177. {
  178. dev->mmio_always_on = 1;
  179. }
  180. DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_ANY_ID, PCI_ANY_ID,
  181. PCI_CLASS_BRIDGE_HOST, 8, quirk_mmio_always_on);
  182. /*
  183. * The Mellanox Tavor device gives false positive parity errors. Mark this
  184. * device with a broken_parity_status to allow PCI scanning code to "skip"
  185. * this now blacklisted device.
  186. */
  187. static void quirk_mellanox_tavor(struct pci_dev *dev)
  188. {
  189. dev->broken_parity_status = 1; /* This device gives false positives */
  190. }
  191. DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_MELLANOX, PCI_DEVICE_ID_MELLANOX_TAVOR, quirk_mellanox_tavor);
  192. DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_MELLANOX, PCI_DEVICE_ID_MELLANOX_TAVOR_BRIDGE, quirk_mellanox_tavor);
  193. /*
  194. * Deal with broken BIOSes that neglect to enable passive release,
  195. * which can cause problems in combination with the 82441FX/PPro MTRRs
  196. */
  197. static void quirk_passive_release(struct pci_dev *dev)
  198. {
  199. struct pci_dev *d = NULL;
  200. unsigned char dlc;
  201. /*
  202. * We have to make sure a particular bit is set in the PIIX3
  203. * ISA bridge, so we have to go out and find it.
  204. */
  205. while ((d = pci_get_device(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82371SB_0, d))) {
  206. pci_read_config_byte(d, 0x82, &dlc);
  207. if (!(dlc & 1<<1)) {
  208. pci_info(d, "PIIX3: Enabling Passive Release\n");
  209. dlc |= 1<<1;
  210. pci_write_config_byte(d, 0x82, dlc);
  211. }
  212. }
  213. }
  214. DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82441, quirk_passive_release);
  215. DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82441, quirk_passive_release);
  216. /*
  217. * The VIA VP2/VP3/MVP3 seem to have some 'features'. There may be a
  218. * workaround but VIA don't answer queries. If you happen to have good
  219. * contacts at VIA ask them for me please -- Alan
  220. *
  221. * This appears to be BIOS not version dependent. So presumably there is a
  222. * chipset level fix.
  223. */
  224. static void quirk_isa_dma_hangs(struct pci_dev *dev)
  225. {
  226. if (!isa_dma_bridge_buggy) {
  227. isa_dma_bridge_buggy = 1;
  228. pci_info(dev, "Activating ISA DMA hang workarounds\n");
  229. }
  230. }
  231. /*
  232. * It's not totally clear which chipsets are the problematic ones. We know
  233. * 82C586 and 82C596 variants are affected.
  234. */
  235. DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C586_0, quirk_isa_dma_hangs);
  236. DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C596, quirk_isa_dma_hangs);
  237. DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82371SB_0, quirk_isa_dma_hangs);
  238. DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AL, PCI_DEVICE_ID_AL_M1533, quirk_isa_dma_hangs);
  239. DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_NEC, PCI_DEVICE_ID_NEC_CBUS_1, quirk_isa_dma_hangs);
  240. DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_NEC, PCI_DEVICE_ID_NEC_CBUS_2, quirk_isa_dma_hangs);
  241. DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_NEC, PCI_DEVICE_ID_NEC_CBUS_3, quirk_isa_dma_hangs);
  242. /*
  243. * Intel NM10 "TigerPoint" LPC PM1a_STS.BM_STS must be clear
  244. * for some HT machines to use C4 w/o hanging.
  245. */
  246. static void quirk_tigerpoint_bm_sts(struct pci_dev *dev)
  247. {
  248. u32 pmbase;
  249. u16 pm1a;
  250. pci_read_config_dword(dev, 0x40, &pmbase);
  251. pmbase = pmbase & 0xff80;
  252. pm1a = inw(pmbase);
  253. if (pm1a & 0x10) {
  254. pci_info(dev, FW_BUG "TigerPoint LPC.BM_STS cleared\n");
  255. outw(0x10, pmbase);
  256. }
  257. }
  258. DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_TGP_LPC, quirk_tigerpoint_bm_sts);
  259. /* Chipsets where PCI->PCI transfers vanish or hang */
  260. static void quirk_nopcipci(struct pci_dev *dev)
  261. {
  262. if ((pci_pci_problems & PCIPCI_FAIL) == 0) {
  263. pci_info(dev, "Disabling direct PCI/PCI transfers\n");
  264. pci_pci_problems |= PCIPCI_FAIL;
  265. }
  266. }
  267. DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_5597, quirk_nopcipci);
  268. DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_496, quirk_nopcipci);
  269. static void quirk_nopciamd(struct pci_dev *dev)
  270. {
  271. u8 rev;
  272. pci_read_config_byte(dev, 0x08, &rev);
  273. if (rev == 0x13) {
  274. /* Erratum 24 */
  275. pci_info(dev, "Chipset erratum: Disabling direct PCI/AGP transfers\n");
  276. pci_pci_problems |= PCIAGP_FAIL;
  277. }
  278. }
  279. DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_8151_0, quirk_nopciamd);
  280. /* Triton requires workarounds to be used by the drivers */
  281. static void quirk_triton(struct pci_dev *dev)
  282. {
  283. if ((pci_pci_problems&PCIPCI_TRITON) == 0) {
  284. pci_info(dev, "Limiting direct PCI/PCI transfers\n");
  285. pci_pci_problems |= PCIPCI_TRITON;
  286. }
  287. }
  288. DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82437, quirk_triton);
  289. DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82437VX, quirk_triton);
  290. DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82439, quirk_triton);
  291. DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82439TX, quirk_triton);
  292. /*
  293. * VIA Apollo KT133 needs PCI latency patch
  294. * Made according to a Windows driver-based patch by George E. Breese;
  295. * see PCI Latency Adjust on http://www.viahardware.com/download/viatweak.shtm
  296. * Also see http://www.au-ja.org/review-kt133a-1-en.phtml for the info on
  297. * which Mr Breese based his work.
  298. *
  299. * Updated based on further information from the site and also on
  300. * information provided by VIA
  301. */
  302. static void quirk_vialatency(struct pci_dev *dev)
  303. {
  304. struct pci_dev *p;
  305. u8 busarb;
  306. /*
  307. * Ok, we have a potential problem chipset here. Now see if we have
  308. * a buggy southbridge.
  309. */
  310. p = pci_get_device(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C686, NULL);
  311. if (p != NULL) {
  312. /*
  313. * 0x40 - 0x4f == 686B, 0x10 - 0x2f == 686A;
  314. * thanks Dan Hollis.
  315. * Check for buggy part revisions
  316. */
  317. if (p->revision < 0x40 || p->revision > 0x42)
  318. goto exit;
  319. } else {
  320. p = pci_get_device(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8231, NULL);
  321. if (p == NULL) /* No problem parts */
  322. goto exit;
  323. /* Check for buggy part revisions */
  324. if (p->revision < 0x10 || p->revision > 0x12)
  325. goto exit;
  326. }
  327. /*
  328. * Ok we have the problem. Now set the PCI master grant to occur
  329. * every master grant. The apparent bug is that under high PCI load
  330. * (quite common in Linux of course) you can get data loss when the
  331. * CPU is held off the bus for 3 bus master requests. This happens
  332. * to include the IDE controllers....
  333. *
  334. * VIA only apply this fix when an SB Live! is present but under
  335. * both Linux and Windows this isn't enough, and we have seen
  336. * corruption without SB Live! but with things like 3 UDMA IDE
  337. * controllers. So we ignore that bit of the VIA recommendation..
  338. */
  339. pci_read_config_byte(dev, 0x76, &busarb);
  340. /*
  341. * Set bit 4 and bit 5 of byte 76 to 0x01
  342. * "Master priority rotation on every PCI master grant"
  343. */
  344. busarb &= ~(1<<5);
  345. busarb |= (1<<4);
  346. pci_write_config_byte(dev, 0x76, busarb);
  347. pci_info(dev, "Applying VIA southbridge workaround\n");
  348. exit:
  349. pci_dev_put(p);
  350. }
  351. DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8363_0, quirk_vialatency);
  352. DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8371_1, quirk_vialatency);
  353. DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8361, quirk_vialatency);
  354. /* Must restore this on a resume from RAM */
  355. DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8363_0, quirk_vialatency);
  356. DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8371_1, quirk_vialatency);
  357. DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8361, quirk_vialatency);
  358. /* VIA Apollo VP3 needs ETBF on BT848/878 */
  359. static void quirk_viaetbf(struct pci_dev *dev)
  360. {
  361. if ((pci_pci_problems&PCIPCI_VIAETBF) == 0) {
  362. pci_info(dev, "Limiting direct PCI/PCI transfers\n");
  363. pci_pci_problems |= PCIPCI_VIAETBF;
  364. }
  365. }
  366. DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C597_0, quirk_viaetbf);
  367. static void quirk_vsfx(struct pci_dev *dev)
  368. {
  369. if ((pci_pci_problems&PCIPCI_VSFX) == 0) {
  370. pci_info(dev, "Limiting direct PCI/PCI transfers\n");
  371. pci_pci_problems |= PCIPCI_VSFX;
  372. }
  373. }
  374. DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C576, quirk_vsfx);
  375. /*
  376. * ALi Magik requires workarounds to be used by the drivers that DMA to AGP
  377. * space. Latency must be set to 0xA and Triton workaround applied too.
  378. * [Info kindly provided by ALi]
  379. */
  380. static void quirk_alimagik(struct pci_dev *dev)
  381. {
  382. if ((pci_pci_problems&PCIPCI_ALIMAGIK) == 0) {
  383. pci_info(dev, "Limiting direct PCI/PCI transfers\n");
  384. pci_pci_problems |= PCIPCI_ALIMAGIK|PCIPCI_TRITON;
  385. }
  386. }
  387. DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AL, PCI_DEVICE_ID_AL_M1647, quirk_alimagik);
  388. DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AL, PCI_DEVICE_ID_AL_M1651, quirk_alimagik);
  389. /* Natoma has some interesting boundary conditions with Zoran stuff at least */
  390. static void quirk_natoma(struct pci_dev *dev)
  391. {
  392. if ((pci_pci_problems&PCIPCI_NATOMA) == 0) {
  393. pci_info(dev, "Limiting direct PCI/PCI transfers\n");
  394. pci_pci_problems |= PCIPCI_NATOMA;
  395. }
  396. }
  397. DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82441, quirk_natoma);
  398. DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82443LX_0, quirk_natoma);
  399. DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82443LX_1, quirk_natoma);
  400. DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82443BX_0, quirk_natoma);
  401. DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82443BX_1, quirk_natoma);
  402. DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82443BX_2, quirk_natoma);
  403. /*
  404. * This chip can cause PCI parity errors if config register 0xA0 is read
  405. * while DMAs are occurring.
  406. */
  407. static void quirk_citrine(struct pci_dev *dev)
  408. {
  409. dev->cfg_size = 0xA0;
  410. }
  411. DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_IBM, PCI_DEVICE_ID_IBM_CITRINE, quirk_citrine);
  412. /*
  413. * This chip can cause bus lockups if config addresses above 0x600
  414. * are read or written.
  415. */
  416. static void quirk_nfp6000(struct pci_dev *dev)
  417. {
  418. dev->cfg_size = 0x600;
  419. }
  420. DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_NETRONOME, PCI_DEVICE_ID_NETRONOME_NFP4000, quirk_nfp6000);
  421. DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_NETRONOME, PCI_DEVICE_ID_NETRONOME_NFP6000, quirk_nfp6000);
  422. DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_NETRONOME, PCI_DEVICE_ID_NETRONOME_NFP5000, quirk_nfp6000);
  423. DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_NETRONOME, PCI_DEVICE_ID_NETRONOME_NFP6000_VF, quirk_nfp6000);
  424. /* On IBM Crocodile ipr SAS adapters, expand BAR to system page size */
  425. static void quirk_extend_bar_to_page(struct pci_dev *dev)
  426. {
  427. int i;
  428. for (i = 0; i < PCI_STD_NUM_BARS; i++) {
  429. struct resource *r = &dev->resource[i];
  430. if (r->flags & IORESOURCE_MEM && resource_size(r) < PAGE_SIZE) {
  431. r->end = PAGE_SIZE - 1;
  432. r->start = 0;
  433. r->flags |= IORESOURCE_UNSET;
  434. pci_info(dev, "expanded BAR %d to page size: %pR\n",
  435. i, r);
  436. }
  437. }
  438. }
  439. DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_IBM, 0x034a, quirk_extend_bar_to_page);
  440. /*
  441. * S3 868 and 968 chips report region size equal to 32M, but they decode 64M.
  442. * If it's needed, re-allocate the region.
  443. */
  444. static void quirk_s3_64M(struct pci_dev *dev)
  445. {
  446. struct resource *r = &dev->resource[0];
  447. if ((r->start & 0x3ffffff) || r->end != r->start + 0x3ffffff) {
  448. r->flags |= IORESOURCE_UNSET;
  449. r->start = 0;
  450. r->end = 0x3ffffff;
  451. }
  452. }
  453. DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_S3, PCI_DEVICE_ID_S3_868, quirk_s3_64M);
  454. DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_S3, PCI_DEVICE_ID_S3_968, quirk_s3_64M);
  455. static void quirk_io(struct pci_dev *dev, int pos, unsigned size,
  456. const char *name)
  457. {
  458. u32 region;
  459. struct pci_bus_region bus_region;
  460. struct resource *res = dev->resource + pos;
  461. pci_read_config_dword(dev, PCI_BASE_ADDRESS_0 + (pos << 2), &region);
  462. if (!region)
  463. return;
  464. res->name = pci_name(dev);
  465. res->flags = region & ~PCI_BASE_ADDRESS_IO_MASK;
  466. res->flags |=
  467. (IORESOURCE_IO | IORESOURCE_PCI_FIXED | IORESOURCE_SIZEALIGN);
  468. region &= ~(size - 1);
  469. /* Convert from PCI bus to resource space */
  470. bus_region.start = region;
  471. bus_region.end = region + size - 1;
  472. pcibios_bus_to_resource(dev->bus, res, &bus_region);
  473. pci_info(dev, FW_BUG "%s quirk: reg 0x%x: %pR\n",
  474. name, PCI_BASE_ADDRESS_0 + (pos << 2), res);
  475. }
  476. /*
  477. * Some CS5536 BIOSes (for example, the Soekris NET5501 board w/ comBIOS
  478. * ver. 1.33 20070103) don't set the correct ISA PCI region header info.
  479. * BAR0 should be 8 bytes; instead, it may be set to something like 8k
  480. * (which conflicts w/ BAR1's memory range).
  481. *
  482. * CS553x's ISA PCI BARs may also be read-only (ref:
  483. * https://bugzilla.kernel.org/show_bug.cgi?id=85991 - Comment #4 forward).
  484. */
  485. static void quirk_cs5536_vsa(struct pci_dev *dev)
  486. {
  487. static char *name = "CS5536 ISA bridge";
  488. if (pci_resource_len(dev, 0) != 8) {
  489. quirk_io(dev, 0, 8, name); /* SMB */
  490. quirk_io(dev, 1, 256, name); /* GPIO */
  491. quirk_io(dev, 2, 64, name); /* MFGPT */
  492. pci_info(dev, "%s bug detected (incorrect header); workaround applied\n",
  493. name);
  494. }
  495. }
  496. DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_CS5536_ISA, quirk_cs5536_vsa);
  497. static void quirk_io_region(struct pci_dev *dev, int port,
  498. unsigned size, int nr, const char *name)
  499. {
  500. u16 region;
  501. struct pci_bus_region bus_region;
  502. struct resource *res = dev->resource + nr;
  503. pci_read_config_word(dev, port, &region);
  504. region &= ~(size - 1);
  505. if (!region)
  506. return;
  507. res->name = pci_name(dev);
  508. res->flags = IORESOURCE_IO;
  509. /* Convert from PCI bus to resource space */
  510. bus_region.start = region;
  511. bus_region.end = region + size - 1;
  512. pcibios_bus_to_resource(dev->bus, res, &bus_region);
  513. if (!pci_claim_resource(dev, nr))
  514. pci_info(dev, "quirk: %pR claimed by %s\n", res, name);
  515. }
  516. /*
  517. * ATI Northbridge setups MCE the processor if you even read somewhere
  518. * between 0x3b0->0x3bb or read 0x3d3
  519. */
  520. static void quirk_ati_exploding_mce(struct pci_dev *dev)
  521. {
  522. pci_info(dev, "ATI Northbridge, reserving I/O ports 0x3b0 to 0x3bb\n");
  523. /* Mae rhaid i ni beidio ag edrych ar y lleoliadiau I/O hyn */
  524. request_region(0x3b0, 0x0C, "RadeonIGP");
  525. request_region(0x3d3, 0x01, "RadeonIGP");
  526. }
  527. DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_RS100, quirk_ati_exploding_mce);
  528. /*
  529. * In the AMD NL platform, this device ([1022:7912]) has a class code of
  530. * PCI_CLASS_SERIAL_USB_XHCI (0x0c0330), which means the xhci driver will
  531. * claim it.
  532. *
  533. * But the dwc3 driver is a more specific driver for this device, and we'd
  534. * prefer to use it instead of xhci. To prevent xhci from claiming the
  535. * device, change the class code to 0x0c03fe, which the PCI r3.0 spec
  536. * defines as "USB device (not host controller)". The dwc3 driver can then
  537. * claim it based on its Vendor and Device ID.
  538. */
  539. static void quirk_amd_nl_class(struct pci_dev *pdev)
  540. {
  541. u32 class = pdev->class;
  542. /* Use "USB Device (not host controller)" class */
  543. pdev->class = PCI_CLASS_SERIAL_USB_DEVICE;
  544. pci_info(pdev, "PCI class overridden (%#08x -> %#08x) so dwc3 driver can claim this instead of xhci\n",
  545. class, pdev->class);
  546. }
  547. DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_NL_USB,
  548. quirk_amd_nl_class);
  549. /*
  550. * Synopsys USB 3.x host HAPS platform has a class code of
  551. * PCI_CLASS_SERIAL_USB_XHCI, and xhci driver can claim it. However, these
  552. * devices should use dwc3-haps driver. Change these devices' class code to
  553. * PCI_CLASS_SERIAL_USB_DEVICE to prevent the xhci-pci driver from claiming
  554. * them.
  555. */
  556. static void quirk_synopsys_haps(struct pci_dev *pdev)
  557. {
  558. u32 class = pdev->class;
  559. switch (pdev->device) {
  560. case PCI_DEVICE_ID_SYNOPSYS_HAPSUSB3:
  561. case PCI_DEVICE_ID_SYNOPSYS_HAPSUSB3_AXI:
  562. case PCI_DEVICE_ID_SYNOPSYS_HAPSUSB31:
  563. pdev->class = PCI_CLASS_SERIAL_USB_DEVICE;
  564. pci_info(pdev, "PCI class overridden (%#08x -> %#08x) so dwc3 driver can claim this instead of xhci\n",
  565. class, pdev->class);
  566. break;
  567. }
  568. }
  569. DECLARE_PCI_FIXUP_CLASS_HEADER(PCI_VENDOR_ID_SYNOPSYS, PCI_ANY_ID,
  570. PCI_CLASS_SERIAL_USB_XHCI, 0,
  571. quirk_synopsys_haps);
  572. /*
  573. * Let's make the southbridge information explicit instead of having to
  574. * worry about people probing the ACPI areas, for example.. (Yes, it
  575. * happens, and if you read the wrong ACPI register it will put the machine
  576. * to sleep with no way of waking it up again. Bummer).
  577. *
  578. * ALI M7101: Two IO regions pointed to by words at
  579. * 0xE0 (64 bytes of ACPI registers)
  580. * 0xE2 (32 bytes of SMB registers)
  581. */
  582. static void quirk_ali7101_acpi(struct pci_dev *dev)
  583. {
  584. quirk_io_region(dev, 0xE0, 64, PCI_BRIDGE_RESOURCES, "ali7101 ACPI");
  585. quirk_io_region(dev, 0xE2, 32, PCI_BRIDGE_RESOURCES+1, "ali7101 SMB");
  586. }
  587. DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_AL, PCI_DEVICE_ID_AL_M7101, quirk_ali7101_acpi);
  588. static void piix4_io_quirk(struct pci_dev *dev, const char *name, unsigned int port, unsigned int enable)
  589. {
  590. u32 devres;
  591. u32 mask, size, base;
  592. pci_read_config_dword(dev, port, &devres);
  593. if ((devres & enable) != enable)
  594. return;
  595. mask = (devres >> 16) & 15;
  596. base = devres & 0xffff;
  597. size = 16;
  598. for (;;) {
  599. unsigned bit = size >> 1;
  600. if ((bit & mask) == bit)
  601. break;
  602. size = bit;
  603. }
  604. /*
  605. * For now we only print it out. Eventually we'll want to
  606. * reserve it (at least if it's in the 0x1000+ range), but
  607. * let's get enough confirmation reports first.
  608. */
  609. base &= -size;
  610. pci_info(dev, "%s PIO at %04x-%04x\n", name, base, base + size - 1);
  611. }
  612. static void piix4_mem_quirk(struct pci_dev *dev, const char *name, unsigned int port, unsigned int enable)
  613. {
  614. u32 devres;
  615. u32 mask, size, base;
  616. pci_read_config_dword(dev, port, &devres);
  617. if ((devres & enable) != enable)
  618. return;
  619. base = devres & 0xffff0000;
  620. mask = (devres & 0x3f) << 16;
  621. size = 128 << 16;
  622. for (;;) {
  623. unsigned bit = size >> 1;
  624. if ((bit & mask) == bit)
  625. break;
  626. size = bit;
  627. }
  628. /*
  629. * For now we only print it out. Eventually we'll want to
  630. * reserve it, but let's get enough confirmation reports first.
  631. */
  632. base &= -size;
  633. pci_info(dev, "%s MMIO at %04x-%04x\n", name, base, base + size - 1);
  634. }
  635. /*
  636. * PIIX4 ACPI: Two IO regions pointed to by longwords at
  637. * 0x40 (64 bytes of ACPI registers)
  638. * 0x90 (16 bytes of SMB registers)
  639. * and a few strange programmable PIIX4 device resources.
  640. */
  641. static void quirk_piix4_acpi(struct pci_dev *dev)
  642. {
  643. u32 res_a;
  644. quirk_io_region(dev, 0x40, 64, PCI_BRIDGE_RESOURCES, "PIIX4 ACPI");
  645. quirk_io_region(dev, 0x90, 16, PCI_BRIDGE_RESOURCES+1, "PIIX4 SMB");
  646. /* Device resource A has enables for some of the other ones */
  647. pci_read_config_dword(dev, 0x5c, &res_a);
  648. piix4_io_quirk(dev, "PIIX4 devres B", 0x60, 3 << 21);
  649. piix4_io_quirk(dev, "PIIX4 devres C", 0x64, 3 << 21);
  650. /* Device resource D is just bitfields for static resources */
  651. /* Device 12 enabled? */
  652. if (res_a & (1 << 29)) {
  653. piix4_io_quirk(dev, "PIIX4 devres E", 0x68, 1 << 20);
  654. piix4_mem_quirk(dev, "PIIX4 devres F", 0x6c, 1 << 7);
  655. }
  656. /* Device 13 enabled? */
  657. if (res_a & (1 << 30)) {
  658. piix4_io_quirk(dev, "PIIX4 devres G", 0x70, 1 << 20);
  659. piix4_mem_quirk(dev, "PIIX4 devres H", 0x74, 1 << 7);
  660. }
  661. piix4_io_quirk(dev, "PIIX4 devres I", 0x78, 1 << 20);
  662. piix4_io_quirk(dev, "PIIX4 devres J", 0x7c, 1 << 20);
  663. }
  664. DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82371AB_3, quirk_piix4_acpi);
  665. DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82443MX_3, quirk_piix4_acpi);
  666. #define ICH_PMBASE 0x40
  667. #define ICH_ACPI_CNTL 0x44
  668. #define ICH4_ACPI_EN 0x10
  669. #define ICH6_ACPI_EN 0x80
  670. #define ICH4_GPIOBASE 0x58
  671. #define ICH4_GPIO_CNTL 0x5c
  672. #define ICH4_GPIO_EN 0x10
  673. #define ICH6_GPIOBASE 0x48
  674. #define ICH6_GPIO_CNTL 0x4c
  675. #define ICH6_GPIO_EN 0x10
  676. /*
  677. * ICH4, ICH4-M, ICH5, ICH5-M ACPI: Three IO regions pointed to by longwords at
  678. * 0x40 (128 bytes of ACPI, GPIO & TCO registers)
  679. * 0x58 (64 bytes of GPIO I/O space)
  680. */
  681. static void quirk_ich4_lpc_acpi(struct pci_dev *dev)
  682. {
  683. u8 enable;
  684. /*
  685. * The check for PCIBIOS_MIN_IO is to ensure we won't create a conflict
  686. * with low legacy (and fixed) ports. We don't know the decoding
  687. * priority and can't tell whether the legacy device or the one created
  688. * here is really at that address. This happens on boards with broken
  689. * BIOSes.
  690. */
  691. pci_read_config_byte(dev, ICH_ACPI_CNTL, &enable);
  692. if (enable & ICH4_ACPI_EN)
  693. quirk_io_region(dev, ICH_PMBASE, 128, PCI_BRIDGE_RESOURCES,
  694. "ICH4 ACPI/GPIO/TCO");
  695. pci_read_config_byte(dev, ICH4_GPIO_CNTL, &enable);
  696. if (enable & ICH4_GPIO_EN)
  697. quirk_io_region(dev, ICH4_GPIOBASE, 64, PCI_BRIDGE_RESOURCES+1,
  698. "ICH4 GPIO");
  699. }
  700. DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801AA_0, quirk_ich4_lpc_acpi);
  701. DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801AB_0, quirk_ich4_lpc_acpi);
  702. DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801BA_0, quirk_ich4_lpc_acpi);
  703. DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801BA_10, quirk_ich4_lpc_acpi);
  704. DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801CA_0, quirk_ich4_lpc_acpi);
  705. DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801CA_12, quirk_ich4_lpc_acpi);
  706. DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801DB_0, quirk_ich4_lpc_acpi);
  707. DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801DB_12, quirk_ich4_lpc_acpi);
  708. DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801EB_0, quirk_ich4_lpc_acpi);
  709. DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ESB_1, quirk_ich4_lpc_acpi);
  710. static void ich6_lpc_acpi_gpio(struct pci_dev *dev)
  711. {
  712. u8 enable;
  713. pci_read_config_byte(dev, ICH_ACPI_CNTL, &enable);
  714. if (enable & ICH6_ACPI_EN)
  715. quirk_io_region(dev, ICH_PMBASE, 128, PCI_BRIDGE_RESOURCES,
  716. "ICH6 ACPI/GPIO/TCO");
  717. pci_read_config_byte(dev, ICH6_GPIO_CNTL, &enable);
  718. if (enable & ICH6_GPIO_EN)
  719. quirk_io_region(dev, ICH6_GPIOBASE, 64, PCI_BRIDGE_RESOURCES+1,
  720. "ICH6 GPIO");
  721. }
  722. static void ich6_lpc_generic_decode(struct pci_dev *dev, unsigned reg,
  723. const char *name, int dynsize)
  724. {
  725. u32 val;
  726. u32 size, base;
  727. pci_read_config_dword(dev, reg, &val);
  728. /* Enabled? */
  729. if (!(val & 1))
  730. return;
  731. base = val & 0xfffc;
  732. if (dynsize) {
  733. /*
  734. * This is not correct. It is 16, 32 or 64 bytes depending on
  735. * register D31:F0:ADh bits 5:4.
  736. *
  737. * But this gets us at least _part_ of it.
  738. */
  739. size = 16;
  740. } else {
  741. size = 128;
  742. }
  743. base &= ~(size-1);
  744. /*
  745. * Just print it out for now. We should reserve it after more
  746. * debugging.
  747. */
  748. pci_info(dev, "%s PIO at %04x-%04x\n", name, base, base+size-1);
  749. }
  750. static void quirk_ich6_lpc(struct pci_dev *dev)
  751. {
  752. /* Shared ACPI/GPIO decode with all ICH6+ */
  753. ich6_lpc_acpi_gpio(dev);
  754. /* ICH6-specific generic IO decode */
  755. ich6_lpc_generic_decode(dev, 0x84, "LPC Generic IO decode 1", 0);
  756. ich6_lpc_generic_decode(dev, 0x88, "LPC Generic IO decode 2", 1);
  757. }
  758. DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH6_0, quirk_ich6_lpc);
  759. DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH6_1, quirk_ich6_lpc);
  760. static void ich7_lpc_generic_decode(struct pci_dev *dev, unsigned reg,
  761. const char *name)
  762. {
  763. u32 val;
  764. u32 mask, base;
  765. pci_read_config_dword(dev, reg, &val);
  766. /* Enabled? */
  767. if (!(val & 1))
  768. return;
  769. /* IO base in bits 15:2, mask in bits 23:18, both are dword-based */
  770. base = val & 0xfffc;
  771. mask = (val >> 16) & 0xfc;
  772. mask |= 3;
  773. /*
  774. * Just print it out for now. We should reserve it after more
  775. * debugging.
  776. */
  777. pci_info(dev, "%s PIO at %04x (mask %04x)\n", name, base, mask);
  778. }
  779. /* ICH7-10 has the same common LPC generic IO decode registers */
  780. static void quirk_ich7_lpc(struct pci_dev *dev)
  781. {
  782. /* We share the common ACPI/GPIO decode with ICH6 */
  783. ich6_lpc_acpi_gpio(dev);
  784. /* And have 4 ICH7+ generic decodes */
  785. ich7_lpc_generic_decode(dev, 0x84, "ICH7 LPC Generic IO decode 1");
  786. ich7_lpc_generic_decode(dev, 0x88, "ICH7 LPC Generic IO decode 2");
  787. ich7_lpc_generic_decode(dev, 0x8c, "ICH7 LPC Generic IO decode 3");
  788. ich7_lpc_generic_decode(dev, 0x90, "ICH7 LPC Generic IO decode 4");
  789. }
  790. DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH7_0, quirk_ich7_lpc);
  791. DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH7_1, quirk_ich7_lpc);
  792. DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH7_31, quirk_ich7_lpc);
  793. DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH8_0, quirk_ich7_lpc);
  794. DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH8_2, quirk_ich7_lpc);
  795. DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH8_3, quirk_ich7_lpc);
  796. DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH8_1, quirk_ich7_lpc);
  797. DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH8_4, quirk_ich7_lpc);
  798. DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH9_2, quirk_ich7_lpc);
  799. DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH9_4, quirk_ich7_lpc);
  800. DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH9_7, quirk_ich7_lpc);
  801. DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH9_8, quirk_ich7_lpc);
  802. DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH10_1, quirk_ich7_lpc);
  803. /*
  804. * VIA ACPI: One IO region pointed to by longword at
  805. * 0x48 or 0x20 (256 bytes of ACPI registers)
  806. */
  807. static void quirk_vt82c586_acpi(struct pci_dev *dev)
  808. {
  809. if (dev->revision & 0x10)
  810. quirk_io_region(dev, 0x48, 256, PCI_BRIDGE_RESOURCES,
  811. "vt82c586 ACPI");
  812. }
  813. DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C586_3, quirk_vt82c586_acpi);
  814. /*
  815. * VIA VT82C686 ACPI: Three IO region pointed to by (long)words at
  816. * 0x48 (256 bytes of ACPI registers)
  817. * 0x70 (128 bytes of hardware monitoring register)
  818. * 0x90 (16 bytes of SMB registers)
  819. */
  820. static void quirk_vt82c686_acpi(struct pci_dev *dev)
  821. {
  822. quirk_vt82c586_acpi(dev);
  823. quirk_io_region(dev, 0x70, 128, PCI_BRIDGE_RESOURCES+1,
  824. "vt82c686 HW-mon");
  825. quirk_io_region(dev, 0x90, 16, PCI_BRIDGE_RESOURCES+2, "vt82c686 SMB");
  826. }
  827. DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C686_4, quirk_vt82c686_acpi);
  828. /*
  829. * VIA VT8235 ISA Bridge: Two IO regions pointed to by words at
  830. * 0x88 (128 bytes of power management registers)
  831. * 0xd0 (16 bytes of SMB registers)
  832. */
  833. static void quirk_vt8235_acpi(struct pci_dev *dev)
  834. {
  835. quirk_io_region(dev, 0x88, 128, PCI_BRIDGE_RESOURCES, "vt8235 PM");
  836. quirk_io_region(dev, 0xd0, 16, PCI_BRIDGE_RESOURCES+1, "vt8235 SMB");
  837. }
  838. DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8235, quirk_vt8235_acpi);
  839. /*
  840. * TI XIO2000a PCIe-PCI Bridge erroneously reports it supports fast
  841. * back-to-back: Disable fast back-to-back on the secondary bus segment
  842. */
  843. static void quirk_xio2000a(struct pci_dev *dev)
  844. {
  845. struct pci_dev *pdev;
  846. u16 command;
  847. pci_warn(dev, "TI XIO2000a quirk detected; secondary bus fast back-to-back transfers disabled\n");
  848. list_for_each_entry(pdev, &dev->subordinate->devices, bus_list) {
  849. pci_read_config_word(pdev, PCI_COMMAND, &command);
  850. if (command & PCI_COMMAND_FAST_BACK)
  851. pci_write_config_word(pdev, PCI_COMMAND, command & ~PCI_COMMAND_FAST_BACK);
  852. }
  853. }
  854. DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_TI, PCI_DEVICE_ID_TI_XIO2000A,
  855. quirk_xio2000a);
  856. #ifdef CONFIG_X86_IO_APIC
  857. #include <asm/io_apic.h>
  858. /*
  859. * VIA 686A/B: If an IO-APIC is active, we need to route all on-chip
  860. * devices to the external APIC.
  861. *
  862. * TODO: When we have device-specific interrupt routers, this code will go
  863. * away from quirks.
  864. */
  865. static void quirk_via_ioapic(struct pci_dev *dev)
  866. {
  867. u8 tmp;
  868. if (nr_ioapics < 1)
  869. tmp = 0; /* nothing routed to external APIC */
  870. else
  871. tmp = 0x1f; /* all known bits (4-0) routed to external APIC */
  872. pci_info(dev, "%sbling VIA external APIC routing\n",
  873. tmp == 0 ? "Disa" : "Ena");
  874. /* Offset 0x58: External APIC IRQ output control */
  875. pci_write_config_byte(dev, 0x58, tmp);
  876. }
  877. DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C686, quirk_via_ioapic);
  878. DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C686, quirk_via_ioapic);
  879. /*
  880. * VIA 8237: Some BIOSes don't set the 'Bypass APIC De-Assert Message' Bit.
  881. * This leads to doubled level interrupt rates.
  882. * Set this bit to get rid of cycle wastage.
  883. * Otherwise uncritical.
  884. */
  885. static void quirk_via_vt8237_bypass_apic_deassert(struct pci_dev *dev)
  886. {
  887. u8 misc_control2;
  888. #define BYPASS_APIC_DEASSERT 8
  889. pci_read_config_byte(dev, 0x5B, &misc_control2);
  890. if (!(misc_control2 & BYPASS_APIC_DEASSERT)) {
  891. pci_info(dev, "Bypassing VIA 8237 APIC De-Assert Message\n");
  892. pci_write_config_byte(dev, 0x5B, misc_control2|BYPASS_APIC_DEASSERT);
  893. }
  894. }
  895. DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8237, quirk_via_vt8237_bypass_apic_deassert);
  896. DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8237, quirk_via_vt8237_bypass_apic_deassert);
  897. /*
  898. * The AMD IO-APIC can hang the box when an APIC IRQ is masked.
  899. * We check all revs >= B0 (yet not in the pre production!) as the bug
  900. * is currently marked NoFix
  901. *
  902. * We have multiple reports of hangs with this chipset that went away with
  903. * noapic specified. For the moment we assume it's the erratum. We may be wrong
  904. * of course. However the advice is demonstrably good even if so.
  905. */
  906. static void quirk_amd_ioapic(struct pci_dev *dev)
  907. {
  908. if (dev->revision >= 0x02) {
  909. pci_warn(dev, "I/O APIC: AMD Erratum #22 may be present. In the event of instability try\n");
  910. pci_warn(dev, " : booting with the \"noapic\" option\n");
  911. }
  912. }
  913. DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_VIPER_7410, quirk_amd_ioapic);
  914. #endif /* CONFIG_X86_IO_APIC */
  915. #if defined(CONFIG_ARM64) && defined(CONFIG_PCI_ATS)
  916. static void quirk_cavium_sriov_rnm_link(struct pci_dev *dev)
  917. {
  918. /* Fix for improper SR-IOV configuration on Cavium cn88xx RNM device */
  919. if (dev->subsystem_device == 0xa118)
  920. dev->sriov->link = dev->devfn;
  921. }
  922. DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_CAVIUM, 0xa018, quirk_cavium_sriov_rnm_link);
  923. #endif
  924. /*
  925. * Some settings of MMRBC can lead to data corruption so block changes.
  926. * See AMD 8131 HyperTransport PCI-X Tunnel Revision Guide
  927. */
  928. static void quirk_amd_8131_mmrbc(struct pci_dev *dev)
  929. {
  930. if (dev->subordinate && dev->revision <= 0x12) {
  931. pci_info(dev, "AMD8131 rev %x detected; disabling PCI-X MMRBC\n",
  932. dev->revision);
  933. dev->subordinate->bus_flags |= PCI_BUS_FLAGS_NO_MMRBC;
  934. }
  935. }
  936. DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_8131_BRIDGE, quirk_amd_8131_mmrbc);
  937. /*
  938. * FIXME: it is questionable that quirk_via_acpi() is needed. It shows up
  939. * as an ISA bridge, and does not support the PCI_INTERRUPT_LINE register
  940. * at all. Therefore it seems like setting the pci_dev's IRQ to the value
  941. * of the ACPI SCI interrupt is only done for convenience.
  942. * -jgarzik
  943. */
  944. static void quirk_via_acpi(struct pci_dev *d)
  945. {
  946. u8 irq;
  947. /* VIA ACPI device: SCI IRQ line in PCI config byte 0x42 */
  948. pci_read_config_byte(d, 0x42, &irq);
  949. irq &= 0xf;
  950. if (irq && (irq != 2))
  951. d->irq = irq;
  952. }
  953. DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C586_3, quirk_via_acpi);
  954. DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C686_4, quirk_via_acpi);
  955. /* VIA bridges which have VLink */
  956. static int via_vlink_dev_lo = -1, via_vlink_dev_hi = 18;
  957. static void quirk_via_bridge(struct pci_dev *dev)
  958. {
  959. /* See what bridge we have and find the device ranges */
  960. switch (dev->device) {
  961. case PCI_DEVICE_ID_VIA_82C686:
  962. /*
  963. * The VT82C686 is special; it attaches to PCI and can have
  964. * any device number. All its subdevices are functions of
  965. * that single device.
  966. */
  967. via_vlink_dev_lo = PCI_SLOT(dev->devfn);
  968. via_vlink_dev_hi = PCI_SLOT(dev->devfn);
  969. break;
  970. case PCI_DEVICE_ID_VIA_8237:
  971. case PCI_DEVICE_ID_VIA_8237A:
  972. via_vlink_dev_lo = 15;
  973. break;
  974. case PCI_DEVICE_ID_VIA_8235:
  975. via_vlink_dev_lo = 16;
  976. break;
  977. case PCI_DEVICE_ID_VIA_8231:
  978. case PCI_DEVICE_ID_VIA_8233_0:
  979. case PCI_DEVICE_ID_VIA_8233A:
  980. case PCI_DEVICE_ID_VIA_8233C_0:
  981. via_vlink_dev_lo = 17;
  982. break;
  983. }
  984. }
  985. DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C686, quirk_via_bridge);
  986. DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8231, quirk_via_bridge);
  987. DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8233_0, quirk_via_bridge);
  988. DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8233A, quirk_via_bridge);
  989. DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8233C_0, quirk_via_bridge);
  990. DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8235, quirk_via_bridge);
  991. DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8237, quirk_via_bridge);
  992. DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8237A, quirk_via_bridge);
  993. /*
  994. * quirk_via_vlink - VIA VLink IRQ number update
  995. * @dev: PCI device
  996. *
  997. * If the device we are dealing with is on a PIC IRQ we need to ensure that
  998. * the IRQ line register which usually is not relevant for PCI cards, is
  999. * actually written so that interrupts get sent to the right place.
  1000. *
  1001. * We only do this on systems where a VIA south bridge was detected, and
  1002. * only for VIA devices on the motherboard (see quirk_via_bridge above).
  1003. */
  1004. static void quirk_via_vlink(struct pci_dev *dev)
  1005. {
  1006. u8 irq, new_irq;
  1007. /* Check if we have VLink at all */
  1008. if (via_vlink_dev_lo == -1)
  1009. return;
  1010. new_irq = dev->irq;
  1011. /* Don't quirk interrupts outside the legacy IRQ range */
  1012. if (!new_irq || new_irq > 15)
  1013. return;
  1014. /* Internal device ? */
  1015. if (dev->bus->number != 0 || PCI_SLOT(dev->devfn) > via_vlink_dev_hi ||
  1016. PCI_SLOT(dev->devfn) < via_vlink_dev_lo)
  1017. return;
  1018. /*
  1019. * This is an internal VLink device on a PIC interrupt. The BIOS
  1020. * ought to have set this but may not have, so we redo it.
  1021. */
  1022. pci_read_config_byte(dev, PCI_INTERRUPT_LINE, &irq);
  1023. if (new_irq != irq) {
  1024. pci_info(dev, "VIA VLink IRQ fixup, from %d to %d\n",
  1025. irq, new_irq);
  1026. udelay(15); /* unknown if delay really needed */
  1027. pci_write_config_byte(dev, PCI_INTERRUPT_LINE, new_irq);
  1028. }
  1029. }
  1030. DECLARE_PCI_FIXUP_ENABLE(PCI_VENDOR_ID_VIA, PCI_ANY_ID, quirk_via_vlink);
  1031. /*
  1032. * VIA VT82C598 has its device ID settable and many BIOSes set it to the ID
  1033. * of VT82C597 for backward compatibility. We need to switch it off to be
  1034. * able to recognize the real type of the chip.
  1035. */
  1036. static void quirk_vt82c598_id(struct pci_dev *dev)
  1037. {
  1038. pci_write_config_byte(dev, 0xfc, 0);
  1039. pci_read_config_word(dev, PCI_DEVICE_ID, &dev->device);
  1040. }
  1041. DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C597_0, quirk_vt82c598_id);
  1042. /*
  1043. * CardBus controllers have a legacy base address that enables them to
  1044. * respond as i82365 pcmcia controllers. We don't want them to do this
  1045. * even if the Linux CardBus driver is not loaded, because the Linux i82365
  1046. * driver does not (and should not) handle CardBus.
  1047. */
  1048. static void quirk_cardbus_legacy(struct pci_dev *dev)
  1049. {
  1050. pci_write_config_dword(dev, PCI_CB_LEGACY_MODE_BASE, 0);
  1051. }
  1052. DECLARE_PCI_FIXUP_CLASS_FINAL(PCI_ANY_ID, PCI_ANY_ID,
  1053. PCI_CLASS_BRIDGE_CARDBUS, 8, quirk_cardbus_legacy);
  1054. DECLARE_PCI_FIXUP_CLASS_RESUME_EARLY(PCI_ANY_ID, PCI_ANY_ID,
  1055. PCI_CLASS_BRIDGE_CARDBUS, 8, quirk_cardbus_legacy);
  1056. /*
  1057. * Following the PCI ordering rules is optional on the AMD762. I'm not sure
  1058. * what the designers were smoking but let's not inhale...
  1059. *
  1060. * To be fair to AMD, it follows the spec by default, it's BIOS people who
  1061. * turn it off!
  1062. */
  1063. static void quirk_amd_ordering(struct pci_dev *dev)
  1064. {
  1065. u32 pcic;
  1066. pci_read_config_dword(dev, 0x4C, &pcic);
  1067. if ((pcic & 6) != 6) {
  1068. pcic |= 6;
  1069. pci_warn(dev, "BIOS failed to enable PCI standards compliance; fixing this error\n");
  1070. pci_write_config_dword(dev, 0x4C, pcic);
  1071. pci_read_config_dword(dev, 0x84, &pcic);
  1072. pcic |= (1 << 23); /* Required in this mode */
  1073. pci_write_config_dword(dev, 0x84, pcic);
  1074. }
  1075. }
  1076. DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_FE_GATE_700C, quirk_amd_ordering);
  1077. DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_FE_GATE_700C, quirk_amd_ordering);
  1078. /*
  1079. * DreamWorks-provided workaround for Dunord I-3000 problem
  1080. *
  1081. * This card decodes and responds to addresses not apparently assigned to
  1082. * it. We force a larger allocation to ensure that nothing gets put too
  1083. * close to it.
  1084. */
  1085. static void quirk_dunord(struct pci_dev *dev)
  1086. {
  1087. struct resource *r = &dev->resource[1];
  1088. r->flags |= IORESOURCE_UNSET;
  1089. r->start = 0;
  1090. r->end = 0xffffff;
  1091. }
  1092. DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_DUNORD, PCI_DEVICE_ID_DUNORD_I3000, quirk_dunord);
  1093. /*
  1094. * i82380FB mobile docking controller: its PCI-to-PCI bridge is subtractive
  1095. * decoding (transparent), and does indicate this in the ProgIf.
  1096. * Unfortunately, the ProgIf value is wrong - 0x80 instead of 0x01.
  1097. */
  1098. static void quirk_transparent_bridge(struct pci_dev *dev)
  1099. {
  1100. dev->transparent = 1;
  1101. }
  1102. DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82380FB, quirk_transparent_bridge);
  1103. DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_TOSHIBA, 0x605, quirk_transparent_bridge);
  1104. /*
  1105. * Common misconfiguration of the MediaGX/Geode PCI master that will reduce
  1106. * PCI bandwidth from 70MB/s to 25MB/s. See the GXM/GXLV/GX1 datasheets
  1107. * found at http://www.national.com/analog for info on what these bits do.
  1108. * <christer@weinigel.se>
  1109. */
  1110. static void quirk_mediagx_master(struct pci_dev *dev)
  1111. {
  1112. u8 reg;
  1113. pci_read_config_byte(dev, 0x41, &reg);
  1114. if (reg & 2) {
  1115. reg &= ~2;
  1116. pci_info(dev, "Fixup for MediaGX/Geode Slave Disconnect Boundary (0x41=0x%02x)\n",
  1117. reg);
  1118. pci_write_config_byte(dev, 0x41, reg);
  1119. }
  1120. }
  1121. DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_CYRIX, PCI_DEVICE_ID_CYRIX_PCI_MASTER, quirk_mediagx_master);
  1122. DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_CYRIX, PCI_DEVICE_ID_CYRIX_PCI_MASTER, quirk_mediagx_master);
  1123. /*
  1124. * Ensure C0 rev restreaming is off. This is normally done by the BIOS but
  1125. * in the odd case it is not the results are corruption hence the presence
  1126. * of a Linux check.
  1127. */
  1128. static void quirk_disable_pxb(struct pci_dev *pdev)
  1129. {
  1130. u16 config;
  1131. if (pdev->revision != 0x04) /* Only C0 requires this */
  1132. return;
  1133. pci_read_config_word(pdev, 0x40, &config);
  1134. if (config & (1<<6)) {
  1135. config &= ~(1<<6);
  1136. pci_write_config_word(pdev, 0x40, config);
  1137. pci_info(pdev, "C0 revision 450NX. Disabling PCI restreaming\n");
  1138. }
  1139. }
  1140. DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82454NX, quirk_disable_pxb);
  1141. DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82454NX, quirk_disable_pxb);
  1142. static void quirk_amd_ide_mode(struct pci_dev *pdev)
  1143. {
  1144. /* set SBX00/Hudson-2 SATA in IDE mode to AHCI mode */
  1145. u8 tmp;
  1146. pci_read_config_byte(pdev, PCI_CLASS_DEVICE, &tmp);
  1147. if (tmp == 0x01) {
  1148. pci_read_config_byte(pdev, 0x40, &tmp);
  1149. pci_write_config_byte(pdev, 0x40, tmp|1);
  1150. pci_write_config_byte(pdev, 0x9, 1);
  1151. pci_write_config_byte(pdev, 0xa, 6);
  1152. pci_write_config_byte(pdev, 0x40, tmp);
  1153. pdev->class = PCI_CLASS_STORAGE_SATA_AHCI;
  1154. pci_info(pdev, "set SATA to AHCI mode\n");
  1155. }
  1156. }
  1157. DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_IXP600_SATA, quirk_amd_ide_mode);
  1158. DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_IXP600_SATA, quirk_amd_ide_mode);
  1159. DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_IXP700_SATA, quirk_amd_ide_mode);
  1160. DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_IXP700_SATA, quirk_amd_ide_mode);
  1161. DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_HUDSON2_SATA_IDE, quirk_amd_ide_mode);
  1162. DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_HUDSON2_SATA_IDE, quirk_amd_ide_mode);
  1163. DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_AMD, 0x7900, quirk_amd_ide_mode);
  1164. DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_AMD, 0x7900, quirk_amd_ide_mode);
  1165. /* Serverworks CSB5 IDE does not fully support native mode */
  1166. static void quirk_svwks_csb5ide(struct pci_dev *pdev)
  1167. {
  1168. u8 prog;
  1169. pci_read_config_byte(pdev, PCI_CLASS_PROG, &prog);
  1170. if (prog & 5) {
  1171. prog &= ~5;
  1172. pdev->class &= ~5;
  1173. pci_write_config_byte(pdev, PCI_CLASS_PROG, prog);
  1174. /* PCI layer will sort out resources */
  1175. }
  1176. }
  1177. DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_SERVERWORKS, PCI_DEVICE_ID_SERVERWORKS_CSB5IDE, quirk_svwks_csb5ide);
  1178. /* Intel 82801CAM ICH3-M datasheet says IDE modes must be the same */
  1179. static void quirk_ide_samemode(struct pci_dev *pdev)
  1180. {
  1181. u8 prog;
  1182. pci_read_config_byte(pdev, PCI_CLASS_PROG, &prog);
  1183. if (((prog & 1) && !(prog & 4)) || ((prog & 4) && !(prog & 1))) {
  1184. pci_info(pdev, "IDE mode mismatch; forcing legacy mode\n");
  1185. prog &= ~5;
  1186. pdev->class &= ~5;
  1187. pci_write_config_byte(pdev, PCI_CLASS_PROG, prog);
  1188. }
  1189. }
  1190. DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801CA_10, quirk_ide_samemode);
  1191. /* Some ATA devices break if put into D3 */
  1192. static void quirk_no_ata_d3(struct pci_dev *pdev)
  1193. {
  1194. pdev->dev_flags |= PCI_DEV_FLAGS_NO_D3;
  1195. }
  1196. /* Quirk the legacy ATA devices only. The AHCI ones are ok */
  1197. DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_SERVERWORKS, PCI_ANY_ID,
  1198. PCI_CLASS_STORAGE_IDE, 8, quirk_no_ata_d3);
  1199. DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_ATI, PCI_ANY_ID,
  1200. PCI_CLASS_STORAGE_IDE, 8, quirk_no_ata_d3);
  1201. /* ALi loses some register settings that we cannot then restore */
  1202. DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_AL, PCI_ANY_ID,
  1203. PCI_CLASS_STORAGE_IDE, 8, quirk_no_ata_d3);
  1204. /* VIA comes back fine but we need to keep it alive or ACPI GTM failures
  1205. occur when mode detecting */
  1206. DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_VIA, PCI_ANY_ID,
  1207. PCI_CLASS_STORAGE_IDE, 8, quirk_no_ata_d3);
  1208. /*
  1209. * This was originally an Alpha-specific thing, but it really fits here.
  1210. * The i82375 PCI/EISA bridge appears as non-classified. Fix that.
  1211. */
  1212. static void quirk_eisa_bridge(struct pci_dev *dev)
  1213. {
  1214. dev->class = PCI_CLASS_BRIDGE_EISA << 8;
  1215. }
  1216. DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82375, quirk_eisa_bridge);
  1217. /*
  1218. * On ASUS P4B boards, the SMBus PCI Device within the ICH2/4 southbridge
  1219. * is not activated. The myth is that Asus said that they do not want the
  1220. * users to be irritated by just another PCI Device in the Win98 device
  1221. * manager. (see the file prog/hotplug/README.p4b in the lm_sensors
  1222. * package 2.7.0 for details)
  1223. *
  1224. * The SMBus PCI Device can be activated by setting a bit in the ICH LPC
  1225. * bridge. Unfortunately, this device has no subvendor/subdevice ID. So it
  1226. * becomes necessary to do this tweak in two steps -- the chosen trigger
  1227. * is either the Host bridge (preferred) or on-board VGA controller.
  1228. *
  1229. * Note that we used to unhide the SMBus that way on Toshiba laptops
  1230. * (Satellite A40 and Tecra M2) but then found that the thermal management
  1231. * was done by SMM code, which could cause unsynchronized concurrent
  1232. * accesses to the SMBus registers, with potentially bad effects. Thus you
  1233. * should be very careful when adding new entries: if SMM is accessing the
  1234. * Intel SMBus, this is a very good reason to leave it hidden.
  1235. *
  1236. * Likewise, many recent laptops use ACPI for thermal management. If the
  1237. * ACPI DSDT code accesses the SMBus, then Linux should not access it
  1238. * natively, and keeping the SMBus hidden is the right thing to do. If you
  1239. * are about to add an entry in the table below, please first disassemble
  1240. * the DSDT and double-check that there is no code accessing the SMBus.
  1241. */
  1242. static int asus_hides_smbus;
  1243. static void asus_hides_smbus_hostbridge(struct pci_dev *dev)
  1244. {
  1245. if (unlikely(dev->subsystem_vendor == PCI_VENDOR_ID_ASUSTEK)) {
  1246. if (dev->device == PCI_DEVICE_ID_INTEL_82845_HB)
  1247. switch (dev->subsystem_device) {
  1248. case 0x8025: /* P4B-LX */
  1249. case 0x8070: /* P4B */
  1250. case 0x8088: /* P4B533 */
  1251. case 0x1626: /* L3C notebook */
  1252. asus_hides_smbus = 1;
  1253. }
  1254. else if (dev->device == PCI_DEVICE_ID_INTEL_82845G_HB)
  1255. switch (dev->subsystem_device) {
  1256. case 0x80b1: /* P4GE-V */
  1257. case 0x80b2: /* P4PE */
  1258. case 0x8093: /* P4B533-V */
  1259. asus_hides_smbus = 1;
  1260. }
  1261. else if (dev->device == PCI_DEVICE_ID_INTEL_82850_HB)
  1262. switch (dev->subsystem_device) {
  1263. case 0x8030: /* P4T533 */
  1264. asus_hides_smbus = 1;
  1265. }
  1266. else if (dev->device == PCI_DEVICE_ID_INTEL_7205_0)
  1267. switch (dev->subsystem_device) {
  1268. case 0x8070: /* P4G8X Deluxe */
  1269. asus_hides_smbus = 1;
  1270. }
  1271. else if (dev->device == PCI_DEVICE_ID_INTEL_E7501_MCH)
  1272. switch (dev->subsystem_device) {
  1273. case 0x80c9: /* PU-DLS */
  1274. asus_hides_smbus = 1;
  1275. }
  1276. else if (dev->device == PCI_DEVICE_ID_INTEL_82855GM_HB)
  1277. switch (dev->subsystem_device) {
  1278. case 0x1751: /* M2N notebook */
  1279. case 0x1821: /* M5N notebook */
  1280. case 0x1897: /* A6L notebook */
  1281. asus_hides_smbus = 1;
  1282. }
  1283. else if (dev->device == PCI_DEVICE_ID_INTEL_82855PM_HB)
  1284. switch (dev->subsystem_device) {
  1285. case 0x184b: /* W1N notebook */
  1286. case 0x186a: /* M6Ne notebook */
  1287. asus_hides_smbus = 1;
  1288. }
  1289. else if (dev->device == PCI_DEVICE_ID_INTEL_82865_HB)
  1290. switch (dev->subsystem_device) {
  1291. case 0x80f2: /* P4P800-X */
  1292. asus_hides_smbus = 1;
  1293. }
  1294. else if (dev->device == PCI_DEVICE_ID_INTEL_82915GM_HB)
  1295. switch (dev->subsystem_device) {
  1296. case 0x1882: /* M6V notebook */
  1297. case 0x1977: /* A6VA notebook */
  1298. asus_hides_smbus = 1;
  1299. }
  1300. } else if (unlikely(dev->subsystem_vendor == PCI_VENDOR_ID_HP)) {
  1301. if (dev->device == PCI_DEVICE_ID_INTEL_82855PM_HB)
  1302. switch (dev->subsystem_device) {
  1303. case 0x088C: /* HP Compaq nc8000 */
  1304. case 0x0890: /* HP Compaq nc6000 */
  1305. asus_hides_smbus = 1;
  1306. }
  1307. else if (dev->device == PCI_DEVICE_ID_INTEL_82865_HB)
  1308. switch (dev->subsystem_device) {
  1309. case 0x12bc: /* HP D330L */
  1310. case 0x12bd: /* HP D530 */
  1311. case 0x006a: /* HP Compaq nx9500 */
  1312. asus_hides_smbus = 1;
  1313. }
  1314. else if (dev->device == PCI_DEVICE_ID_INTEL_82875_HB)
  1315. switch (dev->subsystem_device) {
  1316. case 0x12bf: /* HP xw4100 */
  1317. asus_hides_smbus = 1;
  1318. }
  1319. } else if (unlikely(dev->subsystem_vendor == PCI_VENDOR_ID_SAMSUNG)) {
  1320. if (dev->device == PCI_DEVICE_ID_INTEL_82855PM_HB)
  1321. switch (dev->subsystem_device) {
  1322. case 0xC00C: /* Samsung P35 notebook */
  1323. asus_hides_smbus = 1;
  1324. }
  1325. } else if (unlikely(dev->subsystem_vendor == PCI_VENDOR_ID_COMPAQ)) {
  1326. if (dev->device == PCI_DEVICE_ID_INTEL_82855PM_HB)
  1327. switch (dev->subsystem_device) {
  1328. case 0x0058: /* Compaq Evo N620c */
  1329. asus_hides_smbus = 1;
  1330. }
  1331. else if (dev->device == PCI_DEVICE_ID_INTEL_82810_IG3)
  1332. switch (dev->subsystem_device) {
  1333. case 0xB16C: /* Compaq Deskpro EP 401963-001 (PCA# 010174) */
  1334. /* Motherboard doesn't have Host bridge
  1335. * subvendor/subdevice IDs, therefore checking
  1336. * its on-board VGA controller */
  1337. asus_hides_smbus = 1;
  1338. }
  1339. else if (dev->device == PCI_DEVICE_ID_INTEL_82801DB_2)
  1340. switch (dev->subsystem_device) {
  1341. case 0x00b8: /* Compaq Evo D510 CMT */
  1342. case 0x00b9: /* Compaq Evo D510 SFF */
  1343. case 0x00ba: /* Compaq Evo D510 USDT */
  1344. /* Motherboard doesn't have Host bridge
  1345. * subvendor/subdevice IDs and on-board VGA
  1346. * controller is disabled if an AGP card is
  1347. * inserted, therefore checking USB UHCI
  1348. * Controller #1 */
  1349. asus_hides_smbus = 1;
  1350. }
  1351. else if (dev->device == PCI_DEVICE_ID_INTEL_82815_CGC)
  1352. switch (dev->subsystem_device) {
  1353. case 0x001A: /* Compaq Deskpro EN SSF P667 815E */
  1354. /* Motherboard doesn't have host bridge
  1355. * subvendor/subdevice IDs, therefore checking
  1356. * its on-board VGA controller */
  1357. asus_hides_smbus = 1;
  1358. }
  1359. }
  1360. }
  1361. DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82845_HB, asus_hides_smbus_hostbridge);
  1362. DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82845G_HB, asus_hides_smbus_hostbridge);
  1363. DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82850_HB, asus_hides_smbus_hostbridge);
  1364. DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82865_HB, asus_hides_smbus_hostbridge);
  1365. DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82875_HB, asus_hides_smbus_hostbridge);
  1366. DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_7205_0, asus_hides_smbus_hostbridge);
  1367. DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_E7501_MCH, asus_hides_smbus_hostbridge);
  1368. DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82855PM_HB, asus_hides_smbus_hostbridge);
  1369. DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82855GM_HB, asus_hides_smbus_hostbridge);
  1370. DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82915GM_HB, asus_hides_smbus_hostbridge);
  1371. DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82810_IG3, asus_hides_smbus_hostbridge);
  1372. DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801DB_2, asus_hides_smbus_hostbridge);
  1373. DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82815_CGC, asus_hides_smbus_hostbridge);
  1374. static void asus_hides_smbus_lpc(struct pci_dev *dev)
  1375. {
  1376. u16 val;
  1377. if (likely(!asus_hides_smbus))
  1378. return;
  1379. pci_read_config_word(dev, 0xF2, &val);
  1380. if (val & 0x8) {
  1381. pci_write_config_word(dev, 0xF2, val & (~0x8));
  1382. pci_read_config_word(dev, 0xF2, &val);
  1383. if (val & 0x8)
  1384. pci_info(dev, "i801 SMBus device continues to play 'hide and seek'! 0x%x\n",
  1385. val);
  1386. else
  1387. pci_info(dev, "Enabled i801 SMBus device\n");
  1388. }
  1389. }
  1390. DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801AA_0, asus_hides_smbus_lpc);
  1391. DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801DB_0, asus_hides_smbus_lpc);
  1392. DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801BA_0, asus_hides_smbus_lpc);
  1393. DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801CA_0, asus_hides_smbus_lpc);
  1394. DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801CA_12, asus_hides_smbus_lpc);
  1395. DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801DB_12, asus_hides_smbus_lpc);
  1396. DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801EB_0, asus_hides_smbus_lpc);
  1397. DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801AA_0, asus_hides_smbus_lpc);
  1398. DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801DB_0, asus_hides_smbus_lpc);
  1399. DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801BA_0, asus_hides_smbus_lpc);
  1400. DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801CA_0, asus_hides_smbus_lpc);
  1401. DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801CA_12, asus_hides_smbus_lpc);
  1402. DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801DB_12, asus_hides_smbus_lpc);
  1403. DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801EB_0, asus_hides_smbus_lpc);
  1404. /* It appears we just have one such device. If not, we have a warning */
  1405. static void __iomem *asus_rcba_base;
  1406. static void asus_hides_smbus_lpc_ich6_suspend(struct pci_dev *dev)
  1407. {
  1408. u32 rcba;
  1409. if (likely(!asus_hides_smbus))
  1410. return;
  1411. WARN_ON(asus_rcba_base);
  1412. pci_read_config_dword(dev, 0xF0, &rcba);
  1413. /* use bits 31:14, 16 kB aligned */
  1414. asus_rcba_base = ioremap(rcba & 0xFFFFC000, 0x4000);
  1415. if (asus_rcba_base == NULL)
  1416. return;
  1417. }
  1418. static void asus_hides_smbus_lpc_ich6_resume_early(struct pci_dev *dev)
  1419. {
  1420. u32 val;
  1421. if (likely(!asus_hides_smbus || !asus_rcba_base))
  1422. return;
  1423. /* read the Function Disable register, dword mode only */
  1424. val = readl(asus_rcba_base + 0x3418);
  1425. /* enable the SMBus device */
  1426. writel(val & 0xFFFFFFF7, asus_rcba_base + 0x3418);
  1427. }
  1428. static void asus_hides_smbus_lpc_ich6_resume(struct pci_dev *dev)
  1429. {
  1430. if (likely(!asus_hides_smbus || !asus_rcba_base))
  1431. return;
  1432. iounmap(asus_rcba_base);
  1433. asus_rcba_base = NULL;
  1434. pci_info(dev, "Enabled ICH6/i801 SMBus device\n");
  1435. }
  1436. static void asus_hides_smbus_lpc_ich6(struct pci_dev *dev)
  1437. {
  1438. asus_hides_smbus_lpc_ich6_suspend(dev);
  1439. asus_hides_smbus_lpc_ich6_resume_early(dev);
  1440. asus_hides_smbus_lpc_ich6_resume(dev);
  1441. }
  1442. DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH6_1, asus_hides_smbus_lpc_ich6);
  1443. DECLARE_PCI_FIXUP_SUSPEND(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH6_1, asus_hides_smbus_lpc_ich6_suspend);
  1444. DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH6_1, asus_hides_smbus_lpc_ich6_resume);
  1445. DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH6_1, asus_hides_smbus_lpc_ich6_resume_early);
  1446. /* SiS 96x south bridge: BIOS typically hides SMBus device... */
  1447. static void quirk_sis_96x_smbus(struct pci_dev *dev)
  1448. {
  1449. u8 val = 0;
  1450. pci_read_config_byte(dev, 0x77, &val);
  1451. if (val & 0x10) {
  1452. pci_info(dev, "Enabling SiS 96x SMBus\n");
  1453. pci_write_config_byte(dev, 0x77, val & ~0x10);
  1454. }
  1455. }
  1456. DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_961, quirk_sis_96x_smbus);
  1457. DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_962, quirk_sis_96x_smbus);
  1458. DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_963, quirk_sis_96x_smbus);
  1459. DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_LPC, quirk_sis_96x_smbus);
  1460. DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_961, quirk_sis_96x_smbus);
  1461. DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_962, quirk_sis_96x_smbus);
  1462. DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_963, quirk_sis_96x_smbus);
  1463. DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_LPC, quirk_sis_96x_smbus);
  1464. /*
  1465. * ... This is further complicated by the fact that some SiS96x south
  1466. * bridges pretend to be 85C503/5513 instead. In that case see if we
  1467. * spotted a compatible north bridge to make sure.
  1468. * (pci_find_device() doesn't work yet)
  1469. *
  1470. * We can also enable the sis96x bit in the discovery register..
  1471. */
  1472. #define SIS_DETECT_REGISTER 0x40
  1473. static void quirk_sis_503(struct pci_dev *dev)
  1474. {
  1475. u8 reg;
  1476. u16 devid;
  1477. pci_read_config_byte(dev, SIS_DETECT_REGISTER, &reg);
  1478. pci_write_config_byte(dev, SIS_DETECT_REGISTER, reg | (1 << 6));
  1479. pci_read_config_word(dev, PCI_DEVICE_ID, &devid);
  1480. if (((devid & 0xfff0) != 0x0960) && (devid != 0x0018)) {
  1481. pci_write_config_byte(dev, SIS_DETECT_REGISTER, reg);
  1482. return;
  1483. }
  1484. /*
  1485. * Ok, it now shows up as a 96x. Run the 96x quirk by hand in case
  1486. * it has already been processed. (Depends on link order, which is
  1487. * apparently not guaranteed)
  1488. */
  1489. dev->device = devid;
  1490. quirk_sis_96x_smbus(dev);
  1491. }
  1492. DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_503, quirk_sis_503);
  1493. DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_503, quirk_sis_503);
  1494. /*
  1495. * On ASUS A8V and A8V Deluxe boards, the onboard AC97 audio controller
  1496. * and MC97 modem controller are disabled when a second PCI soundcard is
  1497. * present. This patch, tweaking the VT8237 ISA bridge, enables them.
  1498. * -- bjd
  1499. */
  1500. static void asus_hides_ac97_lpc(struct pci_dev *dev)
  1501. {
  1502. u8 val;
  1503. int asus_hides_ac97 = 0;
  1504. if (likely(dev->subsystem_vendor == PCI_VENDOR_ID_ASUSTEK)) {
  1505. if (dev->device == PCI_DEVICE_ID_VIA_8237)
  1506. asus_hides_ac97 = 1;
  1507. }
  1508. if (!asus_hides_ac97)
  1509. return;
  1510. pci_read_config_byte(dev, 0x50, &val);
  1511. if (val & 0xc0) {
  1512. pci_write_config_byte(dev, 0x50, val & (~0xc0));
  1513. pci_read_config_byte(dev, 0x50, &val);
  1514. if (val & 0xc0)
  1515. pci_info(dev, "Onboard AC97/MC97 devices continue to play 'hide and seek'! 0x%x\n",
  1516. val);
  1517. else
  1518. pci_info(dev, "Enabled onboard AC97/MC97 devices\n");
  1519. }
  1520. }
  1521. DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8237, asus_hides_ac97_lpc);
  1522. DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8237, asus_hides_ac97_lpc);
  1523. #if defined(CONFIG_ATA) || defined(CONFIG_ATA_MODULE)
  1524. /*
  1525. * If we are using libata we can drive this chip properly but must do this
  1526. * early on to make the additional device appear during the PCI scanning.
  1527. */
  1528. static void quirk_jmicron_ata(struct pci_dev *pdev)
  1529. {
  1530. u32 conf1, conf5, class;
  1531. u8 hdr;
  1532. /* Only poke fn 0 */
  1533. if (PCI_FUNC(pdev->devfn))
  1534. return;
  1535. pci_read_config_dword(pdev, 0x40, &conf1);
  1536. pci_read_config_dword(pdev, 0x80, &conf5);
  1537. conf1 &= ~0x00CFF302; /* Clear bit 1, 8, 9, 12-19, 22, 23 */
  1538. conf5 &= ~(1 << 24); /* Clear bit 24 */
  1539. switch (pdev->device) {
  1540. case PCI_DEVICE_ID_JMICRON_JMB360: /* SATA single port */
  1541. case PCI_DEVICE_ID_JMICRON_JMB362: /* SATA dual ports */
  1542. case PCI_DEVICE_ID_JMICRON_JMB364: /* SATA dual ports */
  1543. /* The controller should be in single function ahci mode */
  1544. conf1 |= 0x0002A100; /* Set 8, 13, 15, 17 */
  1545. break;
  1546. case PCI_DEVICE_ID_JMICRON_JMB365:
  1547. case PCI_DEVICE_ID_JMICRON_JMB366:
  1548. /* Redirect IDE second PATA port to the right spot */
  1549. conf5 |= (1 << 24);
  1550. fallthrough;
  1551. case PCI_DEVICE_ID_JMICRON_JMB361:
  1552. case PCI_DEVICE_ID_JMICRON_JMB363:
  1553. case PCI_DEVICE_ID_JMICRON_JMB369:
  1554. /* Enable dual function mode, AHCI on fn 0, IDE fn1 */
  1555. /* Set the class codes correctly and then direct IDE 0 */
  1556. conf1 |= 0x00C2A1B3; /* Set 0, 1, 4, 5, 7, 8, 13, 15, 17, 22, 23 */
  1557. break;
  1558. case PCI_DEVICE_ID_JMICRON_JMB368:
  1559. /* The controller should be in single function IDE mode */
  1560. conf1 |= 0x00C00000; /* Set 22, 23 */
  1561. break;
  1562. }
  1563. pci_write_config_dword(pdev, 0x40, conf1);
  1564. pci_write_config_dword(pdev, 0x80, conf5);
  1565. /* Update pdev accordingly */
  1566. pci_read_config_byte(pdev, PCI_HEADER_TYPE, &hdr);
  1567. pdev->hdr_type = hdr & 0x7f;
  1568. pdev->multifunction = !!(hdr & 0x80);
  1569. pci_read_config_dword(pdev, PCI_CLASS_REVISION, &class);
  1570. pdev->class = class >> 8;
  1571. }
  1572. DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB360, quirk_jmicron_ata);
  1573. DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB361, quirk_jmicron_ata);
  1574. DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB362, quirk_jmicron_ata);
  1575. DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB363, quirk_jmicron_ata);
  1576. DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB364, quirk_jmicron_ata);
  1577. DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB365, quirk_jmicron_ata);
  1578. DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB366, quirk_jmicron_ata);
  1579. DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB368, quirk_jmicron_ata);
  1580. DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB369, quirk_jmicron_ata);
  1581. DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB360, quirk_jmicron_ata);
  1582. DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB361, quirk_jmicron_ata);
  1583. DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB362, quirk_jmicron_ata);
  1584. DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB363, quirk_jmicron_ata);
  1585. DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB364, quirk_jmicron_ata);
  1586. DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB365, quirk_jmicron_ata);
  1587. DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB366, quirk_jmicron_ata);
  1588. DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB368, quirk_jmicron_ata);
  1589. DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB369, quirk_jmicron_ata);
  1590. #endif
  1591. static void quirk_jmicron_async_suspend(struct pci_dev *dev)
  1592. {
  1593. if (dev->multifunction) {
  1594. device_disable_async_suspend(&dev->dev);
  1595. pci_info(dev, "async suspend disabled to avoid multi-function power-on ordering issue\n");
  1596. }
  1597. }
  1598. DECLARE_PCI_FIXUP_CLASS_FINAL(PCI_VENDOR_ID_JMICRON, PCI_ANY_ID, PCI_CLASS_STORAGE_IDE, 8, quirk_jmicron_async_suspend);
  1599. DECLARE_PCI_FIXUP_CLASS_FINAL(PCI_VENDOR_ID_JMICRON, PCI_ANY_ID, PCI_CLASS_STORAGE_SATA_AHCI, 0, quirk_jmicron_async_suspend);
  1600. DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_JMICRON, 0x2362, quirk_jmicron_async_suspend);
  1601. DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_JMICRON, 0x236f, quirk_jmicron_async_suspend);
  1602. #ifdef CONFIG_X86_IO_APIC
  1603. static void quirk_alder_ioapic(struct pci_dev *pdev)
  1604. {
  1605. int i;
  1606. if ((pdev->class >> 8) != 0xff00)
  1607. return;
  1608. /*
  1609. * The first BAR is the location of the IO-APIC... we must
  1610. * not touch this (and it's already covered by the fixmap), so
  1611. * forcibly insert it into the resource tree.
  1612. */
  1613. if (pci_resource_start(pdev, 0) && pci_resource_len(pdev, 0))
  1614. insert_resource(&iomem_resource, &pdev->resource[0]);
  1615. /*
  1616. * The next five BARs all seem to be rubbish, so just clean
  1617. * them out.
  1618. */
  1619. for (i = 1; i < PCI_STD_NUM_BARS; i++)
  1620. memset(&pdev->resource[i], 0, sizeof(pdev->resource[i]));
  1621. }
  1622. DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_EESSC, quirk_alder_ioapic);
  1623. #endif
  1624. static void quirk_no_msi(struct pci_dev *dev)
  1625. {
  1626. pci_info(dev, "avoiding MSI to work around a hardware defect\n");
  1627. dev->no_msi = 1;
  1628. }
  1629. DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0x4386, quirk_no_msi);
  1630. DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0x4387, quirk_no_msi);
  1631. DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0x4388, quirk_no_msi);
  1632. DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0x4389, quirk_no_msi);
  1633. DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0x438a, quirk_no_msi);
  1634. DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0x438b, quirk_no_msi);
  1635. static void quirk_pcie_mch(struct pci_dev *pdev)
  1636. {
  1637. pdev->no_msi = 1;
  1638. }
  1639. DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_E7520_MCH, quirk_pcie_mch);
  1640. DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_E7320_MCH, quirk_pcie_mch);
  1641. DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_E7525_MCH, quirk_pcie_mch);
  1642. DECLARE_PCI_FIXUP_CLASS_FINAL(PCI_VENDOR_ID_HUAWEI, 0x1610, PCI_CLASS_BRIDGE_PCI, 8, quirk_pcie_mch);
  1643. /*
  1644. * It's possible for the MSI to get corrupted if SHPC and ACPI are used
  1645. * together on certain PXH-based systems.
  1646. */
  1647. static void quirk_pcie_pxh(struct pci_dev *dev)
  1648. {
  1649. dev->no_msi = 1;
  1650. pci_warn(dev, "PXH quirk detected; SHPC device MSI disabled\n");
  1651. }
  1652. DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PXHD_0, quirk_pcie_pxh);
  1653. DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PXHD_1, quirk_pcie_pxh);
  1654. DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PXH_0, quirk_pcie_pxh);
  1655. DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PXH_1, quirk_pcie_pxh);
  1656. DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PXHV, quirk_pcie_pxh);
  1657. /*
  1658. * Some Intel PCI Express chipsets have trouble with downstream device
  1659. * power management.
  1660. */
  1661. static void quirk_intel_pcie_pm(struct pci_dev *dev)
  1662. {
  1663. pci_pm_d3hot_delay = 120;
  1664. dev->no_d1d2 = 1;
  1665. }
  1666. DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x25e2, quirk_intel_pcie_pm);
  1667. DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x25e3, quirk_intel_pcie_pm);
  1668. DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x25e4, quirk_intel_pcie_pm);
  1669. DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x25e5, quirk_intel_pcie_pm);
  1670. DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x25e6, quirk_intel_pcie_pm);
  1671. DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x25e7, quirk_intel_pcie_pm);
  1672. DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x25f7, quirk_intel_pcie_pm);
  1673. DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x25f8, quirk_intel_pcie_pm);
  1674. DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x25f9, quirk_intel_pcie_pm);
  1675. DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x25fa, quirk_intel_pcie_pm);
  1676. DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x2601, quirk_intel_pcie_pm);
  1677. DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x2602, quirk_intel_pcie_pm);
  1678. DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x2603, quirk_intel_pcie_pm);
  1679. DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x2604, quirk_intel_pcie_pm);
  1680. DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x2605, quirk_intel_pcie_pm);
  1681. DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x2606, quirk_intel_pcie_pm);
  1682. DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x2607, quirk_intel_pcie_pm);
  1683. DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x2608, quirk_intel_pcie_pm);
  1684. DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x2609, quirk_intel_pcie_pm);
  1685. DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x260a, quirk_intel_pcie_pm);
  1686. DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x260b, quirk_intel_pcie_pm);
  1687. static void quirk_d3hot_delay(struct pci_dev *dev, unsigned int delay)
  1688. {
  1689. if (dev->d3hot_delay >= delay)
  1690. return;
  1691. dev->d3hot_delay = delay;
  1692. pci_info(dev, "extending delay after power-on from D3hot to %d msec\n",
  1693. dev->d3hot_delay);
  1694. }
  1695. static void quirk_radeon_pm(struct pci_dev *dev)
  1696. {
  1697. if (dev->subsystem_vendor == PCI_VENDOR_ID_APPLE &&
  1698. dev->subsystem_device == 0x00e2)
  1699. quirk_d3hot_delay(dev, 20);
  1700. }
  1701. DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0x6741, quirk_radeon_pm);
  1702. /*
  1703. * Ryzen5/7 XHCI controllers fail upon resume from runtime suspend or s2idle.
  1704. * https://bugzilla.kernel.org/show_bug.cgi?id=205587
  1705. *
  1706. * The kernel attempts to transition these devices to D3cold, but that seems
  1707. * to be ineffective on the platforms in question; the PCI device appears to
  1708. * remain on in D3hot state. The D3hot-to-D0 transition then requires an
  1709. * extended delay in order to succeed.
  1710. */
  1711. static void quirk_ryzen_xhci_d3hot(struct pci_dev *dev)
  1712. {
  1713. quirk_d3hot_delay(dev, 20);
  1714. }
  1715. DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AMD, 0x15e0, quirk_ryzen_xhci_d3hot);
  1716. DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AMD, 0x15e1, quirk_ryzen_xhci_d3hot);
  1717. DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AMD, 0x1639, quirk_ryzen_xhci_d3hot);
  1718. #ifdef CONFIG_X86_IO_APIC
  1719. static int dmi_disable_ioapicreroute(const struct dmi_system_id *d)
  1720. {
  1721. noioapicreroute = 1;
  1722. pr_info("%s detected: disable boot interrupt reroute\n", d->ident);
  1723. return 0;
  1724. }
  1725. static const struct dmi_system_id boot_interrupt_dmi_table[] = {
  1726. /*
  1727. * Systems to exclude from boot interrupt reroute quirks
  1728. */
  1729. {
  1730. .callback = dmi_disable_ioapicreroute,
  1731. .ident = "ASUSTek Computer INC. M2N-LR",
  1732. .matches = {
  1733. DMI_MATCH(DMI_SYS_VENDOR, "ASUSTek Computer INC."),
  1734. DMI_MATCH(DMI_PRODUCT_NAME, "M2N-LR"),
  1735. },
  1736. },
  1737. {}
  1738. };
  1739. /*
  1740. * Boot interrupts on some chipsets cannot be turned off. For these chipsets,
  1741. * remap the original interrupt in the Linux kernel to the boot interrupt, so
  1742. * that a PCI device's interrupt handler is installed on the boot interrupt
  1743. * line instead.
  1744. */
  1745. static void quirk_reroute_to_boot_interrupts_intel(struct pci_dev *dev)
  1746. {
  1747. dmi_check_system(boot_interrupt_dmi_table);
  1748. if (noioapicquirk || noioapicreroute)
  1749. return;
  1750. dev->irq_reroute_variant = INTEL_IRQ_REROUTE_VARIANT;
  1751. pci_info(dev, "rerouting interrupts for [%04x:%04x]\n",
  1752. dev->vendor, dev->device);
  1753. }
  1754. DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_80333_0, quirk_reroute_to_boot_interrupts_intel);
  1755. DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_80333_1, quirk_reroute_to_boot_interrupts_intel);
  1756. DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ESB2_0, quirk_reroute_to_boot_interrupts_intel);
  1757. DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PXH_0, quirk_reroute_to_boot_interrupts_intel);
  1758. DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PXH_1, quirk_reroute_to_boot_interrupts_intel);
  1759. DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PXHV, quirk_reroute_to_boot_interrupts_intel);
  1760. DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_80332_0, quirk_reroute_to_boot_interrupts_intel);
  1761. DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_80332_1, quirk_reroute_to_boot_interrupts_intel);
  1762. DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_80333_0, quirk_reroute_to_boot_interrupts_intel);
  1763. DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_80333_1, quirk_reroute_to_boot_interrupts_intel);
  1764. DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ESB2_0, quirk_reroute_to_boot_interrupts_intel);
  1765. DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PXH_0, quirk_reroute_to_boot_interrupts_intel);
  1766. DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PXH_1, quirk_reroute_to_boot_interrupts_intel);
  1767. DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PXHV, quirk_reroute_to_boot_interrupts_intel);
  1768. DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_80332_0, quirk_reroute_to_boot_interrupts_intel);
  1769. DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_80332_1, quirk_reroute_to_boot_interrupts_intel);
  1770. /*
  1771. * On some chipsets we can disable the generation of legacy INTx boot
  1772. * interrupts.
  1773. */
  1774. /*
  1775. * IO-APIC1 on 6300ESB generates boot interrupts, see Intel order no
  1776. * 300641-004US, section 5.7.3.
  1777. *
  1778. * Core IO on Xeon E5 1600/2600/4600, see Intel order no 326509-003.
  1779. * Core IO on Xeon E5 v2, see Intel order no 329188-003.
  1780. * Core IO on Xeon E7 v2, see Intel order no 329595-002.
  1781. * Core IO on Xeon E5 v3, see Intel order no 330784-003.
  1782. * Core IO on Xeon E7 v3, see Intel order no 332315-001US.
  1783. * Core IO on Xeon E5 v4, see Intel order no 333810-002US.
  1784. * Core IO on Xeon E7 v4, see Intel order no 332315-001US.
  1785. * Core IO on Xeon D-1500, see Intel order no 332051-001.
  1786. * Core IO on Xeon Scalable, see Intel order no 610950.
  1787. */
  1788. #define INTEL_6300_IOAPIC_ABAR 0x40 /* Bus 0, Dev 29, Func 5 */
  1789. #define INTEL_6300_DISABLE_BOOT_IRQ (1<<14)
  1790. #define INTEL_CIPINTRC_CFG_OFFSET 0x14C /* Bus 0, Dev 5, Func 0 */
  1791. #define INTEL_CIPINTRC_DIS_INTX_ICH (1<<25)
  1792. static void quirk_disable_intel_boot_interrupt(struct pci_dev *dev)
  1793. {
  1794. u16 pci_config_word;
  1795. u32 pci_config_dword;
  1796. if (noioapicquirk)
  1797. return;
  1798. switch (dev->device) {
  1799. case PCI_DEVICE_ID_INTEL_ESB_10:
  1800. pci_read_config_word(dev, INTEL_6300_IOAPIC_ABAR,
  1801. &pci_config_word);
  1802. pci_config_word |= INTEL_6300_DISABLE_BOOT_IRQ;
  1803. pci_write_config_word(dev, INTEL_6300_IOAPIC_ABAR,
  1804. pci_config_word);
  1805. break;
  1806. case 0x3c28: /* Xeon E5 1600/2600/4600 */
  1807. case 0x0e28: /* Xeon E5/E7 V2 */
  1808. case 0x2f28: /* Xeon E5/E7 V3,V4 */
  1809. case 0x6f28: /* Xeon D-1500 */
  1810. case 0x2034: /* Xeon Scalable Family */
  1811. pci_read_config_dword(dev, INTEL_CIPINTRC_CFG_OFFSET,
  1812. &pci_config_dword);
  1813. pci_config_dword |= INTEL_CIPINTRC_DIS_INTX_ICH;
  1814. pci_write_config_dword(dev, INTEL_CIPINTRC_CFG_OFFSET,
  1815. pci_config_dword);
  1816. break;
  1817. default:
  1818. return;
  1819. }
  1820. pci_info(dev, "disabled boot interrupts on device [%04x:%04x]\n",
  1821. dev->vendor, dev->device);
  1822. }
  1823. /*
  1824. * Device 29 Func 5 Device IDs of IO-APIC
  1825. * containing ABAR—APIC1 Alternate Base Address Register
  1826. */
  1827. DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ESB_10,
  1828. quirk_disable_intel_boot_interrupt);
  1829. DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ESB_10,
  1830. quirk_disable_intel_boot_interrupt);
  1831. /*
  1832. * Device 5 Func 0 Device IDs of Core IO modules/hubs
  1833. * containing Coherent Interface Protocol Interrupt Control
  1834. *
  1835. * Device IDs obtained from volume 2 datasheets of commented
  1836. * families above.
  1837. */
  1838. DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x3c28,
  1839. quirk_disable_intel_boot_interrupt);
  1840. DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x0e28,
  1841. quirk_disable_intel_boot_interrupt);
  1842. DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x2f28,
  1843. quirk_disable_intel_boot_interrupt);
  1844. DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x6f28,
  1845. quirk_disable_intel_boot_interrupt);
  1846. DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x2034,
  1847. quirk_disable_intel_boot_interrupt);
  1848. DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_INTEL, 0x3c28,
  1849. quirk_disable_intel_boot_interrupt);
  1850. DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_INTEL, 0x0e28,
  1851. quirk_disable_intel_boot_interrupt);
  1852. DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_INTEL, 0x2f28,
  1853. quirk_disable_intel_boot_interrupt);
  1854. DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_INTEL, 0x6f28,
  1855. quirk_disable_intel_boot_interrupt);
  1856. DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_INTEL, 0x2034,
  1857. quirk_disable_intel_boot_interrupt);
  1858. /* Disable boot interrupts on HT-1000 */
  1859. #define BC_HT1000_FEATURE_REG 0x64
  1860. #define BC_HT1000_PIC_REGS_ENABLE (1<<0)
  1861. #define BC_HT1000_MAP_IDX 0xC00
  1862. #define BC_HT1000_MAP_DATA 0xC01
  1863. static void quirk_disable_broadcom_boot_interrupt(struct pci_dev *dev)
  1864. {
  1865. u32 pci_config_dword;
  1866. u8 irq;
  1867. if (noioapicquirk)
  1868. return;
  1869. pci_read_config_dword(dev, BC_HT1000_FEATURE_REG, &pci_config_dword);
  1870. pci_write_config_dword(dev, BC_HT1000_FEATURE_REG, pci_config_dword |
  1871. BC_HT1000_PIC_REGS_ENABLE);
  1872. for (irq = 0x10; irq < 0x10 + 32; irq++) {
  1873. outb(irq, BC_HT1000_MAP_IDX);
  1874. outb(0x00, BC_HT1000_MAP_DATA);
  1875. }
  1876. pci_write_config_dword(dev, BC_HT1000_FEATURE_REG, pci_config_dword);
  1877. pci_info(dev, "disabled boot interrupts on device [%04x:%04x]\n",
  1878. dev->vendor, dev->device);
  1879. }
  1880. DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_SERVERWORKS, PCI_DEVICE_ID_SERVERWORKS_HT1000SB, quirk_disable_broadcom_boot_interrupt);
  1881. DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_SERVERWORKS, PCI_DEVICE_ID_SERVERWORKS_HT1000SB, quirk_disable_broadcom_boot_interrupt);
  1882. /* Disable boot interrupts on AMD and ATI chipsets */
  1883. /*
  1884. * NOIOAMODE needs to be disabled to disable "boot interrupts". For AMD 8131
  1885. * rev. A0 and B0, NOIOAMODE needs to be disabled anyway to fix IO-APIC mode
  1886. * (due to an erratum).
  1887. */
  1888. #define AMD_813X_MISC 0x40
  1889. #define AMD_813X_NOIOAMODE (1<<0)
  1890. #define AMD_813X_REV_B1 0x12
  1891. #define AMD_813X_REV_B2 0x13
  1892. static void quirk_disable_amd_813x_boot_interrupt(struct pci_dev *dev)
  1893. {
  1894. u32 pci_config_dword;
  1895. if (noioapicquirk)
  1896. return;
  1897. if ((dev->revision == AMD_813X_REV_B1) ||
  1898. (dev->revision == AMD_813X_REV_B2))
  1899. return;
  1900. pci_read_config_dword(dev, AMD_813X_MISC, &pci_config_dword);
  1901. pci_config_dword &= ~AMD_813X_NOIOAMODE;
  1902. pci_write_config_dword(dev, AMD_813X_MISC, pci_config_dword);
  1903. pci_info(dev, "disabled boot interrupts on device [%04x:%04x]\n",
  1904. dev->vendor, dev->device);
  1905. }
  1906. DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_8131_BRIDGE, quirk_disable_amd_813x_boot_interrupt);
  1907. DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_8131_BRIDGE, quirk_disable_amd_813x_boot_interrupt);
  1908. DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_8132_BRIDGE, quirk_disable_amd_813x_boot_interrupt);
  1909. DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_8132_BRIDGE, quirk_disable_amd_813x_boot_interrupt);
  1910. #define AMD_8111_PCI_IRQ_ROUTING 0x56
  1911. static void quirk_disable_amd_8111_boot_interrupt(struct pci_dev *dev)
  1912. {
  1913. u16 pci_config_word;
  1914. if (noioapicquirk)
  1915. return;
  1916. pci_read_config_word(dev, AMD_8111_PCI_IRQ_ROUTING, &pci_config_word);
  1917. if (!pci_config_word) {
  1918. pci_info(dev, "boot interrupts on device [%04x:%04x] already disabled\n",
  1919. dev->vendor, dev->device);
  1920. return;
  1921. }
  1922. pci_write_config_word(dev, AMD_8111_PCI_IRQ_ROUTING, 0);
  1923. pci_info(dev, "disabled boot interrupts on device [%04x:%04x]\n",
  1924. dev->vendor, dev->device);
  1925. }
  1926. DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_8111_SMBUS, quirk_disable_amd_8111_boot_interrupt);
  1927. DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_8111_SMBUS, quirk_disable_amd_8111_boot_interrupt);
  1928. #endif /* CONFIG_X86_IO_APIC */
  1929. /*
  1930. * Toshiba TC86C001 IDE controller reports the standard 8-byte BAR0 size
  1931. * but the PIO transfers won't work if BAR0 falls at the odd 8 bytes.
  1932. * Re-allocate the region if needed...
  1933. */
  1934. static void quirk_tc86c001_ide(struct pci_dev *dev)
  1935. {
  1936. struct resource *r = &dev->resource[0];
  1937. if (r->start & 0x8) {
  1938. r->flags |= IORESOURCE_UNSET;
  1939. r->start = 0;
  1940. r->end = 0xf;
  1941. }
  1942. }
  1943. DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_TOSHIBA_2,
  1944. PCI_DEVICE_ID_TOSHIBA_TC86C001_IDE,
  1945. quirk_tc86c001_ide);
  1946. /*
  1947. * PLX PCI 9050 PCI Target bridge controller has an erratum that prevents the
  1948. * local configuration registers accessible via BAR0 (memory) or BAR1 (i/o)
  1949. * being read correctly if bit 7 of the base address is set.
  1950. * The BAR0 or BAR1 region may be disabled (size 0) or enabled (size 128).
  1951. * Re-allocate the regions to a 256-byte boundary if necessary.
  1952. */
  1953. static void quirk_plx_pci9050(struct pci_dev *dev)
  1954. {
  1955. unsigned int bar;
  1956. /* Fixed in revision 2 (PCI 9052). */
  1957. if (dev->revision >= 2)
  1958. return;
  1959. for (bar = 0; bar <= 1; bar++)
  1960. if (pci_resource_len(dev, bar) == 0x80 &&
  1961. (pci_resource_start(dev, bar) & 0x80)) {
  1962. struct resource *r = &dev->resource[bar];
  1963. pci_info(dev, "Re-allocating PLX PCI 9050 BAR %u to length 256 to avoid bit 7 bug\n",
  1964. bar);
  1965. r->flags |= IORESOURCE_UNSET;
  1966. r->start = 0;
  1967. r->end = 0xff;
  1968. }
  1969. }
  1970. DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050,
  1971. quirk_plx_pci9050);
  1972. /*
  1973. * The following Meilhaus (vendor ID 0x1402) device IDs (amongst others)
  1974. * may be using the PLX PCI 9050: 0x0630, 0x0940, 0x0950, 0x0960, 0x100b,
  1975. * 0x1400, 0x140a, 0x140b, 0x14e0, 0x14ea, 0x14eb, 0x1604, 0x1608, 0x160c,
  1976. * 0x168f, 0x2000, 0x2600, 0x3000, 0x810a, 0x810b.
  1977. *
  1978. * Currently, device IDs 0x2000 and 0x2600 are used by the Comedi "me_daq"
  1979. * driver.
  1980. */
  1981. DECLARE_PCI_FIXUP_HEADER(0x1402, 0x2000, quirk_plx_pci9050);
  1982. DECLARE_PCI_FIXUP_HEADER(0x1402, 0x2600, quirk_plx_pci9050);
  1983. static void quirk_netmos(struct pci_dev *dev)
  1984. {
  1985. unsigned int num_parallel = (dev->subsystem_device & 0xf0) >> 4;
  1986. unsigned int num_serial = dev->subsystem_device & 0xf;
  1987. /*
  1988. * These Netmos parts are multiport serial devices with optional
  1989. * parallel ports. Even when parallel ports are present, they
  1990. * are identified as class SERIAL, which means the serial driver
  1991. * will claim them. To prevent this, mark them as class OTHER.
  1992. * These combo devices should be claimed by parport_serial.
  1993. *
  1994. * The subdevice ID is of the form 0x00PS, where <P> is the number
  1995. * of parallel ports and <S> is the number of serial ports.
  1996. */
  1997. switch (dev->device) {
  1998. case PCI_DEVICE_ID_NETMOS_9835:
  1999. /* Well, this rule doesn't hold for the following 9835 device */
  2000. if (dev->subsystem_vendor == PCI_VENDOR_ID_IBM &&
  2001. dev->subsystem_device == 0x0299)
  2002. return;
  2003. fallthrough;
  2004. case PCI_DEVICE_ID_NETMOS_9735:
  2005. case PCI_DEVICE_ID_NETMOS_9745:
  2006. case PCI_DEVICE_ID_NETMOS_9845:
  2007. case PCI_DEVICE_ID_NETMOS_9855:
  2008. if (num_parallel) {
  2009. pci_info(dev, "Netmos %04x (%u parallel, %u serial); changing class SERIAL to OTHER (use parport_serial)\n",
  2010. dev->device, num_parallel, num_serial);
  2011. dev->class = (PCI_CLASS_COMMUNICATION_OTHER << 8) |
  2012. (dev->class & 0xff);
  2013. }
  2014. }
  2015. }
  2016. DECLARE_PCI_FIXUP_CLASS_HEADER(PCI_VENDOR_ID_NETMOS, PCI_ANY_ID,
  2017. PCI_CLASS_COMMUNICATION_SERIAL, 8, quirk_netmos);
  2018. static void quirk_e100_interrupt(struct pci_dev *dev)
  2019. {
  2020. u16 command, pmcsr;
  2021. u8 __iomem *csr;
  2022. u8 cmd_hi;
  2023. switch (dev->device) {
  2024. /* PCI IDs taken from drivers/net/e100.c */
  2025. case 0x1029:
  2026. case 0x1030 ... 0x1034:
  2027. case 0x1038 ... 0x103E:
  2028. case 0x1050 ... 0x1057:
  2029. case 0x1059:
  2030. case 0x1064 ... 0x106B:
  2031. case 0x1091 ... 0x1095:
  2032. case 0x1209:
  2033. case 0x1229:
  2034. case 0x2449:
  2035. case 0x2459:
  2036. case 0x245D:
  2037. case 0x27DC:
  2038. break;
  2039. default:
  2040. return;
  2041. }
  2042. /*
  2043. * Some firmware hands off the e100 with interrupts enabled,
  2044. * which can cause a flood of interrupts if packets are
  2045. * received before the driver attaches to the device. So
  2046. * disable all e100 interrupts here. The driver will
  2047. * re-enable them when it's ready.
  2048. */
  2049. pci_read_config_word(dev, PCI_COMMAND, &command);
  2050. if (!(command & PCI_COMMAND_MEMORY) || !pci_resource_start(dev, 0))
  2051. return;
  2052. /*
  2053. * Check that the device is in the D0 power state. If it's not,
  2054. * there is no point to look any further.
  2055. */
  2056. if (dev->pm_cap) {
  2057. pci_read_config_word(dev, dev->pm_cap + PCI_PM_CTRL, &pmcsr);
  2058. if ((pmcsr & PCI_PM_CTRL_STATE_MASK) != PCI_D0)
  2059. return;
  2060. }
  2061. /* Convert from PCI bus to resource space. */
  2062. csr = ioremap(pci_resource_start(dev, 0), 8);
  2063. if (!csr) {
  2064. pci_warn(dev, "Can't map e100 registers\n");
  2065. return;
  2066. }
  2067. cmd_hi = readb(csr + 3);
  2068. if (cmd_hi == 0) {
  2069. pci_warn(dev, "Firmware left e100 interrupts enabled; disabling\n");
  2070. writeb(1, csr + 3);
  2071. }
  2072. iounmap(csr);
  2073. }
  2074. DECLARE_PCI_FIXUP_CLASS_FINAL(PCI_VENDOR_ID_INTEL, PCI_ANY_ID,
  2075. PCI_CLASS_NETWORK_ETHERNET, 8, quirk_e100_interrupt);
  2076. /*
  2077. * The 82575 and 82598 may experience data corruption issues when transitioning
  2078. * out of L0S. To prevent this we need to disable L0S on the PCIe link.
  2079. */
  2080. static void quirk_disable_aspm_l0s(struct pci_dev *dev)
  2081. {
  2082. pci_info(dev, "Disabling L0s\n");
  2083. pci_disable_link_state(dev, PCIE_LINK_STATE_L0S);
  2084. }
  2085. DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x10a7, quirk_disable_aspm_l0s);
  2086. DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x10a9, quirk_disable_aspm_l0s);
  2087. DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x10b6, quirk_disable_aspm_l0s);
  2088. DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x10c6, quirk_disable_aspm_l0s);
  2089. DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x10c7, quirk_disable_aspm_l0s);
  2090. DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x10c8, quirk_disable_aspm_l0s);
  2091. DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x10d6, quirk_disable_aspm_l0s);
  2092. DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x10db, quirk_disable_aspm_l0s);
  2093. DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x10dd, quirk_disable_aspm_l0s);
  2094. DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x10e1, quirk_disable_aspm_l0s);
  2095. DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x10ec, quirk_disable_aspm_l0s);
  2096. DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x10f1, quirk_disable_aspm_l0s);
  2097. DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x10f4, quirk_disable_aspm_l0s);
  2098. DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x1508, quirk_disable_aspm_l0s);
  2099. static void quirk_disable_aspm_l0s_l1(struct pci_dev *dev)
  2100. {
  2101. pci_info(dev, "Disabling ASPM L0s/L1\n");
  2102. pci_disable_link_state(dev, PCIE_LINK_STATE_L0S | PCIE_LINK_STATE_L1);
  2103. }
  2104. /*
  2105. * ASM1083/1085 PCIe-PCI bridge devices cause AER timeout errors on the
  2106. * upstream PCIe root port when ASPM is enabled. At least L0s mode is affected;
  2107. * disable both L0s and L1 for now to be safe.
  2108. */
  2109. DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ASMEDIA, 0x1080, quirk_disable_aspm_l0s_l1);
  2110. /*
  2111. * Some Pericom PCIe-to-PCI bridges in reverse mode need the PCIe Retrain
  2112. * Link bit cleared after starting the link retrain process to allow this
  2113. * process to finish.
  2114. *
  2115. * Affected devices: PI7C9X110, PI7C9X111SL, PI7C9X130. See also the
  2116. * Pericom Errata Sheet PI7C9X111SLB_errata_rev1.2_102711.pdf.
  2117. */
  2118. static void quirk_enable_clear_retrain_link(struct pci_dev *dev)
  2119. {
  2120. dev->clear_retrain_link = 1;
  2121. pci_info(dev, "Enable PCIe Retrain Link quirk\n");
  2122. }
  2123. DECLARE_PCI_FIXUP_HEADER(0x12d8, 0xe110, quirk_enable_clear_retrain_link);
  2124. DECLARE_PCI_FIXUP_HEADER(0x12d8, 0xe111, quirk_enable_clear_retrain_link);
  2125. DECLARE_PCI_FIXUP_HEADER(0x12d8, 0xe130, quirk_enable_clear_retrain_link);
  2126. static void fixup_rev1_53c810(struct pci_dev *dev)
  2127. {
  2128. u32 class = dev->class;
  2129. /*
  2130. * rev 1 ncr53c810 chips don't set the class at all which means
  2131. * they don't get their resources remapped. Fix that here.
  2132. */
  2133. if (class)
  2134. return;
  2135. dev->class = PCI_CLASS_STORAGE_SCSI << 8;
  2136. pci_info(dev, "NCR 53c810 rev 1 PCI class overridden (%#08x -> %#08x)\n",
  2137. class, dev->class);
  2138. }
  2139. DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_NCR, PCI_DEVICE_ID_NCR_53C810, fixup_rev1_53c810);
  2140. /* Enable 1k I/O space granularity on the Intel P64H2 */
  2141. static void quirk_p64h2_1k_io(struct pci_dev *dev)
  2142. {
  2143. u16 en1k;
  2144. pci_read_config_word(dev, 0x40, &en1k);
  2145. if (en1k & 0x200) {
  2146. pci_info(dev, "Enable I/O Space to 1KB granularity\n");
  2147. dev->io_window_1k = 1;
  2148. }
  2149. }
  2150. DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x1460, quirk_p64h2_1k_io);
  2151. /*
  2152. * Under some circumstances, AER is not linked with extended capabilities.
  2153. * Force it to be linked by setting the corresponding control bit in the
  2154. * config space.
  2155. */
  2156. static void quirk_nvidia_ck804_pcie_aer_ext_cap(struct pci_dev *dev)
  2157. {
  2158. uint8_t b;
  2159. if (pci_read_config_byte(dev, 0xf41, &b) == 0) {
  2160. if (!(b & 0x20)) {
  2161. pci_write_config_byte(dev, 0xf41, b | 0x20);
  2162. pci_info(dev, "Linking AER extended capability\n");
  2163. }
  2164. }
  2165. }
  2166. DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_CK804_PCIE,
  2167. quirk_nvidia_ck804_pcie_aer_ext_cap);
  2168. DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_CK804_PCIE,
  2169. quirk_nvidia_ck804_pcie_aer_ext_cap);
  2170. static void quirk_via_cx700_pci_parking_caching(struct pci_dev *dev)
  2171. {
  2172. /*
  2173. * Disable PCI Bus Parking and PCI Master read caching on CX700
  2174. * which causes unspecified timing errors with a VT6212L on the PCI
  2175. * bus leading to USB2.0 packet loss.
  2176. *
  2177. * This quirk is only enabled if a second (on the external PCI bus)
  2178. * VT6212L is found -- the CX700 core itself also contains a USB
  2179. * host controller with the same PCI ID as the VT6212L.
  2180. */
  2181. /* Count VT6212L instances */
  2182. struct pci_dev *p = pci_get_device(PCI_VENDOR_ID_VIA,
  2183. PCI_DEVICE_ID_VIA_8235_USB_2, NULL);
  2184. uint8_t b;
  2185. /*
  2186. * p should contain the first (internal) VT6212L -- see if we have
  2187. * an external one by searching again.
  2188. */
  2189. p = pci_get_device(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8235_USB_2, p);
  2190. if (!p)
  2191. return;
  2192. pci_dev_put(p);
  2193. if (pci_read_config_byte(dev, 0x76, &b) == 0) {
  2194. if (b & 0x40) {
  2195. /* Turn off PCI Bus Parking */
  2196. pci_write_config_byte(dev, 0x76, b ^ 0x40);
  2197. pci_info(dev, "Disabling VIA CX700 PCI parking\n");
  2198. }
  2199. }
  2200. if (pci_read_config_byte(dev, 0x72, &b) == 0) {
  2201. if (b != 0) {
  2202. /* Turn off PCI Master read caching */
  2203. pci_write_config_byte(dev, 0x72, 0x0);
  2204. /* Set PCI Master Bus time-out to "1x16 PCLK" */
  2205. pci_write_config_byte(dev, 0x75, 0x1);
  2206. /* Disable "Read FIFO Timer" */
  2207. pci_write_config_byte(dev, 0x77, 0x0);
  2208. pci_info(dev, "Disabling VIA CX700 PCI caching\n");
  2209. }
  2210. }
  2211. }
  2212. DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, 0x324e, quirk_via_cx700_pci_parking_caching);
  2213. static void quirk_brcm_5719_limit_mrrs(struct pci_dev *dev)
  2214. {
  2215. u32 rev;
  2216. pci_read_config_dword(dev, 0xf4, &rev);
  2217. /* Only CAP the MRRS if the device is a 5719 A0 */
  2218. if (rev == 0x05719000) {
  2219. int readrq = pcie_get_readrq(dev);
  2220. if (readrq > 2048)
  2221. pcie_set_readrq(dev, 2048);
  2222. }
  2223. }
  2224. DECLARE_PCI_FIXUP_ENABLE(PCI_VENDOR_ID_BROADCOM,
  2225. PCI_DEVICE_ID_TIGON3_5719,
  2226. quirk_brcm_5719_limit_mrrs);
  2227. /*
  2228. * Originally in EDAC sources for i82875P: Intel tells BIOS developers to
  2229. * hide device 6 which configures the overflow device access containing the
  2230. * DRBs - this is where we expose device 6.
  2231. * http://www.x86-secret.com/articles/tweak/pat/patsecrets-2.htm
  2232. */
  2233. static void quirk_unhide_mch_dev6(struct pci_dev *dev)
  2234. {
  2235. u8 reg;
  2236. if (pci_read_config_byte(dev, 0xF4, &reg) == 0 && !(reg & 0x02)) {
  2237. pci_info(dev, "Enabling MCH 'Overflow' Device\n");
  2238. pci_write_config_byte(dev, 0xF4, reg | 0x02);
  2239. }
  2240. }
  2241. DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82865_HB,
  2242. quirk_unhide_mch_dev6);
  2243. DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82875_HB,
  2244. quirk_unhide_mch_dev6);
  2245. #ifdef CONFIG_PCI_MSI
  2246. /*
  2247. * Some chipsets do not support MSI. We cannot easily rely on setting
  2248. * PCI_BUS_FLAGS_NO_MSI in its bus flags because there are actually some
  2249. * other buses controlled by the chipset even if Linux is not aware of it.
  2250. * Instead of setting the flag on all buses in the machine, simply disable
  2251. * MSI globally.
  2252. */
  2253. static void quirk_disable_all_msi(struct pci_dev *dev)
  2254. {
  2255. pci_no_msi();
  2256. pci_warn(dev, "MSI quirk detected; MSI disabled\n");
  2257. }
  2258. DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_SERVERWORKS, PCI_DEVICE_ID_SERVERWORKS_GCNB_LE, quirk_disable_all_msi);
  2259. DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_RS400_200, quirk_disable_all_msi);
  2260. DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_RS480, quirk_disable_all_msi);
  2261. DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_VT3336, quirk_disable_all_msi);
  2262. DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_VT3351, quirk_disable_all_msi);
  2263. DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_VT3364, quirk_disable_all_msi);
  2264. DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8380_0, quirk_disable_all_msi);
  2265. DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_SI, 0x0761, quirk_disable_all_msi);
  2266. /* Disable MSI on chipsets that are known to not support it */
  2267. static void quirk_disable_msi(struct pci_dev *dev)
  2268. {
  2269. if (dev->subordinate) {
  2270. pci_warn(dev, "MSI quirk detected; subordinate MSI disabled\n");
  2271. dev->subordinate->bus_flags |= PCI_BUS_FLAGS_NO_MSI;
  2272. }
  2273. }
  2274. DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_8131_BRIDGE, quirk_disable_msi);
  2275. DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, 0xa238, quirk_disable_msi);
  2276. DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0x5a3f, quirk_disable_msi);
  2277. /*
  2278. * The APC bridge device in AMD 780 family northbridges has some random
  2279. * OEM subsystem ID in its vendor ID register (erratum 18), so instead
  2280. * we use the possible vendor/device IDs of the host bridge for the
  2281. * declared quirk, and search for the APC bridge by slot number.
  2282. */
  2283. static void quirk_amd_780_apc_msi(struct pci_dev *host_bridge)
  2284. {
  2285. struct pci_dev *apc_bridge;
  2286. apc_bridge = pci_get_slot(host_bridge->bus, PCI_DEVFN(1, 0));
  2287. if (apc_bridge) {
  2288. if (apc_bridge->device == 0x9602)
  2289. quirk_disable_msi(apc_bridge);
  2290. pci_dev_put(apc_bridge);
  2291. }
  2292. }
  2293. DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AMD, 0x9600, quirk_amd_780_apc_msi);
  2294. DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AMD, 0x9601, quirk_amd_780_apc_msi);
  2295. /*
  2296. * Go through the list of HyperTransport capabilities and return 1 if a HT
  2297. * MSI capability is found and enabled.
  2298. */
  2299. static int msi_ht_cap_enabled(struct pci_dev *dev)
  2300. {
  2301. int pos, ttl = PCI_FIND_CAP_TTL;
  2302. pos = pci_find_ht_capability(dev, HT_CAPTYPE_MSI_MAPPING);
  2303. while (pos && ttl--) {
  2304. u8 flags;
  2305. if (pci_read_config_byte(dev, pos + HT_MSI_FLAGS,
  2306. &flags) == 0) {
  2307. pci_info(dev, "Found %s HT MSI Mapping\n",
  2308. flags & HT_MSI_FLAGS_ENABLE ?
  2309. "enabled" : "disabled");
  2310. return (flags & HT_MSI_FLAGS_ENABLE) != 0;
  2311. }
  2312. pos = pci_find_next_ht_capability(dev, pos,
  2313. HT_CAPTYPE_MSI_MAPPING);
  2314. }
  2315. return 0;
  2316. }
  2317. /* Check the HyperTransport MSI mapping to know whether MSI is enabled or not */
  2318. static void quirk_msi_ht_cap(struct pci_dev *dev)
  2319. {
  2320. if (dev->subordinate && !msi_ht_cap_enabled(dev)) {
  2321. pci_warn(dev, "MSI quirk detected; subordinate MSI disabled\n");
  2322. dev->subordinate->bus_flags |= PCI_BUS_FLAGS_NO_MSI;
  2323. }
  2324. }
  2325. DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_SERVERWORKS, PCI_DEVICE_ID_SERVERWORKS_HT2000_PCIE,
  2326. quirk_msi_ht_cap);
  2327. /*
  2328. * The nVidia CK804 chipset may have 2 HT MSI mappings. MSI is supported
  2329. * if the MSI capability is set in any of these mappings.
  2330. */
  2331. static void quirk_nvidia_ck804_msi_ht_cap(struct pci_dev *dev)
  2332. {
  2333. struct pci_dev *pdev;
  2334. if (!dev->subordinate)
  2335. return;
  2336. /*
  2337. * Check HT MSI cap on this chipset and the root one. A single one
  2338. * having MSI is enough to be sure that MSI is supported.
  2339. */
  2340. pdev = pci_get_slot(dev->bus, 0);
  2341. if (!pdev)
  2342. return;
  2343. if (!msi_ht_cap_enabled(dev) && !msi_ht_cap_enabled(pdev)) {
  2344. pci_warn(dev, "MSI quirk detected; subordinate MSI disabled\n");
  2345. dev->subordinate->bus_flags |= PCI_BUS_FLAGS_NO_MSI;
  2346. }
  2347. pci_dev_put(pdev);
  2348. }
  2349. DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_CK804_PCIE,
  2350. quirk_nvidia_ck804_msi_ht_cap);
  2351. /* Force enable MSI mapping capability on HT bridges */
  2352. static void ht_enable_msi_mapping(struct pci_dev *dev)
  2353. {
  2354. int pos, ttl = PCI_FIND_CAP_TTL;
  2355. pos = pci_find_ht_capability(dev, HT_CAPTYPE_MSI_MAPPING);
  2356. while (pos && ttl--) {
  2357. u8 flags;
  2358. if (pci_read_config_byte(dev, pos + HT_MSI_FLAGS,
  2359. &flags) == 0) {
  2360. pci_info(dev, "Enabling HT MSI Mapping\n");
  2361. pci_write_config_byte(dev, pos + HT_MSI_FLAGS,
  2362. flags | HT_MSI_FLAGS_ENABLE);
  2363. }
  2364. pos = pci_find_next_ht_capability(dev, pos,
  2365. HT_CAPTYPE_MSI_MAPPING);
  2366. }
  2367. }
  2368. DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_SERVERWORKS,
  2369. PCI_DEVICE_ID_SERVERWORKS_HT1000_PXB,
  2370. ht_enable_msi_mapping);
  2371. DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_8132_BRIDGE,
  2372. ht_enable_msi_mapping);
  2373. /*
  2374. * The P5N32-SLI motherboards from Asus have a problem with MSI
  2375. * for the MCP55 NIC. It is not yet determined whether the MSI problem
  2376. * also affects other devices. As for now, turn off MSI for this device.
  2377. */
  2378. static void nvenet_msi_disable(struct pci_dev *dev)
  2379. {
  2380. const char *board_name = dmi_get_system_info(DMI_BOARD_NAME);
  2381. if (board_name &&
  2382. (strstr(board_name, "P5N32-SLI PREMIUM") ||
  2383. strstr(board_name, "P5N32-E SLI"))) {
  2384. pci_info(dev, "Disabling MSI for MCP55 NIC on P5N32-SLI\n");
  2385. dev->no_msi = 1;
  2386. }
  2387. }
  2388. DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_NVIDIA,
  2389. PCI_DEVICE_ID_NVIDIA_NVENET_15,
  2390. nvenet_msi_disable);
  2391. /*
  2392. * PCIe spec r4.0 sec 7.7.1.2 and sec 7.7.2.2 say that if MSI/MSI-X is enabled,
  2393. * then the device can't use INTx interrupts. Tegra's PCIe root ports don't
  2394. * generate MSI interrupts for PME and AER events instead only INTx interrupts
  2395. * are generated. Though Tegra's PCIe root ports can generate MSI interrupts
  2396. * for other events, since PCIe specificiation doesn't support using a mix of
  2397. * INTx and MSI/MSI-X, it is required to disable MSI interrupts to avoid port
  2398. * service drivers registering their respective ISRs for MSIs.
  2399. */
  2400. static void pci_quirk_nvidia_tegra_disable_rp_msi(struct pci_dev *dev)
  2401. {
  2402. dev->no_msi = 1;
  2403. }
  2404. DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_NVIDIA, 0x1ad0,
  2405. PCI_CLASS_BRIDGE_PCI, 8,
  2406. pci_quirk_nvidia_tegra_disable_rp_msi);
  2407. DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_NVIDIA, 0x1ad1,
  2408. PCI_CLASS_BRIDGE_PCI, 8,
  2409. pci_quirk_nvidia_tegra_disable_rp_msi);
  2410. DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_NVIDIA, 0x1ad2,
  2411. PCI_CLASS_BRIDGE_PCI, 8,
  2412. pci_quirk_nvidia_tegra_disable_rp_msi);
  2413. DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_NVIDIA, 0x0bf0,
  2414. PCI_CLASS_BRIDGE_PCI, 8,
  2415. pci_quirk_nvidia_tegra_disable_rp_msi);
  2416. DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_NVIDIA, 0x0bf1,
  2417. PCI_CLASS_BRIDGE_PCI, 8,
  2418. pci_quirk_nvidia_tegra_disable_rp_msi);
  2419. DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_NVIDIA, 0x0e1c,
  2420. PCI_CLASS_BRIDGE_PCI, 8,
  2421. pci_quirk_nvidia_tegra_disable_rp_msi);
  2422. DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_NVIDIA, 0x0e1d,
  2423. PCI_CLASS_BRIDGE_PCI, 8,
  2424. pci_quirk_nvidia_tegra_disable_rp_msi);
  2425. DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_NVIDIA, 0x0e12,
  2426. PCI_CLASS_BRIDGE_PCI, 8,
  2427. pci_quirk_nvidia_tegra_disable_rp_msi);
  2428. DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_NVIDIA, 0x0e13,
  2429. PCI_CLASS_BRIDGE_PCI, 8,
  2430. pci_quirk_nvidia_tegra_disable_rp_msi);
  2431. DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_NVIDIA, 0x0fae,
  2432. PCI_CLASS_BRIDGE_PCI, 8,
  2433. pci_quirk_nvidia_tegra_disable_rp_msi);
  2434. DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_NVIDIA, 0x0faf,
  2435. PCI_CLASS_BRIDGE_PCI, 8,
  2436. pci_quirk_nvidia_tegra_disable_rp_msi);
  2437. DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_NVIDIA, 0x10e5,
  2438. PCI_CLASS_BRIDGE_PCI, 8,
  2439. pci_quirk_nvidia_tegra_disable_rp_msi);
  2440. DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_NVIDIA, 0x10e6,
  2441. PCI_CLASS_BRIDGE_PCI, 8,
  2442. pci_quirk_nvidia_tegra_disable_rp_msi);
  2443. /*
  2444. * Some versions of the MCP55 bridge from Nvidia have a legacy IRQ routing
  2445. * config register. This register controls the routing of legacy
  2446. * interrupts from devices that route through the MCP55. If this register
  2447. * is misprogrammed, interrupts are only sent to the BSP, unlike
  2448. * conventional systems where the IRQ is broadcast to all online CPUs. Not
  2449. * having this register set properly prevents kdump from booting up
  2450. * properly, so let's make sure that we have it set correctly.
  2451. * Note that this is an undocumented register.
  2452. */
  2453. static void nvbridge_check_legacy_irq_routing(struct pci_dev *dev)
  2454. {
  2455. u32 cfg;
  2456. if (!pci_find_capability(dev, PCI_CAP_ID_HT))
  2457. return;
  2458. pci_read_config_dword(dev, 0x74, &cfg);
  2459. if (cfg & ((1 << 2) | (1 << 15))) {
  2460. pr_info("Rewriting IRQ routing register on MCP55\n");
  2461. cfg &= ~((1 << 2) | (1 << 15));
  2462. pci_write_config_dword(dev, 0x74, cfg);
  2463. }
  2464. }
  2465. DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_NVIDIA,
  2466. PCI_DEVICE_ID_NVIDIA_MCP55_BRIDGE_V0,
  2467. nvbridge_check_legacy_irq_routing);
  2468. DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_NVIDIA,
  2469. PCI_DEVICE_ID_NVIDIA_MCP55_BRIDGE_V4,
  2470. nvbridge_check_legacy_irq_routing);
  2471. static int ht_check_msi_mapping(struct pci_dev *dev)
  2472. {
  2473. int pos, ttl = PCI_FIND_CAP_TTL;
  2474. int found = 0;
  2475. /* Check if there is HT MSI cap or enabled on this device */
  2476. pos = pci_find_ht_capability(dev, HT_CAPTYPE_MSI_MAPPING);
  2477. while (pos && ttl--) {
  2478. u8 flags;
  2479. if (found < 1)
  2480. found = 1;
  2481. if (pci_read_config_byte(dev, pos + HT_MSI_FLAGS,
  2482. &flags) == 0) {
  2483. if (flags & HT_MSI_FLAGS_ENABLE) {
  2484. if (found < 2) {
  2485. found = 2;
  2486. break;
  2487. }
  2488. }
  2489. }
  2490. pos = pci_find_next_ht_capability(dev, pos,
  2491. HT_CAPTYPE_MSI_MAPPING);
  2492. }
  2493. return found;
  2494. }
  2495. static int host_bridge_with_leaf(struct pci_dev *host_bridge)
  2496. {
  2497. struct pci_dev *dev;
  2498. int pos;
  2499. int i, dev_no;
  2500. int found = 0;
  2501. dev_no = host_bridge->devfn >> 3;
  2502. for (i = dev_no + 1; i < 0x20; i++) {
  2503. dev = pci_get_slot(host_bridge->bus, PCI_DEVFN(i, 0));
  2504. if (!dev)
  2505. continue;
  2506. /* found next host bridge? */
  2507. pos = pci_find_ht_capability(dev, HT_CAPTYPE_SLAVE);
  2508. if (pos != 0) {
  2509. pci_dev_put(dev);
  2510. break;
  2511. }
  2512. if (ht_check_msi_mapping(dev)) {
  2513. found = 1;
  2514. pci_dev_put(dev);
  2515. break;
  2516. }
  2517. pci_dev_put(dev);
  2518. }
  2519. return found;
  2520. }
  2521. #define PCI_HT_CAP_SLAVE_CTRL0 4 /* link control */
  2522. #define PCI_HT_CAP_SLAVE_CTRL1 8 /* link control to */
  2523. static int is_end_of_ht_chain(struct pci_dev *dev)
  2524. {
  2525. int pos, ctrl_off;
  2526. int end = 0;
  2527. u16 flags, ctrl;
  2528. pos = pci_find_ht_capability(dev, HT_CAPTYPE_SLAVE);
  2529. if (!pos)
  2530. goto out;
  2531. pci_read_config_word(dev, pos + PCI_CAP_FLAGS, &flags);
  2532. ctrl_off = ((flags >> 10) & 1) ?
  2533. PCI_HT_CAP_SLAVE_CTRL0 : PCI_HT_CAP_SLAVE_CTRL1;
  2534. pci_read_config_word(dev, pos + ctrl_off, &ctrl);
  2535. if (ctrl & (1 << 6))
  2536. end = 1;
  2537. out:
  2538. return end;
  2539. }
  2540. static void nv_ht_enable_msi_mapping(struct pci_dev *dev)
  2541. {
  2542. struct pci_dev *host_bridge;
  2543. int pos;
  2544. int i, dev_no;
  2545. int found = 0;
  2546. dev_no = dev->devfn >> 3;
  2547. for (i = dev_no; i >= 0; i--) {
  2548. host_bridge = pci_get_slot(dev->bus, PCI_DEVFN(i, 0));
  2549. if (!host_bridge)
  2550. continue;
  2551. pos = pci_find_ht_capability(host_bridge, HT_CAPTYPE_SLAVE);
  2552. if (pos != 0) {
  2553. found = 1;
  2554. break;
  2555. }
  2556. pci_dev_put(host_bridge);
  2557. }
  2558. if (!found)
  2559. return;
  2560. /* don't enable end_device/host_bridge with leaf directly here */
  2561. if (host_bridge == dev && is_end_of_ht_chain(host_bridge) &&
  2562. host_bridge_with_leaf(host_bridge))
  2563. goto out;
  2564. /* root did that ! */
  2565. if (msi_ht_cap_enabled(host_bridge))
  2566. goto out;
  2567. ht_enable_msi_mapping(dev);
  2568. out:
  2569. pci_dev_put(host_bridge);
  2570. }
  2571. static void ht_disable_msi_mapping(struct pci_dev *dev)
  2572. {
  2573. int pos, ttl = PCI_FIND_CAP_TTL;
  2574. pos = pci_find_ht_capability(dev, HT_CAPTYPE_MSI_MAPPING);
  2575. while (pos && ttl--) {
  2576. u8 flags;
  2577. if (pci_read_config_byte(dev, pos + HT_MSI_FLAGS,
  2578. &flags) == 0) {
  2579. pci_info(dev, "Disabling HT MSI Mapping\n");
  2580. pci_write_config_byte(dev, pos + HT_MSI_FLAGS,
  2581. flags & ~HT_MSI_FLAGS_ENABLE);
  2582. }
  2583. pos = pci_find_next_ht_capability(dev, pos,
  2584. HT_CAPTYPE_MSI_MAPPING);
  2585. }
  2586. }
  2587. static void __nv_msi_ht_cap_quirk(struct pci_dev *dev, int all)
  2588. {
  2589. struct pci_dev *host_bridge;
  2590. int pos;
  2591. int found;
  2592. if (!pci_msi_enabled())
  2593. return;
  2594. /* check if there is HT MSI cap or enabled on this device */
  2595. found = ht_check_msi_mapping(dev);
  2596. /* no HT MSI CAP */
  2597. if (found == 0)
  2598. return;
  2599. /*
  2600. * HT MSI mapping should be disabled on devices that are below
  2601. * a non-Hypertransport host bridge. Locate the host bridge...
  2602. */
  2603. host_bridge = pci_get_domain_bus_and_slot(pci_domain_nr(dev->bus), 0,
  2604. PCI_DEVFN(0, 0));
  2605. if (host_bridge == NULL) {
  2606. pci_warn(dev, "nv_msi_ht_cap_quirk didn't locate host bridge\n");
  2607. return;
  2608. }
  2609. pos = pci_find_ht_capability(host_bridge, HT_CAPTYPE_SLAVE);
  2610. if (pos != 0) {
  2611. /* Host bridge is to HT */
  2612. if (found == 1) {
  2613. /* it is not enabled, try to enable it */
  2614. if (all)
  2615. ht_enable_msi_mapping(dev);
  2616. else
  2617. nv_ht_enable_msi_mapping(dev);
  2618. }
  2619. goto out;
  2620. }
  2621. /* HT MSI is not enabled */
  2622. if (found == 1)
  2623. goto out;
  2624. /* Host bridge is not to HT, disable HT MSI mapping on this device */
  2625. ht_disable_msi_mapping(dev);
  2626. out:
  2627. pci_dev_put(host_bridge);
  2628. }
  2629. static void nv_msi_ht_cap_quirk_all(struct pci_dev *dev)
  2630. {
  2631. return __nv_msi_ht_cap_quirk(dev, 1);
  2632. }
  2633. DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AL, PCI_ANY_ID, nv_msi_ht_cap_quirk_all);
  2634. DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_AL, PCI_ANY_ID, nv_msi_ht_cap_quirk_all);
  2635. static void nv_msi_ht_cap_quirk_leaf(struct pci_dev *dev)
  2636. {
  2637. return __nv_msi_ht_cap_quirk(dev, 0);
  2638. }
  2639. DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_NVIDIA, PCI_ANY_ID, nv_msi_ht_cap_quirk_leaf);
  2640. DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_NVIDIA, PCI_ANY_ID, nv_msi_ht_cap_quirk_leaf);
  2641. static void quirk_msi_intx_disable_bug(struct pci_dev *dev)
  2642. {
  2643. dev->dev_flags |= PCI_DEV_FLAGS_MSI_INTX_DISABLE_BUG;
  2644. }
  2645. static void quirk_msi_intx_disable_ati_bug(struct pci_dev *dev)
  2646. {
  2647. struct pci_dev *p;
  2648. /*
  2649. * SB700 MSI issue will be fixed at HW level from revision A21;
  2650. * we need check PCI REVISION ID of SMBus controller to get SB700
  2651. * revision.
  2652. */
  2653. p = pci_get_device(PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_SBX00_SMBUS,
  2654. NULL);
  2655. if (!p)
  2656. return;
  2657. if ((p->revision < 0x3B) && (p->revision >= 0x30))
  2658. dev->dev_flags |= PCI_DEV_FLAGS_MSI_INTX_DISABLE_BUG;
  2659. pci_dev_put(p);
  2660. }
  2661. static void quirk_msi_intx_disable_qca_bug(struct pci_dev *dev)
  2662. {
  2663. /* AR816X/AR817X/E210X MSI is fixed at HW level from revision 0x18 */
  2664. if (dev->revision < 0x18) {
  2665. pci_info(dev, "set MSI_INTX_DISABLE_BUG flag\n");
  2666. dev->dev_flags |= PCI_DEV_FLAGS_MSI_INTX_DISABLE_BUG;
  2667. }
  2668. }
  2669. DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_BROADCOM,
  2670. PCI_DEVICE_ID_TIGON3_5780,
  2671. quirk_msi_intx_disable_bug);
  2672. DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_BROADCOM,
  2673. PCI_DEVICE_ID_TIGON3_5780S,
  2674. quirk_msi_intx_disable_bug);
  2675. DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_BROADCOM,
  2676. PCI_DEVICE_ID_TIGON3_5714,
  2677. quirk_msi_intx_disable_bug);
  2678. DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_BROADCOM,
  2679. PCI_DEVICE_ID_TIGON3_5714S,
  2680. quirk_msi_intx_disable_bug);
  2681. DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_BROADCOM,
  2682. PCI_DEVICE_ID_TIGON3_5715,
  2683. quirk_msi_intx_disable_bug);
  2684. DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_BROADCOM,
  2685. PCI_DEVICE_ID_TIGON3_5715S,
  2686. quirk_msi_intx_disable_bug);
  2687. DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0x4390,
  2688. quirk_msi_intx_disable_ati_bug);
  2689. DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0x4391,
  2690. quirk_msi_intx_disable_ati_bug);
  2691. DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0x4392,
  2692. quirk_msi_intx_disable_ati_bug);
  2693. DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0x4393,
  2694. quirk_msi_intx_disable_ati_bug);
  2695. DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0x4394,
  2696. quirk_msi_intx_disable_ati_bug);
  2697. DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0x4373,
  2698. quirk_msi_intx_disable_bug);
  2699. DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0x4374,
  2700. quirk_msi_intx_disable_bug);
  2701. DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0x4375,
  2702. quirk_msi_intx_disable_bug);
  2703. DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATTANSIC, 0x1062,
  2704. quirk_msi_intx_disable_bug);
  2705. DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATTANSIC, 0x1063,
  2706. quirk_msi_intx_disable_bug);
  2707. DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATTANSIC, 0x2060,
  2708. quirk_msi_intx_disable_bug);
  2709. DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATTANSIC, 0x2062,
  2710. quirk_msi_intx_disable_bug);
  2711. DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATTANSIC, 0x1073,
  2712. quirk_msi_intx_disable_bug);
  2713. DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATTANSIC, 0x1083,
  2714. quirk_msi_intx_disable_bug);
  2715. DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATTANSIC, 0x1090,
  2716. quirk_msi_intx_disable_qca_bug);
  2717. DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATTANSIC, 0x1091,
  2718. quirk_msi_intx_disable_qca_bug);
  2719. DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATTANSIC, 0x10a0,
  2720. quirk_msi_intx_disable_qca_bug);
  2721. DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATTANSIC, 0x10a1,
  2722. quirk_msi_intx_disable_qca_bug);
  2723. DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATTANSIC, 0xe091,
  2724. quirk_msi_intx_disable_qca_bug);
  2725. /*
  2726. * Amazon's Annapurna Labs 1c36:0031 Root Ports don't support MSI-X, so it
  2727. * should be disabled on platforms where the device (mistakenly) advertises it.
  2728. *
  2729. * Notice that this quirk also disables MSI (which may work, but hasn't been
  2730. * tested), since currently there is no standard way to disable only MSI-X.
  2731. *
  2732. * The 0031 device id is reused for other non Root Port device types,
  2733. * therefore the quirk is registered for the PCI_CLASS_BRIDGE_PCI class.
  2734. */
  2735. static void quirk_al_msi_disable(struct pci_dev *dev)
  2736. {
  2737. dev->no_msi = 1;
  2738. pci_warn(dev, "Disabling MSI/MSI-X\n");
  2739. }
  2740. DECLARE_PCI_FIXUP_CLASS_FINAL(PCI_VENDOR_ID_AMAZON_ANNAPURNA_LABS, 0x0031,
  2741. PCI_CLASS_BRIDGE_PCI, 8, quirk_al_msi_disable);
  2742. #endif /* CONFIG_PCI_MSI */
  2743. /*
  2744. * Allow manual resource allocation for PCI hotplug bridges via
  2745. * pci=hpmemsize=nnM and pci=hpiosize=nnM parameters. For some PCI-PCI
  2746. * hotplug bridges, like PLX 6254 (former HINT HB6), kernel fails to
  2747. * allocate resources when hotplug device is inserted and PCI bus is
  2748. * rescanned.
  2749. */
  2750. static void quirk_hotplug_bridge(struct pci_dev *dev)
  2751. {
  2752. dev->is_hotplug_bridge = 1;
  2753. }
  2754. DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_HINT, 0x0020, quirk_hotplug_bridge);
  2755. /*
  2756. * This is a quirk for the Ricoh MMC controller found as a part of some
  2757. * multifunction chips.
  2758. *
  2759. * This is very similar and based on the ricoh_mmc driver written by
  2760. * Philip Langdale. Thank you for these magic sequences.
  2761. *
  2762. * These chips implement the four main memory card controllers (SD, MMC,
  2763. * MS, xD) and one or both of CardBus or FireWire.
  2764. *
  2765. * It happens that they implement SD and MMC support as separate
  2766. * controllers (and PCI functions). The Linux SDHCI driver supports MMC
  2767. * cards but the chip detects MMC cards in hardware and directs them to the
  2768. * MMC controller - so the SDHCI driver never sees them.
  2769. *
  2770. * To get around this, we must disable the useless MMC controller. At that
  2771. * point, the SDHCI controller will start seeing them. It seems to be the
  2772. * case that the relevant PCI registers to deactivate the MMC controller
  2773. * live on PCI function 0, which might be the CardBus controller or the
  2774. * FireWire controller, depending on the particular chip in question
  2775. *
  2776. * This has to be done early, because as soon as we disable the MMC controller
  2777. * other PCI functions shift up one level, e.g. function #2 becomes function
  2778. * #1, and this will confuse the PCI core.
  2779. */
  2780. #ifdef CONFIG_MMC_RICOH_MMC
  2781. static void ricoh_mmc_fixup_rl5c476(struct pci_dev *dev)
  2782. {
  2783. u8 write_enable;
  2784. u8 write_target;
  2785. u8 disable;
  2786. /*
  2787. * Disable via CardBus interface
  2788. *
  2789. * This must be done via function #0
  2790. */
  2791. if (PCI_FUNC(dev->devfn))
  2792. return;
  2793. pci_read_config_byte(dev, 0xB7, &disable);
  2794. if (disable & 0x02)
  2795. return;
  2796. pci_read_config_byte(dev, 0x8E, &write_enable);
  2797. pci_write_config_byte(dev, 0x8E, 0xAA);
  2798. pci_read_config_byte(dev, 0x8D, &write_target);
  2799. pci_write_config_byte(dev, 0x8D, 0xB7);
  2800. pci_write_config_byte(dev, 0xB7, disable | 0x02);
  2801. pci_write_config_byte(dev, 0x8E, write_enable);
  2802. pci_write_config_byte(dev, 0x8D, write_target);
  2803. pci_notice(dev, "proprietary Ricoh MMC controller disabled (via CardBus function)\n");
  2804. pci_notice(dev, "MMC cards are now supported by standard SDHCI controller\n");
  2805. }
  2806. DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_RICOH, PCI_DEVICE_ID_RICOH_RL5C476, ricoh_mmc_fixup_rl5c476);
  2807. DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_RICOH, PCI_DEVICE_ID_RICOH_RL5C476, ricoh_mmc_fixup_rl5c476);
  2808. static void ricoh_mmc_fixup_r5c832(struct pci_dev *dev)
  2809. {
  2810. u8 write_enable;
  2811. u8 disable;
  2812. /*
  2813. * Disable via FireWire interface
  2814. *
  2815. * This must be done via function #0
  2816. */
  2817. if (PCI_FUNC(dev->devfn))
  2818. return;
  2819. /*
  2820. * RICOH 0xe822 and 0xe823 SD/MMC card readers fail to recognize
  2821. * certain types of SD/MMC cards. Lowering the SD base clock
  2822. * frequency from 200Mhz to 50Mhz fixes this issue.
  2823. *
  2824. * 0x150 - SD2.0 mode enable for changing base clock
  2825. * frequency to 50Mhz
  2826. * 0xe1 - Base clock frequency
  2827. * 0x32 - 50Mhz new clock frequency
  2828. * 0xf9 - Key register for 0x150
  2829. * 0xfc - key register for 0xe1
  2830. */
  2831. if (dev->device == PCI_DEVICE_ID_RICOH_R5CE822 ||
  2832. dev->device == PCI_DEVICE_ID_RICOH_R5CE823) {
  2833. pci_write_config_byte(dev, 0xf9, 0xfc);
  2834. pci_write_config_byte(dev, 0x150, 0x10);
  2835. pci_write_config_byte(dev, 0xf9, 0x00);
  2836. pci_write_config_byte(dev, 0xfc, 0x01);
  2837. pci_write_config_byte(dev, 0xe1, 0x32);
  2838. pci_write_config_byte(dev, 0xfc, 0x00);
  2839. pci_notice(dev, "MMC controller base frequency changed to 50Mhz.\n");
  2840. }
  2841. pci_read_config_byte(dev, 0xCB, &disable);
  2842. if (disable & 0x02)
  2843. return;
  2844. pci_read_config_byte(dev, 0xCA, &write_enable);
  2845. pci_write_config_byte(dev, 0xCA, 0x57);
  2846. pci_write_config_byte(dev, 0xCB, disable | 0x02);
  2847. pci_write_config_byte(dev, 0xCA, write_enable);
  2848. pci_notice(dev, "proprietary Ricoh MMC controller disabled (via FireWire function)\n");
  2849. pci_notice(dev, "MMC cards are now supported by standard SDHCI controller\n");
  2850. }
  2851. DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_RICOH, PCI_DEVICE_ID_RICOH_R5C832, ricoh_mmc_fixup_r5c832);
  2852. DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_RICOH, PCI_DEVICE_ID_RICOH_R5C832, ricoh_mmc_fixup_r5c832);
  2853. DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_RICOH, PCI_DEVICE_ID_RICOH_R5CE822, ricoh_mmc_fixup_r5c832);
  2854. DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_RICOH, PCI_DEVICE_ID_RICOH_R5CE822, ricoh_mmc_fixup_r5c832);
  2855. DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_RICOH, PCI_DEVICE_ID_RICOH_R5CE823, ricoh_mmc_fixup_r5c832);
  2856. DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_RICOH, PCI_DEVICE_ID_RICOH_R5CE823, ricoh_mmc_fixup_r5c832);
  2857. #endif /*CONFIG_MMC_RICOH_MMC*/
  2858. #ifdef CONFIG_DMAR_TABLE
  2859. #define VTUNCERRMSK_REG 0x1ac
  2860. #define VTD_MSK_SPEC_ERRORS (1 << 31)
  2861. /*
  2862. * This is a quirk for masking VT-d spec-defined errors to platform error
  2863. * handling logic. Without this, platforms using Intel 7500, 5500 chipsets
  2864. * (and the derivative chipsets like X58 etc) seem to generate NMI/SMI (based
  2865. * on the RAS config settings of the platform) when a VT-d fault happens.
  2866. * The resulting SMI caused the system to hang.
  2867. *
  2868. * VT-d spec-related errors are already handled by the VT-d OS code, so no
  2869. * need to report the same error through other channels.
  2870. */
  2871. static void vtd_mask_spec_errors(struct pci_dev *dev)
  2872. {
  2873. u32 word;
  2874. pci_read_config_dword(dev, VTUNCERRMSK_REG, &word);
  2875. pci_write_config_dword(dev, VTUNCERRMSK_REG, word | VTD_MSK_SPEC_ERRORS);
  2876. }
  2877. DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL, 0x342e, vtd_mask_spec_errors);
  2878. DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL, 0x3c28, vtd_mask_spec_errors);
  2879. #endif
  2880. static void fixup_ti816x_class(struct pci_dev *dev)
  2881. {
  2882. u32 class = dev->class;
  2883. /* TI 816x devices do not have class code set when in PCIe boot mode */
  2884. dev->class = PCI_CLASS_MULTIMEDIA_VIDEO << 8;
  2885. pci_info(dev, "PCI class overridden (%#08x -> %#08x)\n",
  2886. class, dev->class);
  2887. }
  2888. DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_TI, 0xb800,
  2889. PCI_CLASS_NOT_DEFINED, 8, fixup_ti816x_class);
  2890. /*
  2891. * Some PCIe devices do not work reliably with the claimed maximum
  2892. * payload size supported.
  2893. */
  2894. static void fixup_mpss_256(struct pci_dev *dev)
  2895. {
  2896. dev->pcie_mpss = 1; /* 256 bytes */
  2897. }
  2898. DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_SOLARFLARE,
  2899. PCI_DEVICE_ID_SOLARFLARE_SFC4000A_0, fixup_mpss_256);
  2900. DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_SOLARFLARE,
  2901. PCI_DEVICE_ID_SOLARFLARE_SFC4000A_1, fixup_mpss_256);
  2902. DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_SOLARFLARE,
  2903. PCI_DEVICE_ID_SOLARFLARE_SFC4000B, fixup_mpss_256);
  2904. DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_ASMEDIA, 0x0612, fixup_mpss_256);
  2905. /*
  2906. * Intel 5000 and 5100 Memory controllers have an erratum with read completion
  2907. * coalescing (which is enabled by default on some BIOSes) and MPS of 256B.
  2908. * Since there is no way of knowing what the PCIe MPS on each fabric will be
  2909. * until all of the devices are discovered and buses walked, read completion
  2910. * coalescing must be disabled. Unfortunately, it cannot be re-enabled because
  2911. * it is possible to hotplug a device with MPS of 256B.
  2912. */
  2913. static void quirk_intel_mc_errata(struct pci_dev *dev)
  2914. {
  2915. int err;
  2916. u16 rcc;
  2917. if (pcie_bus_config == PCIE_BUS_TUNE_OFF ||
  2918. pcie_bus_config == PCIE_BUS_DEFAULT)
  2919. return;
  2920. /*
  2921. * Intel erratum specifies bits to change but does not say what
  2922. * they are. Keeping them magical until such time as the registers
  2923. * and values can be explained.
  2924. */
  2925. err = pci_read_config_word(dev, 0x48, &rcc);
  2926. if (err) {
  2927. pci_err(dev, "Error attempting to read the read completion coalescing register\n");
  2928. return;
  2929. }
  2930. if (!(rcc & (1 << 10)))
  2931. return;
  2932. rcc &= ~(1 << 10);
  2933. err = pci_write_config_word(dev, 0x48, rcc);
  2934. if (err) {
  2935. pci_err(dev, "Error attempting to write the read completion coalescing register\n");
  2936. return;
  2937. }
  2938. pr_info_once("Read completion coalescing disabled due to hardware erratum relating to 256B MPS\n");
  2939. }
  2940. /* Intel 5000 series memory controllers and ports 2-7 */
  2941. DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x25c0, quirk_intel_mc_errata);
  2942. DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x25d0, quirk_intel_mc_errata);
  2943. DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x25d4, quirk_intel_mc_errata);
  2944. DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x25d8, quirk_intel_mc_errata);
  2945. DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x25e2, quirk_intel_mc_errata);
  2946. DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x25e3, quirk_intel_mc_errata);
  2947. DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x25e4, quirk_intel_mc_errata);
  2948. DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x25e5, quirk_intel_mc_errata);
  2949. DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x25e6, quirk_intel_mc_errata);
  2950. DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x25e7, quirk_intel_mc_errata);
  2951. DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x25f7, quirk_intel_mc_errata);
  2952. DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x25f8, quirk_intel_mc_errata);
  2953. DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x25f9, quirk_intel_mc_errata);
  2954. DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x25fa, quirk_intel_mc_errata);
  2955. /* Intel 5100 series memory controllers and ports 2-7 */
  2956. DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x65c0, quirk_intel_mc_errata);
  2957. DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x65e2, quirk_intel_mc_errata);
  2958. DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x65e3, quirk_intel_mc_errata);
  2959. DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x65e4, quirk_intel_mc_errata);
  2960. DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x65e5, quirk_intel_mc_errata);
  2961. DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x65e6, quirk_intel_mc_errata);
  2962. DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x65e7, quirk_intel_mc_errata);
  2963. DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x65f7, quirk_intel_mc_errata);
  2964. DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x65f8, quirk_intel_mc_errata);
  2965. DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x65f9, quirk_intel_mc_errata);
  2966. DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x65fa, quirk_intel_mc_errata);
  2967. /*
  2968. * Ivytown NTB BAR sizes are misreported by the hardware due to an erratum.
  2969. * To work around this, query the size it should be configured to by the
  2970. * device and modify the resource end to correspond to this new size.
  2971. */
  2972. static void quirk_intel_ntb(struct pci_dev *dev)
  2973. {
  2974. int rc;
  2975. u8 val;
  2976. rc = pci_read_config_byte(dev, 0x00D0, &val);
  2977. if (rc)
  2978. return;
  2979. dev->resource[2].end = dev->resource[2].start + ((u64) 1 << val) - 1;
  2980. rc = pci_read_config_byte(dev, 0x00D1, &val);
  2981. if (rc)
  2982. return;
  2983. dev->resource[4].end = dev->resource[4].start + ((u64) 1 << val) - 1;
  2984. }
  2985. DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x0e08, quirk_intel_ntb);
  2986. DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x0e0d, quirk_intel_ntb);
  2987. /*
  2988. * Some BIOS implementations leave the Intel GPU interrupts enabled, even
  2989. * though no one is handling them (e.g., if the i915 driver is never
  2990. * loaded). Additionally the interrupt destination is not set up properly
  2991. * and the interrupt ends up -somewhere-.
  2992. *
  2993. * These spurious interrupts are "sticky" and the kernel disables the
  2994. * (shared) interrupt line after 100,000+ generated interrupts.
  2995. *
  2996. * Fix it by disabling the still enabled interrupts. This resolves crashes
  2997. * often seen on monitor unplug.
  2998. */
  2999. #define I915_DEIER_REG 0x4400c
  3000. static void disable_igfx_irq(struct pci_dev *dev)
  3001. {
  3002. void __iomem *regs = pci_iomap(dev, 0, 0);
  3003. if (regs == NULL) {
  3004. pci_warn(dev, "igfx quirk: Can't iomap PCI device\n");
  3005. return;
  3006. }
  3007. /* Check if any interrupt line is still enabled */
  3008. if (readl(regs + I915_DEIER_REG) != 0) {
  3009. pci_warn(dev, "BIOS left Intel GPU interrupts enabled; disabling\n");
  3010. writel(0, regs + I915_DEIER_REG);
  3011. }
  3012. pci_iounmap(dev, regs);
  3013. }
  3014. DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x0042, disable_igfx_irq);
  3015. DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x0046, disable_igfx_irq);
  3016. DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x004a, disable_igfx_irq);
  3017. DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x0102, disable_igfx_irq);
  3018. DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x0106, disable_igfx_irq);
  3019. DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x010a, disable_igfx_irq);
  3020. DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x0152, disable_igfx_irq);
  3021. /*
  3022. * PCI devices which are on Intel chips can skip the 10ms delay
  3023. * before entering D3 mode.
  3024. */
  3025. static void quirk_remove_d3hot_delay(struct pci_dev *dev)
  3026. {
  3027. dev->d3hot_delay = 0;
  3028. }
  3029. /* C600 Series devices do not need 10ms d3hot_delay */
  3030. DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x0412, quirk_remove_d3hot_delay);
  3031. DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x0c00, quirk_remove_d3hot_delay);
  3032. DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x0c0c, quirk_remove_d3hot_delay);
  3033. /* Lynxpoint-H PCH devices do not need 10ms d3hot_delay */
  3034. DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x8c02, quirk_remove_d3hot_delay);
  3035. DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x8c18, quirk_remove_d3hot_delay);
  3036. DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x8c1c, quirk_remove_d3hot_delay);
  3037. DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x8c20, quirk_remove_d3hot_delay);
  3038. DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x8c22, quirk_remove_d3hot_delay);
  3039. DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x8c26, quirk_remove_d3hot_delay);
  3040. DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x8c2d, quirk_remove_d3hot_delay);
  3041. DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x8c31, quirk_remove_d3hot_delay);
  3042. DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x8c3a, quirk_remove_d3hot_delay);
  3043. DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x8c3d, quirk_remove_d3hot_delay);
  3044. DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x8c4e, quirk_remove_d3hot_delay);
  3045. /* Intel Cherrytrail devices do not need 10ms d3hot_delay */
  3046. DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x2280, quirk_remove_d3hot_delay);
  3047. DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x2298, quirk_remove_d3hot_delay);
  3048. DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x229c, quirk_remove_d3hot_delay);
  3049. DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x22b0, quirk_remove_d3hot_delay);
  3050. DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x22b5, quirk_remove_d3hot_delay);
  3051. DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x22b7, quirk_remove_d3hot_delay);
  3052. DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x22b8, quirk_remove_d3hot_delay);
  3053. DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x22d8, quirk_remove_d3hot_delay);
  3054. DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x22dc, quirk_remove_d3hot_delay);
  3055. /*
  3056. * Some devices may pass our check in pci_intx_mask_supported() if
  3057. * PCI_COMMAND_INTX_DISABLE works though they actually do not properly
  3058. * support this feature.
  3059. */
  3060. static void quirk_broken_intx_masking(struct pci_dev *dev)
  3061. {
  3062. dev->broken_intx_masking = 1;
  3063. }
  3064. DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_CHELSIO, 0x0030,
  3065. quirk_broken_intx_masking);
  3066. DECLARE_PCI_FIXUP_FINAL(0x1814, 0x0601, /* Ralink RT2800 802.11n PCI */
  3067. quirk_broken_intx_masking);
  3068. DECLARE_PCI_FIXUP_FINAL(0x1b7c, 0x0004, /* Ceton InfiniTV4 */
  3069. quirk_broken_intx_masking);
  3070. /*
  3071. * Realtek RTL8169 PCI Gigabit Ethernet Controller (rev 10)
  3072. * Subsystem: Realtek RTL8169/8110 Family PCI Gigabit Ethernet NIC
  3073. *
  3074. * RTL8110SC - Fails under PCI device assignment using DisINTx masking.
  3075. */
  3076. DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_REALTEK, 0x8169,
  3077. quirk_broken_intx_masking);
  3078. /*
  3079. * Intel i40e (XL710/X710) 10/20/40GbE NICs all have broken INTx masking,
  3080. * DisINTx can be set but the interrupt status bit is non-functional.
  3081. */
  3082. DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x1572, quirk_broken_intx_masking);
  3083. DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x1574, quirk_broken_intx_masking);
  3084. DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x1580, quirk_broken_intx_masking);
  3085. DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x1581, quirk_broken_intx_masking);
  3086. DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x1583, quirk_broken_intx_masking);
  3087. DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x1584, quirk_broken_intx_masking);
  3088. DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x1585, quirk_broken_intx_masking);
  3089. DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x1586, quirk_broken_intx_masking);
  3090. DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x1587, quirk_broken_intx_masking);
  3091. DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x1588, quirk_broken_intx_masking);
  3092. DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x1589, quirk_broken_intx_masking);
  3093. DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x158a, quirk_broken_intx_masking);
  3094. DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x158b, quirk_broken_intx_masking);
  3095. DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x37d0, quirk_broken_intx_masking);
  3096. DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x37d1, quirk_broken_intx_masking);
  3097. DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x37d2, quirk_broken_intx_masking);
  3098. static u16 mellanox_broken_intx_devs[] = {
  3099. PCI_DEVICE_ID_MELLANOX_HERMON_SDR,
  3100. PCI_DEVICE_ID_MELLANOX_HERMON_DDR,
  3101. PCI_DEVICE_ID_MELLANOX_HERMON_QDR,
  3102. PCI_DEVICE_ID_MELLANOX_HERMON_DDR_GEN2,
  3103. PCI_DEVICE_ID_MELLANOX_HERMON_QDR_GEN2,
  3104. PCI_DEVICE_ID_MELLANOX_HERMON_EN,
  3105. PCI_DEVICE_ID_MELLANOX_HERMON_EN_GEN2,
  3106. PCI_DEVICE_ID_MELLANOX_CONNECTX_EN,
  3107. PCI_DEVICE_ID_MELLANOX_CONNECTX_EN_T_GEN2,
  3108. PCI_DEVICE_ID_MELLANOX_CONNECTX_EN_GEN2,
  3109. PCI_DEVICE_ID_MELLANOX_CONNECTX_EN_5_GEN2,
  3110. PCI_DEVICE_ID_MELLANOX_CONNECTX2,
  3111. PCI_DEVICE_ID_MELLANOX_CONNECTX3,
  3112. PCI_DEVICE_ID_MELLANOX_CONNECTX3_PRO,
  3113. };
  3114. #define CONNECTX_4_CURR_MAX_MINOR 99
  3115. #define CONNECTX_4_INTX_SUPPORT_MINOR 14
  3116. /*
  3117. * Check ConnectX-4/LX FW version to see if it supports legacy interrupts.
  3118. * If so, don't mark it as broken.
  3119. * FW minor > 99 means older FW version format and no INTx masking support.
  3120. * FW minor < 14 means new FW version format and no INTx masking support.
  3121. */
  3122. static void mellanox_check_broken_intx_masking(struct pci_dev *pdev)
  3123. {
  3124. __be32 __iomem *fw_ver;
  3125. u16 fw_major;
  3126. u16 fw_minor;
  3127. u16 fw_subminor;
  3128. u32 fw_maj_min;
  3129. u32 fw_sub_min;
  3130. int i;
  3131. for (i = 0; i < ARRAY_SIZE(mellanox_broken_intx_devs); i++) {
  3132. if (pdev->device == mellanox_broken_intx_devs[i]) {
  3133. pdev->broken_intx_masking = 1;
  3134. return;
  3135. }
  3136. }
  3137. /*
  3138. * Getting here means Connect-IB cards and up. Connect-IB has no INTx
  3139. * support so shouldn't be checked further
  3140. */
  3141. if (pdev->device == PCI_DEVICE_ID_MELLANOX_CONNECTIB)
  3142. return;
  3143. if (pdev->device != PCI_DEVICE_ID_MELLANOX_CONNECTX4 &&
  3144. pdev->device != PCI_DEVICE_ID_MELLANOX_CONNECTX4_LX)
  3145. return;
  3146. /* For ConnectX-4 and ConnectX-4LX, need to check FW support */
  3147. if (pci_enable_device_mem(pdev)) {
  3148. pci_warn(pdev, "Can't enable device memory\n");
  3149. return;
  3150. }
  3151. fw_ver = ioremap(pci_resource_start(pdev, 0), 4);
  3152. if (!fw_ver) {
  3153. pci_warn(pdev, "Can't map ConnectX-4 initialization segment\n");
  3154. goto out;
  3155. }
  3156. /* Reading from resource space should be 32b aligned */
  3157. fw_maj_min = ioread32be(fw_ver);
  3158. fw_sub_min = ioread32be(fw_ver + 1);
  3159. fw_major = fw_maj_min & 0xffff;
  3160. fw_minor = fw_maj_min >> 16;
  3161. fw_subminor = fw_sub_min & 0xffff;
  3162. if (fw_minor > CONNECTX_4_CURR_MAX_MINOR ||
  3163. fw_minor < CONNECTX_4_INTX_SUPPORT_MINOR) {
  3164. pci_warn(pdev, "ConnectX-4: FW %u.%u.%u doesn't support INTx masking, disabling. Please upgrade FW to %d.14.1100 and up for INTx support\n",
  3165. fw_major, fw_minor, fw_subminor, pdev->device ==
  3166. PCI_DEVICE_ID_MELLANOX_CONNECTX4 ? 12 : 14);
  3167. pdev->broken_intx_masking = 1;
  3168. }
  3169. iounmap(fw_ver);
  3170. out:
  3171. pci_disable_device(pdev);
  3172. }
  3173. DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_MELLANOX, PCI_ANY_ID,
  3174. mellanox_check_broken_intx_masking);
  3175. static void quirk_no_bus_reset(struct pci_dev *dev)
  3176. {
  3177. dev->dev_flags |= PCI_DEV_FLAGS_NO_BUS_RESET;
  3178. }
  3179. /*
  3180. * Some NVIDIA GPU devices do not work with bus reset, SBR needs to be
  3181. * prevented for those affected devices.
  3182. */
  3183. static void quirk_nvidia_no_bus_reset(struct pci_dev *dev)
  3184. {
  3185. if ((dev->device & 0xffc0) == 0x2340)
  3186. quirk_no_bus_reset(dev);
  3187. }
  3188. DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_NVIDIA, PCI_ANY_ID,
  3189. quirk_nvidia_no_bus_reset);
  3190. /*
  3191. * Some Atheros AR9xxx and QCA988x chips do not behave after a bus reset.
  3192. * The device will throw a Link Down error on AER-capable systems and
  3193. * regardless of AER, config space of the device is never accessible again
  3194. * and typically causes the system to hang or reset when access is attempted.
  3195. * https://lore.kernel.org/r/20140923210318.498dacbd@dualc.maya.org/
  3196. */
  3197. DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_ATHEROS, 0x0030, quirk_no_bus_reset);
  3198. DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_ATHEROS, 0x0032, quirk_no_bus_reset);
  3199. DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_ATHEROS, 0x003c, quirk_no_bus_reset);
  3200. DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_ATHEROS, 0x0033, quirk_no_bus_reset);
  3201. DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_ATHEROS, 0x0034, quirk_no_bus_reset);
  3202. DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_ATHEROS, 0x003e, quirk_no_bus_reset);
  3203. /*
  3204. * Root port on some Cavium CN8xxx chips do not successfully complete a bus
  3205. * reset when used with certain child devices. After the reset, config
  3206. * accesses to the child may fail.
  3207. */
  3208. DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_CAVIUM, 0xa100, quirk_no_bus_reset);
  3209. /*
  3210. * Some TI KeyStone C667X devices do not support bus/hot reset. The PCIESS
  3211. * automatically disables LTSSM when Secondary Bus Reset is received and
  3212. * the device stops working. Prevent bus reset for these devices. With
  3213. * this change, the device can be assigned to VMs with VFIO, but it will
  3214. * leak state between VMs. Reference
  3215. * https://e2e.ti.com/support/processors/f/791/t/954382
  3216. */
  3217. DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_TI, 0xb005, quirk_no_bus_reset);
  3218. static void quirk_no_pm_reset(struct pci_dev *dev)
  3219. {
  3220. /*
  3221. * We can't do a bus reset on root bus devices, but an ineffective
  3222. * PM reset may be better than nothing.
  3223. */
  3224. if (!pci_is_root_bus(dev->bus))
  3225. dev->dev_flags |= PCI_DEV_FLAGS_NO_PM_RESET;
  3226. }
  3227. /*
  3228. * Some AMD/ATI GPUS (HD8570 - Oland) report that a D3hot->D0 transition
  3229. * causes a reset (i.e., they advertise NoSoftRst-). This transition seems
  3230. * to have no effect on the device: it retains the framebuffer contents and
  3231. * monitor sync. Advertising this support makes other layers, like VFIO,
  3232. * assume pci_reset_function() is viable for this device. Mark it as
  3233. * unavailable to skip it when testing reset methods.
  3234. */
  3235. DECLARE_PCI_FIXUP_CLASS_HEADER(PCI_VENDOR_ID_ATI, PCI_ANY_ID,
  3236. PCI_CLASS_DISPLAY_VGA, 8, quirk_no_pm_reset);
  3237. /*
  3238. * Thunderbolt controllers with broken MSI hotplug signaling:
  3239. * Entire 1st generation (Light Ridge, Eagle Ridge, Light Peak) and part
  3240. * of the 2nd generation (Cactus Ridge 4C up to revision 1, Port Ridge).
  3241. */
  3242. static void quirk_thunderbolt_hotplug_msi(struct pci_dev *pdev)
  3243. {
  3244. if (pdev->is_hotplug_bridge &&
  3245. (pdev->device != PCI_DEVICE_ID_INTEL_CACTUS_RIDGE_4C ||
  3246. pdev->revision <= 1))
  3247. pdev->no_msi = 1;
  3248. }
  3249. DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_LIGHT_RIDGE,
  3250. quirk_thunderbolt_hotplug_msi);
  3251. DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_EAGLE_RIDGE,
  3252. quirk_thunderbolt_hotplug_msi);
  3253. DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_LIGHT_PEAK,
  3254. quirk_thunderbolt_hotplug_msi);
  3255. DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_CACTUS_RIDGE_4C,
  3256. quirk_thunderbolt_hotplug_msi);
  3257. DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PORT_RIDGE,
  3258. quirk_thunderbolt_hotplug_msi);
  3259. #ifdef CONFIG_ACPI
  3260. /*
  3261. * Apple: Shutdown Cactus Ridge Thunderbolt controller.
  3262. *
  3263. * On Apple hardware the Cactus Ridge Thunderbolt controller needs to be
  3264. * shutdown before suspend. Otherwise the native host interface (NHI) will not
  3265. * be present after resume if a device was plugged in before suspend.
  3266. *
  3267. * The Thunderbolt controller consists of a PCIe switch with downstream
  3268. * bridges leading to the NHI and to the tunnel PCI bridges.
  3269. *
  3270. * This quirk cuts power to the whole chip. Therefore we have to apply it
  3271. * during suspend_noirq of the upstream bridge.
  3272. *
  3273. * Power is automagically restored before resume. No action is needed.
  3274. */
  3275. static void quirk_apple_poweroff_thunderbolt(struct pci_dev *dev)
  3276. {
  3277. acpi_handle bridge, SXIO, SXFP, SXLV;
  3278. if (!x86_apple_machine)
  3279. return;
  3280. if (pci_pcie_type(dev) != PCI_EXP_TYPE_UPSTREAM)
  3281. return;
  3282. /*
  3283. * SXIO/SXFP/SXLF turns off power to the Thunderbolt controller.
  3284. * We don't know how to turn it back on again, but firmware does,
  3285. * so we can only use SXIO/SXFP/SXLF if we're suspending via
  3286. * firmware.
  3287. */
  3288. if (!pm_suspend_via_firmware())
  3289. return;
  3290. bridge = ACPI_HANDLE(&dev->dev);
  3291. if (!bridge)
  3292. return;
  3293. /*
  3294. * SXIO and SXLV are present only on machines requiring this quirk.
  3295. * Thunderbolt bridges in external devices might have the same
  3296. * device ID as those on the host, but they will not have the
  3297. * associated ACPI methods. This implicitly checks that we are at
  3298. * the right bridge.
  3299. */
  3300. if (ACPI_FAILURE(acpi_get_handle(bridge, "DSB0.NHI0.SXIO", &SXIO))
  3301. || ACPI_FAILURE(acpi_get_handle(bridge, "DSB0.NHI0.SXFP", &SXFP))
  3302. || ACPI_FAILURE(acpi_get_handle(bridge, "DSB0.NHI0.SXLV", &SXLV)))
  3303. return;
  3304. pci_info(dev, "quirk: cutting power to Thunderbolt controller...\n");
  3305. /* magic sequence */
  3306. acpi_execute_simple_method(SXIO, NULL, 1);
  3307. acpi_execute_simple_method(SXFP, NULL, 0);
  3308. msleep(300);
  3309. acpi_execute_simple_method(SXLV, NULL, 0);
  3310. acpi_execute_simple_method(SXIO, NULL, 0);
  3311. acpi_execute_simple_method(SXLV, NULL, 0);
  3312. }
  3313. DECLARE_PCI_FIXUP_SUSPEND_LATE(PCI_VENDOR_ID_INTEL,
  3314. PCI_DEVICE_ID_INTEL_CACTUS_RIDGE_4C,
  3315. quirk_apple_poweroff_thunderbolt);
  3316. #endif
  3317. /*
  3318. * Following are device-specific reset methods which can be used to
  3319. * reset a single function if other methods (e.g. FLR, PM D0->D3) are
  3320. * not available.
  3321. */
  3322. static int reset_intel_82599_sfp_virtfn(struct pci_dev *dev, int probe)
  3323. {
  3324. /*
  3325. * http://www.intel.com/content/dam/doc/datasheet/82599-10-gbe-controller-datasheet.pdf
  3326. *
  3327. * The 82599 supports FLR on VFs, but FLR support is reported only
  3328. * in the PF DEVCAP (sec 9.3.10.4), not in the VF DEVCAP (sec 9.5).
  3329. * Thus we must call pcie_flr() directly without first checking if it is
  3330. * supported.
  3331. */
  3332. if (!probe)
  3333. pcie_flr(dev);
  3334. return 0;
  3335. }
  3336. #define SOUTH_CHICKEN2 0xc2004
  3337. #define PCH_PP_STATUS 0xc7200
  3338. #define PCH_PP_CONTROL 0xc7204
  3339. #define MSG_CTL 0x45010
  3340. #define NSDE_PWR_STATE 0xd0100
  3341. #define IGD_OPERATION_TIMEOUT 10000 /* set timeout 10 seconds */
  3342. static int reset_ivb_igd(struct pci_dev *dev, int probe)
  3343. {
  3344. void __iomem *mmio_base;
  3345. unsigned long timeout;
  3346. u32 val;
  3347. if (probe)
  3348. return 0;
  3349. mmio_base = pci_iomap(dev, 0, 0);
  3350. if (!mmio_base)
  3351. return -ENOMEM;
  3352. iowrite32(0x00000002, mmio_base + MSG_CTL);
  3353. /*
  3354. * Clobbering SOUTH_CHICKEN2 register is fine only if the next
  3355. * driver loaded sets the right bits. However, this's a reset and
  3356. * the bits have been set by i915 previously, so we clobber
  3357. * SOUTH_CHICKEN2 register directly here.
  3358. */
  3359. iowrite32(0x00000005, mmio_base + SOUTH_CHICKEN2);
  3360. val = ioread32(mmio_base + PCH_PP_CONTROL) & 0xfffffffe;
  3361. iowrite32(val, mmio_base + PCH_PP_CONTROL);
  3362. timeout = jiffies + msecs_to_jiffies(IGD_OPERATION_TIMEOUT);
  3363. do {
  3364. val = ioread32(mmio_base + PCH_PP_STATUS);
  3365. if ((val & 0xb0000000) == 0)
  3366. goto reset_complete;
  3367. msleep(10);
  3368. } while (time_before(jiffies, timeout));
  3369. pci_warn(dev, "timeout during reset\n");
  3370. reset_complete:
  3371. iowrite32(0x00000002, mmio_base + NSDE_PWR_STATE);
  3372. pci_iounmap(dev, mmio_base);
  3373. return 0;
  3374. }
  3375. /* Device-specific reset method for Chelsio T4-based adapters */
  3376. static int reset_chelsio_generic_dev(struct pci_dev *dev, int probe)
  3377. {
  3378. u16 old_command;
  3379. u16 msix_flags;
  3380. /*
  3381. * If this isn't a Chelsio T4-based device, return -ENOTTY indicating
  3382. * that we have no device-specific reset method.
  3383. */
  3384. if ((dev->device & 0xf000) != 0x4000)
  3385. return -ENOTTY;
  3386. /*
  3387. * If this is the "probe" phase, return 0 indicating that we can
  3388. * reset this device.
  3389. */
  3390. if (probe)
  3391. return 0;
  3392. /*
  3393. * T4 can wedge if there are DMAs in flight within the chip and Bus
  3394. * Master has been disabled. We need to have it on till the Function
  3395. * Level Reset completes. (BUS_MASTER is disabled in
  3396. * pci_reset_function()).
  3397. */
  3398. pci_read_config_word(dev, PCI_COMMAND, &old_command);
  3399. pci_write_config_word(dev, PCI_COMMAND,
  3400. old_command | PCI_COMMAND_MASTER);
  3401. /*
  3402. * Perform the actual device function reset, saving and restoring
  3403. * configuration information around the reset.
  3404. */
  3405. pci_save_state(dev);
  3406. /*
  3407. * T4 also suffers a Head-Of-Line blocking problem if MSI-X interrupts
  3408. * are disabled when an MSI-X interrupt message needs to be delivered.
  3409. * So we briefly re-enable MSI-X interrupts for the duration of the
  3410. * FLR. The pci_restore_state() below will restore the original
  3411. * MSI-X state.
  3412. */
  3413. pci_read_config_word(dev, dev->msix_cap+PCI_MSIX_FLAGS, &msix_flags);
  3414. if ((msix_flags & PCI_MSIX_FLAGS_ENABLE) == 0)
  3415. pci_write_config_word(dev, dev->msix_cap+PCI_MSIX_FLAGS,
  3416. msix_flags |
  3417. PCI_MSIX_FLAGS_ENABLE |
  3418. PCI_MSIX_FLAGS_MASKALL);
  3419. pcie_flr(dev);
  3420. /*
  3421. * Restore the configuration information (BAR values, etc.) including
  3422. * the original PCI Configuration Space Command word, and return
  3423. * success.
  3424. */
  3425. pci_restore_state(dev);
  3426. pci_write_config_word(dev, PCI_COMMAND, old_command);
  3427. return 0;
  3428. }
  3429. #define PCI_DEVICE_ID_INTEL_82599_SFP_VF 0x10ed
  3430. #define PCI_DEVICE_ID_INTEL_IVB_M_VGA 0x0156
  3431. #define PCI_DEVICE_ID_INTEL_IVB_M2_VGA 0x0166
  3432. /*
  3433. * The Samsung SM961/PM961 controller can sometimes enter a fatal state after
  3434. * FLR where config space reads from the device return -1. We seem to be
  3435. * able to avoid this condition if we disable the NVMe controller prior to
  3436. * FLR. This quirk is generic for any NVMe class device requiring similar
  3437. * assistance to quiesce the device prior to FLR.
  3438. *
  3439. * NVMe specification: https://nvmexpress.org/resources/specifications/
  3440. * Revision 1.0e:
  3441. * Chapter 2: Required and optional PCI config registers
  3442. * Chapter 3: NVMe control registers
  3443. * Chapter 7.3: Reset behavior
  3444. */
  3445. static int nvme_disable_and_flr(struct pci_dev *dev, int probe)
  3446. {
  3447. void __iomem *bar;
  3448. u16 cmd;
  3449. u32 cfg;
  3450. if (dev->class != PCI_CLASS_STORAGE_EXPRESS ||
  3451. !pcie_has_flr(dev) || !pci_resource_start(dev, 0))
  3452. return -ENOTTY;
  3453. if (probe)
  3454. return 0;
  3455. bar = pci_iomap(dev, 0, NVME_REG_CC + sizeof(cfg));
  3456. if (!bar)
  3457. return -ENOTTY;
  3458. pci_read_config_word(dev, PCI_COMMAND, &cmd);
  3459. pci_write_config_word(dev, PCI_COMMAND, cmd | PCI_COMMAND_MEMORY);
  3460. cfg = readl(bar + NVME_REG_CC);
  3461. /* Disable controller if enabled */
  3462. if (cfg & NVME_CC_ENABLE) {
  3463. u32 cap = readl(bar + NVME_REG_CAP);
  3464. unsigned long timeout;
  3465. /*
  3466. * Per nvme_disable_ctrl() skip shutdown notification as it
  3467. * could complete commands to the admin queue. We only intend
  3468. * to quiesce the device before reset.
  3469. */
  3470. cfg &= ~(NVME_CC_SHN_MASK | NVME_CC_ENABLE);
  3471. writel(cfg, bar + NVME_REG_CC);
  3472. /*
  3473. * Some controllers require an additional delay here, see
  3474. * NVME_QUIRK_DELAY_BEFORE_CHK_RDY. None of those are yet
  3475. * supported by this quirk.
  3476. */
  3477. /* Cap register provides max timeout in 500ms increments */
  3478. timeout = ((NVME_CAP_TIMEOUT(cap) + 1) * HZ / 2) + jiffies;
  3479. for (;;) {
  3480. u32 status = readl(bar + NVME_REG_CSTS);
  3481. /* Ready status becomes zero on disable complete */
  3482. if (!(status & NVME_CSTS_RDY))
  3483. break;
  3484. msleep(100);
  3485. if (time_after(jiffies, timeout)) {
  3486. pci_warn(dev, "Timeout waiting for NVMe ready status to clear after disable\n");
  3487. break;
  3488. }
  3489. }
  3490. }
  3491. pci_iounmap(dev, bar);
  3492. pcie_flr(dev);
  3493. return 0;
  3494. }
  3495. /*
  3496. * Intel DC P3700 NVMe controller will timeout waiting for ready status
  3497. * to change after NVMe enable if the driver starts interacting with the
  3498. * device too soon after FLR. A 250ms delay after FLR has heuristically
  3499. * proven to produce reliably working results for device assignment cases.
  3500. */
  3501. static int delay_250ms_after_flr(struct pci_dev *dev, int probe)
  3502. {
  3503. if (!pcie_has_flr(dev))
  3504. return -ENOTTY;
  3505. if (probe)
  3506. return 0;
  3507. pcie_flr(dev);
  3508. msleep(250);
  3509. return 0;
  3510. }
  3511. #define PCI_DEVICE_ID_HINIC_VF 0x375E
  3512. #define HINIC_VF_FLR_TYPE 0x1000
  3513. #define HINIC_VF_FLR_CAP_BIT (1UL << 30)
  3514. #define HINIC_VF_OP 0xE80
  3515. #define HINIC_VF_FLR_PROC_BIT (1UL << 18)
  3516. #define HINIC_OPERATION_TIMEOUT 15000 /* 15 seconds */
  3517. /* Device-specific reset method for Huawei Intelligent NIC virtual functions */
  3518. static int reset_hinic_vf_dev(struct pci_dev *pdev, int probe)
  3519. {
  3520. unsigned long timeout;
  3521. void __iomem *bar;
  3522. u32 val;
  3523. if (probe)
  3524. return 0;
  3525. bar = pci_iomap(pdev, 0, 0);
  3526. if (!bar)
  3527. return -ENOTTY;
  3528. /* Get and check firmware capabilities */
  3529. val = ioread32be(bar + HINIC_VF_FLR_TYPE);
  3530. if (!(val & HINIC_VF_FLR_CAP_BIT)) {
  3531. pci_iounmap(pdev, bar);
  3532. return -ENOTTY;
  3533. }
  3534. /* Set HINIC_VF_FLR_PROC_BIT for the start of FLR */
  3535. val = ioread32be(bar + HINIC_VF_OP);
  3536. val = val | HINIC_VF_FLR_PROC_BIT;
  3537. iowrite32be(val, bar + HINIC_VF_OP);
  3538. pcie_flr(pdev);
  3539. /*
  3540. * The device must recapture its Bus and Device Numbers after FLR
  3541. * in order generate Completions. Issue a config write to let the
  3542. * device capture this information.
  3543. */
  3544. pci_write_config_word(pdev, PCI_VENDOR_ID, 0);
  3545. /* Firmware clears HINIC_VF_FLR_PROC_BIT when reset is complete */
  3546. timeout = jiffies + msecs_to_jiffies(HINIC_OPERATION_TIMEOUT);
  3547. do {
  3548. val = ioread32be(bar + HINIC_VF_OP);
  3549. if (!(val & HINIC_VF_FLR_PROC_BIT))
  3550. goto reset_complete;
  3551. msleep(20);
  3552. } while (time_before(jiffies, timeout));
  3553. val = ioread32be(bar + HINIC_VF_OP);
  3554. if (!(val & HINIC_VF_FLR_PROC_BIT))
  3555. goto reset_complete;
  3556. pci_warn(pdev, "Reset dev timeout, FLR ack reg: %#010x\n", val);
  3557. reset_complete:
  3558. pci_iounmap(pdev, bar);
  3559. return 0;
  3560. }
  3561. static const struct pci_dev_reset_methods pci_dev_reset_methods[] = {
  3562. { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82599_SFP_VF,
  3563. reset_intel_82599_sfp_virtfn },
  3564. { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_IVB_M_VGA,
  3565. reset_ivb_igd },
  3566. { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_IVB_M2_VGA,
  3567. reset_ivb_igd },
  3568. { PCI_VENDOR_ID_SAMSUNG, 0xa804, nvme_disable_and_flr },
  3569. { PCI_VENDOR_ID_INTEL, 0x0953, delay_250ms_after_flr },
  3570. { PCI_VENDOR_ID_CHELSIO, PCI_ANY_ID,
  3571. reset_chelsio_generic_dev },
  3572. { PCI_VENDOR_ID_HUAWEI, PCI_DEVICE_ID_HINIC_VF,
  3573. reset_hinic_vf_dev },
  3574. { 0 }
  3575. };
  3576. /*
  3577. * These device-specific reset methods are here rather than in a driver
  3578. * because when a host assigns a device to a guest VM, the host may need
  3579. * to reset the device but probably doesn't have a driver for it.
  3580. */
  3581. int pci_dev_specific_reset(struct pci_dev *dev, int probe)
  3582. {
  3583. const struct pci_dev_reset_methods *i;
  3584. for (i = pci_dev_reset_methods; i->reset; i++) {
  3585. if ((i->vendor == dev->vendor ||
  3586. i->vendor == (u16)PCI_ANY_ID) &&
  3587. (i->device == dev->device ||
  3588. i->device == (u16)PCI_ANY_ID))
  3589. return i->reset(dev, probe);
  3590. }
  3591. return -ENOTTY;
  3592. }
  3593. static void quirk_dma_func0_alias(struct pci_dev *dev)
  3594. {
  3595. if (PCI_FUNC(dev->devfn) != 0)
  3596. pci_add_dma_alias(dev, PCI_DEVFN(PCI_SLOT(dev->devfn), 0), 1);
  3597. }
  3598. /*
  3599. * https://bugzilla.redhat.com/show_bug.cgi?id=605888
  3600. *
  3601. * Some Ricoh devices use function 0 as the PCIe requester ID for DMA.
  3602. */
  3603. DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_RICOH, 0xe832, quirk_dma_func0_alias);
  3604. DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_RICOH, 0xe476, quirk_dma_func0_alias);
  3605. static void quirk_dma_func1_alias(struct pci_dev *dev)
  3606. {
  3607. if (PCI_FUNC(dev->devfn) != 1)
  3608. pci_add_dma_alias(dev, PCI_DEVFN(PCI_SLOT(dev->devfn), 1), 1);
  3609. }
  3610. /*
  3611. * Marvell 88SE9123 uses function 1 as the requester ID for DMA. In some
  3612. * SKUs function 1 is present and is a legacy IDE controller, in other
  3613. * SKUs this function is not present, making this a ghost requester.
  3614. * https://bugzilla.kernel.org/show_bug.cgi?id=42679
  3615. */
  3616. DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_MARVELL_EXT, 0x9120,
  3617. quirk_dma_func1_alias);
  3618. DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_MARVELL_EXT, 0x9123,
  3619. quirk_dma_func1_alias);
  3620. /* https://bugzilla.kernel.org/show_bug.cgi?id=42679#c136 */
  3621. DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_MARVELL_EXT, 0x9125,
  3622. quirk_dma_func1_alias);
  3623. DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_MARVELL_EXT, 0x9128,
  3624. quirk_dma_func1_alias);
  3625. /* https://bugzilla.kernel.org/show_bug.cgi?id=42679#c14 */
  3626. DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_MARVELL_EXT, 0x9130,
  3627. quirk_dma_func1_alias);
  3628. DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_MARVELL_EXT, 0x9170,
  3629. quirk_dma_func1_alias);
  3630. /* https://bugzilla.kernel.org/show_bug.cgi?id=42679#c47 + c57 */
  3631. DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_MARVELL_EXT, 0x9172,
  3632. quirk_dma_func1_alias);
  3633. /* https://bugzilla.kernel.org/show_bug.cgi?id=42679#c59 */
  3634. DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_MARVELL_EXT, 0x917a,
  3635. quirk_dma_func1_alias);
  3636. /* https://bugzilla.kernel.org/show_bug.cgi?id=42679#c78 */
  3637. DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_MARVELL_EXT, 0x9182,
  3638. quirk_dma_func1_alias);
  3639. /* https://bugzilla.kernel.org/show_bug.cgi?id=42679#c134 */
  3640. DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_MARVELL_EXT, 0x9183,
  3641. quirk_dma_func1_alias);
  3642. /* https://bugzilla.kernel.org/show_bug.cgi?id=42679#c46 */
  3643. DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_MARVELL_EXT, 0x91a0,
  3644. quirk_dma_func1_alias);
  3645. /* https://bugzilla.kernel.org/show_bug.cgi?id=42679#c135 */
  3646. DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_MARVELL_EXT, 0x9215,
  3647. quirk_dma_func1_alias);
  3648. /* https://bugzilla.kernel.org/show_bug.cgi?id=42679#c127 */
  3649. DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_MARVELL_EXT, 0x9220,
  3650. quirk_dma_func1_alias);
  3651. /* https://bugzilla.kernel.org/show_bug.cgi?id=42679#c49 */
  3652. DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_MARVELL_EXT, 0x9230,
  3653. quirk_dma_func1_alias);
  3654. DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_TTI, 0x0642,
  3655. quirk_dma_func1_alias);
  3656. DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_TTI, 0x0645,
  3657. quirk_dma_func1_alias);
  3658. /* https://bugs.gentoo.org/show_bug.cgi?id=497630 */
  3659. DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_JMICRON,
  3660. PCI_DEVICE_ID_JMICRON_JMB388_ESD,
  3661. quirk_dma_func1_alias);
  3662. /* https://bugzilla.kernel.org/show_bug.cgi?id=42679#c117 */
  3663. DECLARE_PCI_FIXUP_HEADER(0x1c28, /* Lite-On */
  3664. 0x0122, /* Plextor M6E (Marvell 88SS9183)*/
  3665. quirk_dma_func1_alias);
  3666. /*
  3667. * Some devices DMA with the wrong devfn, not just the wrong function.
  3668. * quirk_fixed_dma_alias() uses this table to create fixed aliases, where
  3669. * the alias is "fixed" and independent of the device devfn.
  3670. *
  3671. * For example, the Adaptec 3405 is a PCIe card with an Intel 80333 I/O
  3672. * processor. To software, this appears as a PCIe-to-PCI/X bridge with a
  3673. * single device on the secondary bus. In reality, the single exposed
  3674. * device at 0e.0 is the Address Translation Unit (ATU) of the controller
  3675. * that provides a bridge to the internal bus of the I/O processor. The
  3676. * controller supports private devices, which can be hidden from PCI config
  3677. * space. In the case of the Adaptec 3405, a private device at 01.0
  3678. * appears to be the DMA engine, which therefore needs to become a DMA
  3679. * alias for the device.
  3680. */
  3681. static const struct pci_device_id fixed_dma_alias_tbl[] = {
  3682. { PCI_DEVICE_SUB(PCI_VENDOR_ID_ADAPTEC2, 0x0285,
  3683. PCI_VENDOR_ID_ADAPTEC2, 0x02bb), /* Adaptec 3405 */
  3684. .driver_data = PCI_DEVFN(1, 0) },
  3685. { PCI_DEVICE_SUB(PCI_VENDOR_ID_ADAPTEC2, 0x0285,
  3686. PCI_VENDOR_ID_ADAPTEC2, 0x02bc), /* Adaptec 3805 */
  3687. .driver_data = PCI_DEVFN(1, 0) },
  3688. { 0 }
  3689. };
  3690. static void quirk_fixed_dma_alias(struct pci_dev *dev)
  3691. {
  3692. const struct pci_device_id *id;
  3693. id = pci_match_id(fixed_dma_alias_tbl, dev);
  3694. if (id)
  3695. pci_add_dma_alias(dev, id->driver_data, 1);
  3696. }
  3697. DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_ADAPTEC2, 0x0285, quirk_fixed_dma_alias);
  3698. /*
  3699. * A few PCIe-to-PCI bridges fail to expose a PCIe capability, resulting in
  3700. * using the wrong DMA alias for the device. Some of these devices can be
  3701. * used as either forward or reverse bridges, so we need to test whether the
  3702. * device is operating in the correct mode. We could probably apply this
  3703. * quirk to PCI_ANY_ID, but for now we'll just use known offenders. The test
  3704. * is for a non-root, non-PCIe bridge where the upstream device is PCIe and
  3705. * is not a PCIe-to-PCI bridge, then @pdev is actually a PCIe-to-PCI bridge.
  3706. */
  3707. static void quirk_use_pcie_bridge_dma_alias(struct pci_dev *pdev)
  3708. {
  3709. if (!pci_is_root_bus(pdev->bus) &&
  3710. pdev->hdr_type == PCI_HEADER_TYPE_BRIDGE &&
  3711. !pci_is_pcie(pdev) && pci_is_pcie(pdev->bus->self) &&
  3712. pci_pcie_type(pdev->bus->self) != PCI_EXP_TYPE_PCI_BRIDGE)
  3713. pdev->dev_flags |= PCI_DEV_FLAG_PCIE_BRIDGE_ALIAS;
  3714. }
  3715. /* ASM1083/1085, https://bugzilla.kernel.org/show_bug.cgi?id=44881#c46 */
  3716. DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_ASMEDIA, 0x1080,
  3717. quirk_use_pcie_bridge_dma_alias);
  3718. /* Tundra 8113, https://bugzilla.kernel.org/show_bug.cgi?id=44881#c43 */
  3719. DECLARE_PCI_FIXUP_HEADER(0x10e3, 0x8113, quirk_use_pcie_bridge_dma_alias);
  3720. /* ITE 8892, https://bugzilla.kernel.org/show_bug.cgi?id=73551 */
  3721. DECLARE_PCI_FIXUP_HEADER(0x1283, 0x8892, quirk_use_pcie_bridge_dma_alias);
  3722. /* ITE 8893 has the same problem as the 8892 */
  3723. DECLARE_PCI_FIXUP_HEADER(0x1283, 0x8893, quirk_use_pcie_bridge_dma_alias);
  3724. /* Intel 82801, https://bugzilla.kernel.org/show_bug.cgi?id=44881#c49 */
  3725. DECLARE_PCI_FIXUP_HEADER(0x8086, 0x244e, quirk_use_pcie_bridge_dma_alias);
  3726. /*
  3727. * MIC x200 NTB forwards PCIe traffic using multiple alien RIDs. They have to
  3728. * be added as aliases to the DMA device in order to allow buffer access
  3729. * when IOMMU is enabled. Following devfns have to match RIT-LUT table
  3730. * programmed in the EEPROM.
  3731. */
  3732. static void quirk_mic_x200_dma_alias(struct pci_dev *pdev)
  3733. {
  3734. pci_add_dma_alias(pdev, PCI_DEVFN(0x10, 0x0), 1);
  3735. pci_add_dma_alias(pdev, PCI_DEVFN(0x11, 0x0), 1);
  3736. pci_add_dma_alias(pdev, PCI_DEVFN(0x12, 0x3), 1);
  3737. }
  3738. DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x2260, quirk_mic_x200_dma_alias);
  3739. DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x2264, quirk_mic_x200_dma_alias);
  3740. /*
  3741. * Intel Visual Compute Accelerator (VCA) is a family of PCIe add-in devices
  3742. * exposing computational units via Non Transparent Bridges (NTB, PEX 87xx).
  3743. *
  3744. * Similarly to MIC x200, we need to add DMA aliases to allow buffer access
  3745. * when IOMMU is enabled. These aliases allow computational unit access to
  3746. * host memory. These aliases mark the whole VCA device as one IOMMU
  3747. * group.
  3748. *
  3749. * All possible slot numbers (0x20) are used, since we are unable to tell
  3750. * what slot is used on other side. This quirk is intended for both host
  3751. * and computational unit sides. The VCA devices have up to five functions
  3752. * (four for DMA channels and one additional).
  3753. */
  3754. static void quirk_pex_vca_alias(struct pci_dev *pdev)
  3755. {
  3756. const unsigned int num_pci_slots = 0x20;
  3757. unsigned int slot;
  3758. for (slot = 0; slot < num_pci_slots; slot++)
  3759. pci_add_dma_alias(pdev, PCI_DEVFN(slot, 0x0), 5);
  3760. }
  3761. DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x2954, quirk_pex_vca_alias);
  3762. DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x2955, quirk_pex_vca_alias);
  3763. DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x2956, quirk_pex_vca_alias);
  3764. DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x2958, quirk_pex_vca_alias);
  3765. DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x2959, quirk_pex_vca_alias);
  3766. DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x295A, quirk_pex_vca_alias);
  3767. /*
  3768. * The IOMMU and interrupt controller on Broadcom Vulcan/Cavium ThunderX2 are
  3769. * associated not at the root bus, but at a bridge below. This quirk avoids
  3770. * generating invalid DMA aliases.
  3771. */
  3772. static void quirk_bridge_cavm_thrx2_pcie_root(struct pci_dev *pdev)
  3773. {
  3774. pdev->dev_flags |= PCI_DEV_FLAGS_BRIDGE_XLATE_ROOT;
  3775. }
  3776. DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_BROADCOM, 0x9000,
  3777. quirk_bridge_cavm_thrx2_pcie_root);
  3778. DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_BROADCOM, 0x9084,
  3779. quirk_bridge_cavm_thrx2_pcie_root);
  3780. /*
  3781. * Intersil/Techwell TW686[4589]-based video capture cards have an empty (zero)
  3782. * class code. Fix it.
  3783. */
  3784. static void quirk_tw686x_class(struct pci_dev *pdev)
  3785. {
  3786. u32 class = pdev->class;
  3787. /* Use "Multimedia controller" class */
  3788. pdev->class = (PCI_CLASS_MULTIMEDIA_OTHER << 8) | 0x01;
  3789. pci_info(pdev, "TW686x PCI class overridden (%#08x -> %#08x)\n",
  3790. class, pdev->class);
  3791. }
  3792. DECLARE_PCI_FIXUP_CLASS_EARLY(0x1797, 0x6864, PCI_CLASS_NOT_DEFINED, 8,
  3793. quirk_tw686x_class);
  3794. DECLARE_PCI_FIXUP_CLASS_EARLY(0x1797, 0x6865, PCI_CLASS_NOT_DEFINED, 8,
  3795. quirk_tw686x_class);
  3796. DECLARE_PCI_FIXUP_CLASS_EARLY(0x1797, 0x6868, PCI_CLASS_NOT_DEFINED, 8,
  3797. quirk_tw686x_class);
  3798. DECLARE_PCI_FIXUP_CLASS_EARLY(0x1797, 0x6869, PCI_CLASS_NOT_DEFINED, 8,
  3799. quirk_tw686x_class);
  3800. /*
  3801. * Some devices have problems with Transaction Layer Packets with the Relaxed
  3802. * Ordering Attribute set. Such devices should mark themselves and other
  3803. * device drivers should check before sending TLPs with RO set.
  3804. */
  3805. static void quirk_relaxedordering_disable(struct pci_dev *dev)
  3806. {
  3807. dev->dev_flags |= PCI_DEV_FLAGS_NO_RELAXED_ORDERING;
  3808. pci_info(dev, "Disable Relaxed Ordering Attributes to avoid PCIe Completion erratum\n");
  3809. }
  3810. /*
  3811. * Intel Xeon processors based on Broadwell/Haswell microarchitecture Root
  3812. * Complex have a Flow Control Credit issue which can cause performance
  3813. * problems with Upstream Transaction Layer Packets with Relaxed Ordering set.
  3814. */
  3815. DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_INTEL, 0x6f01, PCI_CLASS_NOT_DEFINED, 8,
  3816. quirk_relaxedordering_disable);
  3817. DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_INTEL, 0x6f02, PCI_CLASS_NOT_DEFINED, 8,
  3818. quirk_relaxedordering_disable);
  3819. DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_INTEL, 0x6f03, PCI_CLASS_NOT_DEFINED, 8,
  3820. quirk_relaxedordering_disable);
  3821. DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_INTEL, 0x6f04, PCI_CLASS_NOT_DEFINED, 8,
  3822. quirk_relaxedordering_disable);
  3823. DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_INTEL, 0x6f05, PCI_CLASS_NOT_DEFINED, 8,
  3824. quirk_relaxedordering_disable);
  3825. DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_INTEL, 0x6f06, PCI_CLASS_NOT_DEFINED, 8,
  3826. quirk_relaxedordering_disable);
  3827. DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_INTEL, 0x6f07, PCI_CLASS_NOT_DEFINED, 8,
  3828. quirk_relaxedordering_disable);
  3829. DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_INTEL, 0x6f08, PCI_CLASS_NOT_DEFINED, 8,
  3830. quirk_relaxedordering_disable);
  3831. DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_INTEL, 0x6f09, PCI_CLASS_NOT_DEFINED, 8,
  3832. quirk_relaxedordering_disable);
  3833. DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_INTEL, 0x6f0a, PCI_CLASS_NOT_DEFINED, 8,
  3834. quirk_relaxedordering_disable);
  3835. DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_INTEL, 0x6f0b, PCI_CLASS_NOT_DEFINED, 8,
  3836. quirk_relaxedordering_disable);
  3837. DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_INTEL, 0x6f0c, PCI_CLASS_NOT_DEFINED, 8,
  3838. quirk_relaxedordering_disable);
  3839. DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_INTEL, 0x6f0d, PCI_CLASS_NOT_DEFINED, 8,
  3840. quirk_relaxedordering_disable);
  3841. DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_INTEL, 0x6f0e, PCI_CLASS_NOT_DEFINED, 8,
  3842. quirk_relaxedordering_disable);
  3843. DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_INTEL, 0x2f01, PCI_CLASS_NOT_DEFINED, 8,
  3844. quirk_relaxedordering_disable);
  3845. DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_INTEL, 0x2f02, PCI_CLASS_NOT_DEFINED, 8,
  3846. quirk_relaxedordering_disable);
  3847. DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_INTEL, 0x2f03, PCI_CLASS_NOT_DEFINED, 8,
  3848. quirk_relaxedordering_disable);
  3849. DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_INTEL, 0x2f04, PCI_CLASS_NOT_DEFINED, 8,
  3850. quirk_relaxedordering_disable);
  3851. DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_INTEL, 0x2f05, PCI_CLASS_NOT_DEFINED, 8,
  3852. quirk_relaxedordering_disable);
  3853. DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_INTEL, 0x2f06, PCI_CLASS_NOT_DEFINED, 8,
  3854. quirk_relaxedordering_disable);
  3855. DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_INTEL, 0x2f07, PCI_CLASS_NOT_DEFINED, 8,
  3856. quirk_relaxedordering_disable);
  3857. DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_INTEL, 0x2f08, PCI_CLASS_NOT_DEFINED, 8,
  3858. quirk_relaxedordering_disable);
  3859. DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_INTEL, 0x2f09, PCI_CLASS_NOT_DEFINED, 8,
  3860. quirk_relaxedordering_disable);
  3861. DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_INTEL, 0x2f0a, PCI_CLASS_NOT_DEFINED, 8,
  3862. quirk_relaxedordering_disable);
  3863. DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_INTEL, 0x2f0b, PCI_CLASS_NOT_DEFINED, 8,
  3864. quirk_relaxedordering_disable);
  3865. DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_INTEL, 0x2f0c, PCI_CLASS_NOT_DEFINED, 8,
  3866. quirk_relaxedordering_disable);
  3867. DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_INTEL, 0x2f0d, PCI_CLASS_NOT_DEFINED, 8,
  3868. quirk_relaxedordering_disable);
  3869. DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_INTEL, 0x2f0e, PCI_CLASS_NOT_DEFINED, 8,
  3870. quirk_relaxedordering_disable);
  3871. /*
  3872. * The AMD ARM A1100 (aka "SEATTLE") SoC has a bug in its PCIe Root Complex
  3873. * where Upstream Transaction Layer Packets with the Relaxed Ordering
  3874. * Attribute clear are allowed to bypass earlier TLPs with Relaxed Ordering
  3875. * set. This is a violation of the PCIe 3.0 Transaction Ordering Rules
  3876. * outlined in Section 2.4.1 (PCI Express(r) Base Specification Revision 3.0
  3877. * November 10, 2010). As a result, on this platform we can't use Relaxed
  3878. * Ordering for Upstream TLPs.
  3879. */
  3880. DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_AMD, 0x1a00, PCI_CLASS_NOT_DEFINED, 8,
  3881. quirk_relaxedordering_disable);
  3882. DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_AMD, 0x1a01, PCI_CLASS_NOT_DEFINED, 8,
  3883. quirk_relaxedordering_disable);
  3884. DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_AMD, 0x1a02, PCI_CLASS_NOT_DEFINED, 8,
  3885. quirk_relaxedordering_disable);
  3886. /*
  3887. * Per PCIe r3.0, sec 2.2.9, "Completion headers must supply the same
  3888. * values for the Attribute as were supplied in the header of the
  3889. * corresponding Request, except as explicitly allowed when IDO is used."
  3890. *
  3891. * If a non-compliant device generates a completion with a different
  3892. * attribute than the request, the receiver may accept it (which itself
  3893. * seems non-compliant based on sec 2.3.2), or it may handle it as a
  3894. * Malformed TLP or an Unexpected Completion, which will probably lead to a
  3895. * device access timeout.
  3896. *
  3897. * If the non-compliant device generates completions with zero attributes
  3898. * (instead of copying the attributes from the request), we can work around
  3899. * this by disabling the "Relaxed Ordering" and "No Snoop" attributes in
  3900. * upstream devices so they always generate requests with zero attributes.
  3901. *
  3902. * This affects other devices under the same Root Port, but since these
  3903. * attributes are performance hints, there should be no functional problem.
  3904. *
  3905. * Note that Configuration Space accesses are never supposed to have TLP
  3906. * Attributes, so we're safe waiting till after any Configuration Space
  3907. * accesses to do the Root Port fixup.
  3908. */
  3909. static void quirk_disable_root_port_attributes(struct pci_dev *pdev)
  3910. {
  3911. struct pci_dev *root_port = pcie_find_root_port(pdev);
  3912. if (!root_port) {
  3913. pci_warn(pdev, "PCIe Completion erratum may cause device errors\n");
  3914. return;
  3915. }
  3916. pci_info(root_port, "Disabling No Snoop/Relaxed Ordering Attributes to avoid PCIe Completion erratum in %s\n",
  3917. dev_name(&pdev->dev));
  3918. pcie_capability_clear_and_set_word(root_port, PCI_EXP_DEVCTL,
  3919. PCI_EXP_DEVCTL_RELAX_EN |
  3920. PCI_EXP_DEVCTL_NOSNOOP_EN, 0);
  3921. }
  3922. /*
  3923. * The Chelsio T5 chip fails to copy TLP Attributes from a Request to the
  3924. * Completion it generates.
  3925. */
  3926. static void quirk_chelsio_T5_disable_root_port_attributes(struct pci_dev *pdev)
  3927. {
  3928. /*
  3929. * This mask/compare operation selects for Physical Function 4 on a
  3930. * T5. We only need to fix up the Root Port once for any of the
  3931. * PFs. PF[0..3] have PCI Device IDs of 0x50xx, but PF4 is uniquely
  3932. * 0x54xx so we use that one.
  3933. */
  3934. if ((pdev->device & 0xff00) == 0x5400)
  3935. quirk_disable_root_port_attributes(pdev);
  3936. }
  3937. DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_CHELSIO, PCI_ANY_ID,
  3938. quirk_chelsio_T5_disable_root_port_attributes);
  3939. /*
  3940. * pci_acs_ctrl_enabled - compare desired ACS controls with those provided
  3941. * by a device
  3942. * @acs_ctrl_req: Bitmask of desired ACS controls
  3943. * @acs_ctrl_ena: Bitmask of ACS controls enabled or provided implicitly by
  3944. * the hardware design
  3945. *
  3946. * Return 1 if all ACS controls in the @acs_ctrl_req bitmask are included
  3947. * in @acs_ctrl_ena, i.e., the device provides all the access controls the
  3948. * caller desires. Return 0 otherwise.
  3949. */
  3950. static int pci_acs_ctrl_enabled(u16 acs_ctrl_req, u16 acs_ctrl_ena)
  3951. {
  3952. if ((acs_ctrl_req & acs_ctrl_ena) == acs_ctrl_req)
  3953. return 1;
  3954. return 0;
  3955. }
  3956. /*
  3957. * AMD has indicated that the devices below do not support peer-to-peer
  3958. * in any system where they are found in the southbridge with an AMD
  3959. * IOMMU in the system. Multifunction devices that do not support
  3960. * peer-to-peer between functions can claim to support a subset of ACS.
  3961. * Such devices effectively enable request redirect (RR) and completion
  3962. * redirect (CR) since all transactions are redirected to the upstream
  3963. * root complex.
  3964. *
  3965. * https://lore.kernel.org/r/201207111426.q6BEQTbh002928@mail.maya.org/
  3966. * https://lore.kernel.org/r/20120711165854.GM25282@amd.com/
  3967. * https://lore.kernel.org/r/20121005130857.GX4009@amd.com/
  3968. *
  3969. * 1002:4385 SBx00 SMBus Controller
  3970. * 1002:439c SB7x0/SB8x0/SB9x0 IDE Controller
  3971. * 1002:4383 SBx00 Azalia (Intel HDA)
  3972. * 1002:439d SB7x0/SB8x0/SB9x0 LPC host controller
  3973. * 1002:4384 SBx00 PCI to PCI Bridge
  3974. * 1002:4399 SB7x0/SB8x0/SB9x0 USB OHCI2 Controller
  3975. *
  3976. * https://bugzilla.kernel.org/show_bug.cgi?id=81841#c15
  3977. *
  3978. * 1022:780f [AMD] FCH PCI Bridge
  3979. * 1022:7809 [AMD] FCH USB OHCI Controller
  3980. */
  3981. static int pci_quirk_amd_sb_acs(struct pci_dev *dev, u16 acs_flags)
  3982. {
  3983. #ifdef CONFIG_ACPI
  3984. struct acpi_table_header *header = NULL;
  3985. acpi_status status;
  3986. /* Targeting multifunction devices on the SB (appears on root bus) */
  3987. if (!dev->multifunction || !pci_is_root_bus(dev->bus))
  3988. return -ENODEV;
  3989. /* The IVRS table describes the AMD IOMMU */
  3990. status = acpi_get_table("IVRS", 0, &header);
  3991. if (ACPI_FAILURE(status))
  3992. return -ENODEV;
  3993. acpi_put_table(header);
  3994. /* Filter out flags not applicable to multifunction */
  3995. acs_flags &= (PCI_ACS_RR | PCI_ACS_CR | PCI_ACS_EC | PCI_ACS_DT);
  3996. return pci_acs_ctrl_enabled(acs_flags, PCI_ACS_RR | PCI_ACS_CR);
  3997. #else
  3998. return -ENODEV;
  3999. #endif
  4000. }
  4001. static bool pci_quirk_cavium_acs_match(struct pci_dev *dev)
  4002. {
  4003. if (!pci_is_pcie(dev) || pci_pcie_type(dev) != PCI_EXP_TYPE_ROOT_PORT)
  4004. return false;
  4005. switch (dev->device) {
  4006. /*
  4007. * Effectively selects all downstream ports for whole ThunderX1
  4008. * (which represents 8 SoCs).
  4009. */
  4010. case 0xa000 ... 0xa7ff: /* ThunderX1 */
  4011. case 0xaf84: /* ThunderX2 */
  4012. case 0xb884: /* ThunderX3 */
  4013. return true;
  4014. default:
  4015. return false;
  4016. }
  4017. }
  4018. static int pci_quirk_cavium_acs(struct pci_dev *dev, u16 acs_flags)
  4019. {
  4020. if (!pci_quirk_cavium_acs_match(dev))
  4021. return -ENOTTY;
  4022. /*
  4023. * Cavium Root Ports don't advertise an ACS capability. However,
  4024. * the RTL internally implements similar protection as if ACS had
  4025. * Source Validation, Request Redirection, Completion Redirection,
  4026. * and Upstream Forwarding features enabled. Assert that the
  4027. * hardware implements and enables equivalent ACS functionality for
  4028. * these flags.
  4029. */
  4030. return pci_acs_ctrl_enabled(acs_flags,
  4031. PCI_ACS_SV | PCI_ACS_RR | PCI_ACS_CR | PCI_ACS_UF);
  4032. }
  4033. static int pci_quirk_xgene_acs(struct pci_dev *dev, u16 acs_flags)
  4034. {
  4035. /*
  4036. * X-Gene Root Ports matching this quirk do not allow peer-to-peer
  4037. * transactions with others, allowing masking out these bits as if they
  4038. * were unimplemented in the ACS capability.
  4039. */
  4040. return pci_acs_ctrl_enabled(acs_flags,
  4041. PCI_ACS_SV | PCI_ACS_RR | PCI_ACS_CR | PCI_ACS_UF);
  4042. }
  4043. /*
  4044. * Many Zhaoxin Root Ports and Switch Downstream Ports have no ACS capability.
  4045. * But the implementation could block peer-to-peer transactions between them
  4046. * and provide ACS-like functionality.
  4047. */
  4048. static int pci_quirk_zhaoxin_pcie_ports_acs(struct pci_dev *dev, u16 acs_flags)
  4049. {
  4050. if (!pci_is_pcie(dev) ||
  4051. ((pci_pcie_type(dev) != PCI_EXP_TYPE_ROOT_PORT) &&
  4052. (pci_pcie_type(dev) != PCI_EXP_TYPE_DOWNSTREAM)))
  4053. return -ENOTTY;
  4054. switch (dev->device) {
  4055. case 0x0710 ... 0x071e:
  4056. case 0x0721:
  4057. case 0x0723 ... 0x0732:
  4058. return pci_acs_ctrl_enabled(acs_flags,
  4059. PCI_ACS_SV | PCI_ACS_RR | PCI_ACS_CR | PCI_ACS_UF);
  4060. }
  4061. return false;
  4062. }
  4063. /*
  4064. * Many Intel PCH Root Ports do provide ACS-like features to disable peer
  4065. * transactions and validate bus numbers in requests, but do not provide an
  4066. * actual PCIe ACS capability. This is the list of device IDs known to fall
  4067. * into that category as provided by Intel in Red Hat bugzilla 1037684.
  4068. */
  4069. static const u16 pci_quirk_intel_pch_acs_ids[] = {
  4070. /* Ibexpeak PCH */
  4071. 0x3b42, 0x3b43, 0x3b44, 0x3b45, 0x3b46, 0x3b47, 0x3b48, 0x3b49,
  4072. 0x3b4a, 0x3b4b, 0x3b4c, 0x3b4d, 0x3b4e, 0x3b4f, 0x3b50, 0x3b51,
  4073. /* Cougarpoint PCH */
  4074. 0x1c10, 0x1c11, 0x1c12, 0x1c13, 0x1c14, 0x1c15, 0x1c16, 0x1c17,
  4075. 0x1c18, 0x1c19, 0x1c1a, 0x1c1b, 0x1c1c, 0x1c1d, 0x1c1e, 0x1c1f,
  4076. /* Pantherpoint PCH */
  4077. 0x1e10, 0x1e11, 0x1e12, 0x1e13, 0x1e14, 0x1e15, 0x1e16, 0x1e17,
  4078. 0x1e18, 0x1e19, 0x1e1a, 0x1e1b, 0x1e1c, 0x1e1d, 0x1e1e, 0x1e1f,
  4079. /* Lynxpoint-H PCH */
  4080. 0x8c10, 0x8c11, 0x8c12, 0x8c13, 0x8c14, 0x8c15, 0x8c16, 0x8c17,
  4081. 0x8c18, 0x8c19, 0x8c1a, 0x8c1b, 0x8c1c, 0x8c1d, 0x8c1e, 0x8c1f,
  4082. /* Lynxpoint-LP PCH */
  4083. 0x9c10, 0x9c11, 0x9c12, 0x9c13, 0x9c14, 0x9c15, 0x9c16, 0x9c17,
  4084. 0x9c18, 0x9c19, 0x9c1a, 0x9c1b,
  4085. /* Wildcat PCH */
  4086. 0x9c90, 0x9c91, 0x9c92, 0x9c93, 0x9c94, 0x9c95, 0x9c96, 0x9c97,
  4087. 0x9c98, 0x9c99, 0x9c9a, 0x9c9b,
  4088. /* Patsburg (X79) PCH */
  4089. 0x1d10, 0x1d12, 0x1d14, 0x1d16, 0x1d18, 0x1d1a, 0x1d1c, 0x1d1e,
  4090. /* Wellsburg (X99) PCH */
  4091. 0x8d10, 0x8d11, 0x8d12, 0x8d13, 0x8d14, 0x8d15, 0x8d16, 0x8d17,
  4092. 0x8d18, 0x8d19, 0x8d1a, 0x8d1b, 0x8d1c, 0x8d1d, 0x8d1e,
  4093. /* Lynx Point (9 series) PCH */
  4094. 0x8c90, 0x8c92, 0x8c94, 0x8c96, 0x8c98, 0x8c9a, 0x8c9c, 0x8c9e,
  4095. };
  4096. static bool pci_quirk_intel_pch_acs_match(struct pci_dev *dev)
  4097. {
  4098. int i;
  4099. /* Filter out a few obvious non-matches first */
  4100. if (!pci_is_pcie(dev) || pci_pcie_type(dev) != PCI_EXP_TYPE_ROOT_PORT)
  4101. return false;
  4102. for (i = 0; i < ARRAY_SIZE(pci_quirk_intel_pch_acs_ids); i++)
  4103. if (pci_quirk_intel_pch_acs_ids[i] == dev->device)
  4104. return true;
  4105. return false;
  4106. }
  4107. static int pci_quirk_intel_pch_acs(struct pci_dev *dev, u16 acs_flags)
  4108. {
  4109. if (!pci_quirk_intel_pch_acs_match(dev))
  4110. return -ENOTTY;
  4111. if (dev->dev_flags & PCI_DEV_FLAGS_ACS_ENABLED_QUIRK)
  4112. return pci_acs_ctrl_enabled(acs_flags,
  4113. PCI_ACS_SV | PCI_ACS_RR | PCI_ACS_CR | PCI_ACS_UF);
  4114. return pci_acs_ctrl_enabled(acs_flags, 0);
  4115. }
  4116. /*
  4117. * These QCOM Root Ports do provide ACS-like features to disable peer
  4118. * transactions and validate bus numbers in requests, but do not provide an
  4119. * actual PCIe ACS capability. Hardware supports source validation but it
  4120. * will report the issue as Completer Abort instead of ACS Violation.
  4121. * Hardware doesn't support peer-to-peer and each Root Port is a Root
  4122. * Complex with unique segment numbers. It is not possible for one Root
  4123. * Port to pass traffic to another Root Port. All PCIe transactions are
  4124. * terminated inside the Root Port.
  4125. */
  4126. static int pci_quirk_qcom_rp_acs(struct pci_dev *dev, u16 acs_flags)
  4127. {
  4128. return pci_acs_ctrl_enabled(acs_flags,
  4129. PCI_ACS_SV | PCI_ACS_RR | PCI_ACS_CR | PCI_ACS_UF);
  4130. }
  4131. /*
  4132. * Each of these NXP Root Ports is in a Root Complex with a unique segment
  4133. * number and does provide isolation features to disable peer transactions
  4134. * and validate bus numbers in requests, but does not provide an ACS
  4135. * capability.
  4136. */
  4137. static int pci_quirk_nxp_rp_acs(struct pci_dev *dev, u16 acs_flags)
  4138. {
  4139. return pci_acs_ctrl_enabled(acs_flags,
  4140. PCI_ACS_SV | PCI_ACS_RR | PCI_ACS_CR | PCI_ACS_UF);
  4141. }
  4142. static int pci_quirk_al_acs(struct pci_dev *dev, u16 acs_flags)
  4143. {
  4144. if (pci_pcie_type(dev) != PCI_EXP_TYPE_ROOT_PORT)
  4145. return -ENOTTY;
  4146. /*
  4147. * Amazon's Annapurna Labs root ports don't include an ACS capability,
  4148. * but do include ACS-like functionality. The hardware doesn't support
  4149. * peer-to-peer transactions via the root port and each has a unique
  4150. * segment number.
  4151. *
  4152. * Additionally, the root ports cannot send traffic to each other.
  4153. */
  4154. acs_flags &= ~(PCI_ACS_SV | PCI_ACS_RR | PCI_ACS_CR | PCI_ACS_UF);
  4155. return acs_flags ? 0 : 1;
  4156. }
  4157. /*
  4158. * Sunrise Point PCH root ports implement ACS, but unfortunately as shown in
  4159. * the datasheet (Intel 100 Series Chipset Family PCH Datasheet, Vol. 2,
  4160. * 12.1.46, 12.1.47)[1] this chipset uses dwords for the ACS capability and
  4161. * control registers whereas the PCIe spec packs them into words (Rev 3.0,
  4162. * 7.16 ACS Extended Capability). The bit definitions are correct, but the
  4163. * control register is at offset 8 instead of 6 and we should probably use
  4164. * dword accesses to them. This applies to the following PCI Device IDs, as
  4165. * found in volume 1 of the datasheet[2]:
  4166. *
  4167. * 0xa110-0xa11f Sunrise Point-H PCI Express Root Port #{0-16}
  4168. * 0xa167-0xa16a Sunrise Point-H PCI Express Root Port #{17-20}
  4169. *
  4170. * N.B. This doesn't fix what lspci shows.
  4171. *
  4172. * The 100 series chipset specification update includes this as errata #23[3].
  4173. *
  4174. * The 200 series chipset (Union Point) has the same bug according to the
  4175. * specification update (Intel 200 Series Chipset Family Platform Controller
  4176. * Hub, Specification Update, January 2017, Revision 001, Document# 335194-001,
  4177. * Errata 22)[4]. Per the datasheet[5], root port PCI Device IDs for this
  4178. * chipset include:
  4179. *
  4180. * 0xa290-0xa29f PCI Express Root port #{0-16}
  4181. * 0xa2e7-0xa2ee PCI Express Root port #{17-24}
  4182. *
  4183. * Mobile chipsets are also affected, 7th & 8th Generation
  4184. * Specification update confirms ACS errata 22, status no fix: (7th Generation
  4185. * Intel Processor Family I/O for U/Y Platforms and 8th Generation Intel
  4186. * Processor Family I/O for U Quad Core Platforms Specification Update,
  4187. * August 2017, Revision 002, Document#: 334660-002)[6]
  4188. * Device IDs from I/O datasheet: (7th Generation Intel Processor Family I/O
  4189. * for U/Y Platforms and 8th Generation Intel ® Processor Family I/O for U
  4190. * Quad Core Platforms, Vol 1 of 2, August 2017, Document#: 334658-003)[7]
  4191. *
  4192. * 0x9d10-0x9d1b PCI Express Root port #{1-12}
  4193. *
  4194. * [1] https://www.intel.com/content/www/us/en/chipsets/100-series-chipset-datasheet-vol-2.html
  4195. * [2] https://www.intel.com/content/www/us/en/chipsets/100-series-chipset-datasheet-vol-1.html
  4196. * [3] https://www.intel.com/content/www/us/en/chipsets/100-series-chipset-spec-update.html
  4197. * [4] https://www.intel.com/content/www/us/en/chipsets/200-series-chipset-pch-spec-update.html
  4198. * [5] https://www.intel.com/content/www/us/en/chipsets/200-series-chipset-pch-datasheet-vol-1.html
  4199. * [6] https://www.intel.com/content/www/us/en/processors/core/7th-gen-core-family-mobile-u-y-processor-lines-i-o-spec-update.html
  4200. * [7] https://www.intel.com/content/www/us/en/processors/core/7th-gen-core-family-mobile-u-y-processor-lines-i-o-datasheet-vol-1.html
  4201. */
  4202. static bool pci_quirk_intel_spt_pch_acs_match(struct pci_dev *dev)
  4203. {
  4204. if (!pci_is_pcie(dev) || pci_pcie_type(dev) != PCI_EXP_TYPE_ROOT_PORT)
  4205. return false;
  4206. switch (dev->device) {
  4207. case 0xa110 ... 0xa11f: case 0xa167 ... 0xa16a: /* Sunrise Point */
  4208. case 0xa290 ... 0xa29f: case 0xa2e7 ... 0xa2ee: /* Union Point */
  4209. case 0x9d10 ... 0x9d1b: /* 7th & 8th Gen Mobile */
  4210. return true;
  4211. }
  4212. return false;
  4213. }
  4214. #define INTEL_SPT_ACS_CTRL (PCI_ACS_CAP + 4)
  4215. static int pci_quirk_intel_spt_pch_acs(struct pci_dev *dev, u16 acs_flags)
  4216. {
  4217. int pos;
  4218. u32 cap, ctrl;
  4219. if (!pci_quirk_intel_spt_pch_acs_match(dev))
  4220. return -ENOTTY;
  4221. pos = dev->acs_cap;
  4222. if (!pos)
  4223. return -ENOTTY;
  4224. /* see pci_acs_flags_enabled() */
  4225. pci_read_config_dword(dev, pos + PCI_ACS_CAP, &cap);
  4226. acs_flags &= (cap | PCI_ACS_EC);
  4227. pci_read_config_dword(dev, pos + INTEL_SPT_ACS_CTRL, &ctrl);
  4228. return pci_acs_ctrl_enabled(acs_flags, ctrl);
  4229. }
  4230. static int pci_quirk_mf_endpoint_acs(struct pci_dev *dev, u16 acs_flags)
  4231. {
  4232. /*
  4233. * SV, TB, and UF are not relevant to multifunction endpoints.
  4234. *
  4235. * Multifunction devices are only required to implement RR, CR, and DT
  4236. * in their ACS capability if they support peer-to-peer transactions.
  4237. * Devices matching this quirk have been verified by the vendor to not
  4238. * perform peer-to-peer with other functions, allowing us to mask out
  4239. * these bits as if they were unimplemented in the ACS capability.
  4240. */
  4241. return pci_acs_ctrl_enabled(acs_flags,
  4242. PCI_ACS_SV | PCI_ACS_TB | PCI_ACS_RR |
  4243. PCI_ACS_CR | PCI_ACS_UF | PCI_ACS_DT);
  4244. }
  4245. static int pci_quirk_rciep_acs(struct pci_dev *dev, u16 acs_flags)
  4246. {
  4247. /*
  4248. * Intel RCiEP's are required to allow p2p only on translated
  4249. * addresses. Refer to Intel VT-d specification, r3.1, sec 3.16,
  4250. * "Root-Complex Peer to Peer Considerations".
  4251. */
  4252. if (pci_pcie_type(dev) != PCI_EXP_TYPE_RC_END)
  4253. return -ENOTTY;
  4254. return pci_acs_ctrl_enabled(acs_flags,
  4255. PCI_ACS_SV | PCI_ACS_RR | PCI_ACS_CR | PCI_ACS_UF);
  4256. }
  4257. static int pci_quirk_brcm_acs(struct pci_dev *dev, u16 acs_flags)
  4258. {
  4259. /*
  4260. * iProc PAXB Root Ports don't advertise an ACS capability, but
  4261. * they do not allow peer-to-peer transactions between Root Ports.
  4262. * Allow each Root Port to be in a separate IOMMU group by masking
  4263. * SV/RR/CR/UF bits.
  4264. */
  4265. return pci_acs_ctrl_enabled(acs_flags,
  4266. PCI_ACS_SV | PCI_ACS_RR | PCI_ACS_CR | PCI_ACS_UF);
  4267. }
  4268. static const struct pci_dev_acs_enabled {
  4269. u16 vendor;
  4270. u16 device;
  4271. int (*acs_enabled)(struct pci_dev *dev, u16 acs_flags);
  4272. } pci_dev_acs_enabled[] = {
  4273. { PCI_VENDOR_ID_ATI, 0x4385, pci_quirk_amd_sb_acs },
  4274. { PCI_VENDOR_ID_ATI, 0x439c, pci_quirk_amd_sb_acs },
  4275. { PCI_VENDOR_ID_ATI, 0x4383, pci_quirk_amd_sb_acs },
  4276. { PCI_VENDOR_ID_ATI, 0x439d, pci_quirk_amd_sb_acs },
  4277. { PCI_VENDOR_ID_ATI, 0x4384, pci_quirk_amd_sb_acs },
  4278. { PCI_VENDOR_ID_ATI, 0x4399, pci_quirk_amd_sb_acs },
  4279. { PCI_VENDOR_ID_AMD, 0x780f, pci_quirk_amd_sb_acs },
  4280. { PCI_VENDOR_ID_AMD, 0x7809, pci_quirk_amd_sb_acs },
  4281. { PCI_VENDOR_ID_SOLARFLARE, 0x0903, pci_quirk_mf_endpoint_acs },
  4282. { PCI_VENDOR_ID_SOLARFLARE, 0x0923, pci_quirk_mf_endpoint_acs },
  4283. { PCI_VENDOR_ID_SOLARFLARE, 0x0A03, pci_quirk_mf_endpoint_acs },
  4284. { PCI_VENDOR_ID_INTEL, 0x10C6, pci_quirk_mf_endpoint_acs },
  4285. { PCI_VENDOR_ID_INTEL, 0x10DB, pci_quirk_mf_endpoint_acs },
  4286. { PCI_VENDOR_ID_INTEL, 0x10DD, pci_quirk_mf_endpoint_acs },
  4287. { PCI_VENDOR_ID_INTEL, 0x10E1, pci_quirk_mf_endpoint_acs },
  4288. { PCI_VENDOR_ID_INTEL, 0x10F1, pci_quirk_mf_endpoint_acs },
  4289. { PCI_VENDOR_ID_INTEL, 0x10F7, pci_quirk_mf_endpoint_acs },
  4290. { PCI_VENDOR_ID_INTEL, 0x10F8, pci_quirk_mf_endpoint_acs },
  4291. { PCI_VENDOR_ID_INTEL, 0x10F9, pci_quirk_mf_endpoint_acs },
  4292. { PCI_VENDOR_ID_INTEL, 0x10FA, pci_quirk_mf_endpoint_acs },
  4293. { PCI_VENDOR_ID_INTEL, 0x10FB, pci_quirk_mf_endpoint_acs },
  4294. { PCI_VENDOR_ID_INTEL, 0x10FC, pci_quirk_mf_endpoint_acs },
  4295. { PCI_VENDOR_ID_INTEL, 0x1507, pci_quirk_mf_endpoint_acs },
  4296. { PCI_VENDOR_ID_INTEL, 0x1514, pci_quirk_mf_endpoint_acs },
  4297. { PCI_VENDOR_ID_INTEL, 0x151C, pci_quirk_mf_endpoint_acs },
  4298. { PCI_VENDOR_ID_INTEL, 0x1529, pci_quirk_mf_endpoint_acs },
  4299. { PCI_VENDOR_ID_INTEL, 0x152A, pci_quirk_mf_endpoint_acs },
  4300. { PCI_VENDOR_ID_INTEL, 0x154D, pci_quirk_mf_endpoint_acs },
  4301. { PCI_VENDOR_ID_INTEL, 0x154F, pci_quirk_mf_endpoint_acs },
  4302. { PCI_VENDOR_ID_INTEL, 0x1551, pci_quirk_mf_endpoint_acs },
  4303. { PCI_VENDOR_ID_INTEL, 0x1558, pci_quirk_mf_endpoint_acs },
  4304. /* 82580 */
  4305. { PCI_VENDOR_ID_INTEL, 0x1509, pci_quirk_mf_endpoint_acs },
  4306. { PCI_VENDOR_ID_INTEL, 0x150E, pci_quirk_mf_endpoint_acs },
  4307. { PCI_VENDOR_ID_INTEL, 0x150F, pci_quirk_mf_endpoint_acs },
  4308. { PCI_VENDOR_ID_INTEL, 0x1510, pci_quirk_mf_endpoint_acs },
  4309. { PCI_VENDOR_ID_INTEL, 0x1511, pci_quirk_mf_endpoint_acs },
  4310. { PCI_VENDOR_ID_INTEL, 0x1516, pci_quirk_mf_endpoint_acs },
  4311. { PCI_VENDOR_ID_INTEL, 0x1527, pci_quirk_mf_endpoint_acs },
  4312. /* 82576 */
  4313. { PCI_VENDOR_ID_INTEL, 0x10C9, pci_quirk_mf_endpoint_acs },
  4314. { PCI_VENDOR_ID_INTEL, 0x10E6, pci_quirk_mf_endpoint_acs },
  4315. { PCI_VENDOR_ID_INTEL, 0x10E7, pci_quirk_mf_endpoint_acs },
  4316. { PCI_VENDOR_ID_INTEL, 0x10E8, pci_quirk_mf_endpoint_acs },
  4317. { PCI_VENDOR_ID_INTEL, 0x150A, pci_quirk_mf_endpoint_acs },
  4318. { PCI_VENDOR_ID_INTEL, 0x150D, pci_quirk_mf_endpoint_acs },
  4319. { PCI_VENDOR_ID_INTEL, 0x1518, pci_quirk_mf_endpoint_acs },
  4320. { PCI_VENDOR_ID_INTEL, 0x1526, pci_quirk_mf_endpoint_acs },
  4321. /* 82575 */
  4322. { PCI_VENDOR_ID_INTEL, 0x10A7, pci_quirk_mf_endpoint_acs },
  4323. { PCI_VENDOR_ID_INTEL, 0x10A9, pci_quirk_mf_endpoint_acs },
  4324. { PCI_VENDOR_ID_INTEL, 0x10D6, pci_quirk_mf_endpoint_acs },
  4325. /* I350 */
  4326. { PCI_VENDOR_ID_INTEL, 0x1521, pci_quirk_mf_endpoint_acs },
  4327. { PCI_VENDOR_ID_INTEL, 0x1522, pci_quirk_mf_endpoint_acs },
  4328. { PCI_VENDOR_ID_INTEL, 0x1523, pci_quirk_mf_endpoint_acs },
  4329. { PCI_VENDOR_ID_INTEL, 0x1524, pci_quirk_mf_endpoint_acs },
  4330. /* 82571 (Quads omitted due to non-ACS switch) */
  4331. { PCI_VENDOR_ID_INTEL, 0x105E, pci_quirk_mf_endpoint_acs },
  4332. { PCI_VENDOR_ID_INTEL, 0x105F, pci_quirk_mf_endpoint_acs },
  4333. { PCI_VENDOR_ID_INTEL, 0x1060, pci_quirk_mf_endpoint_acs },
  4334. { PCI_VENDOR_ID_INTEL, 0x10D9, pci_quirk_mf_endpoint_acs },
  4335. /* I219 */
  4336. { PCI_VENDOR_ID_INTEL, 0x15b7, pci_quirk_mf_endpoint_acs },
  4337. { PCI_VENDOR_ID_INTEL, 0x15b8, pci_quirk_mf_endpoint_acs },
  4338. { PCI_VENDOR_ID_INTEL, PCI_ANY_ID, pci_quirk_rciep_acs },
  4339. /* QCOM QDF2xxx root ports */
  4340. { PCI_VENDOR_ID_QCOM, 0x0400, pci_quirk_qcom_rp_acs },
  4341. { PCI_VENDOR_ID_QCOM, 0x0401, pci_quirk_qcom_rp_acs },
  4342. /* HXT SD4800 root ports. The ACS design is same as QCOM QDF2xxx */
  4343. { PCI_VENDOR_ID_HXT, 0x0401, pci_quirk_qcom_rp_acs },
  4344. /* Intel PCH root ports */
  4345. { PCI_VENDOR_ID_INTEL, PCI_ANY_ID, pci_quirk_intel_pch_acs },
  4346. { PCI_VENDOR_ID_INTEL, PCI_ANY_ID, pci_quirk_intel_spt_pch_acs },
  4347. { 0x19a2, 0x710, pci_quirk_mf_endpoint_acs }, /* Emulex BE3-R */
  4348. { 0x10df, 0x720, pci_quirk_mf_endpoint_acs }, /* Emulex Skyhawk-R */
  4349. /* Cavium ThunderX */
  4350. { PCI_VENDOR_ID_CAVIUM, PCI_ANY_ID, pci_quirk_cavium_acs },
  4351. /* Cavium multi-function devices */
  4352. { PCI_VENDOR_ID_CAVIUM, 0xA026, pci_quirk_mf_endpoint_acs },
  4353. { PCI_VENDOR_ID_CAVIUM, 0xA059, pci_quirk_mf_endpoint_acs },
  4354. { PCI_VENDOR_ID_CAVIUM, 0xA060, pci_quirk_mf_endpoint_acs },
  4355. /* APM X-Gene */
  4356. { PCI_VENDOR_ID_AMCC, 0xE004, pci_quirk_xgene_acs },
  4357. /* Ampere Computing */
  4358. { PCI_VENDOR_ID_AMPERE, 0xE005, pci_quirk_xgene_acs },
  4359. { PCI_VENDOR_ID_AMPERE, 0xE006, pci_quirk_xgene_acs },
  4360. { PCI_VENDOR_ID_AMPERE, 0xE007, pci_quirk_xgene_acs },
  4361. { PCI_VENDOR_ID_AMPERE, 0xE008, pci_quirk_xgene_acs },
  4362. { PCI_VENDOR_ID_AMPERE, 0xE009, pci_quirk_xgene_acs },
  4363. { PCI_VENDOR_ID_AMPERE, 0xE00A, pci_quirk_xgene_acs },
  4364. { PCI_VENDOR_ID_AMPERE, 0xE00B, pci_quirk_xgene_acs },
  4365. { PCI_VENDOR_ID_AMPERE, 0xE00C, pci_quirk_xgene_acs },
  4366. /* Broadcom multi-function device */
  4367. { PCI_VENDOR_ID_BROADCOM, 0x16D7, pci_quirk_mf_endpoint_acs },
  4368. { PCI_VENDOR_ID_BROADCOM, 0xD714, pci_quirk_brcm_acs },
  4369. /* Amazon Annapurna Labs */
  4370. { PCI_VENDOR_ID_AMAZON_ANNAPURNA_LABS, 0x0031, pci_quirk_al_acs },
  4371. /* Zhaoxin multi-function devices */
  4372. { PCI_VENDOR_ID_ZHAOXIN, 0x3038, pci_quirk_mf_endpoint_acs },
  4373. { PCI_VENDOR_ID_ZHAOXIN, 0x3104, pci_quirk_mf_endpoint_acs },
  4374. { PCI_VENDOR_ID_ZHAOXIN, 0x9083, pci_quirk_mf_endpoint_acs },
  4375. /* NXP root ports, xx=16, 12, or 08 cores */
  4376. /* LX2xx0A : without security features + CAN-FD */
  4377. { PCI_VENDOR_ID_NXP, 0x8d81, pci_quirk_nxp_rp_acs },
  4378. { PCI_VENDOR_ID_NXP, 0x8da1, pci_quirk_nxp_rp_acs },
  4379. { PCI_VENDOR_ID_NXP, 0x8d83, pci_quirk_nxp_rp_acs },
  4380. /* LX2xx0C : security features + CAN-FD */
  4381. { PCI_VENDOR_ID_NXP, 0x8d80, pci_quirk_nxp_rp_acs },
  4382. { PCI_VENDOR_ID_NXP, 0x8da0, pci_quirk_nxp_rp_acs },
  4383. { PCI_VENDOR_ID_NXP, 0x8d82, pci_quirk_nxp_rp_acs },
  4384. /* LX2xx0E : security features + CAN */
  4385. { PCI_VENDOR_ID_NXP, 0x8d90, pci_quirk_nxp_rp_acs },
  4386. { PCI_VENDOR_ID_NXP, 0x8db0, pci_quirk_nxp_rp_acs },
  4387. { PCI_VENDOR_ID_NXP, 0x8d92, pci_quirk_nxp_rp_acs },
  4388. /* LX2xx0N : without security features + CAN */
  4389. { PCI_VENDOR_ID_NXP, 0x8d91, pci_quirk_nxp_rp_acs },
  4390. { PCI_VENDOR_ID_NXP, 0x8db1, pci_quirk_nxp_rp_acs },
  4391. { PCI_VENDOR_ID_NXP, 0x8d93, pci_quirk_nxp_rp_acs },
  4392. /* LX2xx2A : without security features + CAN-FD */
  4393. { PCI_VENDOR_ID_NXP, 0x8d89, pci_quirk_nxp_rp_acs },
  4394. { PCI_VENDOR_ID_NXP, 0x8da9, pci_quirk_nxp_rp_acs },
  4395. { PCI_VENDOR_ID_NXP, 0x8d8b, pci_quirk_nxp_rp_acs },
  4396. /* LX2xx2C : security features + CAN-FD */
  4397. { PCI_VENDOR_ID_NXP, 0x8d88, pci_quirk_nxp_rp_acs },
  4398. { PCI_VENDOR_ID_NXP, 0x8da8, pci_quirk_nxp_rp_acs },
  4399. { PCI_VENDOR_ID_NXP, 0x8d8a, pci_quirk_nxp_rp_acs },
  4400. /* LX2xx2E : security features + CAN */
  4401. { PCI_VENDOR_ID_NXP, 0x8d98, pci_quirk_nxp_rp_acs },
  4402. { PCI_VENDOR_ID_NXP, 0x8db8, pci_quirk_nxp_rp_acs },
  4403. { PCI_VENDOR_ID_NXP, 0x8d9a, pci_quirk_nxp_rp_acs },
  4404. /* LX2xx2N : without security features + CAN */
  4405. { PCI_VENDOR_ID_NXP, 0x8d99, pci_quirk_nxp_rp_acs },
  4406. { PCI_VENDOR_ID_NXP, 0x8db9, pci_quirk_nxp_rp_acs },
  4407. { PCI_VENDOR_ID_NXP, 0x8d9b, pci_quirk_nxp_rp_acs },
  4408. /* Zhaoxin Root/Downstream Ports */
  4409. { PCI_VENDOR_ID_ZHAOXIN, PCI_ANY_ID, pci_quirk_zhaoxin_pcie_ports_acs },
  4410. { 0 }
  4411. };
  4412. /*
  4413. * pci_dev_specific_acs_enabled - check whether device provides ACS controls
  4414. * @dev: PCI device
  4415. * @acs_flags: Bitmask of desired ACS controls
  4416. *
  4417. * Returns:
  4418. * -ENOTTY: No quirk applies to this device; we can't tell whether the
  4419. * device provides the desired controls
  4420. * 0: Device does not provide all the desired controls
  4421. * >0: Device provides all the controls in @acs_flags
  4422. */
  4423. int pci_dev_specific_acs_enabled(struct pci_dev *dev, u16 acs_flags)
  4424. {
  4425. const struct pci_dev_acs_enabled *i;
  4426. int ret;
  4427. /*
  4428. * Allow devices that do not expose standard PCIe ACS capabilities
  4429. * or control to indicate their support here. Multi-function express
  4430. * devices which do not allow internal peer-to-peer between functions,
  4431. * but do not implement PCIe ACS may wish to return true here.
  4432. */
  4433. for (i = pci_dev_acs_enabled; i->acs_enabled; i++) {
  4434. if ((i->vendor == dev->vendor ||
  4435. i->vendor == (u16)PCI_ANY_ID) &&
  4436. (i->device == dev->device ||
  4437. i->device == (u16)PCI_ANY_ID)) {
  4438. ret = i->acs_enabled(dev, acs_flags);
  4439. if (ret >= 0)
  4440. return ret;
  4441. }
  4442. }
  4443. return -ENOTTY;
  4444. }
  4445. /* Config space offset of Root Complex Base Address register */
  4446. #define INTEL_LPC_RCBA_REG 0xf0
  4447. /* 31:14 RCBA address */
  4448. #define INTEL_LPC_RCBA_MASK 0xffffc000
  4449. /* RCBA Enable */
  4450. #define INTEL_LPC_RCBA_ENABLE (1 << 0)
  4451. /* Backbone Scratch Pad Register */
  4452. #define INTEL_BSPR_REG 0x1104
  4453. /* Backbone Peer Non-Posted Disable */
  4454. #define INTEL_BSPR_REG_BPNPD (1 << 8)
  4455. /* Backbone Peer Posted Disable */
  4456. #define INTEL_BSPR_REG_BPPD (1 << 9)
  4457. /* Upstream Peer Decode Configuration Register */
  4458. #define INTEL_UPDCR_REG 0x1014
  4459. /* 5:0 Peer Decode Enable bits */
  4460. #define INTEL_UPDCR_REG_MASK 0x3f
  4461. static int pci_quirk_enable_intel_lpc_acs(struct pci_dev *dev)
  4462. {
  4463. u32 rcba, bspr, updcr;
  4464. void __iomem *rcba_mem;
  4465. /*
  4466. * Read the RCBA register from the LPC (D31:F0). PCH root ports
  4467. * are D28:F* and therefore get probed before LPC, thus we can't
  4468. * use pci_get_slot()/pci_read_config_dword() here.
  4469. */
  4470. pci_bus_read_config_dword(dev->bus, PCI_DEVFN(31, 0),
  4471. INTEL_LPC_RCBA_REG, &rcba);
  4472. if (!(rcba & INTEL_LPC_RCBA_ENABLE))
  4473. return -EINVAL;
  4474. rcba_mem = ioremap(rcba & INTEL_LPC_RCBA_MASK,
  4475. PAGE_ALIGN(INTEL_UPDCR_REG));
  4476. if (!rcba_mem)
  4477. return -ENOMEM;
  4478. /*
  4479. * The BSPR can disallow peer cycles, but it's set by soft strap and
  4480. * therefore read-only. If both posted and non-posted peer cycles are
  4481. * disallowed, we're ok. If either are allowed, then we need to use
  4482. * the UPDCR to disable peer decodes for each port. This provides the
  4483. * PCIe ACS equivalent of PCI_ACS_RR | PCI_ACS_CR | PCI_ACS_UF
  4484. */
  4485. bspr = readl(rcba_mem + INTEL_BSPR_REG);
  4486. bspr &= INTEL_BSPR_REG_BPNPD | INTEL_BSPR_REG_BPPD;
  4487. if (bspr != (INTEL_BSPR_REG_BPNPD | INTEL_BSPR_REG_BPPD)) {
  4488. updcr = readl(rcba_mem + INTEL_UPDCR_REG);
  4489. if (updcr & INTEL_UPDCR_REG_MASK) {
  4490. pci_info(dev, "Disabling UPDCR peer decodes\n");
  4491. updcr &= ~INTEL_UPDCR_REG_MASK;
  4492. writel(updcr, rcba_mem + INTEL_UPDCR_REG);
  4493. }
  4494. }
  4495. iounmap(rcba_mem);
  4496. return 0;
  4497. }
  4498. /* Miscellaneous Port Configuration register */
  4499. #define INTEL_MPC_REG 0xd8
  4500. /* MPC: Invalid Receive Bus Number Check Enable */
  4501. #define INTEL_MPC_REG_IRBNCE (1 << 26)
  4502. static void pci_quirk_enable_intel_rp_mpc_acs(struct pci_dev *dev)
  4503. {
  4504. u32 mpc;
  4505. /*
  4506. * When enabled, the IRBNCE bit of the MPC register enables the
  4507. * equivalent of PCI ACS Source Validation (PCI_ACS_SV), which
  4508. * ensures that requester IDs fall within the bus number range
  4509. * of the bridge. Enable if not already.
  4510. */
  4511. pci_read_config_dword(dev, INTEL_MPC_REG, &mpc);
  4512. if (!(mpc & INTEL_MPC_REG_IRBNCE)) {
  4513. pci_info(dev, "Enabling MPC IRBNCE\n");
  4514. mpc |= INTEL_MPC_REG_IRBNCE;
  4515. pci_write_config_word(dev, INTEL_MPC_REG, mpc);
  4516. }
  4517. }
  4518. /*
  4519. * Currently this quirk does the equivalent of
  4520. * PCI_ACS_SV | PCI_ACS_RR | PCI_ACS_CR | PCI_ACS_UF
  4521. *
  4522. * TODO: This quirk also needs to do equivalent of PCI_ACS_TB,
  4523. * if dev->external_facing || dev->untrusted
  4524. */
  4525. static int pci_quirk_enable_intel_pch_acs(struct pci_dev *dev)
  4526. {
  4527. if (!pci_quirk_intel_pch_acs_match(dev))
  4528. return -ENOTTY;
  4529. if (pci_quirk_enable_intel_lpc_acs(dev)) {
  4530. pci_warn(dev, "Failed to enable Intel PCH ACS quirk\n");
  4531. return 0;
  4532. }
  4533. pci_quirk_enable_intel_rp_mpc_acs(dev);
  4534. dev->dev_flags |= PCI_DEV_FLAGS_ACS_ENABLED_QUIRK;
  4535. pci_info(dev, "Intel PCH root port ACS workaround enabled\n");
  4536. return 0;
  4537. }
  4538. static int pci_quirk_enable_intel_spt_pch_acs(struct pci_dev *dev)
  4539. {
  4540. int pos;
  4541. u32 cap, ctrl;
  4542. if (!pci_quirk_intel_spt_pch_acs_match(dev))
  4543. return -ENOTTY;
  4544. pos = dev->acs_cap;
  4545. if (!pos)
  4546. return -ENOTTY;
  4547. pci_read_config_dword(dev, pos + PCI_ACS_CAP, &cap);
  4548. pci_read_config_dword(dev, pos + INTEL_SPT_ACS_CTRL, &ctrl);
  4549. ctrl |= (cap & PCI_ACS_SV);
  4550. ctrl |= (cap & PCI_ACS_RR);
  4551. ctrl |= (cap & PCI_ACS_CR);
  4552. ctrl |= (cap & PCI_ACS_UF);
  4553. if (dev->external_facing || dev->untrusted)
  4554. ctrl |= (cap & PCI_ACS_TB);
  4555. pci_write_config_dword(dev, pos + INTEL_SPT_ACS_CTRL, ctrl);
  4556. pci_info(dev, "Intel SPT PCH root port ACS workaround enabled\n");
  4557. return 0;
  4558. }
  4559. static int pci_quirk_disable_intel_spt_pch_acs_redir(struct pci_dev *dev)
  4560. {
  4561. int pos;
  4562. u32 cap, ctrl;
  4563. if (!pci_quirk_intel_spt_pch_acs_match(dev))
  4564. return -ENOTTY;
  4565. pos = dev->acs_cap;
  4566. if (!pos)
  4567. return -ENOTTY;
  4568. pci_read_config_dword(dev, pos + PCI_ACS_CAP, &cap);
  4569. pci_read_config_dword(dev, pos + INTEL_SPT_ACS_CTRL, &ctrl);
  4570. ctrl &= ~(PCI_ACS_RR | PCI_ACS_CR | PCI_ACS_EC);
  4571. pci_write_config_dword(dev, pos + INTEL_SPT_ACS_CTRL, ctrl);
  4572. pci_info(dev, "Intel SPT PCH root port workaround: disabled ACS redirect\n");
  4573. return 0;
  4574. }
  4575. static const struct pci_dev_acs_ops {
  4576. u16 vendor;
  4577. u16 device;
  4578. int (*enable_acs)(struct pci_dev *dev);
  4579. int (*disable_acs_redir)(struct pci_dev *dev);
  4580. } pci_dev_acs_ops[] = {
  4581. { PCI_VENDOR_ID_INTEL, PCI_ANY_ID,
  4582. .enable_acs = pci_quirk_enable_intel_pch_acs,
  4583. },
  4584. { PCI_VENDOR_ID_INTEL, PCI_ANY_ID,
  4585. .enable_acs = pci_quirk_enable_intel_spt_pch_acs,
  4586. .disable_acs_redir = pci_quirk_disable_intel_spt_pch_acs_redir,
  4587. },
  4588. };
  4589. int pci_dev_specific_enable_acs(struct pci_dev *dev)
  4590. {
  4591. const struct pci_dev_acs_ops *p;
  4592. int i, ret;
  4593. for (i = 0; i < ARRAY_SIZE(pci_dev_acs_ops); i++) {
  4594. p = &pci_dev_acs_ops[i];
  4595. if ((p->vendor == dev->vendor ||
  4596. p->vendor == (u16)PCI_ANY_ID) &&
  4597. (p->device == dev->device ||
  4598. p->device == (u16)PCI_ANY_ID) &&
  4599. p->enable_acs) {
  4600. ret = p->enable_acs(dev);
  4601. if (ret >= 0)
  4602. return ret;
  4603. }
  4604. }
  4605. return -ENOTTY;
  4606. }
  4607. int pci_dev_specific_disable_acs_redir(struct pci_dev *dev)
  4608. {
  4609. const struct pci_dev_acs_ops *p;
  4610. int i, ret;
  4611. for (i = 0; i < ARRAY_SIZE(pci_dev_acs_ops); i++) {
  4612. p = &pci_dev_acs_ops[i];
  4613. if ((p->vendor == dev->vendor ||
  4614. p->vendor == (u16)PCI_ANY_ID) &&
  4615. (p->device == dev->device ||
  4616. p->device == (u16)PCI_ANY_ID) &&
  4617. p->disable_acs_redir) {
  4618. ret = p->disable_acs_redir(dev);
  4619. if (ret >= 0)
  4620. return ret;
  4621. }
  4622. }
  4623. return -ENOTTY;
  4624. }
  4625. /*
  4626. * The PCI capabilities list for Intel DH895xCC VFs (device ID 0x0443) with
  4627. * QuickAssist Technology (QAT) is prematurely terminated in hardware. The
  4628. * Next Capability pointer in the MSI Capability Structure should point to
  4629. * the PCIe Capability Structure but is incorrectly hardwired as 0 terminating
  4630. * the list.
  4631. */
  4632. static void quirk_intel_qat_vf_cap(struct pci_dev *pdev)
  4633. {
  4634. int pos, i = 0;
  4635. u8 next_cap;
  4636. u16 reg16, *cap;
  4637. struct pci_cap_saved_state *state;
  4638. /* Bail if the hardware bug is fixed */
  4639. if (pdev->pcie_cap || pci_find_capability(pdev, PCI_CAP_ID_EXP))
  4640. return;
  4641. /* Bail if MSI Capability Structure is not found for some reason */
  4642. pos = pci_find_capability(pdev, PCI_CAP_ID_MSI);
  4643. if (!pos)
  4644. return;
  4645. /*
  4646. * Bail if Next Capability pointer in the MSI Capability Structure
  4647. * is not the expected incorrect 0x00.
  4648. */
  4649. pci_read_config_byte(pdev, pos + 1, &next_cap);
  4650. if (next_cap)
  4651. return;
  4652. /*
  4653. * PCIe Capability Structure is expected to be at 0x50 and should
  4654. * terminate the list (Next Capability pointer is 0x00). Verify
  4655. * Capability Id and Next Capability pointer is as expected.
  4656. * Open-code some of set_pcie_port_type() and pci_cfg_space_size_ext()
  4657. * to correctly set kernel data structures which have already been
  4658. * set incorrectly due to the hardware bug.
  4659. */
  4660. pos = 0x50;
  4661. pci_read_config_word(pdev, pos, &reg16);
  4662. if (reg16 == (0x0000 | PCI_CAP_ID_EXP)) {
  4663. u32 status;
  4664. #ifndef PCI_EXP_SAVE_REGS
  4665. #define PCI_EXP_SAVE_REGS 7
  4666. #endif
  4667. int size = PCI_EXP_SAVE_REGS * sizeof(u16);
  4668. pdev->pcie_cap = pos;
  4669. pci_read_config_word(pdev, pos + PCI_EXP_FLAGS, &reg16);
  4670. pdev->pcie_flags_reg = reg16;
  4671. pci_read_config_word(pdev, pos + PCI_EXP_DEVCAP, &reg16);
  4672. pdev->pcie_mpss = reg16 & PCI_EXP_DEVCAP_PAYLOAD;
  4673. pdev->cfg_size = PCI_CFG_SPACE_EXP_SIZE;
  4674. if (pci_read_config_dword(pdev, PCI_CFG_SPACE_SIZE, &status) !=
  4675. PCIBIOS_SUCCESSFUL || (status == 0xffffffff))
  4676. pdev->cfg_size = PCI_CFG_SPACE_SIZE;
  4677. if (pci_find_saved_cap(pdev, PCI_CAP_ID_EXP))
  4678. return;
  4679. /* Save PCIe cap */
  4680. state = kzalloc(sizeof(*state) + size, GFP_KERNEL);
  4681. if (!state)
  4682. return;
  4683. state->cap.cap_nr = PCI_CAP_ID_EXP;
  4684. state->cap.cap_extended = 0;
  4685. state->cap.size = size;
  4686. cap = (u16 *)&state->cap.data[0];
  4687. pcie_capability_read_word(pdev, PCI_EXP_DEVCTL, &cap[i++]);
  4688. pcie_capability_read_word(pdev, PCI_EXP_LNKCTL, &cap[i++]);
  4689. pcie_capability_read_word(pdev, PCI_EXP_SLTCTL, &cap[i++]);
  4690. pcie_capability_read_word(pdev, PCI_EXP_RTCTL, &cap[i++]);
  4691. pcie_capability_read_word(pdev, PCI_EXP_DEVCTL2, &cap[i++]);
  4692. pcie_capability_read_word(pdev, PCI_EXP_LNKCTL2, &cap[i++]);
  4693. pcie_capability_read_word(pdev, PCI_EXP_SLTCTL2, &cap[i++]);
  4694. hlist_add_head(&state->next, &pdev->saved_cap_space);
  4695. }
  4696. }
  4697. DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL, 0x443, quirk_intel_qat_vf_cap);
  4698. /*
  4699. * FLR may cause the following to devices to hang:
  4700. *
  4701. * AMD Starship/Matisse HD Audio Controller 0x1487
  4702. * AMD Starship USB 3.0 Host Controller 0x148c
  4703. * AMD Matisse USB 3.0 Host Controller 0x149c
  4704. * Intel 82579LM Gigabit Ethernet Controller 0x1502
  4705. * Intel 82579V Gigabit Ethernet Controller 0x1503
  4706. *
  4707. */
  4708. static void quirk_no_flr(struct pci_dev *dev)
  4709. {
  4710. dev->dev_flags |= PCI_DEV_FLAGS_NO_FLR_RESET;
  4711. }
  4712. DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_AMD, 0x1487, quirk_no_flr);
  4713. DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_AMD, 0x148c, quirk_no_flr);
  4714. DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_AMD, 0x149c, quirk_no_flr);
  4715. DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL, 0x1502, quirk_no_flr);
  4716. DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL, 0x1503, quirk_no_flr);
  4717. static void quirk_no_ext_tags(struct pci_dev *pdev)
  4718. {
  4719. struct pci_host_bridge *bridge = pci_find_host_bridge(pdev->bus);
  4720. if (!bridge)
  4721. return;
  4722. bridge->no_ext_tags = 1;
  4723. pci_info(pdev, "disabling Extended Tags (this device can't handle them)\n");
  4724. pci_walk_bus(bridge->bus, pci_configure_extended_tags, NULL);
  4725. }
  4726. DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_SERVERWORKS, 0x0132, quirk_no_ext_tags);
  4727. DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_SERVERWORKS, 0x0140, quirk_no_ext_tags);
  4728. DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_SERVERWORKS, 0x0141, quirk_no_ext_tags);
  4729. DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_SERVERWORKS, 0x0142, quirk_no_ext_tags);
  4730. DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_SERVERWORKS, 0x0144, quirk_no_ext_tags);
  4731. DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_SERVERWORKS, 0x0420, quirk_no_ext_tags);
  4732. DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_SERVERWORKS, 0x0422, quirk_no_ext_tags);
  4733. #ifdef CONFIG_PCI_ATS
  4734. /*
  4735. * Some devices require additional driver setup to enable ATS. Don't use
  4736. * ATS for those devices as ATS will be enabled before the driver has had a
  4737. * chance to load and configure the device.
  4738. */
  4739. static void quirk_amd_harvest_no_ats(struct pci_dev *pdev)
  4740. {
  4741. if ((pdev->device == 0x7312 && pdev->revision != 0x00) ||
  4742. (pdev->device == 0x7340 && pdev->revision != 0xc5) ||
  4743. (pdev->device == 0x7341 && pdev->revision != 0x00))
  4744. return;
  4745. pci_info(pdev, "disabling ATS\n");
  4746. pdev->ats_cap = 0;
  4747. }
  4748. /* AMD Stoney platform GPU */
  4749. DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0x98e4, quirk_amd_harvest_no_ats);
  4750. /* AMD Iceland dGPU */
  4751. DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0x6900, quirk_amd_harvest_no_ats);
  4752. /* AMD Navi10 dGPU */
  4753. DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0x7312, quirk_amd_harvest_no_ats);
  4754. /* AMD Navi14 dGPU */
  4755. DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0x7340, quirk_amd_harvest_no_ats);
  4756. DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0x7341, quirk_amd_harvest_no_ats);
  4757. #endif /* CONFIG_PCI_ATS */
  4758. /* Freescale PCIe doesn't support MSI in RC mode */
  4759. static void quirk_fsl_no_msi(struct pci_dev *pdev)
  4760. {
  4761. if (pci_pcie_type(pdev) == PCI_EXP_TYPE_ROOT_PORT)
  4762. pdev->no_msi = 1;
  4763. }
  4764. DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_FREESCALE, PCI_ANY_ID, quirk_fsl_no_msi);
  4765. /*
  4766. * Although not allowed by the spec, some multi-function devices have
  4767. * dependencies of one function (consumer) on another (supplier). For the
  4768. * consumer to work in D0, the supplier must also be in D0. Create a
  4769. * device link from the consumer to the supplier to enforce this
  4770. * dependency. Runtime PM is allowed by default on the consumer to prevent
  4771. * it from permanently keeping the supplier awake.
  4772. */
  4773. static void pci_create_device_link(struct pci_dev *pdev, unsigned int consumer,
  4774. unsigned int supplier, unsigned int class,
  4775. unsigned int class_shift)
  4776. {
  4777. struct pci_dev *supplier_pdev;
  4778. if (PCI_FUNC(pdev->devfn) != consumer)
  4779. return;
  4780. supplier_pdev = pci_get_domain_bus_and_slot(pci_domain_nr(pdev->bus),
  4781. pdev->bus->number,
  4782. PCI_DEVFN(PCI_SLOT(pdev->devfn), supplier));
  4783. if (!supplier_pdev || (supplier_pdev->class >> class_shift) != class) {
  4784. pci_dev_put(supplier_pdev);
  4785. return;
  4786. }
  4787. if (device_link_add(&pdev->dev, &supplier_pdev->dev,
  4788. DL_FLAG_STATELESS | DL_FLAG_PM_RUNTIME))
  4789. pci_info(pdev, "D0 power state depends on %s\n",
  4790. pci_name(supplier_pdev));
  4791. else
  4792. pci_err(pdev, "Cannot enforce power dependency on %s\n",
  4793. pci_name(supplier_pdev));
  4794. pm_runtime_allow(&pdev->dev);
  4795. pci_dev_put(supplier_pdev);
  4796. }
  4797. /*
  4798. * Create device link for GPUs with integrated HDA controller for streaming
  4799. * audio to attached displays.
  4800. */
  4801. static void quirk_gpu_hda(struct pci_dev *hda)
  4802. {
  4803. pci_create_device_link(hda, 1, 0, PCI_BASE_CLASS_DISPLAY, 16);
  4804. }
  4805. DECLARE_PCI_FIXUP_CLASS_FINAL(PCI_VENDOR_ID_ATI, PCI_ANY_ID,
  4806. PCI_CLASS_MULTIMEDIA_HD_AUDIO, 8, quirk_gpu_hda);
  4807. DECLARE_PCI_FIXUP_CLASS_FINAL(PCI_VENDOR_ID_AMD, PCI_ANY_ID,
  4808. PCI_CLASS_MULTIMEDIA_HD_AUDIO, 8, quirk_gpu_hda);
  4809. DECLARE_PCI_FIXUP_CLASS_FINAL(PCI_VENDOR_ID_NVIDIA, PCI_ANY_ID,
  4810. PCI_CLASS_MULTIMEDIA_HD_AUDIO, 8, quirk_gpu_hda);
  4811. /*
  4812. * Create device link for GPUs with integrated USB xHCI Host
  4813. * controller to VGA.
  4814. */
  4815. static void quirk_gpu_usb(struct pci_dev *usb)
  4816. {
  4817. pci_create_device_link(usb, 2, 0, PCI_BASE_CLASS_DISPLAY, 16);
  4818. }
  4819. DECLARE_PCI_FIXUP_CLASS_FINAL(PCI_VENDOR_ID_NVIDIA, PCI_ANY_ID,
  4820. PCI_CLASS_SERIAL_USB, 8, quirk_gpu_usb);
  4821. DECLARE_PCI_FIXUP_CLASS_FINAL(PCI_VENDOR_ID_ATI, PCI_ANY_ID,
  4822. PCI_CLASS_SERIAL_USB, 8, quirk_gpu_usb);
  4823. /*
  4824. * Create device link for GPUs with integrated Type-C UCSI controller
  4825. * to VGA. Currently there is no class code defined for UCSI device over PCI
  4826. * so using UNKNOWN class for now and it will be updated when UCSI
  4827. * over PCI gets a class code.
  4828. */
  4829. #define PCI_CLASS_SERIAL_UNKNOWN 0x0c80
  4830. static void quirk_gpu_usb_typec_ucsi(struct pci_dev *ucsi)
  4831. {
  4832. pci_create_device_link(ucsi, 3, 0, PCI_BASE_CLASS_DISPLAY, 16);
  4833. }
  4834. DECLARE_PCI_FIXUP_CLASS_FINAL(PCI_VENDOR_ID_NVIDIA, PCI_ANY_ID,
  4835. PCI_CLASS_SERIAL_UNKNOWN, 8,
  4836. quirk_gpu_usb_typec_ucsi);
  4837. DECLARE_PCI_FIXUP_CLASS_FINAL(PCI_VENDOR_ID_ATI, PCI_ANY_ID,
  4838. PCI_CLASS_SERIAL_UNKNOWN, 8,
  4839. quirk_gpu_usb_typec_ucsi);
  4840. /*
  4841. * Enable the NVIDIA GPU integrated HDA controller if the BIOS left it
  4842. * disabled. https://devtalk.nvidia.com/default/topic/1024022
  4843. */
  4844. static void quirk_nvidia_hda(struct pci_dev *gpu)
  4845. {
  4846. u8 hdr_type;
  4847. u32 val;
  4848. /* There was no integrated HDA controller before MCP89 */
  4849. if (gpu->device < PCI_DEVICE_ID_NVIDIA_GEFORCE_320M)
  4850. return;
  4851. /* Bit 25 at offset 0x488 enables the HDA controller */
  4852. pci_read_config_dword(gpu, 0x488, &val);
  4853. if (val & BIT(25))
  4854. return;
  4855. pci_info(gpu, "Enabling HDA controller\n");
  4856. pci_write_config_dword(gpu, 0x488, val | BIT(25));
  4857. /* The GPU becomes a multi-function device when the HDA is enabled */
  4858. pci_read_config_byte(gpu, PCI_HEADER_TYPE, &hdr_type);
  4859. gpu->multifunction = !!(hdr_type & 0x80);
  4860. }
  4861. DECLARE_PCI_FIXUP_CLASS_HEADER(PCI_VENDOR_ID_NVIDIA, PCI_ANY_ID,
  4862. PCI_BASE_CLASS_DISPLAY, 16, quirk_nvidia_hda);
  4863. DECLARE_PCI_FIXUP_CLASS_RESUME_EARLY(PCI_VENDOR_ID_NVIDIA, PCI_ANY_ID,
  4864. PCI_BASE_CLASS_DISPLAY, 16, quirk_nvidia_hda);
  4865. /*
  4866. * Some IDT switches incorrectly flag an ACS Source Validation error on
  4867. * completions for config read requests even though PCIe r4.0, sec
  4868. * 6.12.1.1, says that completions are never affected by ACS Source
  4869. * Validation. Here's the text of IDT 89H32H8G3-YC, erratum #36:
  4870. *
  4871. * Item #36 - Downstream port applies ACS Source Validation to Completions
  4872. * Section 6.12.1.1 of the PCI Express Base Specification 3.1 states that
  4873. * completions are never affected by ACS Source Validation. However,
  4874. * completions received by a downstream port of the PCIe switch from a
  4875. * device that has not yet captured a PCIe bus number are incorrectly
  4876. * dropped by ACS Source Validation by the switch downstream port.
  4877. *
  4878. * The workaround suggested by IDT is to issue a config write to the
  4879. * downstream device before issuing the first config read. This allows the
  4880. * downstream device to capture its bus and device numbers (see PCIe r4.0,
  4881. * sec 2.2.9), thus avoiding the ACS error on the completion.
  4882. *
  4883. * However, we don't know when the device is ready to accept the config
  4884. * write, so we do config reads until we receive a non-Config Request Retry
  4885. * Status, then do the config write.
  4886. *
  4887. * To avoid hitting the erratum when doing the config reads, we disable ACS
  4888. * SV around this process.
  4889. */
  4890. int pci_idt_bus_quirk(struct pci_bus *bus, int devfn, u32 *l, int timeout)
  4891. {
  4892. int pos;
  4893. u16 ctrl = 0;
  4894. bool found;
  4895. struct pci_dev *bridge = bus->self;
  4896. pos = bridge->acs_cap;
  4897. /* Disable ACS SV before initial config reads */
  4898. if (pos) {
  4899. pci_read_config_word(bridge, pos + PCI_ACS_CTRL, &ctrl);
  4900. if (ctrl & PCI_ACS_SV)
  4901. pci_write_config_word(bridge, pos + PCI_ACS_CTRL,
  4902. ctrl & ~PCI_ACS_SV);
  4903. }
  4904. found = pci_bus_generic_read_dev_vendor_id(bus, devfn, l, timeout);
  4905. /* Write Vendor ID (read-only) so the endpoint latches its bus/dev */
  4906. if (found)
  4907. pci_bus_write_config_word(bus, devfn, PCI_VENDOR_ID, 0);
  4908. /* Re-enable ACS_SV if it was previously enabled */
  4909. if (ctrl & PCI_ACS_SV)
  4910. pci_write_config_word(bridge, pos + PCI_ACS_CTRL, ctrl);
  4911. return found;
  4912. }
  4913. /*
  4914. * Microsemi Switchtec NTB uses devfn proxy IDs to move TLPs between
  4915. * NT endpoints via the internal switch fabric. These IDs replace the
  4916. * originating requestor ID TLPs which access host memory on peer NTB
  4917. * ports. Therefore, all proxy IDs must be aliased to the NTB device
  4918. * to permit access when the IOMMU is turned on.
  4919. */
  4920. static void quirk_switchtec_ntb_dma_alias(struct pci_dev *pdev)
  4921. {
  4922. void __iomem *mmio;
  4923. struct ntb_info_regs __iomem *mmio_ntb;
  4924. struct ntb_ctrl_regs __iomem *mmio_ctrl;
  4925. u64 partition_map;
  4926. u8 partition;
  4927. int pp;
  4928. if (pci_enable_device(pdev)) {
  4929. pci_err(pdev, "Cannot enable Switchtec device\n");
  4930. return;
  4931. }
  4932. mmio = pci_iomap(pdev, 0, 0);
  4933. if (mmio == NULL) {
  4934. pci_disable_device(pdev);
  4935. pci_err(pdev, "Cannot iomap Switchtec device\n");
  4936. return;
  4937. }
  4938. pci_info(pdev, "Setting Switchtec proxy ID aliases\n");
  4939. mmio_ntb = mmio + SWITCHTEC_GAS_NTB_OFFSET;
  4940. mmio_ctrl = (void __iomem *) mmio_ntb + SWITCHTEC_NTB_REG_CTRL_OFFSET;
  4941. partition = ioread8(&mmio_ntb->partition_id);
  4942. partition_map = ioread32(&mmio_ntb->ep_map);
  4943. partition_map |= ((u64) ioread32(&mmio_ntb->ep_map + 4)) << 32;
  4944. partition_map &= ~(1ULL << partition);
  4945. for (pp = 0; pp < (sizeof(partition_map) * 8); pp++) {
  4946. struct ntb_ctrl_regs __iomem *mmio_peer_ctrl;
  4947. u32 table_sz = 0;
  4948. int te;
  4949. if (!(partition_map & (1ULL << pp)))
  4950. continue;
  4951. pci_dbg(pdev, "Processing partition %d\n", pp);
  4952. mmio_peer_ctrl = &mmio_ctrl[pp];
  4953. table_sz = ioread16(&mmio_peer_ctrl->req_id_table_size);
  4954. if (!table_sz) {
  4955. pci_warn(pdev, "Partition %d table_sz 0\n", pp);
  4956. continue;
  4957. }
  4958. if (table_sz > 512) {
  4959. pci_warn(pdev,
  4960. "Invalid Switchtec partition %d table_sz %d\n",
  4961. pp, table_sz);
  4962. continue;
  4963. }
  4964. for (te = 0; te < table_sz; te++) {
  4965. u32 rid_entry;
  4966. u8 devfn;
  4967. rid_entry = ioread32(&mmio_peer_ctrl->req_id_table[te]);
  4968. devfn = (rid_entry >> 1) & 0xFF;
  4969. pci_dbg(pdev,
  4970. "Aliasing Partition %d Proxy ID %02x.%d\n",
  4971. pp, PCI_SLOT(devfn), PCI_FUNC(devfn));
  4972. pci_add_dma_alias(pdev, devfn, 1);
  4973. }
  4974. }
  4975. pci_iounmap(pdev, mmio);
  4976. pci_disable_device(pdev);
  4977. }
  4978. #define SWITCHTEC_QUIRK(vid) \
  4979. DECLARE_PCI_FIXUP_CLASS_FINAL(PCI_VENDOR_ID_MICROSEMI, vid, \
  4980. PCI_CLASS_BRIDGE_OTHER, 8, quirk_switchtec_ntb_dma_alias)
  4981. SWITCHTEC_QUIRK(0x8531); /* PFX 24xG3 */
  4982. SWITCHTEC_QUIRK(0x8532); /* PFX 32xG3 */
  4983. SWITCHTEC_QUIRK(0x8533); /* PFX 48xG3 */
  4984. SWITCHTEC_QUIRK(0x8534); /* PFX 64xG3 */
  4985. SWITCHTEC_QUIRK(0x8535); /* PFX 80xG3 */
  4986. SWITCHTEC_QUIRK(0x8536); /* PFX 96xG3 */
  4987. SWITCHTEC_QUIRK(0x8541); /* PSX 24xG3 */
  4988. SWITCHTEC_QUIRK(0x8542); /* PSX 32xG3 */
  4989. SWITCHTEC_QUIRK(0x8543); /* PSX 48xG3 */
  4990. SWITCHTEC_QUIRK(0x8544); /* PSX 64xG3 */
  4991. SWITCHTEC_QUIRK(0x8545); /* PSX 80xG3 */
  4992. SWITCHTEC_QUIRK(0x8546); /* PSX 96xG3 */
  4993. SWITCHTEC_QUIRK(0x8551); /* PAX 24XG3 */
  4994. SWITCHTEC_QUIRK(0x8552); /* PAX 32XG3 */
  4995. SWITCHTEC_QUIRK(0x8553); /* PAX 48XG3 */
  4996. SWITCHTEC_QUIRK(0x8554); /* PAX 64XG3 */
  4997. SWITCHTEC_QUIRK(0x8555); /* PAX 80XG3 */
  4998. SWITCHTEC_QUIRK(0x8556); /* PAX 96XG3 */
  4999. SWITCHTEC_QUIRK(0x8561); /* PFXL 24XG3 */
  5000. SWITCHTEC_QUIRK(0x8562); /* PFXL 32XG3 */
  5001. SWITCHTEC_QUIRK(0x8563); /* PFXL 48XG3 */
  5002. SWITCHTEC_QUIRK(0x8564); /* PFXL 64XG3 */
  5003. SWITCHTEC_QUIRK(0x8565); /* PFXL 80XG3 */
  5004. SWITCHTEC_QUIRK(0x8566); /* PFXL 96XG3 */
  5005. SWITCHTEC_QUIRK(0x8571); /* PFXI 24XG3 */
  5006. SWITCHTEC_QUIRK(0x8572); /* PFXI 32XG3 */
  5007. SWITCHTEC_QUIRK(0x8573); /* PFXI 48XG3 */
  5008. SWITCHTEC_QUIRK(0x8574); /* PFXI 64XG3 */
  5009. SWITCHTEC_QUIRK(0x8575); /* PFXI 80XG3 */
  5010. SWITCHTEC_QUIRK(0x8576); /* PFXI 96XG3 */
  5011. SWITCHTEC_QUIRK(0x4000); /* PFX 100XG4 */
  5012. SWITCHTEC_QUIRK(0x4084); /* PFX 84XG4 */
  5013. SWITCHTEC_QUIRK(0x4068); /* PFX 68XG4 */
  5014. SWITCHTEC_QUIRK(0x4052); /* PFX 52XG4 */
  5015. SWITCHTEC_QUIRK(0x4036); /* PFX 36XG4 */
  5016. SWITCHTEC_QUIRK(0x4028); /* PFX 28XG4 */
  5017. SWITCHTEC_QUIRK(0x4100); /* PSX 100XG4 */
  5018. SWITCHTEC_QUIRK(0x4184); /* PSX 84XG4 */
  5019. SWITCHTEC_QUIRK(0x4168); /* PSX 68XG4 */
  5020. SWITCHTEC_QUIRK(0x4152); /* PSX 52XG4 */
  5021. SWITCHTEC_QUIRK(0x4136); /* PSX 36XG4 */
  5022. SWITCHTEC_QUIRK(0x4128); /* PSX 28XG4 */
  5023. SWITCHTEC_QUIRK(0x4200); /* PAX 100XG4 */
  5024. SWITCHTEC_QUIRK(0x4284); /* PAX 84XG4 */
  5025. SWITCHTEC_QUIRK(0x4268); /* PAX 68XG4 */
  5026. SWITCHTEC_QUIRK(0x4252); /* PAX 52XG4 */
  5027. SWITCHTEC_QUIRK(0x4236); /* PAX 36XG4 */
  5028. SWITCHTEC_QUIRK(0x4228); /* PAX 28XG4 */
  5029. /*
  5030. * The PLX NTB uses devfn proxy IDs to move TLPs between NT endpoints.
  5031. * These IDs are used to forward responses to the originator on the other
  5032. * side of the NTB. Alias all possible IDs to the NTB to permit access when
  5033. * the IOMMU is turned on.
  5034. */
  5035. static void quirk_plx_ntb_dma_alias(struct pci_dev *pdev)
  5036. {
  5037. pci_info(pdev, "Setting PLX NTB proxy ID aliases\n");
  5038. /* PLX NTB may use all 256 devfns */
  5039. pci_add_dma_alias(pdev, 0, 256);
  5040. }
  5041. DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_PLX, 0x87b0, quirk_plx_ntb_dma_alias);
  5042. DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_PLX, 0x87b1, quirk_plx_ntb_dma_alias);
  5043. /*
  5044. * On Lenovo Thinkpad P50 SKUs with a Nvidia Quadro M1000M, the BIOS does
  5045. * not always reset the secondary Nvidia GPU between reboots if the system
  5046. * is configured to use Hybrid Graphics mode. This results in the GPU
  5047. * being left in whatever state it was in during the *previous* boot, which
  5048. * causes spurious interrupts from the GPU, which in turn causes us to
  5049. * disable the wrong IRQ and end up breaking the touchpad. Unsurprisingly,
  5050. * this also completely breaks nouveau.
  5051. *
  5052. * Luckily, it seems a simple reset of the Nvidia GPU brings it back to a
  5053. * clean state and fixes all these issues.
  5054. *
  5055. * When the machine is configured in Dedicated display mode, the issue
  5056. * doesn't occur. Fortunately the GPU advertises NoReset+ when in this
  5057. * mode, so we can detect that and avoid resetting it.
  5058. */
  5059. static void quirk_reset_lenovo_thinkpad_p50_nvgpu(struct pci_dev *pdev)
  5060. {
  5061. void __iomem *map;
  5062. int ret;
  5063. if (pdev->subsystem_vendor != PCI_VENDOR_ID_LENOVO ||
  5064. pdev->subsystem_device != 0x222e ||
  5065. !pdev->reset_fn)
  5066. return;
  5067. if (pci_enable_device_mem(pdev))
  5068. return;
  5069. /*
  5070. * Based on nvkm_device_ctor() in
  5071. * drivers/gpu/drm/nouveau/nvkm/engine/device/base.c
  5072. */
  5073. map = pci_iomap(pdev, 0, 0x23000);
  5074. if (!map) {
  5075. pci_err(pdev, "Can't map MMIO space\n");
  5076. goto out_disable;
  5077. }
  5078. /*
  5079. * Make sure the GPU looks like it's been POSTed before resetting
  5080. * it.
  5081. */
  5082. if (ioread32(map + 0x2240c) & 0x2) {
  5083. pci_info(pdev, FW_BUG "GPU left initialized by EFI, resetting\n");
  5084. ret = pci_reset_bus(pdev);
  5085. if (ret < 0)
  5086. pci_err(pdev, "Failed to reset GPU: %d\n", ret);
  5087. }
  5088. iounmap(map);
  5089. out_disable:
  5090. pci_disable_device(pdev);
  5091. }
  5092. DECLARE_PCI_FIXUP_CLASS_FINAL(PCI_VENDOR_ID_NVIDIA, 0x13b1,
  5093. PCI_CLASS_DISPLAY_VGA, 8,
  5094. quirk_reset_lenovo_thinkpad_p50_nvgpu);
  5095. /*
  5096. * Device [1b21:2142]
  5097. * When in D0, PME# doesn't get asserted when plugging USB 3.0 device.
  5098. */
  5099. static void pci_fixup_no_d0_pme(struct pci_dev *dev)
  5100. {
  5101. pci_info(dev, "PME# does not work under D0, disabling it\n");
  5102. dev->pme_support &= ~(PCI_PM_CAP_PME_D0 >> PCI_PM_CAP_PME_SHIFT);
  5103. }
  5104. DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ASMEDIA, 0x2142, pci_fixup_no_d0_pme);
  5105. /*
  5106. * Device 12d8:0x400e [OHCI] and 12d8:0x400f [EHCI]
  5107. *
  5108. * These devices advertise PME# support in all power states but don't
  5109. * reliably assert it.
  5110. *
  5111. * These devices also advertise MSI, but documentation (PI7C9X440SL.pdf)
  5112. * says "The MSI Function is not implemented on this device" in chapters
  5113. * 7.3.27, 7.3.29-7.3.31.
  5114. */
  5115. static void pci_fixup_no_msi_no_pme(struct pci_dev *dev)
  5116. {
  5117. #ifdef CONFIG_PCI_MSI
  5118. pci_info(dev, "MSI is not implemented on this device, disabling it\n");
  5119. dev->no_msi = 1;
  5120. #endif
  5121. pci_info(dev, "PME# is unreliable, disabling it\n");
  5122. dev->pme_support = 0;
  5123. }
  5124. DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_PERICOM, 0x400e, pci_fixup_no_msi_no_pme);
  5125. DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_PERICOM, 0x400f, pci_fixup_no_msi_no_pme);
  5126. static void apex_pci_fixup_class(struct pci_dev *pdev)
  5127. {
  5128. pdev->class = (PCI_CLASS_SYSTEM_OTHER << 8) | pdev->class;
  5129. }
  5130. DECLARE_PCI_FIXUP_CLASS_HEADER(0x1ac1, 0x089a,
  5131. PCI_CLASS_NOT_DEFINED, 8, apex_pci_fixup_class);
  5132. static void nvidia_ion_ahci_fixup(struct pci_dev *pdev)
  5133. {
  5134. pdev->dev_flags |= PCI_DEV_FLAGS_HAS_MSI_MASKING;
  5135. }
  5136. DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_NVIDIA, 0x0ab8, nvidia_ion_ahci_fixup);