proc.c 9.5 KB

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  1. // SPDX-License-Identifier: GPL-2.0
  2. /*
  3. * Procfs interface for the PCI bus
  4. *
  5. * Copyright (c) 1997--1999 Martin Mares <mj@ucw.cz>
  6. */
  7. #include <linux/init.h>
  8. #include <linux/pci.h>
  9. #include <linux/slab.h>
  10. #include <linux/module.h>
  11. #include <linux/proc_fs.h>
  12. #include <linux/seq_file.h>
  13. #include <linux/capability.h>
  14. #include <linux/uaccess.h>
  15. #include <linux/security.h>
  16. #include <asm/byteorder.h>
  17. #include "pci.h"
  18. static int proc_initialized; /* = 0 */
  19. static loff_t proc_bus_pci_lseek(struct file *file, loff_t off, int whence)
  20. {
  21. struct pci_dev *dev = PDE_DATA(file_inode(file));
  22. return fixed_size_llseek(file, off, whence, dev->cfg_size);
  23. }
  24. static ssize_t proc_bus_pci_read(struct file *file, char __user *buf,
  25. size_t nbytes, loff_t *ppos)
  26. {
  27. struct pci_dev *dev = PDE_DATA(file_inode(file));
  28. unsigned int pos = *ppos;
  29. unsigned int cnt, size;
  30. /*
  31. * Normal users can read only the standardized portion of the
  32. * configuration space as several chips lock up when trying to read
  33. * undefined locations (think of Intel PIIX4 as a typical example).
  34. */
  35. if (capable(CAP_SYS_ADMIN))
  36. size = dev->cfg_size;
  37. else if (dev->hdr_type == PCI_HEADER_TYPE_CARDBUS)
  38. size = 128;
  39. else
  40. size = 64;
  41. if (pos >= size)
  42. return 0;
  43. if (nbytes >= size)
  44. nbytes = size;
  45. if (pos + nbytes > size)
  46. nbytes = size - pos;
  47. cnt = nbytes;
  48. if (!access_ok(buf, cnt))
  49. return -EINVAL;
  50. pci_config_pm_runtime_get(dev);
  51. if ((pos & 1) && cnt) {
  52. unsigned char val;
  53. pci_user_read_config_byte(dev, pos, &val);
  54. __put_user(val, buf);
  55. buf++;
  56. pos++;
  57. cnt--;
  58. }
  59. if ((pos & 3) && cnt > 2) {
  60. unsigned short val;
  61. pci_user_read_config_word(dev, pos, &val);
  62. __put_user(cpu_to_le16(val), (__le16 __user *) buf);
  63. buf += 2;
  64. pos += 2;
  65. cnt -= 2;
  66. }
  67. while (cnt >= 4) {
  68. unsigned int val;
  69. pci_user_read_config_dword(dev, pos, &val);
  70. __put_user(cpu_to_le32(val), (__le32 __user *) buf);
  71. buf += 4;
  72. pos += 4;
  73. cnt -= 4;
  74. }
  75. if (cnt >= 2) {
  76. unsigned short val;
  77. pci_user_read_config_word(dev, pos, &val);
  78. __put_user(cpu_to_le16(val), (__le16 __user *) buf);
  79. buf += 2;
  80. pos += 2;
  81. cnt -= 2;
  82. }
  83. if (cnt) {
  84. unsigned char val;
  85. pci_user_read_config_byte(dev, pos, &val);
  86. __put_user(val, buf);
  87. buf++;
  88. pos++;
  89. cnt--;
  90. }
  91. pci_config_pm_runtime_put(dev);
  92. *ppos = pos;
  93. return nbytes;
  94. }
  95. static ssize_t proc_bus_pci_write(struct file *file, const char __user *buf,
  96. size_t nbytes, loff_t *ppos)
  97. {
  98. struct inode *ino = file_inode(file);
  99. struct pci_dev *dev = PDE_DATA(ino);
  100. int pos = *ppos;
  101. int size = dev->cfg_size;
  102. int cnt, ret;
  103. ret = security_locked_down(LOCKDOWN_PCI_ACCESS);
  104. if (ret)
  105. return ret;
  106. if (pos >= size)
  107. return 0;
  108. if (nbytes >= size)
  109. nbytes = size;
  110. if (pos + nbytes > size)
  111. nbytes = size - pos;
  112. cnt = nbytes;
  113. if (!access_ok(buf, cnt))
  114. return -EINVAL;
  115. pci_config_pm_runtime_get(dev);
  116. if ((pos & 1) && cnt) {
  117. unsigned char val;
  118. __get_user(val, buf);
  119. pci_user_write_config_byte(dev, pos, val);
  120. buf++;
  121. pos++;
  122. cnt--;
  123. }
  124. if ((pos & 3) && cnt > 2) {
  125. __le16 val;
  126. __get_user(val, (__le16 __user *) buf);
  127. pci_user_write_config_word(dev, pos, le16_to_cpu(val));
  128. buf += 2;
  129. pos += 2;
  130. cnt -= 2;
  131. }
  132. while (cnt >= 4) {
  133. __le32 val;
  134. __get_user(val, (__le32 __user *) buf);
  135. pci_user_write_config_dword(dev, pos, le32_to_cpu(val));
  136. buf += 4;
  137. pos += 4;
  138. cnt -= 4;
  139. }
  140. if (cnt >= 2) {
  141. __le16 val;
  142. __get_user(val, (__le16 __user *) buf);
  143. pci_user_write_config_word(dev, pos, le16_to_cpu(val));
  144. buf += 2;
  145. pos += 2;
  146. cnt -= 2;
  147. }
  148. if (cnt) {
  149. unsigned char val;
  150. __get_user(val, buf);
  151. pci_user_write_config_byte(dev, pos, val);
  152. buf++;
  153. pos++;
  154. cnt--;
  155. }
  156. pci_config_pm_runtime_put(dev);
  157. *ppos = pos;
  158. i_size_write(ino, dev->cfg_size);
  159. return nbytes;
  160. }
  161. struct pci_filp_private {
  162. enum pci_mmap_state mmap_state;
  163. int write_combine;
  164. };
  165. static long proc_bus_pci_ioctl(struct file *file, unsigned int cmd,
  166. unsigned long arg)
  167. {
  168. struct pci_dev *dev = PDE_DATA(file_inode(file));
  169. #ifdef HAVE_PCI_MMAP
  170. struct pci_filp_private *fpriv = file->private_data;
  171. #endif /* HAVE_PCI_MMAP */
  172. int ret = 0;
  173. ret = security_locked_down(LOCKDOWN_PCI_ACCESS);
  174. if (ret)
  175. return ret;
  176. switch (cmd) {
  177. case PCIIOC_CONTROLLER:
  178. ret = pci_domain_nr(dev->bus);
  179. break;
  180. #ifdef HAVE_PCI_MMAP
  181. case PCIIOC_MMAP_IS_IO:
  182. if (!arch_can_pci_mmap_io())
  183. return -EINVAL;
  184. fpriv->mmap_state = pci_mmap_io;
  185. break;
  186. case PCIIOC_MMAP_IS_MEM:
  187. fpriv->mmap_state = pci_mmap_mem;
  188. break;
  189. case PCIIOC_WRITE_COMBINE:
  190. if (arch_can_pci_mmap_wc()) {
  191. if (arg)
  192. fpriv->write_combine = 1;
  193. else
  194. fpriv->write_combine = 0;
  195. break;
  196. }
  197. /* If arch decided it can't, fall through... */
  198. #endif /* HAVE_PCI_MMAP */
  199. fallthrough;
  200. default:
  201. ret = -EINVAL;
  202. break;
  203. }
  204. return ret;
  205. }
  206. #ifdef HAVE_PCI_MMAP
  207. static int proc_bus_pci_mmap(struct file *file, struct vm_area_struct *vma)
  208. {
  209. struct pci_dev *dev = PDE_DATA(file_inode(file));
  210. struct pci_filp_private *fpriv = file->private_data;
  211. int i, ret, write_combine = 0, res_bit = IORESOURCE_MEM;
  212. if (!capable(CAP_SYS_RAWIO) ||
  213. security_locked_down(LOCKDOWN_PCI_ACCESS))
  214. return -EPERM;
  215. if (fpriv->mmap_state == pci_mmap_io) {
  216. if (!arch_can_pci_mmap_io())
  217. return -EINVAL;
  218. res_bit = IORESOURCE_IO;
  219. }
  220. /* Make sure the caller is mapping a real resource for this device */
  221. for (i = 0; i < PCI_STD_NUM_BARS; i++) {
  222. if (dev->resource[i].flags & res_bit &&
  223. pci_mmap_fits(dev, i, vma, PCI_MMAP_PROCFS))
  224. break;
  225. }
  226. if (i >= PCI_STD_NUM_BARS)
  227. return -ENODEV;
  228. if (fpriv->mmap_state == pci_mmap_mem &&
  229. fpriv->write_combine) {
  230. if (dev->resource[i].flags & IORESOURCE_PREFETCH)
  231. write_combine = 1;
  232. else
  233. return -EINVAL;
  234. }
  235. ret = pci_mmap_page_range(dev, i, vma,
  236. fpriv->mmap_state, write_combine);
  237. if (ret < 0)
  238. return ret;
  239. return 0;
  240. }
  241. static int proc_bus_pci_open(struct inode *inode, struct file *file)
  242. {
  243. struct pci_filp_private *fpriv = kmalloc(sizeof(*fpriv), GFP_KERNEL);
  244. if (!fpriv)
  245. return -ENOMEM;
  246. fpriv->mmap_state = pci_mmap_io;
  247. fpriv->write_combine = 0;
  248. file->private_data = fpriv;
  249. return 0;
  250. }
  251. static int proc_bus_pci_release(struct inode *inode, struct file *file)
  252. {
  253. kfree(file->private_data);
  254. file->private_data = NULL;
  255. return 0;
  256. }
  257. #endif /* HAVE_PCI_MMAP */
  258. static const struct proc_ops proc_bus_pci_ops = {
  259. .proc_lseek = proc_bus_pci_lseek,
  260. .proc_read = proc_bus_pci_read,
  261. .proc_write = proc_bus_pci_write,
  262. .proc_ioctl = proc_bus_pci_ioctl,
  263. #ifdef CONFIG_COMPAT
  264. .proc_compat_ioctl = proc_bus_pci_ioctl,
  265. #endif
  266. #ifdef HAVE_PCI_MMAP
  267. .proc_open = proc_bus_pci_open,
  268. .proc_release = proc_bus_pci_release,
  269. .proc_mmap = proc_bus_pci_mmap,
  270. #ifdef HAVE_ARCH_PCI_GET_UNMAPPED_AREA
  271. .proc_get_unmapped_area = get_pci_unmapped_area,
  272. #endif /* HAVE_ARCH_PCI_GET_UNMAPPED_AREA */
  273. #endif /* HAVE_PCI_MMAP */
  274. };
  275. /* iterator */
  276. static void *pci_seq_start(struct seq_file *m, loff_t *pos)
  277. {
  278. struct pci_dev *dev = NULL;
  279. loff_t n = *pos;
  280. for_each_pci_dev(dev) {
  281. if (!n--)
  282. break;
  283. }
  284. return dev;
  285. }
  286. static void *pci_seq_next(struct seq_file *m, void *v, loff_t *pos)
  287. {
  288. struct pci_dev *dev = v;
  289. (*pos)++;
  290. dev = pci_get_device(PCI_ANY_ID, PCI_ANY_ID, dev);
  291. return dev;
  292. }
  293. static void pci_seq_stop(struct seq_file *m, void *v)
  294. {
  295. if (v) {
  296. struct pci_dev *dev = v;
  297. pci_dev_put(dev);
  298. }
  299. }
  300. static int show_device(struct seq_file *m, void *v)
  301. {
  302. const struct pci_dev *dev = v;
  303. const struct pci_driver *drv;
  304. int i;
  305. if (dev == NULL)
  306. return 0;
  307. drv = pci_dev_driver(dev);
  308. seq_printf(m, "%02x%02x\t%04x%04x\t%x",
  309. dev->bus->number,
  310. dev->devfn,
  311. dev->vendor,
  312. dev->device,
  313. dev->irq);
  314. /* only print standard and ROM resources to preserve compatibility */
  315. for (i = 0; i <= PCI_ROM_RESOURCE; i++) {
  316. resource_size_t start, end;
  317. pci_resource_to_user(dev, i, &dev->resource[i], &start, &end);
  318. seq_printf(m, "\t%16llx",
  319. (unsigned long long)(start |
  320. (dev->resource[i].flags & PCI_REGION_FLAG_MASK)));
  321. }
  322. for (i = 0; i <= PCI_ROM_RESOURCE; i++) {
  323. resource_size_t start, end;
  324. pci_resource_to_user(dev, i, &dev->resource[i], &start, &end);
  325. seq_printf(m, "\t%16llx",
  326. dev->resource[i].start < dev->resource[i].end ?
  327. (unsigned long long)(end - start) + 1 : 0);
  328. }
  329. seq_putc(m, '\t');
  330. if (drv)
  331. seq_puts(m, drv->name);
  332. seq_putc(m, '\n');
  333. return 0;
  334. }
  335. static const struct seq_operations proc_bus_pci_devices_op = {
  336. .start = pci_seq_start,
  337. .next = pci_seq_next,
  338. .stop = pci_seq_stop,
  339. .show = show_device
  340. };
  341. static struct proc_dir_entry *proc_bus_pci_dir;
  342. int pci_proc_attach_device(struct pci_dev *dev)
  343. {
  344. struct pci_bus *bus = dev->bus;
  345. struct proc_dir_entry *e;
  346. char name[16];
  347. if (!proc_initialized)
  348. return -EACCES;
  349. if (!bus->procdir) {
  350. if (pci_proc_domain(bus)) {
  351. sprintf(name, "%04x:%02x", pci_domain_nr(bus),
  352. bus->number);
  353. } else {
  354. sprintf(name, "%02x", bus->number);
  355. }
  356. bus->procdir = proc_mkdir(name, proc_bus_pci_dir);
  357. if (!bus->procdir)
  358. return -ENOMEM;
  359. }
  360. sprintf(name, "%02x.%x", PCI_SLOT(dev->devfn), PCI_FUNC(dev->devfn));
  361. e = proc_create_data(name, S_IFREG | S_IRUGO | S_IWUSR, bus->procdir,
  362. &proc_bus_pci_ops, dev);
  363. if (!e)
  364. return -ENOMEM;
  365. proc_set_size(e, dev->cfg_size);
  366. dev->procent = e;
  367. return 0;
  368. }
  369. int pci_proc_detach_device(struct pci_dev *dev)
  370. {
  371. proc_remove(dev->procent);
  372. dev->procent = NULL;
  373. return 0;
  374. }
  375. int pci_proc_detach_bus(struct pci_bus *bus)
  376. {
  377. proc_remove(bus->procdir);
  378. return 0;
  379. }
  380. static int __init pci_proc_init(void)
  381. {
  382. struct pci_dev *dev = NULL;
  383. proc_bus_pci_dir = proc_mkdir("bus/pci", NULL);
  384. proc_create_seq("devices", 0, proc_bus_pci_dir,
  385. &proc_bus_pci_devices_op);
  386. proc_initialized = 1;
  387. for_each_pci_dev(dev)
  388. pci_proc_attach_device(dev);
  389. return 0;
  390. }
  391. device_initcall(pci_proc_init);