probe.c 84 KB

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  1. // SPDX-License-Identifier: GPL-2.0
  2. /*
  3. * PCI detection and setup code
  4. */
  5. #include <linux/kernel.h>
  6. #include <linux/delay.h>
  7. #include <linux/init.h>
  8. #include <linux/pci.h>
  9. #include <linux/msi.h>
  10. #include <linux/of_device.h>
  11. #include <linux/of_pci.h>
  12. #include <linux/pci_hotplug.h>
  13. #include <linux/slab.h>
  14. #include <linux/module.h>
  15. #include <linux/cpumask.h>
  16. #include <linux/aer.h>
  17. #include <linux/acpi.h>
  18. #include <linux/hypervisor.h>
  19. #include <linux/irqdomain.h>
  20. #include <linux/pm_runtime.h>
  21. #include "pci.h"
  22. #define CARDBUS_LATENCY_TIMER 176 /* secondary latency timer */
  23. #define CARDBUS_RESERVE_BUSNR 3
  24. static struct resource busn_resource = {
  25. .name = "PCI busn",
  26. .start = 0,
  27. .end = 255,
  28. .flags = IORESOURCE_BUS,
  29. };
  30. /* Ugh. Need to stop exporting this to modules. */
  31. LIST_HEAD(pci_root_buses);
  32. EXPORT_SYMBOL(pci_root_buses);
  33. static LIST_HEAD(pci_domain_busn_res_list);
  34. struct pci_domain_busn_res {
  35. struct list_head list;
  36. struct resource res;
  37. int domain_nr;
  38. };
  39. static struct resource *get_pci_domain_busn_res(int domain_nr)
  40. {
  41. struct pci_domain_busn_res *r;
  42. list_for_each_entry(r, &pci_domain_busn_res_list, list)
  43. if (r->domain_nr == domain_nr)
  44. return &r->res;
  45. r = kzalloc(sizeof(*r), GFP_KERNEL);
  46. if (!r)
  47. return NULL;
  48. r->domain_nr = domain_nr;
  49. r->res.start = 0;
  50. r->res.end = 0xff;
  51. r->res.flags = IORESOURCE_BUS | IORESOURCE_PCI_FIXED;
  52. list_add_tail(&r->list, &pci_domain_busn_res_list);
  53. return &r->res;
  54. }
  55. /*
  56. * Some device drivers need know if PCI is initiated.
  57. * Basically, we think PCI is not initiated when there
  58. * is no device to be found on the pci_bus_type.
  59. */
  60. int no_pci_devices(void)
  61. {
  62. struct device *dev;
  63. int no_devices;
  64. dev = bus_find_next_device(&pci_bus_type, NULL);
  65. no_devices = (dev == NULL);
  66. put_device(dev);
  67. return no_devices;
  68. }
  69. EXPORT_SYMBOL(no_pci_devices);
  70. /*
  71. * PCI Bus Class
  72. */
  73. static void release_pcibus_dev(struct device *dev)
  74. {
  75. struct pci_bus *pci_bus = to_pci_bus(dev);
  76. put_device(pci_bus->bridge);
  77. pci_bus_remove_resources(pci_bus);
  78. pci_release_bus_of_node(pci_bus);
  79. kfree(pci_bus);
  80. }
  81. static struct class pcibus_class = {
  82. .name = "pci_bus",
  83. .dev_release = &release_pcibus_dev,
  84. .dev_groups = pcibus_groups,
  85. };
  86. static int __init pcibus_class_init(void)
  87. {
  88. return class_register(&pcibus_class);
  89. }
  90. postcore_initcall(pcibus_class_init);
  91. static u64 pci_size(u64 base, u64 maxbase, u64 mask)
  92. {
  93. u64 size = mask & maxbase; /* Find the significant bits */
  94. if (!size)
  95. return 0;
  96. /*
  97. * Get the lowest of them to find the decode size, and from that
  98. * the extent.
  99. */
  100. size = size & ~(size-1);
  101. /*
  102. * base == maxbase can be valid only if the BAR has already been
  103. * programmed with all 1s.
  104. */
  105. if (base == maxbase && ((base | (size - 1)) & mask) != mask)
  106. return 0;
  107. return size;
  108. }
  109. static inline unsigned long decode_bar(struct pci_dev *dev, u32 bar)
  110. {
  111. u32 mem_type;
  112. unsigned long flags;
  113. if ((bar & PCI_BASE_ADDRESS_SPACE) == PCI_BASE_ADDRESS_SPACE_IO) {
  114. flags = bar & ~PCI_BASE_ADDRESS_IO_MASK;
  115. flags |= IORESOURCE_IO;
  116. return flags;
  117. }
  118. flags = bar & ~PCI_BASE_ADDRESS_MEM_MASK;
  119. flags |= IORESOURCE_MEM;
  120. if (flags & PCI_BASE_ADDRESS_MEM_PREFETCH)
  121. flags |= IORESOURCE_PREFETCH;
  122. mem_type = bar & PCI_BASE_ADDRESS_MEM_TYPE_MASK;
  123. switch (mem_type) {
  124. case PCI_BASE_ADDRESS_MEM_TYPE_32:
  125. break;
  126. case PCI_BASE_ADDRESS_MEM_TYPE_1M:
  127. /* 1M mem BAR treated as 32-bit BAR */
  128. break;
  129. case PCI_BASE_ADDRESS_MEM_TYPE_64:
  130. flags |= IORESOURCE_MEM_64;
  131. break;
  132. default:
  133. /* mem unknown type treated as 32-bit BAR */
  134. break;
  135. }
  136. return flags;
  137. }
  138. #define PCI_COMMAND_DECODE_ENABLE (PCI_COMMAND_MEMORY | PCI_COMMAND_IO)
  139. /**
  140. * pci_read_base - Read a PCI BAR
  141. * @dev: the PCI device
  142. * @type: type of the BAR
  143. * @res: resource buffer to be filled in
  144. * @pos: BAR position in the config space
  145. *
  146. * Returns 1 if the BAR is 64-bit, or 0 if 32-bit.
  147. */
  148. int __pci_read_base(struct pci_dev *dev, enum pci_bar_type type,
  149. struct resource *res, unsigned int pos)
  150. {
  151. u32 l = 0, sz = 0, mask;
  152. u64 l64, sz64, mask64;
  153. u16 orig_cmd;
  154. struct pci_bus_region region, inverted_region;
  155. mask = type ? PCI_ROM_ADDRESS_MASK : ~0;
  156. /* No printks while decoding is disabled! */
  157. if (!dev->mmio_always_on) {
  158. pci_read_config_word(dev, PCI_COMMAND, &orig_cmd);
  159. if (orig_cmd & PCI_COMMAND_DECODE_ENABLE) {
  160. pci_write_config_word(dev, PCI_COMMAND,
  161. orig_cmd & ~PCI_COMMAND_DECODE_ENABLE);
  162. }
  163. }
  164. res->name = pci_name(dev);
  165. pci_read_config_dword(dev, pos, &l);
  166. pci_write_config_dword(dev, pos, l | mask);
  167. pci_read_config_dword(dev, pos, &sz);
  168. pci_write_config_dword(dev, pos, l);
  169. /*
  170. * All bits set in sz means the device isn't working properly.
  171. * If the BAR isn't implemented, all bits must be 0. If it's a
  172. * memory BAR or a ROM, bit 0 must be clear; if it's an io BAR, bit
  173. * 1 must be clear.
  174. */
  175. if (sz == 0xffffffff)
  176. sz = 0;
  177. /*
  178. * I don't know how l can have all bits set. Copied from old code.
  179. * Maybe it fixes a bug on some ancient platform.
  180. */
  181. if (l == 0xffffffff)
  182. l = 0;
  183. if (type == pci_bar_unknown) {
  184. res->flags = decode_bar(dev, l);
  185. res->flags |= IORESOURCE_SIZEALIGN;
  186. if (res->flags & IORESOURCE_IO) {
  187. l64 = l & PCI_BASE_ADDRESS_IO_MASK;
  188. sz64 = sz & PCI_BASE_ADDRESS_IO_MASK;
  189. mask64 = PCI_BASE_ADDRESS_IO_MASK & (u32)IO_SPACE_LIMIT;
  190. } else {
  191. l64 = l & PCI_BASE_ADDRESS_MEM_MASK;
  192. sz64 = sz & PCI_BASE_ADDRESS_MEM_MASK;
  193. mask64 = (u32)PCI_BASE_ADDRESS_MEM_MASK;
  194. }
  195. } else {
  196. if (l & PCI_ROM_ADDRESS_ENABLE)
  197. res->flags |= IORESOURCE_ROM_ENABLE;
  198. l64 = l & PCI_ROM_ADDRESS_MASK;
  199. sz64 = sz & PCI_ROM_ADDRESS_MASK;
  200. mask64 = PCI_ROM_ADDRESS_MASK;
  201. }
  202. if (res->flags & IORESOURCE_MEM_64) {
  203. pci_read_config_dword(dev, pos + 4, &l);
  204. pci_write_config_dword(dev, pos + 4, ~0);
  205. pci_read_config_dword(dev, pos + 4, &sz);
  206. pci_write_config_dword(dev, pos + 4, l);
  207. l64 |= ((u64)l << 32);
  208. sz64 |= ((u64)sz << 32);
  209. mask64 |= ((u64)~0 << 32);
  210. }
  211. if (!dev->mmio_always_on && (orig_cmd & PCI_COMMAND_DECODE_ENABLE))
  212. pci_write_config_word(dev, PCI_COMMAND, orig_cmd);
  213. if (!sz64)
  214. goto fail;
  215. sz64 = pci_size(l64, sz64, mask64);
  216. if (!sz64) {
  217. pci_info(dev, FW_BUG "reg 0x%x: invalid BAR (can't size)\n",
  218. pos);
  219. goto fail;
  220. }
  221. if (res->flags & IORESOURCE_MEM_64) {
  222. if ((sizeof(pci_bus_addr_t) < 8 || sizeof(resource_size_t) < 8)
  223. && sz64 > 0x100000000ULL) {
  224. res->flags |= IORESOURCE_UNSET | IORESOURCE_DISABLED;
  225. res->start = 0;
  226. res->end = 0;
  227. pci_err(dev, "reg 0x%x: can't handle BAR larger than 4GB (size %#010llx)\n",
  228. pos, (unsigned long long)sz64);
  229. goto out;
  230. }
  231. if ((sizeof(pci_bus_addr_t) < 8) && l) {
  232. /* Above 32-bit boundary; try to reallocate */
  233. res->flags |= IORESOURCE_UNSET;
  234. res->start = 0;
  235. res->end = sz64 - 1;
  236. pci_info(dev, "reg 0x%x: can't handle BAR above 4GB (bus address %#010llx)\n",
  237. pos, (unsigned long long)l64);
  238. goto out;
  239. }
  240. }
  241. region.start = l64;
  242. region.end = l64 + sz64 - 1;
  243. pcibios_bus_to_resource(dev->bus, res, &region);
  244. pcibios_resource_to_bus(dev->bus, &inverted_region, res);
  245. /*
  246. * If "A" is a BAR value (a bus address), "bus_to_resource(A)" is
  247. * the corresponding resource address (the physical address used by
  248. * the CPU. Converting that resource address back to a bus address
  249. * should yield the original BAR value:
  250. *
  251. * resource_to_bus(bus_to_resource(A)) == A
  252. *
  253. * If it doesn't, CPU accesses to "bus_to_resource(A)" will not
  254. * be claimed by the device.
  255. */
  256. if (inverted_region.start != region.start) {
  257. res->flags |= IORESOURCE_UNSET;
  258. res->start = 0;
  259. res->end = region.end - region.start;
  260. pci_info(dev, "reg 0x%x: initial BAR value %#010llx invalid\n",
  261. pos, (unsigned long long)region.start);
  262. }
  263. goto out;
  264. fail:
  265. res->flags = 0;
  266. out:
  267. if (res->flags)
  268. pci_info(dev, "reg 0x%x: %pR\n", pos, res);
  269. return (res->flags & IORESOURCE_MEM_64) ? 1 : 0;
  270. }
  271. static void pci_read_bases(struct pci_dev *dev, unsigned int howmany, int rom)
  272. {
  273. unsigned int pos, reg;
  274. if (dev->non_compliant_bars)
  275. return;
  276. /* Per PCIe r4.0, sec 9.3.4.1.11, the VF BARs are all RO Zero */
  277. if (dev->is_virtfn)
  278. return;
  279. for (pos = 0; pos < howmany; pos++) {
  280. struct resource *res = &dev->resource[pos];
  281. reg = PCI_BASE_ADDRESS_0 + (pos << 2);
  282. pos += __pci_read_base(dev, pci_bar_unknown, res, reg);
  283. }
  284. if (rom) {
  285. struct resource *res = &dev->resource[PCI_ROM_RESOURCE];
  286. dev->rom_base_reg = rom;
  287. res->flags = IORESOURCE_MEM | IORESOURCE_PREFETCH |
  288. IORESOURCE_READONLY | IORESOURCE_SIZEALIGN;
  289. __pci_read_base(dev, pci_bar_mem32, res, rom);
  290. }
  291. }
  292. static void pci_read_bridge_windows(struct pci_dev *bridge)
  293. {
  294. u16 io;
  295. u32 pmem, tmp;
  296. pci_read_config_word(bridge, PCI_IO_BASE, &io);
  297. if (!io) {
  298. pci_write_config_word(bridge, PCI_IO_BASE, 0xe0f0);
  299. pci_read_config_word(bridge, PCI_IO_BASE, &io);
  300. pci_write_config_word(bridge, PCI_IO_BASE, 0x0);
  301. }
  302. if (io)
  303. bridge->io_window = 1;
  304. /*
  305. * DECchip 21050 pass 2 errata: the bridge may miss an address
  306. * disconnect boundary by one PCI data phase. Workaround: do not
  307. * use prefetching on this device.
  308. */
  309. if (bridge->vendor == PCI_VENDOR_ID_DEC && bridge->device == 0x0001)
  310. return;
  311. pci_read_config_dword(bridge, PCI_PREF_MEMORY_BASE, &pmem);
  312. if (!pmem) {
  313. pci_write_config_dword(bridge, PCI_PREF_MEMORY_BASE,
  314. 0xffe0fff0);
  315. pci_read_config_dword(bridge, PCI_PREF_MEMORY_BASE, &pmem);
  316. pci_write_config_dword(bridge, PCI_PREF_MEMORY_BASE, 0x0);
  317. }
  318. if (!pmem)
  319. return;
  320. bridge->pref_window = 1;
  321. if ((pmem & PCI_PREF_RANGE_TYPE_MASK) == PCI_PREF_RANGE_TYPE_64) {
  322. /*
  323. * Bridge claims to have a 64-bit prefetchable memory
  324. * window; verify that the upper bits are actually
  325. * writable.
  326. */
  327. pci_read_config_dword(bridge, PCI_PREF_BASE_UPPER32, &pmem);
  328. pci_write_config_dword(bridge, PCI_PREF_BASE_UPPER32,
  329. 0xffffffff);
  330. pci_read_config_dword(bridge, PCI_PREF_BASE_UPPER32, &tmp);
  331. pci_write_config_dword(bridge, PCI_PREF_BASE_UPPER32, pmem);
  332. if (tmp)
  333. bridge->pref_64_window = 1;
  334. }
  335. }
  336. static void pci_read_bridge_io(struct pci_bus *child)
  337. {
  338. struct pci_dev *dev = child->self;
  339. u8 io_base_lo, io_limit_lo;
  340. unsigned long io_mask, io_granularity, base, limit;
  341. struct pci_bus_region region;
  342. struct resource *res;
  343. io_mask = PCI_IO_RANGE_MASK;
  344. io_granularity = 0x1000;
  345. if (dev->io_window_1k) {
  346. /* Support 1K I/O space granularity */
  347. io_mask = PCI_IO_1K_RANGE_MASK;
  348. io_granularity = 0x400;
  349. }
  350. res = child->resource[0];
  351. pci_read_config_byte(dev, PCI_IO_BASE, &io_base_lo);
  352. pci_read_config_byte(dev, PCI_IO_LIMIT, &io_limit_lo);
  353. base = (io_base_lo & io_mask) << 8;
  354. limit = (io_limit_lo & io_mask) << 8;
  355. if ((io_base_lo & PCI_IO_RANGE_TYPE_MASK) == PCI_IO_RANGE_TYPE_32) {
  356. u16 io_base_hi, io_limit_hi;
  357. pci_read_config_word(dev, PCI_IO_BASE_UPPER16, &io_base_hi);
  358. pci_read_config_word(dev, PCI_IO_LIMIT_UPPER16, &io_limit_hi);
  359. base |= ((unsigned long) io_base_hi << 16);
  360. limit |= ((unsigned long) io_limit_hi << 16);
  361. }
  362. if (base <= limit) {
  363. res->flags = (io_base_lo & PCI_IO_RANGE_TYPE_MASK) | IORESOURCE_IO;
  364. region.start = base;
  365. region.end = limit + io_granularity - 1;
  366. pcibios_bus_to_resource(dev->bus, res, &region);
  367. pci_info(dev, " bridge window %pR\n", res);
  368. }
  369. }
  370. static void pci_read_bridge_mmio(struct pci_bus *child)
  371. {
  372. struct pci_dev *dev = child->self;
  373. u16 mem_base_lo, mem_limit_lo;
  374. unsigned long base, limit;
  375. struct pci_bus_region region;
  376. struct resource *res;
  377. res = child->resource[1];
  378. pci_read_config_word(dev, PCI_MEMORY_BASE, &mem_base_lo);
  379. pci_read_config_word(dev, PCI_MEMORY_LIMIT, &mem_limit_lo);
  380. base = ((unsigned long) mem_base_lo & PCI_MEMORY_RANGE_MASK) << 16;
  381. limit = ((unsigned long) mem_limit_lo & PCI_MEMORY_RANGE_MASK) << 16;
  382. if (base <= limit) {
  383. res->flags = (mem_base_lo & PCI_MEMORY_RANGE_TYPE_MASK) | IORESOURCE_MEM;
  384. region.start = base;
  385. region.end = limit + 0xfffff;
  386. pcibios_bus_to_resource(dev->bus, res, &region);
  387. pci_info(dev, " bridge window %pR\n", res);
  388. }
  389. }
  390. static void pci_read_bridge_mmio_pref(struct pci_bus *child)
  391. {
  392. struct pci_dev *dev = child->self;
  393. u16 mem_base_lo, mem_limit_lo;
  394. u64 base64, limit64;
  395. pci_bus_addr_t base, limit;
  396. struct pci_bus_region region;
  397. struct resource *res;
  398. res = child->resource[2];
  399. pci_read_config_word(dev, PCI_PREF_MEMORY_BASE, &mem_base_lo);
  400. pci_read_config_word(dev, PCI_PREF_MEMORY_LIMIT, &mem_limit_lo);
  401. base64 = (mem_base_lo & PCI_PREF_RANGE_MASK) << 16;
  402. limit64 = (mem_limit_lo & PCI_PREF_RANGE_MASK) << 16;
  403. if ((mem_base_lo & PCI_PREF_RANGE_TYPE_MASK) == PCI_PREF_RANGE_TYPE_64) {
  404. u32 mem_base_hi, mem_limit_hi;
  405. pci_read_config_dword(dev, PCI_PREF_BASE_UPPER32, &mem_base_hi);
  406. pci_read_config_dword(dev, PCI_PREF_LIMIT_UPPER32, &mem_limit_hi);
  407. /*
  408. * Some bridges set the base > limit by default, and some
  409. * (broken) BIOSes do not initialize them. If we find
  410. * this, just assume they are not being used.
  411. */
  412. if (mem_base_hi <= mem_limit_hi) {
  413. base64 |= (u64) mem_base_hi << 32;
  414. limit64 |= (u64) mem_limit_hi << 32;
  415. }
  416. }
  417. base = (pci_bus_addr_t) base64;
  418. limit = (pci_bus_addr_t) limit64;
  419. if (base != base64) {
  420. pci_err(dev, "can't handle bridge window above 4GB (bus address %#010llx)\n",
  421. (unsigned long long) base64);
  422. return;
  423. }
  424. if (base <= limit) {
  425. res->flags = (mem_base_lo & PCI_PREF_RANGE_TYPE_MASK) |
  426. IORESOURCE_MEM | IORESOURCE_PREFETCH;
  427. if (res->flags & PCI_PREF_RANGE_TYPE_64)
  428. res->flags |= IORESOURCE_MEM_64;
  429. region.start = base;
  430. region.end = limit + 0xfffff;
  431. pcibios_bus_to_resource(dev->bus, res, &region);
  432. pci_info(dev, " bridge window %pR\n", res);
  433. }
  434. }
  435. void pci_read_bridge_bases(struct pci_bus *child)
  436. {
  437. struct pci_dev *dev = child->self;
  438. struct resource *res;
  439. int i;
  440. if (pci_is_root_bus(child)) /* It's a host bus, nothing to read */
  441. return;
  442. pci_info(dev, "PCI bridge to %pR%s\n",
  443. &child->busn_res,
  444. dev->transparent ? " (subtractive decode)" : "");
  445. pci_bus_remove_resources(child);
  446. for (i = 0; i < PCI_BRIDGE_RESOURCE_NUM; i++)
  447. child->resource[i] = &dev->resource[PCI_BRIDGE_RESOURCES+i];
  448. pci_read_bridge_io(child);
  449. pci_read_bridge_mmio(child);
  450. pci_read_bridge_mmio_pref(child);
  451. if (dev->transparent) {
  452. pci_bus_for_each_resource(child->parent, res, i) {
  453. if (res && res->flags) {
  454. pci_bus_add_resource(child, res,
  455. PCI_SUBTRACTIVE_DECODE);
  456. pci_info(dev, " bridge window %pR (subtractive decode)\n",
  457. res);
  458. }
  459. }
  460. }
  461. }
  462. static struct pci_bus *pci_alloc_bus(struct pci_bus *parent)
  463. {
  464. struct pci_bus *b;
  465. b = kzalloc(sizeof(*b), GFP_KERNEL);
  466. if (!b)
  467. return NULL;
  468. INIT_LIST_HEAD(&b->node);
  469. INIT_LIST_HEAD(&b->children);
  470. INIT_LIST_HEAD(&b->devices);
  471. INIT_LIST_HEAD(&b->slots);
  472. INIT_LIST_HEAD(&b->resources);
  473. b->max_bus_speed = PCI_SPEED_UNKNOWN;
  474. b->cur_bus_speed = PCI_SPEED_UNKNOWN;
  475. #ifdef CONFIG_PCI_DOMAINS_GENERIC
  476. if (parent)
  477. b->domain_nr = parent->domain_nr;
  478. #endif
  479. return b;
  480. }
  481. static void pci_release_host_bridge_dev(struct device *dev)
  482. {
  483. struct pci_host_bridge *bridge = to_pci_host_bridge(dev);
  484. if (bridge->release_fn)
  485. bridge->release_fn(bridge);
  486. pci_free_resource_list(&bridge->windows);
  487. pci_free_resource_list(&bridge->dma_ranges);
  488. kfree(bridge);
  489. }
  490. static void pci_init_host_bridge(struct pci_host_bridge *bridge)
  491. {
  492. INIT_LIST_HEAD(&bridge->windows);
  493. INIT_LIST_HEAD(&bridge->dma_ranges);
  494. /*
  495. * We assume we can manage these PCIe features. Some systems may
  496. * reserve these for use by the platform itself, e.g., an ACPI BIOS
  497. * may implement its own AER handling and use _OSC to prevent the
  498. * OS from interfering.
  499. */
  500. bridge->native_aer = 1;
  501. bridge->native_pcie_hotplug = 1;
  502. bridge->native_shpc_hotplug = 1;
  503. bridge->native_pme = 1;
  504. bridge->native_ltr = 1;
  505. bridge->native_dpc = 1;
  506. device_initialize(&bridge->dev);
  507. }
  508. struct pci_host_bridge *pci_alloc_host_bridge(size_t priv)
  509. {
  510. struct pci_host_bridge *bridge;
  511. bridge = kzalloc(sizeof(*bridge) + priv, GFP_KERNEL);
  512. if (!bridge)
  513. return NULL;
  514. pci_init_host_bridge(bridge);
  515. bridge->dev.release = pci_release_host_bridge_dev;
  516. return bridge;
  517. }
  518. EXPORT_SYMBOL(pci_alloc_host_bridge);
  519. static void devm_pci_alloc_host_bridge_release(void *data)
  520. {
  521. pci_free_host_bridge(data);
  522. }
  523. struct pci_host_bridge *devm_pci_alloc_host_bridge(struct device *dev,
  524. size_t priv)
  525. {
  526. int ret;
  527. struct pci_host_bridge *bridge;
  528. bridge = pci_alloc_host_bridge(priv);
  529. if (!bridge)
  530. return NULL;
  531. bridge->dev.parent = dev;
  532. ret = devm_add_action_or_reset(dev, devm_pci_alloc_host_bridge_release,
  533. bridge);
  534. if (ret)
  535. return NULL;
  536. ret = devm_of_pci_bridge_init(dev, bridge);
  537. if (ret)
  538. return NULL;
  539. return bridge;
  540. }
  541. EXPORT_SYMBOL(devm_pci_alloc_host_bridge);
  542. void pci_free_host_bridge(struct pci_host_bridge *bridge)
  543. {
  544. put_device(&bridge->dev);
  545. }
  546. EXPORT_SYMBOL(pci_free_host_bridge);
  547. /* Indexed by PCI_X_SSTATUS_FREQ (secondary bus mode and frequency) */
  548. static const unsigned char pcix_bus_speed[] = {
  549. PCI_SPEED_UNKNOWN, /* 0 */
  550. PCI_SPEED_66MHz_PCIX, /* 1 */
  551. PCI_SPEED_100MHz_PCIX, /* 2 */
  552. PCI_SPEED_133MHz_PCIX, /* 3 */
  553. PCI_SPEED_UNKNOWN, /* 4 */
  554. PCI_SPEED_66MHz_PCIX_ECC, /* 5 */
  555. PCI_SPEED_100MHz_PCIX_ECC, /* 6 */
  556. PCI_SPEED_133MHz_PCIX_ECC, /* 7 */
  557. PCI_SPEED_UNKNOWN, /* 8 */
  558. PCI_SPEED_66MHz_PCIX_266, /* 9 */
  559. PCI_SPEED_100MHz_PCIX_266, /* A */
  560. PCI_SPEED_133MHz_PCIX_266, /* B */
  561. PCI_SPEED_UNKNOWN, /* C */
  562. PCI_SPEED_66MHz_PCIX_533, /* D */
  563. PCI_SPEED_100MHz_PCIX_533, /* E */
  564. PCI_SPEED_133MHz_PCIX_533 /* F */
  565. };
  566. /* Indexed by PCI_EXP_LNKCAP_SLS, PCI_EXP_LNKSTA_CLS */
  567. const unsigned char pcie_link_speed[] = {
  568. PCI_SPEED_UNKNOWN, /* 0 */
  569. PCIE_SPEED_2_5GT, /* 1 */
  570. PCIE_SPEED_5_0GT, /* 2 */
  571. PCIE_SPEED_8_0GT, /* 3 */
  572. PCIE_SPEED_16_0GT, /* 4 */
  573. PCIE_SPEED_32_0GT, /* 5 */
  574. PCI_SPEED_UNKNOWN, /* 6 */
  575. PCI_SPEED_UNKNOWN, /* 7 */
  576. PCI_SPEED_UNKNOWN, /* 8 */
  577. PCI_SPEED_UNKNOWN, /* 9 */
  578. PCI_SPEED_UNKNOWN, /* A */
  579. PCI_SPEED_UNKNOWN, /* B */
  580. PCI_SPEED_UNKNOWN, /* C */
  581. PCI_SPEED_UNKNOWN, /* D */
  582. PCI_SPEED_UNKNOWN, /* E */
  583. PCI_SPEED_UNKNOWN /* F */
  584. };
  585. EXPORT_SYMBOL_GPL(pcie_link_speed);
  586. const char *pci_speed_string(enum pci_bus_speed speed)
  587. {
  588. /* Indexed by the pci_bus_speed enum */
  589. static const char *speed_strings[] = {
  590. "33 MHz PCI", /* 0x00 */
  591. "66 MHz PCI", /* 0x01 */
  592. "66 MHz PCI-X", /* 0x02 */
  593. "100 MHz PCI-X", /* 0x03 */
  594. "133 MHz PCI-X", /* 0x04 */
  595. NULL, /* 0x05 */
  596. NULL, /* 0x06 */
  597. NULL, /* 0x07 */
  598. NULL, /* 0x08 */
  599. "66 MHz PCI-X 266", /* 0x09 */
  600. "100 MHz PCI-X 266", /* 0x0a */
  601. "133 MHz PCI-X 266", /* 0x0b */
  602. "Unknown AGP", /* 0x0c */
  603. "1x AGP", /* 0x0d */
  604. "2x AGP", /* 0x0e */
  605. "4x AGP", /* 0x0f */
  606. "8x AGP", /* 0x10 */
  607. "66 MHz PCI-X 533", /* 0x11 */
  608. "100 MHz PCI-X 533", /* 0x12 */
  609. "133 MHz PCI-X 533", /* 0x13 */
  610. "2.5 GT/s PCIe", /* 0x14 */
  611. "5.0 GT/s PCIe", /* 0x15 */
  612. "8.0 GT/s PCIe", /* 0x16 */
  613. "16.0 GT/s PCIe", /* 0x17 */
  614. "32.0 GT/s PCIe", /* 0x18 */
  615. };
  616. if (speed < ARRAY_SIZE(speed_strings))
  617. return speed_strings[speed];
  618. return "Unknown";
  619. }
  620. EXPORT_SYMBOL_GPL(pci_speed_string);
  621. void pcie_update_link_speed(struct pci_bus *bus, u16 linksta)
  622. {
  623. bus->cur_bus_speed = pcie_link_speed[linksta & PCI_EXP_LNKSTA_CLS];
  624. }
  625. EXPORT_SYMBOL_GPL(pcie_update_link_speed);
  626. static unsigned char agp_speeds[] = {
  627. AGP_UNKNOWN,
  628. AGP_1X,
  629. AGP_2X,
  630. AGP_4X,
  631. AGP_8X
  632. };
  633. static enum pci_bus_speed agp_speed(int agp3, int agpstat)
  634. {
  635. int index = 0;
  636. if (agpstat & 4)
  637. index = 3;
  638. else if (agpstat & 2)
  639. index = 2;
  640. else if (agpstat & 1)
  641. index = 1;
  642. else
  643. goto out;
  644. if (agp3) {
  645. index += 2;
  646. if (index == 5)
  647. index = 0;
  648. }
  649. out:
  650. return agp_speeds[index];
  651. }
  652. static void pci_set_bus_speed(struct pci_bus *bus)
  653. {
  654. struct pci_dev *bridge = bus->self;
  655. int pos;
  656. pos = pci_find_capability(bridge, PCI_CAP_ID_AGP);
  657. if (!pos)
  658. pos = pci_find_capability(bridge, PCI_CAP_ID_AGP3);
  659. if (pos) {
  660. u32 agpstat, agpcmd;
  661. pci_read_config_dword(bridge, pos + PCI_AGP_STATUS, &agpstat);
  662. bus->max_bus_speed = agp_speed(agpstat & 8, agpstat & 7);
  663. pci_read_config_dword(bridge, pos + PCI_AGP_COMMAND, &agpcmd);
  664. bus->cur_bus_speed = agp_speed(agpstat & 8, agpcmd & 7);
  665. }
  666. pos = pci_find_capability(bridge, PCI_CAP_ID_PCIX);
  667. if (pos) {
  668. u16 status;
  669. enum pci_bus_speed max;
  670. pci_read_config_word(bridge, pos + PCI_X_BRIDGE_SSTATUS,
  671. &status);
  672. if (status & PCI_X_SSTATUS_533MHZ) {
  673. max = PCI_SPEED_133MHz_PCIX_533;
  674. } else if (status & PCI_X_SSTATUS_266MHZ) {
  675. max = PCI_SPEED_133MHz_PCIX_266;
  676. } else if (status & PCI_X_SSTATUS_133MHZ) {
  677. if ((status & PCI_X_SSTATUS_VERS) == PCI_X_SSTATUS_V2)
  678. max = PCI_SPEED_133MHz_PCIX_ECC;
  679. else
  680. max = PCI_SPEED_133MHz_PCIX;
  681. } else {
  682. max = PCI_SPEED_66MHz_PCIX;
  683. }
  684. bus->max_bus_speed = max;
  685. bus->cur_bus_speed = pcix_bus_speed[
  686. (status & PCI_X_SSTATUS_FREQ) >> 6];
  687. return;
  688. }
  689. if (pci_is_pcie(bridge)) {
  690. u32 linkcap;
  691. u16 linksta;
  692. pcie_capability_read_dword(bridge, PCI_EXP_LNKCAP, &linkcap);
  693. bus->max_bus_speed = pcie_link_speed[linkcap & PCI_EXP_LNKCAP_SLS];
  694. bridge->link_active_reporting = !!(linkcap & PCI_EXP_LNKCAP_DLLLARC);
  695. pcie_capability_read_word(bridge, PCI_EXP_LNKSTA, &linksta);
  696. pcie_update_link_speed(bus, linksta);
  697. }
  698. }
  699. static struct irq_domain *pci_host_bridge_msi_domain(struct pci_bus *bus)
  700. {
  701. struct irq_domain *d;
  702. /*
  703. * Any firmware interface that can resolve the msi_domain
  704. * should be called from here.
  705. */
  706. d = pci_host_bridge_of_msi_domain(bus);
  707. if (!d)
  708. d = pci_host_bridge_acpi_msi_domain(bus);
  709. #ifdef CONFIG_PCI_MSI_IRQ_DOMAIN
  710. /*
  711. * If no IRQ domain was found via the OF tree, try looking it up
  712. * directly through the fwnode_handle.
  713. */
  714. if (!d) {
  715. struct fwnode_handle *fwnode = pci_root_bus_fwnode(bus);
  716. if (fwnode)
  717. d = irq_find_matching_fwnode(fwnode,
  718. DOMAIN_BUS_PCI_MSI);
  719. }
  720. #endif
  721. return d;
  722. }
  723. static void pci_set_bus_msi_domain(struct pci_bus *bus)
  724. {
  725. struct irq_domain *d;
  726. struct pci_bus *b;
  727. /*
  728. * The bus can be a root bus, a subordinate bus, or a virtual bus
  729. * created by an SR-IOV device. Walk up to the first bridge device
  730. * found or derive the domain from the host bridge.
  731. */
  732. for (b = bus, d = NULL; !d && !pci_is_root_bus(b); b = b->parent) {
  733. if (b->self)
  734. d = dev_get_msi_domain(&b->self->dev);
  735. }
  736. if (!d)
  737. d = pci_host_bridge_msi_domain(b);
  738. dev_set_msi_domain(&bus->dev, d);
  739. }
  740. static int pci_register_host_bridge(struct pci_host_bridge *bridge)
  741. {
  742. struct device *parent = bridge->dev.parent;
  743. struct resource_entry *window, *n;
  744. struct pci_bus *bus, *b;
  745. resource_size_t offset;
  746. LIST_HEAD(resources);
  747. struct resource *res;
  748. char addr[64], *fmt;
  749. const char *name;
  750. int err;
  751. bus = pci_alloc_bus(NULL);
  752. if (!bus)
  753. return -ENOMEM;
  754. bridge->bus = bus;
  755. /* Temporarily move resources off the list */
  756. list_splice_init(&bridge->windows, &resources);
  757. bus->sysdata = bridge->sysdata;
  758. bus->msi = bridge->msi;
  759. bus->ops = bridge->ops;
  760. bus->number = bus->busn_res.start = bridge->busnr;
  761. #ifdef CONFIG_PCI_DOMAINS_GENERIC
  762. bus->domain_nr = pci_bus_find_domain_nr(bus, parent);
  763. #endif
  764. b = pci_find_bus(pci_domain_nr(bus), bridge->busnr);
  765. if (b) {
  766. /* Ignore it if we already got here via a different bridge */
  767. dev_dbg(&b->dev, "bus already known\n");
  768. err = -EEXIST;
  769. goto free;
  770. }
  771. dev_set_name(&bridge->dev, "pci%04x:%02x", pci_domain_nr(bus),
  772. bridge->busnr);
  773. err = pcibios_root_bridge_prepare(bridge);
  774. if (err)
  775. goto free;
  776. err = device_add(&bridge->dev);
  777. if (err) {
  778. put_device(&bridge->dev);
  779. goto free;
  780. }
  781. bus->bridge = get_device(&bridge->dev);
  782. device_enable_async_suspend(bus->bridge);
  783. pci_set_bus_of_node(bus);
  784. pci_set_bus_msi_domain(bus);
  785. if (!parent)
  786. set_dev_node(bus->bridge, pcibus_to_node(bus));
  787. bus->dev.class = &pcibus_class;
  788. bus->dev.parent = bus->bridge;
  789. dev_set_name(&bus->dev, "%04x:%02x", pci_domain_nr(bus), bus->number);
  790. name = dev_name(&bus->dev);
  791. err = device_register(&bus->dev);
  792. if (err)
  793. goto unregister;
  794. pcibios_add_bus(bus);
  795. if (bus->ops->add_bus) {
  796. err = bus->ops->add_bus(bus);
  797. if (WARN_ON(err < 0))
  798. dev_err(&bus->dev, "failed to add bus: %d\n", err);
  799. }
  800. /* Create legacy_io and legacy_mem files for this bus */
  801. pci_create_legacy_files(bus);
  802. if (parent)
  803. dev_info(parent, "PCI host bridge to bus %s\n", name);
  804. else
  805. pr_info("PCI host bridge to bus %s\n", name);
  806. if (nr_node_ids > 1 && pcibus_to_node(bus) == NUMA_NO_NODE)
  807. dev_warn(&bus->dev, "Unknown NUMA node; performance will be reduced\n");
  808. /* Add initial resources to the bus */
  809. resource_list_for_each_entry_safe(window, n, &resources) {
  810. list_move_tail(&window->node, &bridge->windows);
  811. offset = window->offset;
  812. res = window->res;
  813. if (res->flags & IORESOURCE_BUS)
  814. pci_bus_insert_busn_res(bus, bus->number, res->end);
  815. else
  816. pci_bus_add_resource(bus, res, 0);
  817. if (offset) {
  818. if (resource_type(res) == IORESOURCE_IO)
  819. fmt = " (bus address [%#06llx-%#06llx])";
  820. else
  821. fmt = " (bus address [%#010llx-%#010llx])";
  822. snprintf(addr, sizeof(addr), fmt,
  823. (unsigned long long)(res->start - offset),
  824. (unsigned long long)(res->end - offset));
  825. } else
  826. addr[0] = '\0';
  827. dev_info(&bus->dev, "root bus resource %pR%s\n", res, addr);
  828. }
  829. down_write(&pci_bus_sem);
  830. list_add_tail(&bus->node, &pci_root_buses);
  831. up_write(&pci_bus_sem);
  832. return 0;
  833. unregister:
  834. put_device(&bridge->dev);
  835. device_del(&bridge->dev);
  836. free:
  837. kfree(bus);
  838. return err;
  839. }
  840. static bool pci_bridge_child_ext_cfg_accessible(struct pci_dev *bridge)
  841. {
  842. int pos;
  843. u32 status;
  844. /*
  845. * If extended config space isn't accessible on a bridge's primary
  846. * bus, we certainly can't access it on the secondary bus.
  847. */
  848. if (bridge->bus->bus_flags & PCI_BUS_FLAGS_NO_EXTCFG)
  849. return false;
  850. /*
  851. * PCIe Root Ports and switch ports are PCIe on both sides, so if
  852. * extended config space is accessible on the primary, it's also
  853. * accessible on the secondary.
  854. */
  855. if (pci_is_pcie(bridge) &&
  856. (pci_pcie_type(bridge) == PCI_EXP_TYPE_ROOT_PORT ||
  857. pci_pcie_type(bridge) == PCI_EXP_TYPE_UPSTREAM ||
  858. pci_pcie_type(bridge) == PCI_EXP_TYPE_DOWNSTREAM))
  859. return true;
  860. /*
  861. * For the other bridge types:
  862. * - PCI-to-PCI bridges
  863. * - PCIe-to-PCI/PCI-X forward bridges
  864. * - PCI/PCI-X-to-PCIe reverse bridges
  865. * extended config space on the secondary side is only accessible
  866. * if the bridge supports PCI-X Mode 2.
  867. */
  868. pos = pci_find_capability(bridge, PCI_CAP_ID_PCIX);
  869. if (!pos)
  870. return false;
  871. pci_read_config_dword(bridge, pos + PCI_X_STATUS, &status);
  872. return status & (PCI_X_STATUS_266MHZ | PCI_X_STATUS_533MHZ);
  873. }
  874. static struct pci_bus *pci_alloc_child_bus(struct pci_bus *parent,
  875. struct pci_dev *bridge, int busnr)
  876. {
  877. struct pci_bus *child;
  878. struct pci_host_bridge *host;
  879. int i;
  880. int ret;
  881. /* Allocate a new bus and inherit stuff from the parent */
  882. child = pci_alloc_bus(parent);
  883. if (!child)
  884. return NULL;
  885. child->parent = parent;
  886. child->msi = parent->msi;
  887. child->sysdata = parent->sysdata;
  888. child->bus_flags = parent->bus_flags;
  889. host = pci_find_host_bridge(parent);
  890. if (host->child_ops)
  891. child->ops = host->child_ops;
  892. else
  893. child->ops = parent->ops;
  894. /*
  895. * Initialize some portions of the bus device, but don't register
  896. * it now as the parent is not properly set up yet.
  897. */
  898. child->dev.class = &pcibus_class;
  899. dev_set_name(&child->dev, "%04x:%02x", pci_domain_nr(child), busnr);
  900. /* Set up the primary, secondary and subordinate bus numbers */
  901. child->number = child->busn_res.start = busnr;
  902. child->primary = parent->busn_res.start;
  903. child->busn_res.end = 0xff;
  904. if (!bridge) {
  905. child->dev.parent = parent->bridge;
  906. goto add_dev;
  907. }
  908. child->self = bridge;
  909. child->bridge = get_device(&bridge->dev);
  910. child->dev.parent = child->bridge;
  911. pci_set_bus_of_node(child);
  912. pci_set_bus_speed(child);
  913. /*
  914. * Check whether extended config space is accessible on the child
  915. * bus. Note that we currently assume it is always accessible on
  916. * the root bus.
  917. */
  918. if (!pci_bridge_child_ext_cfg_accessible(bridge)) {
  919. child->bus_flags |= PCI_BUS_FLAGS_NO_EXTCFG;
  920. pci_info(child, "extended config space not accessible\n");
  921. }
  922. /* Set up default resource pointers and names */
  923. for (i = 0; i < PCI_BRIDGE_RESOURCE_NUM; i++) {
  924. child->resource[i] = &bridge->resource[PCI_BRIDGE_RESOURCES+i];
  925. child->resource[i]->name = child->name;
  926. }
  927. bridge->subordinate = child;
  928. add_dev:
  929. pci_set_bus_msi_domain(child);
  930. ret = device_register(&child->dev);
  931. WARN_ON(ret < 0);
  932. pcibios_add_bus(child);
  933. if (child->ops->add_bus) {
  934. ret = child->ops->add_bus(child);
  935. if (WARN_ON(ret < 0))
  936. dev_err(&child->dev, "failed to add bus: %d\n", ret);
  937. }
  938. /* Create legacy_io and legacy_mem files for this bus */
  939. pci_create_legacy_files(child);
  940. return child;
  941. }
  942. struct pci_bus *pci_add_new_bus(struct pci_bus *parent, struct pci_dev *dev,
  943. int busnr)
  944. {
  945. struct pci_bus *child;
  946. child = pci_alloc_child_bus(parent, dev, busnr);
  947. if (child) {
  948. down_write(&pci_bus_sem);
  949. list_add_tail(&child->node, &parent->children);
  950. up_write(&pci_bus_sem);
  951. }
  952. return child;
  953. }
  954. EXPORT_SYMBOL(pci_add_new_bus);
  955. static void pci_enable_crs(struct pci_dev *pdev)
  956. {
  957. u16 root_cap = 0;
  958. /* Enable CRS Software Visibility if supported */
  959. pcie_capability_read_word(pdev, PCI_EXP_RTCAP, &root_cap);
  960. if (root_cap & PCI_EXP_RTCAP_CRSVIS)
  961. pcie_capability_set_word(pdev, PCI_EXP_RTCTL,
  962. PCI_EXP_RTCTL_CRSSVE);
  963. }
  964. static unsigned int pci_scan_child_bus_extend(struct pci_bus *bus,
  965. unsigned int available_buses);
  966. /**
  967. * pci_ea_fixed_busnrs() - Read fixed Secondary and Subordinate bus
  968. * numbers from EA capability.
  969. * @dev: Bridge
  970. * @sec: updated with secondary bus number from EA
  971. * @sub: updated with subordinate bus number from EA
  972. *
  973. * If @dev is a bridge with EA capability that specifies valid secondary
  974. * and subordinate bus numbers, return true with the bus numbers in @sec
  975. * and @sub. Otherwise return false.
  976. */
  977. static bool pci_ea_fixed_busnrs(struct pci_dev *dev, u8 *sec, u8 *sub)
  978. {
  979. int ea, offset;
  980. u32 dw;
  981. u8 ea_sec, ea_sub;
  982. if (dev->hdr_type != PCI_HEADER_TYPE_BRIDGE)
  983. return false;
  984. /* find PCI EA capability in list */
  985. ea = pci_find_capability(dev, PCI_CAP_ID_EA);
  986. if (!ea)
  987. return false;
  988. offset = ea + PCI_EA_FIRST_ENT;
  989. pci_read_config_dword(dev, offset, &dw);
  990. ea_sec = dw & PCI_EA_SEC_BUS_MASK;
  991. ea_sub = (dw & PCI_EA_SUB_BUS_MASK) >> PCI_EA_SUB_BUS_SHIFT;
  992. if (ea_sec == 0 || ea_sub < ea_sec)
  993. return false;
  994. *sec = ea_sec;
  995. *sub = ea_sub;
  996. return true;
  997. }
  998. /*
  999. * pci_scan_bridge_extend() - Scan buses behind a bridge
  1000. * @bus: Parent bus the bridge is on
  1001. * @dev: Bridge itself
  1002. * @max: Starting subordinate number of buses behind this bridge
  1003. * @available_buses: Total number of buses available for this bridge and
  1004. * the devices below. After the minimal bus space has
  1005. * been allocated the remaining buses will be
  1006. * distributed equally between hotplug-capable bridges.
  1007. * @pass: Either %0 (scan already configured bridges) or %1 (scan bridges
  1008. * that need to be reconfigured.
  1009. *
  1010. * If it's a bridge, configure it and scan the bus behind it.
  1011. * For CardBus bridges, we don't scan behind as the devices will
  1012. * be handled by the bridge driver itself.
  1013. *
  1014. * We need to process bridges in two passes -- first we scan those
  1015. * already configured by the BIOS and after we are done with all of
  1016. * them, we proceed to assigning numbers to the remaining buses in
  1017. * order to avoid overlaps between old and new bus numbers.
  1018. *
  1019. * Return: New subordinate number covering all buses behind this bridge.
  1020. */
  1021. static int pci_scan_bridge_extend(struct pci_bus *bus, struct pci_dev *dev,
  1022. int max, unsigned int available_buses,
  1023. int pass)
  1024. {
  1025. struct pci_bus *child;
  1026. int is_cardbus = (dev->hdr_type == PCI_HEADER_TYPE_CARDBUS);
  1027. u32 buses, i, j = 0;
  1028. u16 bctl;
  1029. u8 primary, secondary, subordinate;
  1030. int broken = 0;
  1031. bool fixed_buses;
  1032. u8 fixed_sec, fixed_sub;
  1033. int next_busnr;
  1034. /*
  1035. * Make sure the bridge is powered on to be able to access config
  1036. * space of devices below it.
  1037. */
  1038. pm_runtime_get_sync(&dev->dev);
  1039. pci_read_config_dword(dev, PCI_PRIMARY_BUS, &buses);
  1040. primary = buses & 0xFF;
  1041. secondary = (buses >> 8) & 0xFF;
  1042. subordinate = (buses >> 16) & 0xFF;
  1043. pci_dbg(dev, "scanning [bus %02x-%02x] behind bridge, pass %d\n",
  1044. secondary, subordinate, pass);
  1045. if (!primary && (primary != bus->number) && secondary && subordinate) {
  1046. pci_warn(dev, "Primary bus is hard wired to 0\n");
  1047. primary = bus->number;
  1048. }
  1049. /* Check if setup is sensible at all */
  1050. if (!pass &&
  1051. (primary != bus->number || secondary <= bus->number ||
  1052. secondary > subordinate)) {
  1053. pci_info(dev, "bridge configuration invalid ([bus %02x-%02x]), reconfiguring\n",
  1054. secondary, subordinate);
  1055. broken = 1;
  1056. }
  1057. /*
  1058. * Disable Master-Abort Mode during probing to avoid reporting of
  1059. * bus errors in some architectures.
  1060. */
  1061. pci_read_config_word(dev, PCI_BRIDGE_CONTROL, &bctl);
  1062. pci_write_config_word(dev, PCI_BRIDGE_CONTROL,
  1063. bctl & ~PCI_BRIDGE_CTL_MASTER_ABORT);
  1064. pci_enable_crs(dev);
  1065. if ((secondary || subordinate) && !pcibios_assign_all_busses() &&
  1066. !is_cardbus && !broken) {
  1067. unsigned int cmax;
  1068. /*
  1069. * Bus already configured by firmware, process it in the
  1070. * first pass and just note the configuration.
  1071. */
  1072. if (pass)
  1073. goto out;
  1074. /*
  1075. * The bus might already exist for two reasons: Either we
  1076. * are rescanning the bus or the bus is reachable through
  1077. * more than one bridge. The second case can happen with
  1078. * the i450NX chipset.
  1079. */
  1080. child = pci_find_bus(pci_domain_nr(bus), secondary);
  1081. if (!child) {
  1082. child = pci_add_new_bus(bus, dev, secondary);
  1083. if (!child)
  1084. goto out;
  1085. child->primary = primary;
  1086. pci_bus_insert_busn_res(child, secondary, subordinate);
  1087. child->bridge_ctl = bctl;
  1088. }
  1089. cmax = pci_scan_child_bus(child);
  1090. if (cmax > subordinate)
  1091. pci_warn(dev, "bridge has subordinate %02x but max busn %02x\n",
  1092. subordinate, cmax);
  1093. /* Subordinate should equal child->busn_res.end */
  1094. if (subordinate > max)
  1095. max = subordinate;
  1096. } else {
  1097. /*
  1098. * We need to assign a number to this bus which we always
  1099. * do in the second pass.
  1100. */
  1101. if (!pass) {
  1102. if (pcibios_assign_all_busses() || broken || is_cardbus)
  1103. /*
  1104. * Temporarily disable forwarding of the
  1105. * configuration cycles on all bridges in
  1106. * this bus segment to avoid possible
  1107. * conflicts in the second pass between two
  1108. * bridges programmed with overlapping bus
  1109. * ranges.
  1110. */
  1111. pci_write_config_dword(dev, PCI_PRIMARY_BUS,
  1112. buses & ~0xffffff);
  1113. goto out;
  1114. }
  1115. /* Clear errors */
  1116. pci_write_config_word(dev, PCI_STATUS, 0xffff);
  1117. /* Read bus numbers from EA Capability (if present) */
  1118. fixed_buses = pci_ea_fixed_busnrs(dev, &fixed_sec, &fixed_sub);
  1119. if (fixed_buses)
  1120. next_busnr = fixed_sec;
  1121. else
  1122. next_busnr = max + 1;
  1123. /*
  1124. * Prevent assigning a bus number that already exists.
  1125. * This can happen when a bridge is hot-plugged, so in this
  1126. * case we only re-scan this bus.
  1127. */
  1128. child = pci_find_bus(pci_domain_nr(bus), next_busnr);
  1129. if (!child) {
  1130. child = pci_add_new_bus(bus, dev, next_busnr);
  1131. if (!child)
  1132. goto out;
  1133. pci_bus_insert_busn_res(child, next_busnr,
  1134. bus->busn_res.end);
  1135. }
  1136. max++;
  1137. if (available_buses)
  1138. available_buses--;
  1139. buses = (buses & 0xff000000)
  1140. | ((unsigned int)(child->primary) << 0)
  1141. | ((unsigned int)(child->busn_res.start) << 8)
  1142. | ((unsigned int)(child->busn_res.end) << 16);
  1143. /*
  1144. * yenta.c forces a secondary latency timer of 176.
  1145. * Copy that behaviour here.
  1146. */
  1147. if (is_cardbus) {
  1148. buses &= ~0xff000000;
  1149. buses |= CARDBUS_LATENCY_TIMER << 24;
  1150. }
  1151. /* We need to blast all three values with a single write */
  1152. pci_write_config_dword(dev, PCI_PRIMARY_BUS, buses);
  1153. if (!is_cardbus) {
  1154. child->bridge_ctl = bctl;
  1155. max = pci_scan_child_bus_extend(child, available_buses);
  1156. } else {
  1157. /*
  1158. * For CardBus bridges, we leave 4 bus numbers as
  1159. * cards with a PCI-to-PCI bridge can be inserted
  1160. * later.
  1161. */
  1162. for (i = 0; i < CARDBUS_RESERVE_BUSNR; i++) {
  1163. struct pci_bus *parent = bus;
  1164. if (pci_find_bus(pci_domain_nr(bus),
  1165. max+i+1))
  1166. break;
  1167. while (parent->parent) {
  1168. if ((!pcibios_assign_all_busses()) &&
  1169. (parent->busn_res.end > max) &&
  1170. (parent->busn_res.end <= max+i)) {
  1171. j = 1;
  1172. }
  1173. parent = parent->parent;
  1174. }
  1175. if (j) {
  1176. /*
  1177. * Often, there are two CardBus
  1178. * bridges -- try to leave one
  1179. * valid bus number for each one.
  1180. */
  1181. i /= 2;
  1182. break;
  1183. }
  1184. }
  1185. max += i;
  1186. }
  1187. /*
  1188. * Set subordinate bus number to its real value.
  1189. * If fixed subordinate bus number exists from EA
  1190. * capability then use it.
  1191. */
  1192. if (fixed_buses)
  1193. max = fixed_sub;
  1194. pci_bus_update_busn_res_end(child, max);
  1195. pci_write_config_byte(dev, PCI_SUBORDINATE_BUS, max);
  1196. }
  1197. sprintf(child->name,
  1198. (is_cardbus ? "PCI CardBus %04x:%02x" : "PCI Bus %04x:%02x"),
  1199. pci_domain_nr(bus), child->number);
  1200. /* Check that all devices are accessible */
  1201. while (bus->parent) {
  1202. if ((child->busn_res.end > bus->busn_res.end) ||
  1203. (child->number > bus->busn_res.end) ||
  1204. (child->number < bus->number) ||
  1205. (child->busn_res.end < bus->number)) {
  1206. dev_info(&dev->dev, "devices behind bridge are unusable because %pR cannot be assigned for them\n",
  1207. &child->busn_res);
  1208. break;
  1209. }
  1210. bus = bus->parent;
  1211. }
  1212. out:
  1213. pci_write_config_word(dev, PCI_BRIDGE_CONTROL, bctl);
  1214. pm_runtime_put(&dev->dev);
  1215. return max;
  1216. }
  1217. /*
  1218. * pci_scan_bridge() - Scan buses behind a bridge
  1219. * @bus: Parent bus the bridge is on
  1220. * @dev: Bridge itself
  1221. * @max: Starting subordinate number of buses behind this bridge
  1222. * @pass: Either %0 (scan already configured bridges) or %1 (scan bridges
  1223. * that need to be reconfigured.
  1224. *
  1225. * If it's a bridge, configure it and scan the bus behind it.
  1226. * For CardBus bridges, we don't scan behind as the devices will
  1227. * be handled by the bridge driver itself.
  1228. *
  1229. * We need to process bridges in two passes -- first we scan those
  1230. * already configured by the BIOS and after we are done with all of
  1231. * them, we proceed to assigning numbers to the remaining buses in
  1232. * order to avoid overlaps between old and new bus numbers.
  1233. *
  1234. * Return: New subordinate number covering all buses behind this bridge.
  1235. */
  1236. int pci_scan_bridge(struct pci_bus *bus, struct pci_dev *dev, int max, int pass)
  1237. {
  1238. return pci_scan_bridge_extend(bus, dev, max, 0, pass);
  1239. }
  1240. EXPORT_SYMBOL(pci_scan_bridge);
  1241. /*
  1242. * Read interrupt line and base address registers.
  1243. * The architecture-dependent code can tweak these, of course.
  1244. */
  1245. static void pci_read_irq(struct pci_dev *dev)
  1246. {
  1247. unsigned char irq;
  1248. /* VFs are not allowed to use INTx, so skip the config reads */
  1249. if (dev->is_virtfn) {
  1250. dev->pin = 0;
  1251. dev->irq = 0;
  1252. return;
  1253. }
  1254. pci_read_config_byte(dev, PCI_INTERRUPT_PIN, &irq);
  1255. dev->pin = irq;
  1256. if (irq)
  1257. pci_read_config_byte(dev, PCI_INTERRUPT_LINE, &irq);
  1258. dev->irq = irq;
  1259. }
  1260. void set_pcie_port_type(struct pci_dev *pdev)
  1261. {
  1262. int pos;
  1263. u16 reg16;
  1264. int type;
  1265. struct pci_dev *parent;
  1266. pos = pci_find_capability(pdev, PCI_CAP_ID_EXP);
  1267. if (!pos)
  1268. return;
  1269. pdev->pcie_cap = pos;
  1270. pci_read_config_word(pdev, pos + PCI_EXP_FLAGS, &reg16);
  1271. pdev->pcie_flags_reg = reg16;
  1272. pci_read_config_word(pdev, pos + PCI_EXP_DEVCAP, &reg16);
  1273. pdev->pcie_mpss = reg16 & PCI_EXP_DEVCAP_PAYLOAD;
  1274. parent = pci_upstream_bridge(pdev);
  1275. if (!parent)
  1276. return;
  1277. /*
  1278. * Some systems do not identify their upstream/downstream ports
  1279. * correctly so detect impossible configurations here and correct
  1280. * the port type accordingly.
  1281. */
  1282. type = pci_pcie_type(pdev);
  1283. if (type == PCI_EXP_TYPE_DOWNSTREAM) {
  1284. /*
  1285. * If pdev claims to be downstream port but the parent
  1286. * device is also downstream port assume pdev is actually
  1287. * upstream port.
  1288. */
  1289. if (pcie_downstream_port(parent)) {
  1290. pci_info(pdev, "claims to be downstream port but is acting as upstream port, correcting type\n");
  1291. pdev->pcie_flags_reg &= ~PCI_EXP_FLAGS_TYPE;
  1292. pdev->pcie_flags_reg |= PCI_EXP_TYPE_UPSTREAM;
  1293. }
  1294. } else if (type == PCI_EXP_TYPE_UPSTREAM) {
  1295. /*
  1296. * If pdev claims to be upstream port but the parent
  1297. * device is also upstream port assume pdev is actually
  1298. * downstream port.
  1299. */
  1300. if (pci_pcie_type(parent) == PCI_EXP_TYPE_UPSTREAM) {
  1301. pci_info(pdev, "claims to be upstream port but is acting as downstream port, correcting type\n");
  1302. pdev->pcie_flags_reg &= ~PCI_EXP_FLAGS_TYPE;
  1303. pdev->pcie_flags_reg |= PCI_EXP_TYPE_DOWNSTREAM;
  1304. }
  1305. }
  1306. }
  1307. void set_pcie_hotplug_bridge(struct pci_dev *pdev)
  1308. {
  1309. u32 reg32;
  1310. pcie_capability_read_dword(pdev, PCI_EXP_SLTCAP, &reg32);
  1311. if (reg32 & PCI_EXP_SLTCAP_HPC)
  1312. pdev->is_hotplug_bridge = 1;
  1313. }
  1314. static void set_pcie_thunderbolt(struct pci_dev *dev)
  1315. {
  1316. int vsec = 0;
  1317. u32 header;
  1318. while ((vsec = pci_find_next_ext_capability(dev, vsec,
  1319. PCI_EXT_CAP_ID_VNDR))) {
  1320. pci_read_config_dword(dev, vsec + PCI_VNDR_HEADER, &header);
  1321. /* Is the device part of a Thunderbolt controller? */
  1322. if (dev->vendor == PCI_VENDOR_ID_INTEL &&
  1323. PCI_VNDR_HEADER_ID(header) == PCI_VSEC_ID_INTEL_TBT) {
  1324. dev->is_thunderbolt = 1;
  1325. return;
  1326. }
  1327. }
  1328. }
  1329. static void set_pcie_untrusted(struct pci_dev *dev)
  1330. {
  1331. struct pci_dev *parent;
  1332. /*
  1333. * If the upstream bridge is untrusted we treat this device
  1334. * untrusted as well.
  1335. */
  1336. parent = pci_upstream_bridge(dev);
  1337. if (parent && (parent->untrusted || parent->external_facing))
  1338. dev->untrusted = true;
  1339. }
  1340. /**
  1341. * pci_ext_cfg_is_aliased - Is ext config space just an alias of std config?
  1342. * @dev: PCI device
  1343. *
  1344. * PCI Express to PCI/PCI-X Bridge Specification, rev 1.0, 4.1.4 says that
  1345. * when forwarding a type1 configuration request the bridge must check that
  1346. * the extended register address field is zero. The bridge is not permitted
  1347. * to forward the transactions and must handle it as an Unsupported Request.
  1348. * Some bridges do not follow this rule and simply drop the extended register
  1349. * bits, resulting in the standard config space being aliased, every 256
  1350. * bytes across the entire configuration space. Test for this condition by
  1351. * comparing the first dword of each potential alias to the vendor/device ID.
  1352. * Known offenders:
  1353. * ASM1083/1085 PCIe-to-PCI Reversible Bridge (1b21:1080, rev 01 & 03)
  1354. * AMD/ATI SBx00 PCI to PCI Bridge (1002:4384, rev 40)
  1355. */
  1356. static bool pci_ext_cfg_is_aliased(struct pci_dev *dev)
  1357. {
  1358. #ifdef CONFIG_PCI_QUIRKS
  1359. int pos;
  1360. u32 header, tmp;
  1361. pci_read_config_dword(dev, PCI_VENDOR_ID, &header);
  1362. for (pos = PCI_CFG_SPACE_SIZE;
  1363. pos < PCI_CFG_SPACE_EXP_SIZE; pos += PCI_CFG_SPACE_SIZE) {
  1364. if (pci_read_config_dword(dev, pos, &tmp) != PCIBIOS_SUCCESSFUL
  1365. || header != tmp)
  1366. return false;
  1367. }
  1368. return true;
  1369. #else
  1370. return false;
  1371. #endif
  1372. }
  1373. /**
  1374. * pci_cfg_space_size - Get the configuration space size of the PCI device
  1375. * @dev: PCI device
  1376. *
  1377. * Regular PCI devices have 256 bytes, but PCI-X 2 and PCI Express devices
  1378. * have 4096 bytes. Even if the device is capable, that doesn't mean we can
  1379. * access it. Maybe we don't have a way to generate extended config space
  1380. * accesses, or the device is behind a reverse Express bridge. So we try
  1381. * reading the dword at 0x100 which must either be 0 or a valid extended
  1382. * capability header.
  1383. */
  1384. static int pci_cfg_space_size_ext(struct pci_dev *dev)
  1385. {
  1386. u32 status;
  1387. int pos = PCI_CFG_SPACE_SIZE;
  1388. if (pci_read_config_dword(dev, pos, &status) != PCIBIOS_SUCCESSFUL)
  1389. return PCI_CFG_SPACE_SIZE;
  1390. if (status == 0xffffffff || pci_ext_cfg_is_aliased(dev))
  1391. return PCI_CFG_SPACE_SIZE;
  1392. return PCI_CFG_SPACE_EXP_SIZE;
  1393. }
  1394. int pci_cfg_space_size(struct pci_dev *dev)
  1395. {
  1396. int pos;
  1397. u32 status;
  1398. u16 class;
  1399. #ifdef CONFIG_PCI_IOV
  1400. /*
  1401. * Per the SR-IOV specification (rev 1.1, sec 3.5), VFs are required to
  1402. * implement a PCIe capability and therefore must implement extended
  1403. * config space. We can skip the NO_EXTCFG test below and the
  1404. * reachability/aliasing test in pci_cfg_space_size_ext() by virtue of
  1405. * the fact that the SR-IOV capability on the PF resides in extended
  1406. * config space and must be accessible and non-aliased to have enabled
  1407. * support for this VF. This is a micro performance optimization for
  1408. * systems supporting many VFs.
  1409. */
  1410. if (dev->is_virtfn)
  1411. return PCI_CFG_SPACE_EXP_SIZE;
  1412. #endif
  1413. if (dev->bus->bus_flags & PCI_BUS_FLAGS_NO_EXTCFG)
  1414. return PCI_CFG_SPACE_SIZE;
  1415. class = dev->class >> 8;
  1416. if (class == PCI_CLASS_BRIDGE_HOST)
  1417. return pci_cfg_space_size_ext(dev);
  1418. if (pci_is_pcie(dev))
  1419. return pci_cfg_space_size_ext(dev);
  1420. pos = pci_find_capability(dev, PCI_CAP_ID_PCIX);
  1421. if (!pos)
  1422. return PCI_CFG_SPACE_SIZE;
  1423. pci_read_config_dword(dev, pos + PCI_X_STATUS, &status);
  1424. if (status & (PCI_X_STATUS_266MHZ | PCI_X_STATUS_533MHZ))
  1425. return pci_cfg_space_size_ext(dev);
  1426. return PCI_CFG_SPACE_SIZE;
  1427. }
  1428. static u32 pci_class(struct pci_dev *dev)
  1429. {
  1430. u32 class;
  1431. #ifdef CONFIG_PCI_IOV
  1432. if (dev->is_virtfn)
  1433. return dev->physfn->sriov->class;
  1434. #endif
  1435. pci_read_config_dword(dev, PCI_CLASS_REVISION, &class);
  1436. return class;
  1437. }
  1438. static void pci_subsystem_ids(struct pci_dev *dev, u16 *vendor, u16 *device)
  1439. {
  1440. #ifdef CONFIG_PCI_IOV
  1441. if (dev->is_virtfn) {
  1442. *vendor = dev->physfn->sriov->subsystem_vendor;
  1443. *device = dev->physfn->sriov->subsystem_device;
  1444. return;
  1445. }
  1446. #endif
  1447. pci_read_config_word(dev, PCI_SUBSYSTEM_VENDOR_ID, vendor);
  1448. pci_read_config_word(dev, PCI_SUBSYSTEM_ID, device);
  1449. }
  1450. static u8 pci_hdr_type(struct pci_dev *dev)
  1451. {
  1452. u8 hdr_type;
  1453. #ifdef CONFIG_PCI_IOV
  1454. if (dev->is_virtfn)
  1455. return dev->physfn->sriov->hdr_type;
  1456. #endif
  1457. pci_read_config_byte(dev, PCI_HEADER_TYPE, &hdr_type);
  1458. return hdr_type;
  1459. }
  1460. #define LEGACY_IO_RESOURCE (IORESOURCE_IO | IORESOURCE_PCI_FIXED)
  1461. static void pci_msi_setup_pci_dev(struct pci_dev *dev)
  1462. {
  1463. /*
  1464. * Disable the MSI hardware to avoid screaming interrupts
  1465. * during boot. This is the power on reset default so
  1466. * usually this should be a noop.
  1467. */
  1468. dev->msi_cap = pci_find_capability(dev, PCI_CAP_ID_MSI);
  1469. if (dev->msi_cap)
  1470. pci_msi_set_enable(dev, 0);
  1471. dev->msix_cap = pci_find_capability(dev, PCI_CAP_ID_MSIX);
  1472. if (dev->msix_cap)
  1473. pci_msix_clear_and_set_ctrl(dev, PCI_MSIX_FLAGS_ENABLE, 0);
  1474. }
  1475. /**
  1476. * pci_intx_mask_broken - Test PCI_COMMAND_INTX_DISABLE writability
  1477. * @dev: PCI device
  1478. *
  1479. * Test whether PCI_COMMAND_INTX_DISABLE is writable for @dev. Check this
  1480. * at enumeration-time to avoid modifying PCI_COMMAND at run-time.
  1481. */
  1482. static int pci_intx_mask_broken(struct pci_dev *dev)
  1483. {
  1484. u16 orig, toggle, new;
  1485. pci_read_config_word(dev, PCI_COMMAND, &orig);
  1486. toggle = orig ^ PCI_COMMAND_INTX_DISABLE;
  1487. pci_write_config_word(dev, PCI_COMMAND, toggle);
  1488. pci_read_config_word(dev, PCI_COMMAND, &new);
  1489. pci_write_config_word(dev, PCI_COMMAND, orig);
  1490. /*
  1491. * PCI_COMMAND_INTX_DISABLE was reserved and read-only prior to PCI
  1492. * r2.3, so strictly speaking, a device is not *broken* if it's not
  1493. * writable. But we'll live with the misnomer for now.
  1494. */
  1495. if (new != toggle)
  1496. return 1;
  1497. return 0;
  1498. }
  1499. static void early_dump_pci_device(struct pci_dev *pdev)
  1500. {
  1501. u32 value[256 / 4];
  1502. int i;
  1503. pci_info(pdev, "config space:\n");
  1504. for (i = 0; i < 256; i += 4)
  1505. pci_read_config_dword(pdev, i, &value[i / 4]);
  1506. print_hex_dump(KERN_INFO, "", DUMP_PREFIX_OFFSET, 16, 1,
  1507. value, 256, false);
  1508. }
  1509. /**
  1510. * pci_setup_device - Fill in class and map information of a device
  1511. * @dev: the device structure to fill
  1512. *
  1513. * Initialize the device structure with information about the device's
  1514. * vendor,class,memory and IO-space addresses, IRQ lines etc.
  1515. * Called at initialisation of the PCI subsystem and by CardBus services.
  1516. * Returns 0 on success and negative if unknown type of device (not normal,
  1517. * bridge or CardBus).
  1518. */
  1519. int pci_setup_device(struct pci_dev *dev)
  1520. {
  1521. u32 class;
  1522. u16 cmd;
  1523. u8 hdr_type;
  1524. int pos = 0;
  1525. struct pci_bus_region region;
  1526. struct resource *res;
  1527. hdr_type = pci_hdr_type(dev);
  1528. dev->sysdata = dev->bus->sysdata;
  1529. dev->dev.parent = dev->bus->bridge;
  1530. dev->dev.bus = &pci_bus_type;
  1531. dev->hdr_type = hdr_type & 0x7f;
  1532. dev->multifunction = !!(hdr_type & 0x80);
  1533. dev->error_state = pci_channel_io_normal;
  1534. set_pcie_port_type(dev);
  1535. pci_dev_assign_slot(dev);
  1536. /*
  1537. * Assume 32-bit PCI; let 64-bit PCI cards (which are far rarer)
  1538. * set this higher, assuming the system even supports it.
  1539. */
  1540. dev->dma_mask = 0xffffffff;
  1541. dev_set_name(&dev->dev, "%04x:%02x:%02x.%d", pci_domain_nr(dev->bus),
  1542. dev->bus->number, PCI_SLOT(dev->devfn),
  1543. PCI_FUNC(dev->devfn));
  1544. class = pci_class(dev);
  1545. dev->revision = class & 0xff;
  1546. dev->class = class >> 8; /* upper 3 bytes */
  1547. if (pci_early_dump)
  1548. early_dump_pci_device(dev);
  1549. /* Need to have dev->class ready */
  1550. dev->cfg_size = pci_cfg_space_size(dev);
  1551. /* Need to have dev->cfg_size ready */
  1552. set_pcie_thunderbolt(dev);
  1553. set_pcie_untrusted(dev);
  1554. /* "Unknown power state" */
  1555. dev->current_state = PCI_UNKNOWN;
  1556. /* Early fixups, before probing the BARs */
  1557. pci_fixup_device(pci_fixup_early, dev);
  1558. pci_info(dev, "[%04x:%04x] type %02x class %#08x\n",
  1559. dev->vendor, dev->device, dev->hdr_type, dev->class);
  1560. /* Device class may be changed after fixup */
  1561. class = dev->class >> 8;
  1562. if (dev->non_compliant_bars && !dev->mmio_always_on) {
  1563. pci_read_config_word(dev, PCI_COMMAND, &cmd);
  1564. if (cmd & (PCI_COMMAND_IO | PCI_COMMAND_MEMORY)) {
  1565. pci_info(dev, "device has non-compliant BARs; disabling IO/MEM decoding\n");
  1566. cmd &= ~PCI_COMMAND_IO;
  1567. cmd &= ~PCI_COMMAND_MEMORY;
  1568. pci_write_config_word(dev, PCI_COMMAND, cmd);
  1569. }
  1570. }
  1571. dev->broken_intx_masking = pci_intx_mask_broken(dev);
  1572. switch (dev->hdr_type) { /* header type */
  1573. case PCI_HEADER_TYPE_NORMAL: /* standard header */
  1574. if (class == PCI_CLASS_BRIDGE_PCI)
  1575. goto bad;
  1576. pci_read_irq(dev);
  1577. pci_read_bases(dev, 6, PCI_ROM_ADDRESS);
  1578. pci_subsystem_ids(dev, &dev->subsystem_vendor, &dev->subsystem_device);
  1579. /*
  1580. * Do the ugly legacy mode stuff here rather than broken chip
  1581. * quirk code. Legacy mode ATA controllers have fixed
  1582. * addresses. These are not always echoed in BAR0-3, and
  1583. * BAR0-3 in a few cases contain junk!
  1584. */
  1585. if (class == PCI_CLASS_STORAGE_IDE) {
  1586. u8 progif;
  1587. pci_read_config_byte(dev, PCI_CLASS_PROG, &progif);
  1588. if ((progif & 1) == 0) {
  1589. region.start = 0x1F0;
  1590. region.end = 0x1F7;
  1591. res = &dev->resource[0];
  1592. res->flags = LEGACY_IO_RESOURCE;
  1593. pcibios_bus_to_resource(dev->bus, res, &region);
  1594. pci_info(dev, "legacy IDE quirk: reg 0x10: %pR\n",
  1595. res);
  1596. region.start = 0x3F6;
  1597. region.end = 0x3F6;
  1598. res = &dev->resource[1];
  1599. res->flags = LEGACY_IO_RESOURCE;
  1600. pcibios_bus_to_resource(dev->bus, res, &region);
  1601. pci_info(dev, "legacy IDE quirk: reg 0x14: %pR\n",
  1602. res);
  1603. }
  1604. if ((progif & 4) == 0) {
  1605. region.start = 0x170;
  1606. region.end = 0x177;
  1607. res = &dev->resource[2];
  1608. res->flags = LEGACY_IO_RESOURCE;
  1609. pcibios_bus_to_resource(dev->bus, res, &region);
  1610. pci_info(dev, "legacy IDE quirk: reg 0x18: %pR\n",
  1611. res);
  1612. region.start = 0x376;
  1613. region.end = 0x376;
  1614. res = &dev->resource[3];
  1615. res->flags = LEGACY_IO_RESOURCE;
  1616. pcibios_bus_to_resource(dev->bus, res, &region);
  1617. pci_info(dev, "legacy IDE quirk: reg 0x1c: %pR\n",
  1618. res);
  1619. }
  1620. }
  1621. break;
  1622. case PCI_HEADER_TYPE_BRIDGE: /* bridge header */
  1623. /*
  1624. * The PCI-to-PCI bridge spec requires that subtractive
  1625. * decoding (i.e. transparent) bridge must have programming
  1626. * interface code of 0x01.
  1627. */
  1628. pci_read_irq(dev);
  1629. dev->transparent = ((dev->class & 0xff) == 1);
  1630. pci_read_bases(dev, 2, PCI_ROM_ADDRESS1);
  1631. pci_read_bridge_windows(dev);
  1632. set_pcie_hotplug_bridge(dev);
  1633. pos = pci_find_capability(dev, PCI_CAP_ID_SSVID);
  1634. if (pos) {
  1635. pci_read_config_word(dev, pos + PCI_SSVID_VENDOR_ID, &dev->subsystem_vendor);
  1636. pci_read_config_word(dev, pos + PCI_SSVID_DEVICE_ID, &dev->subsystem_device);
  1637. }
  1638. break;
  1639. case PCI_HEADER_TYPE_CARDBUS: /* CardBus bridge header */
  1640. if (class != PCI_CLASS_BRIDGE_CARDBUS)
  1641. goto bad;
  1642. pci_read_irq(dev);
  1643. pci_read_bases(dev, 1, 0);
  1644. pci_read_config_word(dev, PCI_CB_SUBSYSTEM_VENDOR_ID, &dev->subsystem_vendor);
  1645. pci_read_config_word(dev, PCI_CB_SUBSYSTEM_ID, &dev->subsystem_device);
  1646. break;
  1647. default: /* unknown header */
  1648. pci_err(dev, "unknown header type %02x, ignoring device\n",
  1649. dev->hdr_type);
  1650. return -EIO;
  1651. bad:
  1652. pci_err(dev, "ignoring class %#08x (doesn't match header type %02x)\n",
  1653. dev->class, dev->hdr_type);
  1654. dev->class = PCI_CLASS_NOT_DEFINED << 8;
  1655. }
  1656. /* We found a fine healthy device, go go go... */
  1657. return 0;
  1658. }
  1659. static void pci_configure_mps(struct pci_dev *dev)
  1660. {
  1661. struct pci_dev *bridge = pci_upstream_bridge(dev);
  1662. int mps, mpss, p_mps, rc;
  1663. if (!pci_is_pcie(dev))
  1664. return;
  1665. /* MPS and MRRS fields are of type 'RsvdP' for VFs, short-circuit out */
  1666. if (dev->is_virtfn)
  1667. return;
  1668. /*
  1669. * For Root Complex Integrated Endpoints, program the maximum
  1670. * supported value unless limited by the PCIE_BUS_PEER2PEER case.
  1671. */
  1672. if (pci_pcie_type(dev) == PCI_EXP_TYPE_RC_END) {
  1673. if (pcie_bus_config == PCIE_BUS_PEER2PEER)
  1674. mps = 128;
  1675. else
  1676. mps = 128 << dev->pcie_mpss;
  1677. rc = pcie_set_mps(dev, mps);
  1678. if (rc) {
  1679. pci_warn(dev, "can't set Max Payload Size to %d; if necessary, use \"pci=pcie_bus_safe\" and report a bug\n",
  1680. mps);
  1681. }
  1682. return;
  1683. }
  1684. if (!bridge || !pci_is_pcie(bridge))
  1685. return;
  1686. mps = pcie_get_mps(dev);
  1687. p_mps = pcie_get_mps(bridge);
  1688. if (mps == p_mps)
  1689. return;
  1690. if (pcie_bus_config == PCIE_BUS_TUNE_OFF) {
  1691. pci_warn(dev, "Max Payload Size %d, but upstream %s set to %d; if necessary, use \"pci=pcie_bus_safe\" and report a bug\n",
  1692. mps, pci_name(bridge), p_mps);
  1693. return;
  1694. }
  1695. /*
  1696. * Fancier MPS configuration is done later by
  1697. * pcie_bus_configure_settings()
  1698. */
  1699. if (pcie_bus_config != PCIE_BUS_DEFAULT)
  1700. return;
  1701. mpss = 128 << dev->pcie_mpss;
  1702. if (mpss < p_mps && pci_pcie_type(bridge) == PCI_EXP_TYPE_ROOT_PORT) {
  1703. pcie_set_mps(bridge, mpss);
  1704. pci_info(dev, "Upstream bridge's Max Payload Size set to %d (was %d, max %d)\n",
  1705. mpss, p_mps, 128 << bridge->pcie_mpss);
  1706. p_mps = pcie_get_mps(bridge);
  1707. }
  1708. rc = pcie_set_mps(dev, p_mps);
  1709. if (rc) {
  1710. pci_warn(dev, "can't set Max Payload Size to %d; if necessary, use \"pci=pcie_bus_safe\" and report a bug\n",
  1711. p_mps);
  1712. return;
  1713. }
  1714. pci_info(dev, "Max Payload Size set to %d (was %d, max %d)\n",
  1715. p_mps, mps, mpss);
  1716. }
  1717. int pci_configure_extended_tags(struct pci_dev *dev, void *ign)
  1718. {
  1719. struct pci_host_bridge *host;
  1720. u32 cap;
  1721. u16 ctl;
  1722. int ret;
  1723. if (!pci_is_pcie(dev))
  1724. return 0;
  1725. ret = pcie_capability_read_dword(dev, PCI_EXP_DEVCAP, &cap);
  1726. if (ret)
  1727. return 0;
  1728. if (!(cap & PCI_EXP_DEVCAP_EXT_TAG))
  1729. return 0;
  1730. ret = pcie_capability_read_word(dev, PCI_EXP_DEVCTL, &ctl);
  1731. if (ret)
  1732. return 0;
  1733. host = pci_find_host_bridge(dev->bus);
  1734. if (!host)
  1735. return 0;
  1736. /*
  1737. * If some device in the hierarchy doesn't handle Extended Tags
  1738. * correctly, make sure they're disabled.
  1739. */
  1740. if (host->no_ext_tags) {
  1741. if (ctl & PCI_EXP_DEVCTL_EXT_TAG) {
  1742. pci_info(dev, "disabling Extended Tags\n");
  1743. pcie_capability_clear_word(dev, PCI_EXP_DEVCTL,
  1744. PCI_EXP_DEVCTL_EXT_TAG);
  1745. }
  1746. return 0;
  1747. }
  1748. if (!(ctl & PCI_EXP_DEVCTL_EXT_TAG)) {
  1749. pci_info(dev, "enabling Extended Tags\n");
  1750. pcie_capability_set_word(dev, PCI_EXP_DEVCTL,
  1751. PCI_EXP_DEVCTL_EXT_TAG);
  1752. }
  1753. return 0;
  1754. }
  1755. /**
  1756. * pcie_relaxed_ordering_enabled - Probe for PCIe relaxed ordering enable
  1757. * @dev: PCI device to query
  1758. *
  1759. * Returns true if the device has enabled relaxed ordering attribute.
  1760. */
  1761. bool pcie_relaxed_ordering_enabled(struct pci_dev *dev)
  1762. {
  1763. u16 v;
  1764. pcie_capability_read_word(dev, PCI_EXP_DEVCTL, &v);
  1765. return !!(v & PCI_EXP_DEVCTL_RELAX_EN);
  1766. }
  1767. EXPORT_SYMBOL(pcie_relaxed_ordering_enabled);
  1768. static void pci_configure_relaxed_ordering(struct pci_dev *dev)
  1769. {
  1770. struct pci_dev *root;
  1771. /* PCI_EXP_DEVICE_RELAX_EN is RsvdP in VFs */
  1772. if (dev->is_virtfn)
  1773. return;
  1774. if (!pcie_relaxed_ordering_enabled(dev))
  1775. return;
  1776. /*
  1777. * For now, we only deal with Relaxed Ordering issues with Root
  1778. * Ports. Peer-to-Peer DMA is another can of worms.
  1779. */
  1780. root = pcie_find_root_port(dev);
  1781. if (!root)
  1782. return;
  1783. if (root->dev_flags & PCI_DEV_FLAGS_NO_RELAXED_ORDERING) {
  1784. pcie_capability_clear_word(dev, PCI_EXP_DEVCTL,
  1785. PCI_EXP_DEVCTL_RELAX_EN);
  1786. pci_info(dev, "Relaxed Ordering disabled because the Root Port didn't support it\n");
  1787. }
  1788. }
  1789. static void pci_configure_ltr(struct pci_dev *dev)
  1790. {
  1791. #ifdef CONFIG_PCIEASPM
  1792. struct pci_host_bridge *host = pci_find_host_bridge(dev->bus);
  1793. struct pci_dev *bridge;
  1794. u32 cap, ctl;
  1795. if (!pci_is_pcie(dev))
  1796. return;
  1797. /* Read L1 PM substate capabilities */
  1798. dev->l1ss = pci_find_ext_capability(dev, PCI_EXT_CAP_ID_L1SS);
  1799. pcie_capability_read_dword(dev, PCI_EXP_DEVCAP2, &cap);
  1800. if (!(cap & PCI_EXP_DEVCAP2_LTR))
  1801. return;
  1802. pcie_capability_read_dword(dev, PCI_EXP_DEVCTL2, &ctl);
  1803. if (ctl & PCI_EXP_DEVCTL2_LTR_EN) {
  1804. if (pci_pcie_type(dev) == PCI_EXP_TYPE_ROOT_PORT) {
  1805. dev->ltr_path = 1;
  1806. return;
  1807. }
  1808. bridge = pci_upstream_bridge(dev);
  1809. if (bridge && bridge->ltr_path)
  1810. dev->ltr_path = 1;
  1811. return;
  1812. }
  1813. if (!host->native_ltr)
  1814. return;
  1815. /*
  1816. * Software must not enable LTR in an Endpoint unless the Root
  1817. * Complex and all intermediate Switches indicate support for LTR.
  1818. * PCIe r4.0, sec 6.18.
  1819. */
  1820. if (pci_pcie_type(dev) == PCI_EXP_TYPE_ROOT_PORT ||
  1821. ((bridge = pci_upstream_bridge(dev)) &&
  1822. bridge->ltr_path)) {
  1823. pcie_capability_set_word(dev, PCI_EXP_DEVCTL2,
  1824. PCI_EXP_DEVCTL2_LTR_EN);
  1825. dev->ltr_path = 1;
  1826. }
  1827. #endif
  1828. }
  1829. static void pci_configure_eetlp_prefix(struct pci_dev *dev)
  1830. {
  1831. #ifdef CONFIG_PCI_PASID
  1832. struct pci_dev *bridge;
  1833. int pcie_type;
  1834. u32 cap;
  1835. if (!pci_is_pcie(dev))
  1836. return;
  1837. pcie_capability_read_dword(dev, PCI_EXP_DEVCAP2, &cap);
  1838. if (!(cap & PCI_EXP_DEVCAP2_EE_PREFIX))
  1839. return;
  1840. pcie_type = pci_pcie_type(dev);
  1841. if (pcie_type == PCI_EXP_TYPE_ROOT_PORT ||
  1842. pcie_type == PCI_EXP_TYPE_RC_END)
  1843. dev->eetlp_prefix_path = 1;
  1844. else {
  1845. bridge = pci_upstream_bridge(dev);
  1846. if (bridge && bridge->eetlp_prefix_path)
  1847. dev->eetlp_prefix_path = 1;
  1848. }
  1849. #endif
  1850. }
  1851. static void pci_configure_serr(struct pci_dev *dev)
  1852. {
  1853. u16 control;
  1854. if (dev->hdr_type == PCI_HEADER_TYPE_BRIDGE) {
  1855. /*
  1856. * A bridge will not forward ERR_ messages coming from an
  1857. * endpoint unless SERR# forwarding is enabled.
  1858. */
  1859. pci_read_config_word(dev, PCI_BRIDGE_CONTROL, &control);
  1860. if (!(control & PCI_BRIDGE_CTL_SERR)) {
  1861. control |= PCI_BRIDGE_CTL_SERR;
  1862. pci_write_config_word(dev, PCI_BRIDGE_CONTROL, control);
  1863. }
  1864. }
  1865. }
  1866. static void pci_configure_device(struct pci_dev *dev)
  1867. {
  1868. pci_configure_mps(dev);
  1869. pci_configure_extended_tags(dev, NULL);
  1870. pci_configure_relaxed_ordering(dev);
  1871. pci_configure_ltr(dev);
  1872. pci_configure_eetlp_prefix(dev);
  1873. pci_configure_serr(dev);
  1874. pci_acpi_program_hp_params(dev);
  1875. }
  1876. static void pci_release_capabilities(struct pci_dev *dev)
  1877. {
  1878. pci_aer_exit(dev);
  1879. pci_vpd_release(dev);
  1880. pci_iov_release(dev);
  1881. pci_free_cap_save_buffers(dev);
  1882. }
  1883. /**
  1884. * pci_release_dev - Free a PCI device structure when all users of it are
  1885. * finished
  1886. * @dev: device that's been disconnected
  1887. *
  1888. * Will be called only by the device core when all users of this PCI device are
  1889. * done.
  1890. */
  1891. static void pci_release_dev(struct device *dev)
  1892. {
  1893. struct pci_dev *pci_dev;
  1894. pci_dev = to_pci_dev(dev);
  1895. pci_release_capabilities(pci_dev);
  1896. pci_release_of_node(pci_dev);
  1897. pcibios_release_device(pci_dev);
  1898. pci_bus_put(pci_dev->bus);
  1899. kfree(pci_dev->driver_override);
  1900. bitmap_free(pci_dev->dma_alias_mask);
  1901. kfree(pci_dev);
  1902. }
  1903. struct pci_dev *pci_alloc_dev(struct pci_bus *bus)
  1904. {
  1905. struct pci_dev *dev;
  1906. dev = kzalloc(sizeof(struct pci_dev), GFP_KERNEL);
  1907. if (!dev)
  1908. return NULL;
  1909. INIT_LIST_HEAD(&dev->bus_list);
  1910. dev->dev.type = &pci_dev_type;
  1911. dev->bus = pci_bus_get(bus);
  1912. return dev;
  1913. }
  1914. EXPORT_SYMBOL(pci_alloc_dev);
  1915. static bool pci_bus_crs_vendor_id(u32 l)
  1916. {
  1917. return (l & 0xffff) == 0x0001;
  1918. }
  1919. static bool pci_bus_wait_crs(struct pci_bus *bus, int devfn, u32 *l,
  1920. int timeout)
  1921. {
  1922. int delay = 1;
  1923. if (!pci_bus_crs_vendor_id(*l))
  1924. return true; /* not a CRS completion */
  1925. if (!timeout)
  1926. return false; /* CRS, but caller doesn't want to wait */
  1927. /*
  1928. * We got the reserved Vendor ID that indicates a completion with
  1929. * Configuration Request Retry Status (CRS). Retry until we get a
  1930. * valid Vendor ID or we time out.
  1931. */
  1932. while (pci_bus_crs_vendor_id(*l)) {
  1933. if (delay > timeout) {
  1934. pr_warn("pci %04x:%02x:%02x.%d: not ready after %dms; giving up\n",
  1935. pci_domain_nr(bus), bus->number,
  1936. PCI_SLOT(devfn), PCI_FUNC(devfn), delay - 1);
  1937. return false;
  1938. }
  1939. if (delay >= 1000)
  1940. pr_info("pci %04x:%02x:%02x.%d: not ready after %dms; waiting\n",
  1941. pci_domain_nr(bus), bus->number,
  1942. PCI_SLOT(devfn), PCI_FUNC(devfn), delay - 1);
  1943. msleep(delay);
  1944. delay *= 2;
  1945. if (pci_bus_read_config_dword(bus, devfn, PCI_VENDOR_ID, l))
  1946. return false;
  1947. }
  1948. if (delay >= 1000)
  1949. pr_info("pci %04x:%02x:%02x.%d: ready after %dms\n",
  1950. pci_domain_nr(bus), bus->number,
  1951. PCI_SLOT(devfn), PCI_FUNC(devfn), delay - 1);
  1952. return true;
  1953. }
  1954. bool pci_bus_generic_read_dev_vendor_id(struct pci_bus *bus, int devfn, u32 *l,
  1955. int timeout)
  1956. {
  1957. if (pci_bus_read_config_dword(bus, devfn, PCI_VENDOR_ID, l))
  1958. return false;
  1959. /* Some broken boards return 0 or ~0 if a slot is empty: */
  1960. if (*l == 0xffffffff || *l == 0x00000000 ||
  1961. *l == 0x0000ffff || *l == 0xffff0000)
  1962. return false;
  1963. if (pci_bus_crs_vendor_id(*l))
  1964. return pci_bus_wait_crs(bus, devfn, l, timeout);
  1965. return true;
  1966. }
  1967. bool pci_bus_read_dev_vendor_id(struct pci_bus *bus, int devfn, u32 *l,
  1968. int timeout)
  1969. {
  1970. #ifdef CONFIG_PCI_QUIRKS
  1971. struct pci_dev *bridge = bus->self;
  1972. /*
  1973. * Certain IDT switches have an issue where they improperly trigger
  1974. * ACS Source Validation errors on completions for config reads.
  1975. */
  1976. if (bridge && bridge->vendor == PCI_VENDOR_ID_IDT &&
  1977. bridge->device == 0x80b5)
  1978. return pci_idt_bus_quirk(bus, devfn, l, timeout);
  1979. #endif
  1980. return pci_bus_generic_read_dev_vendor_id(bus, devfn, l, timeout);
  1981. }
  1982. EXPORT_SYMBOL(pci_bus_read_dev_vendor_id);
  1983. /*
  1984. * Read the config data for a PCI device, sanity-check it,
  1985. * and fill in the dev structure.
  1986. */
  1987. static struct pci_dev *pci_scan_device(struct pci_bus *bus, int devfn)
  1988. {
  1989. struct pci_dev *dev;
  1990. u32 l;
  1991. if (!pci_bus_read_dev_vendor_id(bus, devfn, &l, 60*1000))
  1992. return NULL;
  1993. dev = pci_alloc_dev(bus);
  1994. if (!dev)
  1995. return NULL;
  1996. dev->devfn = devfn;
  1997. dev->vendor = l & 0xffff;
  1998. dev->device = (l >> 16) & 0xffff;
  1999. pci_set_of_node(dev);
  2000. if (pci_setup_device(dev)) {
  2001. pci_release_of_node(dev);
  2002. pci_bus_put(dev->bus);
  2003. kfree(dev);
  2004. return NULL;
  2005. }
  2006. return dev;
  2007. }
  2008. void pcie_report_downtraining(struct pci_dev *dev)
  2009. {
  2010. if (!pci_is_pcie(dev))
  2011. return;
  2012. /* Look from the device up to avoid downstream ports with no devices */
  2013. if ((pci_pcie_type(dev) != PCI_EXP_TYPE_ENDPOINT) &&
  2014. (pci_pcie_type(dev) != PCI_EXP_TYPE_LEG_END) &&
  2015. (pci_pcie_type(dev) != PCI_EXP_TYPE_UPSTREAM))
  2016. return;
  2017. /* Multi-function PCIe devices share the same link/status */
  2018. if (PCI_FUNC(dev->devfn) != 0 || dev->is_virtfn)
  2019. return;
  2020. /* Print link status only if the device is constrained by the fabric */
  2021. __pcie_print_link_status(dev, false);
  2022. }
  2023. static void pci_init_capabilities(struct pci_dev *dev)
  2024. {
  2025. pci_ea_init(dev); /* Enhanced Allocation */
  2026. /* Setup MSI caps & disable MSI/MSI-X interrupts */
  2027. pci_msi_setup_pci_dev(dev);
  2028. /* Buffers for saving PCIe and PCI-X capabilities */
  2029. pci_allocate_cap_save_buffers(dev);
  2030. pci_pm_init(dev); /* Power Management */
  2031. pci_vpd_init(dev); /* Vital Product Data */
  2032. pci_configure_ari(dev); /* Alternative Routing-ID Forwarding */
  2033. pci_iov_init(dev); /* Single Root I/O Virtualization */
  2034. pci_ats_init(dev); /* Address Translation Services */
  2035. pci_pri_init(dev); /* Page Request Interface */
  2036. pci_pasid_init(dev); /* Process Address Space ID */
  2037. pci_acs_init(dev); /* Access Control Services */
  2038. pci_ptm_init(dev); /* Precision Time Measurement */
  2039. pci_aer_init(dev); /* Advanced Error Reporting */
  2040. pci_dpc_init(dev); /* Downstream Port Containment */
  2041. pcie_report_downtraining(dev);
  2042. if (pci_probe_reset_function(dev) == 0)
  2043. dev->reset_fn = 1;
  2044. }
  2045. /*
  2046. * This is the equivalent of pci_host_bridge_msi_domain() that acts on
  2047. * devices. Firmware interfaces that can select the MSI domain on a
  2048. * per-device basis should be called from here.
  2049. */
  2050. static struct irq_domain *pci_dev_msi_domain(struct pci_dev *dev)
  2051. {
  2052. struct irq_domain *d;
  2053. /*
  2054. * If a domain has been set through the pcibios_add_device()
  2055. * callback, then this is the one (platform code knows best).
  2056. */
  2057. d = dev_get_msi_domain(&dev->dev);
  2058. if (d)
  2059. return d;
  2060. /*
  2061. * Let's see if we have a firmware interface able to provide
  2062. * the domain.
  2063. */
  2064. d = pci_msi_get_device_domain(dev);
  2065. if (d)
  2066. return d;
  2067. return NULL;
  2068. }
  2069. static void pci_set_msi_domain(struct pci_dev *dev)
  2070. {
  2071. struct irq_domain *d;
  2072. /*
  2073. * If the platform or firmware interfaces cannot supply a
  2074. * device-specific MSI domain, then inherit the default domain
  2075. * from the host bridge itself.
  2076. */
  2077. d = pci_dev_msi_domain(dev);
  2078. if (!d)
  2079. d = dev_get_msi_domain(&dev->bus->dev);
  2080. dev_set_msi_domain(&dev->dev, d);
  2081. }
  2082. void pci_device_add(struct pci_dev *dev, struct pci_bus *bus)
  2083. {
  2084. int ret;
  2085. pci_configure_device(dev);
  2086. device_initialize(&dev->dev);
  2087. dev->dev.release = pci_release_dev;
  2088. set_dev_node(&dev->dev, pcibus_to_node(bus));
  2089. dev->dev.dma_mask = &dev->dma_mask;
  2090. dev->dev.dma_parms = &dev->dma_parms;
  2091. dev->dev.coherent_dma_mask = 0xffffffffull;
  2092. dma_set_max_seg_size(&dev->dev, 65536);
  2093. dma_set_seg_boundary(&dev->dev, 0xffffffff);
  2094. /* Fix up broken headers */
  2095. pci_fixup_device(pci_fixup_header, dev);
  2096. pci_reassigndev_resource_alignment(dev);
  2097. dev->state_saved = false;
  2098. pci_init_capabilities(dev);
  2099. /*
  2100. * Add the device to our list of discovered devices
  2101. * and the bus list for fixup functions, etc.
  2102. */
  2103. down_write(&pci_bus_sem);
  2104. list_add_tail(&dev->bus_list, &bus->devices);
  2105. up_write(&pci_bus_sem);
  2106. ret = pcibios_add_device(dev);
  2107. WARN_ON(ret < 0);
  2108. /* Set up MSI IRQ domain */
  2109. pci_set_msi_domain(dev);
  2110. /* Notifier could use PCI capabilities */
  2111. dev->match_driver = false;
  2112. ret = device_add(&dev->dev);
  2113. WARN_ON(ret < 0);
  2114. }
  2115. struct pci_dev *pci_scan_single_device(struct pci_bus *bus, int devfn)
  2116. {
  2117. struct pci_dev *dev;
  2118. dev = pci_get_slot(bus, devfn);
  2119. if (dev) {
  2120. pci_dev_put(dev);
  2121. return dev;
  2122. }
  2123. dev = pci_scan_device(bus, devfn);
  2124. if (!dev)
  2125. return NULL;
  2126. pci_device_add(dev, bus);
  2127. return dev;
  2128. }
  2129. EXPORT_SYMBOL(pci_scan_single_device);
  2130. static unsigned next_fn(struct pci_bus *bus, struct pci_dev *dev, unsigned fn)
  2131. {
  2132. int pos;
  2133. u16 cap = 0;
  2134. unsigned next_fn;
  2135. if (pci_ari_enabled(bus)) {
  2136. if (!dev)
  2137. return 0;
  2138. pos = pci_find_ext_capability(dev, PCI_EXT_CAP_ID_ARI);
  2139. if (!pos)
  2140. return 0;
  2141. pci_read_config_word(dev, pos + PCI_ARI_CAP, &cap);
  2142. next_fn = PCI_ARI_CAP_NFN(cap);
  2143. if (next_fn <= fn)
  2144. return 0; /* protect against malformed list */
  2145. return next_fn;
  2146. }
  2147. /* dev may be NULL for non-contiguous multifunction devices */
  2148. if (!dev || dev->multifunction)
  2149. return (fn + 1) % 8;
  2150. return 0;
  2151. }
  2152. static int only_one_child(struct pci_bus *bus)
  2153. {
  2154. struct pci_dev *bridge = bus->self;
  2155. /*
  2156. * Systems with unusual topologies set PCI_SCAN_ALL_PCIE_DEVS so
  2157. * we scan for all possible devices, not just Device 0.
  2158. */
  2159. if (pci_has_flag(PCI_SCAN_ALL_PCIE_DEVS))
  2160. return 0;
  2161. /*
  2162. * A PCIe Downstream Port normally leads to a Link with only Device
  2163. * 0 on it (PCIe spec r3.1, sec 7.3.1). As an optimization, scan
  2164. * only for Device 0 in that situation.
  2165. */
  2166. if (bridge && pci_is_pcie(bridge) && pcie_downstream_port(bridge))
  2167. return 1;
  2168. return 0;
  2169. }
  2170. /**
  2171. * pci_scan_slot - Scan a PCI slot on a bus for devices
  2172. * @bus: PCI bus to scan
  2173. * @devfn: slot number to scan (must have zero function)
  2174. *
  2175. * Scan a PCI slot on the specified PCI bus for devices, adding
  2176. * discovered devices to the @bus->devices list. New devices
  2177. * will not have is_added set.
  2178. *
  2179. * Returns the number of new devices found.
  2180. */
  2181. int pci_scan_slot(struct pci_bus *bus, int devfn)
  2182. {
  2183. unsigned fn, nr = 0;
  2184. struct pci_dev *dev;
  2185. if (only_one_child(bus) && (devfn > 0))
  2186. return 0; /* Already scanned the entire slot */
  2187. dev = pci_scan_single_device(bus, devfn);
  2188. if (!dev)
  2189. return 0;
  2190. if (!pci_dev_is_added(dev))
  2191. nr++;
  2192. for (fn = next_fn(bus, dev, 0); fn > 0; fn = next_fn(bus, dev, fn)) {
  2193. dev = pci_scan_single_device(bus, devfn + fn);
  2194. if (dev) {
  2195. if (!pci_dev_is_added(dev))
  2196. nr++;
  2197. dev->multifunction = 1;
  2198. }
  2199. }
  2200. /* Only one slot has PCIe device */
  2201. if (bus->self && nr)
  2202. pcie_aspm_init_link_state(bus->self);
  2203. return nr;
  2204. }
  2205. EXPORT_SYMBOL(pci_scan_slot);
  2206. static int pcie_find_smpss(struct pci_dev *dev, void *data)
  2207. {
  2208. u8 *smpss = data;
  2209. if (!pci_is_pcie(dev))
  2210. return 0;
  2211. /*
  2212. * We don't have a way to change MPS settings on devices that have
  2213. * drivers attached. A hot-added device might support only the minimum
  2214. * MPS setting (MPS=128). Therefore, if the fabric contains a bridge
  2215. * where devices may be hot-added, we limit the fabric MPS to 128 so
  2216. * hot-added devices will work correctly.
  2217. *
  2218. * However, if we hot-add a device to a slot directly below a Root
  2219. * Port, it's impossible for there to be other existing devices below
  2220. * the port. We don't limit the MPS in this case because we can
  2221. * reconfigure MPS on both the Root Port and the hot-added device,
  2222. * and there are no other devices involved.
  2223. *
  2224. * Note that this PCIE_BUS_SAFE path assumes no peer-to-peer DMA.
  2225. */
  2226. if (dev->is_hotplug_bridge &&
  2227. pci_pcie_type(dev) != PCI_EXP_TYPE_ROOT_PORT)
  2228. *smpss = 0;
  2229. if (*smpss > dev->pcie_mpss)
  2230. *smpss = dev->pcie_mpss;
  2231. return 0;
  2232. }
  2233. static void pcie_write_mps(struct pci_dev *dev, int mps)
  2234. {
  2235. int rc;
  2236. if (pcie_bus_config == PCIE_BUS_PERFORMANCE) {
  2237. mps = 128 << dev->pcie_mpss;
  2238. if (pci_pcie_type(dev) != PCI_EXP_TYPE_ROOT_PORT &&
  2239. dev->bus->self)
  2240. /*
  2241. * For "Performance", the assumption is made that
  2242. * downstream communication will never be larger than
  2243. * the MRRS. So, the MPS only needs to be configured
  2244. * for the upstream communication. This being the case,
  2245. * walk from the top down and set the MPS of the child
  2246. * to that of the parent bus.
  2247. *
  2248. * Configure the device MPS with the smaller of the
  2249. * device MPSS or the bridge MPS (which is assumed to be
  2250. * properly configured at this point to the largest
  2251. * allowable MPS based on its parent bus).
  2252. */
  2253. mps = min(mps, pcie_get_mps(dev->bus->self));
  2254. }
  2255. rc = pcie_set_mps(dev, mps);
  2256. if (rc)
  2257. pci_err(dev, "Failed attempting to set the MPS\n");
  2258. }
  2259. static void pcie_write_mrrs(struct pci_dev *dev)
  2260. {
  2261. int rc, mrrs;
  2262. /*
  2263. * In the "safe" case, do not configure the MRRS. There appear to be
  2264. * issues with setting MRRS to 0 on a number of devices.
  2265. */
  2266. if (pcie_bus_config != PCIE_BUS_PERFORMANCE)
  2267. return;
  2268. /*
  2269. * For max performance, the MRRS must be set to the largest supported
  2270. * value. However, it cannot be configured larger than the MPS the
  2271. * device or the bus can support. This should already be properly
  2272. * configured by a prior call to pcie_write_mps().
  2273. */
  2274. mrrs = pcie_get_mps(dev);
  2275. /*
  2276. * MRRS is a R/W register. Invalid values can be written, but a
  2277. * subsequent read will verify if the value is acceptable or not.
  2278. * If the MRRS value provided is not acceptable (e.g., too large),
  2279. * shrink the value until it is acceptable to the HW.
  2280. */
  2281. while (mrrs != pcie_get_readrq(dev) && mrrs >= 128) {
  2282. rc = pcie_set_readrq(dev, mrrs);
  2283. if (!rc)
  2284. break;
  2285. pci_warn(dev, "Failed attempting to set the MRRS\n");
  2286. mrrs /= 2;
  2287. }
  2288. if (mrrs < 128)
  2289. pci_err(dev, "MRRS was unable to be configured with a safe value. If problems are experienced, try running with pci=pcie_bus_safe\n");
  2290. }
  2291. static int pcie_bus_configure_set(struct pci_dev *dev, void *data)
  2292. {
  2293. int mps, orig_mps;
  2294. if (!pci_is_pcie(dev))
  2295. return 0;
  2296. if (pcie_bus_config == PCIE_BUS_TUNE_OFF ||
  2297. pcie_bus_config == PCIE_BUS_DEFAULT)
  2298. return 0;
  2299. mps = 128 << *(u8 *)data;
  2300. orig_mps = pcie_get_mps(dev);
  2301. pcie_write_mps(dev, mps);
  2302. pcie_write_mrrs(dev);
  2303. pci_info(dev, "Max Payload Size set to %4d/%4d (was %4d), Max Read Rq %4d\n",
  2304. pcie_get_mps(dev), 128 << dev->pcie_mpss,
  2305. orig_mps, pcie_get_readrq(dev));
  2306. return 0;
  2307. }
  2308. /*
  2309. * pcie_bus_configure_settings() requires that pci_walk_bus work in a top-down,
  2310. * parents then children fashion. If this changes, then this code will not
  2311. * work as designed.
  2312. */
  2313. void pcie_bus_configure_settings(struct pci_bus *bus)
  2314. {
  2315. u8 smpss = 0;
  2316. if (!bus->self)
  2317. return;
  2318. if (!pci_is_pcie(bus->self))
  2319. return;
  2320. /*
  2321. * FIXME - Peer to peer DMA is possible, though the endpoint would need
  2322. * to be aware of the MPS of the destination. To work around this,
  2323. * simply force the MPS of the entire system to the smallest possible.
  2324. */
  2325. if (pcie_bus_config == PCIE_BUS_PEER2PEER)
  2326. smpss = 0;
  2327. if (pcie_bus_config == PCIE_BUS_SAFE) {
  2328. smpss = bus->self->pcie_mpss;
  2329. pcie_find_smpss(bus->self, &smpss);
  2330. pci_walk_bus(bus, pcie_find_smpss, &smpss);
  2331. }
  2332. pcie_bus_configure_set(bus->self, &smpss);
  2333. pci_walk_bus(bus, pcie_bus_configure_set, &smpss);
  2334. }
  2335. EXPORT_SYMBOL_GPL(pcie_bus_configure_settings);
  2336. /*
  2337. * Called after each bus is probed, but before its children are examined. This
  2338. * is marked as __weak because multiple architectures define it.
  2339. */
  2340. void __weak pcibios_fixup_bus(struct pci_bus *bus)
  2341. {
  2342. /* nothing to do, expected to be removed in the future */
  2343. }
  2344. /**
  2345. * pci_scan_child_bus_extend() - Scan devices below a bus
  2346. * @bus: Bus to scan for devices
  2347. * @available_buses: Total number of buses available (%0 does not try to
  2348. * extend beyond the minimal)
  2349. *
  2350. * Scans devices below @bus including subordinate buses. Returns new
  2351. * subordinate number including all the found devices. Passing
  2352. * @available_buses causes the remaining bus space to be distributed
  2353. * equally between hotplug-capable bridges to allow future extension of the
  2354. * hierarchy.
  2355. */
  2356. static unsigned int pci_scan_child_bus_extend(struct pci_bus *bus,
  2357. unsigned int available_buses)
  2358. {
  2359. unsigned int used_buses, normal_bridges = 0, hotplug_bridges = 0;
  2360. unsigned int start = bus->busn_res.start;
  2361. unsigned int devfn, fn, cmax, max = start;
  2362. struct pci_dev *dev;
  2363. int nr_devs;
  2364. dev_dbg(&bus->dev, "scanning bus\n");
  2365. /* Go find them, Rover! */
  2366. for (devfn = 0; devfn < 256; devfn += 8) {
  2367. nr_devs = pci_scan_slot(bus, devfn);
  2368. /*
  2369. * The Jailhouse hypervisor may pass individual functions of a
  2370. * multi-function device to a guest without passing function 0.
  2371. * Look for them as well.
  2372. */
  2373. if (jailhouse_paravirt() && nr_devs == 0) {
  2374. for (fn = 1; fn < 8; fn++) {
  2375. dev = pci_scan_single_device(bus, devfn + fn);
  2376. if (dev)
  2377. dev->multifunction = 1;
  2378. }
  2379. }
  2380. }
  2381. /* Reserve buses for SR-IOV capability */
  2382. used_buses = pci_iov_bus_range(bus);
  2383. max += used_buses;
  2384. /*
  2385. * After performing arch-dependent fixup of the bus, look behind
  2386. * all PCI-to-PCI bridges on this bus.
  2387. */
  2388. if (!bus->is_added) {
  2389. dev_dbg(&bus->dev, "fixups for bus\n");
  2390. pcibios_fixup_bus(bus);
  2391. bus->is_added = 1;
  2392. }
  2393. /*
  2394. * Calculate how many hotplug bridges and normal bridges there
  2395. * are on this bus. We will distribute the additional available
  2396. * buses between hotplug bridges.
  2397. */
  2398. for_each_pci_bridge(dev, bus) {
  2399. if (dev->is_hotplug_bridge)
  2400. hotplug_bridges++;
  2401. else
  2402. normal_bridges++;
  2403. }
  2404. /*
  2405. * Scan bridges that are already configured. We don't touch them
  2406. * unless they are misconfigured (which will be done in the second
  2407. * scan below).
  2408. */
  2409. for_each_pci_bridge(dev, bus) {
  2410. cmax = max;
  2411. max = pci_scan_bridge_extend(bus, dev, max, 0, 0);
  2412. /*
  2413. * Reserve one bus for each bridge now to avoid extending
  2414. * hotplug bridges too much during the second scan below.
  2415. */
  2416. used_buses++;
  2417. if (cmax - max > 1)
  2418. used_buses += cmax - max - 1;
  2419. }
  2420. /* Scan bridges that need to be reconfigured */
  2421. for_each_pci_bridge(dev, bus) {
  2422. unsigned int buses = 0;
  2423. if (!hotplug_bridges && normal_bridges == 1) {
  2424. /*
  2425. * There is only one bridge on the bus (upstream
  2426. * port) so it gets all available buses which it
  2427. * can then distribute to the possible hotplug
  2428. * bridges below.
  2429. */
  2430. buses = available_buses;
  2431. } else if (dev->is_hotplug_bridge) {
  2432. /*
  2433. * Distribute the extra buses between hotplug
  2434. * bridges if any.
  2435. */
  2436. buses = available_buses / hotplug_bridges;
  2437. buses = min(buses, available_buses - used_buses + 1);
  2438. }
  2439. cmax = max;
  2440. max = pci_scan_bridge_extend(bus, dev, cmax, buses, 1);
  2441. /* One bus is already accounted so don't add it again */
  2442. if (max - cmax > 1)
  2443. used_buses += max - cmax - 1;
  2444. }
  2445. /*
  2446. * Make sure a hotplug bridge has at least the minimum requested
  2447. * number of buses but allow it to grow up to the maximum available
  2448. * bus number of there is room.
  2449. */
  2450. if (bus->self && bus->self->is_hotplug_bridge) {
  2451. used_buses = max_t(unsigned int, available_buses,
  2452. pci_hotplug_bus_size - 1);
  2453. if (max - start < used_buses) {
  2454. max = start + used_buses;
  2455. /* Do not allocate more buses than we have room left */
  2456. if (max > bus->busn_res.end)
  2457. max = bus->busn_res.end;
  2458. dev_dbg(&bus->dev, "%pR extended by %#02x\n",
  2459. &bus->busn_res, max - start);
  2460. }
  2461. }
  2462. /*
  2463. * We've scanned the bus and so we know all about what's on
  2464. * the other side of any bridges that may be on this bus plus
  2465. * any devices.
  2466. *
  2467. * Return how far we've got finding sub-buses.
  2468. */
  2469. dev_dbg(&bus->dev, "bus scan returning with max=%02x\n", max);
  2470. return max;
  2471. }
  2472. /**
  2473. * pci_scan_child_bus() - Scan devices below a bus
  2474. * @bus: Bus to scan for devices
  2475. *
  2476. * Scans devices below @bus including subordinate buses. Returns new
  2477. * subordinate number including all the found devices.
  2478. */
  2479. unsigned int pci_scan_child_bus(struct pci_bus *bus)
  2480. {
  2481. return pci_scan_child_bus_extend(bus, 0);
  2482. }
  2483. EXPORT_SYMBOL_GPL(pci_scan_child_bus);
  2484. /**
  2485. * pcibios_root_bridge_prepare - Platform-specific host bridge setup
  2486. * @bridge: Host bridge to set up
  2487. *
  2488. * Default empty implementation. Replace with an architecture-specific setup
  2489. * routine, if necessary.
  2490. */
  2491. int __weak pcibios_root_bridge_prepare(struct pci_host_bridge *bridge)
  2492. {
  2493. return 0;
  2494. }
  2495. void __weak pcibios_add_bus(struct pci_bus *bus)
  2496. {
  2497. }
  2498. void __weak pcibios_remove_bus(struct pci_bus *bus)
  2499. {
  2500. }
  2501. struct pci_bus *pci_create_root_bus(struct device *parent, int bus,
  2502. struct pci_ops *ops, void *sysdata, struct list_head *resources)
  2503. {
  2504. int error;
  2505. struct pci_host_bridge *bridge;
  2506. bridge = pci_alloc_host_bridge(0);
  2507. if (!bridge)
  2508. return NULL;
  2509. bridge->dev.parent = parent;
  2510. list_splice_init(resources, &bridge->windows);
  2511. bridge->sysdata = sysdata;
  2512. bridge->busnr = bus;
  2513. bridge->ops = ops;
  2514. error = pci_register_host_bridge(bridge);
  2515. if (error < 0)
  2516. goto err_out;
  2517. return bridge->bus;
  2518. err_out:
  2519. put_device(&bridge->dev);
  2520. return NULL;
  2521. }
  2522. EXPORT_SYMBOL_GPL(pci_create_root_bus);
  2523. int pci_host_probe(struct pci_host_bridge *bridge)
  2524. {
  2525. struct pci_bus *bus, *child;
  2526. int ret;
  2527. ret = pci_scan_root_bus_bridge(bridge);
  2528. if (ret < 0) {
  2529. dev_err(bridge->dev.parent, "Scanning root bridge failed");
  2530. return ret;
  2531. }
  2532. bus = bridge->bus;
  2533. /*
  2534. * We insert PCI resources into the iomem_resource and
  2535. * ioport_resource trees in either pci_bus_claim_resources()
  2536. * or pci_bus_assign_resources().
  2537. */
  2538. if (pci_has_flag(PCI_PROBE_ONLY)) {
  2539. pci_bus_claim_resources(bus);
  2540. } else {
  2541. pci_bus_size_bridges(bus);
  2542. pci_bus_assign_resources(bus);
  2543. list_for_each_entry(child, &bus->children, node)
  2544. pcie_bus_configure_settings(child);
  2545. }
  2546. pci_bus_add_devices(bus);
  2547. return 0;
  2548. }
  2549. EXPORT_SYMBOL_GPL(pci_host_probe);
  2550. int pci_bus_insert_busn_res(struct pci_bus *b, int bus, int bus_max)
  2551. {
  2552. struct resource *res = &b->busn_res;
  2553. struct resource *parent_res, *conflict;
  2554. res->start = bus;
  2555. res->end = bus_max;
  2556. res->flags = IORESOURCE_BUS;
  2557. if (!pci_is_root_bus(b))
  2558. parent_res = &b->parent->busn_res;
  2559. else {
  2560. parent_res = get_pci_domain_busn_res(pci_domain_nr(b));
  2561. res->flags |= IORESOURCE_PCI_FIXED;
  2562. }
  2563. conflict = request_resource_conflict(parent_res, res);
  2564. if (conflict)
  2565. dev_info(&b->dev,
  2566. "busn_res: can not insert %pR under %s%pR (conflicts with %s %pR)\n",
  2567. res, pci_is_root_bus(b) ? "domain " : "",
  2568. parent_res, conflict->name, conflict);
  2569. return conflict == NULL;
  2570. }
  2571. int pci_bus_update_busn_res_end(struct pci_bus *b, int bus_max)
  2572. {
  2573. struct resource *res = &b->busn_res;
  2574. struct resource old_res = *res;
  2575. resource_size_t size;
  2576. int ret;
  2577. if (res->start > bus_max)
  2578. return -EINVAL;
  2579. size = bus_max - res->start + 1;
  2580. ret = adjust_resource(res, res->start, size);
  2581. dev_info(&b->dev, "busn_res: %pR end %s updated to %02x\n",
  2582. &old_res, ret ? "can not be" : "is", bus_max);
  2583. if (!ret && !res->parent)
  2584. pci_bus_insert_busn_res(b, res->start, res->end);
  2585. return ret;
  2586. }
  2587. void pci_bus_release_busn_res(struct pci_bus *b)
  2588. {
  2589. struct resource *res = &b->busn_res;
  2590. int ret;
  2591. if (!res->flags || !res->parent)
  2592. return;
  2593. ret = release_resource(res);
  2594. dev_info(&b->dev, "busn_res: %pR %s released\n",
  2595. res, ret ? "can not be" : "is");
  2596. }
  2597. int pci_scan_root_bus_bridge(struct pci_host_bridge *bridge)
  2598. {
  2599. struct resource_entry *window;
  2600. bool found = false;
  2601. struct pci_bus *b;
  2602. int max, bus, ret;
  2603. if (!bridge)
  2604. return -EINVAL;
  2605. resource_list_for_each_entry(window, &bridge->windows)
  2606. if (window->res->flags & IORESOURCE_BUS) {
  2607. bridge->busnr = window->res->start;
  2608. found = true;
  2609. break;
  2610. }
  2611. ret = pci_register_host_bridge(bridge);
  2612. if (ret < 0)
  2613. return ret;
  2614. b = bridge->bus;
  2615. bus = bridge->busnr;
  2616. if (!found) {
  2617. dev_info(&b->dev,
  2618. "No busn resource found for root bus, will use [bus %02x-ff]\n",
  2619. bus);
  2620. pci_bus_insert_busn_res(b, bus, 255);
  2621. }
  2622. max = pci_scan_child_bus(b);
  2623. if (!found)
  2624. pci_bus_update_busn_res_end(b, max);
  2625. return 0;
  2626. }
  2627. EXPORT_SYMBOL(pci_scan_root_bus_bridge);
  2628. struct pci_bus *pci_scan_root_bus(struct device *parent, int bus,
  2629. struct pci_ops *ops, void *sysdata, struct list_head *resources)
  2630. {
  2631. struct resource_entry *window;
  2632. bool found = false;
  2633. struct pci_bus *b;
  2634. int max;
  2635. resource_list_for_each_entry(window, resources)
  2636. if (window->res->flags & IORESOURCE_BUS) {
  2637. found = true;
  2638. break;
  2639. }
  2640. b = pci_create_root_bus(parent, bus, ops, sysdata, resources);
  2641. if (!b)
  2642. return NULL;
  2643. if (!found) {
  2644. dev_info(&b->dev,
  2645. "No busn resource found for root bus, will use [bus %02x-ff]\n",
  2646. bus);
  2647. pci_bus_insert_busn_res(b, bus, 255);
  2648. }
  2649. max = pci_scan_child_bus(b);
  2650. if (!found)
  2651. pci_bus_update_busn_res_end(b, max);
  2652. return b;
  2653. }
  2654. EXPORT_SYMBOL(pci_scan_root_bus);
  2655. struct pci_bus *pci_scan_bus(int bus, struct pci_ops *ops,
  2656. void *sysdata)
  2657. {
  2658. LIST_HEAD(resources);
  2659. struct pci_bus *b;
  2660. pci_add_resource(&resources, &ioport_resource);
  2661. pci_add_resource(&resources, &iomem_resource);
  2662. pci_add_resource(&resources, &busn_resource);
  2663. b = pci_create_root_bus(NULL, bus, ops, sysdata, &resources);
  2664. if (b) {
  2665. pci_scan_child_bus(b);
  2666. } else {
  2667. pci_free_resource_list(&resources);
  2668. }
  2669. return b;
  2670. }
  2671. EXPORT_SYMBOL(pci_scan_bus);
  2672. /**
  2673. * pci_rescan_bus_bridge_resize - Scan a PCI bus for devices
  2674. * @bridge: PCI bridge for the bus to scan
  2675. *
  2676. * Scan a PCI bus and child buses for new devices, add them,
  2677. * and enable them, resizing bridge mmio/io resource if necessary
  2678. * and possible. The caller must ensure the child devices are already
  2679. * removed for resizing to occur.
  2680. *
  2681. * Returns the max number of subordinate bus discovered.
  2682. */
  2683. unsigned int pci_rescan_bus_bridge_resize(struct pci_dev *bridge)
  2684. {
  2685. unsigned int max;
  2686. struct pci_bus *bus = bridge->subordinate;
  2687. max = pci_scan_child_bus(bus);
  2688. pci_assign_unassigned_bridge_resources(bridge);
  2689. pci_bus_add_devices(bus);
  2690. return max;
  2691. }
  2692. /**
  2693. * pci_rescan_bus - Scan a PCI bus for devices
  2694. * @bus: PCI bus to scan
  2695. *
  2696. * Scan a PCI bus and child buses for new devices, add them,
  2697. * and enable them.
  2698. *
  2699. * Returns the max number of subordinate bus discovered.
  2700. */
  2701. unsigned int pci_rescan_bus(struct pci_bus *bus)
  2702. {
  2703. unsigned int max;
  2704. max = pci_scan_child_bus(bus);
  2705. pci_assign_unassigned_bus_resources(bus);
  2706. pci_bus_add_devices(bus);
  2707. return max;
  2708. }
  2709. EXPORT_SYMBOL_GPL(pci_rescan_bus);
  2710. /*
  2711. * pci_rescan_bus(), pci_rescan_bus_bridge_resize() and PCI device removal
  2712. * routines should always be executed under this mutex.
  2713. */
  2714. static DEFINE_MUTEX(pci_rescan_remove_lock);
  2715. void pci_lock_rescan_remove(void)
  2716. {
  2717. mutex_lock(&pci_rescan_remove_lock);
  2718. }
  2719. EXPORT_SYMBOL_GPL(pci_lock_rescan_remove);
  2720. void pci_unlock_rescan_remove(void)
  2721. {
  2722. mutex_unlock(&pci_rescan_remove_lock);
  2723. }
  2724. EXPORT_SYMBOL_GPL(pci_unlock_rescan_remove);
  2725. static int __init pci_sort_bf_cmp(const struct device *d_a,
  2726. const struct device *d_b)
  2727. {
  2728. const struct pci_dev *a = to_pci_dev(d_a);
  2729. const struct pci_dev *b = to_pci_dev(d_b);
  2730. if (pci_domain_nr(a->bus) < pci_domain_nr(b->bus)) return -1;
  2731. else if (pci_domain_nr(a->bus) > pci_domain_nr(b->bus)) return 1;
  2732. if (a->bus->number < b->bus->number) return -1;
  2733. else if (a->bus->number > b->bus->number) return 1;
  2734. if (a->devfn < b->devfn) return -1;
  2735. else if (a->devfn > b->devfn) return 1;
  2736. return 0;
  2737. }
  2738. void __init pci_sort_breadthfirst(void)
  2739. {
  2740. bus_sort_breadthfirst(&pci_bus_type, &pci_sort_bf_cmp);
  2741. }
  2742. int pci_hp_add_bridge(struct pci_dev *dev)
  2743. {
  2744. struct pci_bus *parent = dev->bus;
  2745. int busnr, start = parent->busn_res.start;
  2746. unsigned int available_buses = 0;
  2747. int end = parent->busn_res.end;
  2748. for (busnr = start; busnr <= end; busnr++) {
  2749. if (!pci_find_bus(pci_domain_nr(parent), busnr))
  2750. break;
  2751. }
  2752. if (busnr-- > end) {
  2753. pci_err(dev, "No bus number available for hot-added bridge\n");
  2754. return -1;
  2755. }
  2756. /* Scan bridges that are already configured */
  2757. busnr = pci_scan_bridge(parent, dev, busnr, 0);
  2758. /*
  2759. * Distribute the available bus numbers between hotplug-capable
  2760. * bridges to make extending the chain later possible.
  2761. */
  2762. available_buses = end - busnr;
  2763. /* Scan bridges that need to be reconfigured */
  2764. pci_scan_bridge_extend(parent, dev, busnr, available_buses, 1);
  2765. if (!dev->subordinate)
  2766. return -1;
  2767. return 0;
  2768. }
  2769. EXPORT_SYMBOL_GPL(pci_hp_add_bridge);