aer_inject.c 13 KB

123456789101112131415161718192021222324252627282930313233343536373839404142434445464748495051525354555657585960616263646566676869707172737475767778798081828384858687888990919293949596979899100101102103104105106107108109110111112113114115116117118119120121122123124125126127128129130131132133134135136137138139140141142143144145146147148149150151152153154155156157158159160161162163164165166167168169170171172173174175176177178179180181182183184185186187188189190191192193194195196197198199200201202203204205206207208209210211212213214215216217218219220221222223224225226227228229230231232233234235236237238239240241242243244245246247248249250251252253254255256257258259260261262263264265266267268269270271272273274275276277278279280281282283284285286287288289290291292293294295296297298299300301302303304305306307308309310311312313314315316317318319320321322323324325326327328329330331332333334335336337338339340341342343344345346347348349350351352353354355356357358359360361362363364365366367368369370371372373374375376377378379380381382383384385386387388389390391392393394395396397398399400401402403404405406407408409410411412413414415416417418419420421422423424425426427428429430431432433434435436437438439440441442443444445446447448449450451452453454455456457458459460461462463464465466467468469470471472473474475476477478479480481482483484485486487488489490491492493494495496497498499500501502503504505506507508509510511512513514515516517518519520521522523524525526527528529530531532533534535536537538539540541542543544545
  1. // SPDX-License-Identifier: GPL-2.0
  2. /*
  3. * PCIe AER software error injection support.
  4. *
  5. * Debugging PCIe AER code is quite difficult because it is hard to
  6. * trigger various real hardware errors. Software based error
  7. * injection can fake almost all kinds of errors with the help of a
  8. * user space helper tool aer-inject, which can be gotten from:
  9. * https://www.kernel.org/pub/linux/utils/pci/aer-inject/
  10. *
  11. * Copyright 2009 Intel Corporation.
  12. * Huang Ying <ying.huang@intel.com>
  13. */
  14. #define dev_fmt(fmt) "aer_inject: " fmt
  15. #include <linux/module.h>
  16. #include <linux/init.h>
  17. #include <linux/interrupt.h>
  18. #include <linux/miscdevice.h>
  19. #include <linux/pci.h>
  20. #include <linux/slab.h>
  21. #include <linux/fs.h>
  22. #include <linux/uaccess.h>
  23. #include <linux/stddef.h>
  24. #include <linux/device.h>
  25. #include "portdrv.h"
  26. /* Override the existing corrected and uncorrected error masks */
  27. static bool aer_mask_override;
  28. module_param(aer_mask_override, bool, 0);
  29. struct aer_error_inj {
  30. u8 bus;
  31. u8 dev;
  32. u8 fn;
  33. u32 uncor_status;
  34. u32 cor_status;
  35. u32 header_log0;
  36. u32 header_log1;
  37. u32 header_log2;
  38. u32 header_log3;
  39. u32 domain;
  40. };
  41. struct aer_error {
  42. struct list_head list;
  43. u32 domain;
  44. unsigned int bus;
  45. unsigned int devfn;
  46. int pos_cap_err;
  47. u32 uncor_status;
  48. u32 cor_status;
  49. u32 header_log0;
  50. u32 header_log1;
  51. u32 header_log2;
  52. u32 header_log3;
  53. u32 root_status;
  54. u32 source_id;
  55. };
  56. struct pci_bus_ops {
  57. struct list_head list;
  58. struct pci_bus *bus;
  59. struct pci_ops *ops;
  60. };
  61. static LIST_HEAD(einjected);
  62. static LIST_HEAD(pci_bus_ops_list);
  63. /* Protect einjected and pci_bus_ops_list */
  64. static DEFINE_SPINLOCK(inject_lock);
  65. static void aer_error_init(struct aer_error *err, u32 domain,
  66. unsigned int bus, unsigned int devfn,
  67. int pos_cap_err)
  68. {
  69. INIT_LIST_HEAD(&err->list);
  70. err->domain = domain;
  71. err->bus = bus;
  72. err->devfn = devfn;
  73. err->pos_cap_err = pos_cap_err;
  74. }
  75. /* inject_lock must be held before calling */
  76. static struct aer_error *__find_aer_error(u32 domain, unsigned int bus,
  77. unsigned int devfn)
  78. {
  79. struct aer_error *err;
  80. list_for_each_entry(err, &einjected, list) {
  81. if (domain == err->domain &&
  82. bus == err->bus &&
  83. devfn == err->devfn)
  84. return err;
  85. }
  86. return NULL;
  87. }
  88. /* inject_lock must be held before calling */
  89. static struct aer_error *__find_aer_error_by_dev(struct pci_dev *dev)
  90. {
  91. int domain = pci_domain_nr(dev->bus);
  92. if (domain < 0)
  93. return NULL;
  94. return __find_aer_error(domain, dev->bus->number, dev->devfn);
  95. }
  96. /* inject_lock must be held before calling */
  97. static struct pci_ops *__find_pci_bus_ops(struct pci_bus *bus)
  98. {
  99. struct pci_bus_ops *bus_ops;
  100. list_for_each_entry(bus_ops, &pci_bus_ops_list, list) {
  101. if (bus_ops->bus == bus)
  102. return bus_ops->ops;
  103. }
  104. return NULL;
  105. }
  106. static struct pci_bus_ops *pci_bus_ops_pop(void)
  107. {
  108. unsigned long flags;
  109. struct pci_bus_ops *bus_ops;
  110. spin_lock_irqsave(&inject_lock, flags);
  111. bus_ops = list_first_entry_or_null(&pci_bus_ops_list,
  112. struct pci_bus_ops, list);
  113. if (bus_ops)
  114. list_del(&bus_ops->list);
  115. spin_unlock_irqrestore(&inject_lock, flags);
  116. return bus_ops;
  117. }
  118. static u32 *find_pci_config_dword(struct aer_error *err, int where,
  119. int *prw1cs)
  120. {
  121. int rw1cs = 0;
  122. u32 *target = NULL;
  123. if (err->pos_cap_err == -1)
  124. return NULL;
  125. switch (where - err->pos_cap_err) {
  126. case PCI_ERR_UNCOR_STATUS:
  127. target = &err->uncor_status;
  128. rw1cs = 1;
  129. break;
  130. case PCI_ERR_COR_STATUS:
  131. target = &err->cor_status;
  132. rw1cs = 1;
  133. break;
  134. case PCI_ERR_HEADER_LOG:
  135. target = &err->header_log0;
  136. break;
  137. case PCI_ERR_HEADER_LOG+4:
  138. target = &err->header_log1;
  139. break;
  140. case PCI_ERR_HEADER_LOG+8:
  141. target = &err->header_log2;
  142. break;
  143. case PCI_ERR_HEADER_LOG+12:
  144. target = &err->header_log3;
  145. break;
  146. case PCI_ERR_ROOT_STATUS:
  147. target = &err->root_status;
  148. rw1cs = 1;
  149. break;
  150. case PCI_ERR_ROOT_ERR_SRC:
  151. target = &err->source_id;
  152. break;
  153. }
  154. if (prw1cs)
  155. *prw1cs = rw1cs;
  156. return target;
  157. }
  158. static int aer_inj_read(struct pci_bus *bus, unsigned int devfn, int where,
  159. int size, u32 *val)
  160. {
  161. struct pci_ops *ops, *my_ops;
  162. int rv;
  163. ops = __find_pci_bus_ops(bus);
  164. if (!ops)
  165. return -1;
  166. my_ops = bus->ops;
  167. bus->ops = ops;
  168. rv = ops->read(bus, devfn, where, size, val);
  169. bus->ops = my_ops;
  170. return rv;
  171. }
  172. static int aer_inj_write(struct pci_bus *bus, unsigned int devfn, int where,
  173. int size, u32 val)
  174. {
  175. struct pci_ops *ops, *my_ops;
  176. int rv;
  177. ops = __find_pci_bus_ops(bus);
  178. if (!ops)
  179. return -1;
  180. my_ops = bus->ops;
  181. bus->ops = ops;
  182. rv = ops->write(bus, devfn, where, size, val);
  183. bus->ops = my_ops;
  184. return rv;
  185. }
  186. static int aer_inj_read_config(struct pci_bus *bus, unsigned int devfn,
  187. int where, int size, u32 *val)
  188. {
  189. u32 *sim;
  190. struct aer_error *err;
  191. unsigned long flags;
  192. int domain;
  193. int rv;
  194. spin_lock_irqsave(&inject_lock, flags);
  195. if (size != sizeof(u32))
  196. goto out;
  197. domain = pci_domain_nr(bus);
  198. if (domain < 0)
  199. goto out;
  200. err = __find_aer_error(domain, bus->number, devfn);
  201. if (!err)
  202. goto out;
  203. sim = find_pci_config_dword(err, where, NULL);
  204. if (sim) {
  205. *val = *sim;
  206. spin_unlock_irqrestore(&inject_lock, flags);
  207. return 0;
  208. }
  209. out:
  210. rv = aer_inj_read(bus, devfn, where, size, val);
  211. spin_unlock_irqrestore(&inject_lock, flags);
  212. return rv;
  213. }
  214. static int aer_inj_write_config(struct pci_bus *bus, unsigned int devfn,
  215. int where, int size, u32 val)
  216. {
  217. u32 *sim;
  218. struct aer_error *err;
  219. unsigned long flags;
  220. int rw1cs;
  221. int domain;
  222. int rv;
  223. spin_lock_irqsave(&inject_lock, flags);
  224. if (size != sizeof(u32))
  225. goto out;
  226. domain = pci_domain_nr(bus);
  227. if (domain < 0)
  228. goto out;
  229. err = __find_aer_error(domain, bus->number, devfn);
  230. if (!err)
  231. goto out;
  232. sim = find_pci_config_dword(err, where, &rw1cs);
  233. if (sim) {
  234. if (rw1cs)
  235. *sim ^= val;
  236. else
  237. *sim = val;
  238. spin_unlock_irqrestore(&inject_lock, flags);
  239. return 0;
  240. }
  241. out:
  242. rv = aer_inj_write(bus, devfn, where, size, val);
  243. spin_unlock_irqrestore(&inject_lock, flags);
  244. return rv;
  245. }
  246. static struct pci_ops aer_inj_pci_ops = {
  247. .read = aer_inj_read_config,
  248. .write = aer_inj_write_config,
  249. };
  250. static void pci_bus_ops_init(struct pci_bus_ops *bus_ops,
  251. struct pci_bus *bus,
  252. struct pci_ops *ops)
  253. {
  254. INIT_LIST_HEAD(&bus_ops->list);
  255. bus_ops->bus = bus;
  256. bus_ops->ops = ops;
  257. }
  258. static int pci_bus_set_aer_ops(struct pci_bus *bus)
  259. {
  260. struct pci_ops *ops;
  261. struct pci_bus_ops *bus_ops;
  262. unsigned long flags;
  263. bus_ops = kmalloc(sizeof(*bus_ops), GFP_KERNEL);
  264. if (!bus_ops)
  265. return -ENOMEM;
  266. ops = pci_bus_set_ops(bus, &aer_inj_pci_ops);
  267. spin_lock_irqsave(&inject_lock, flags);
  268. if (ops == &aer_inj_pci_ops)
  269. goto out;
  270. pci_bus_ops_init(bus_ops, bus, ops);
  271. list_add(&bus_ops->list, &pci_bus_ops_list);
  272. bus_ops = NULL;
  273. out:
  274. spin_unlock_irqrestore(&inject_lock, flags);
  275. kfree(bus_ops);
  276. return 0;
  277. }
  278. static int aer_inject(struct aer_error_inj *einj)
  279. {
  280. struct aer_error *err, *rperr;
  281. struct aer_error *err_alloc = NULL, *rperr_alloc = NULL;
  282. struct pci_dev *dev, *rpdev;
  283. struct pcie_device *edev;
  284. struct device *device;
  285. unsigned long flags;
  286. unsigned int devfn = PCI_DEVFN(einj->dev, einj->fn);
  287. int pos_cap_err, rp_pos_cap_err;
  288. u32 sever, cor_mask, uncor_mask, cor_mask_orig = 0, uncor_mask_orig = 0;
  289. int ret = 0;
  290. dev = pci_get_domain_bus_and_slot(einj->domain, einj->bus, devfn);
  291. if (!dev)
  292. return -ENODEV;
  293. rpdev = pcie_find_root_port(dev);
  294. if (!rpdev) {
  295. pci_err(dev, "Root port not found\n");
  296. ret = -ENODEV;
  297. goto out_put;
  298. }
  299. pos_cap_err = dev->aer_cap;
  300. if (!pos_cap_err) {
  301. pci_err(dev, "Device doesn't support AER\n");
  302. ret = -EPROTONOSUPPORT;
  303. goto out_put;
  304. }
  305. pci_read_config_dword(dev, pos_cap_err + PCI_ERR_UNCOR_SEVER, &sever);
  306. pci_read_config_dword(dev, pos_cap_err + PCI_ERR_COR_MASK, &cor_mask);
  307. pci_read_config_dword(dev, pos_cap_err + PCI_ERR_UNCOR_MASK,
  308. &uncor_mask);
  309. rp_pos_cap_err = rpdev->aer_cap;
  310. if (!rp_pos_cap_err) {
  311. pci_err(rpdev, "Root port doesn't support AER\n");
  312. ret = -EPROTONOSUPPORT;
  313. goto out_put;
  314. }
  315. err_alloc = kzalloc(sizeof(struct aer_error), GFP_KERNEL);
  316. if (!err_alloc) {
  317. ret = -ENOMEM;
  318. goto out_put;
  319. }
  320. rperr_alloc = kzalloc(sizeof(struct aer_error), GFP_KERNEL);
  321. if (!rperr_alloc) {
  322. ret = -ENOMEM;
  323. goto out_put;
  324. }
  325. if (aer_mask_override) {
  326. cor_mask_orig = cor_mask;
  327. cor_mask &= !(einj->cor_status);
  328. pci_write_config_dword(dev, pos_cap_err + PCI_ERR_COR_MASK,
  329. cor_mask);
  330. uncor_mask_orig = uncor_mask;
  331. uncor_mask &= !(einj->uncor_status);
  332. pci_write_config_dword(dev, pos_cap_err + PCI_ERR_UNCOR_MASK,
  333. uncor_mask);
  334. }
  335. spin_lock_irqsave(&inject_lock, flags);
  336. err = __find_aer_error_by_dev(dev);
  337. if (!err) {
  338. err = err_alloc;
  339. err_alloc = NULL;
  340. aer_error_init(err, einj->domain, einj->bus, devfn,
  341. pos_cap_err);
  342. list_add(&err->list, &einjected);
  343. }
  344. err->uncor_status |= einj->uncor_status;
  345. err->cor_status |= einj->cor_status;
  346. err->header_log0 = einj->header_log0;
  347. err->header_log1 = einj->header_log1;
  348. err->header_log2 = einj->header_log2;
  349. err->header_log3 = einj->header_log3;
  350. if (!aer_mask_override && einj->cor_status &&
  351. !(einj->cor_status & ~cor_mask)) {
  352. ret = -EINVAL;
  353. pci_warn(dev, "The correctable error(s) is masked by device\n");
  354. spin_unlock_irqrestore(&inject_lock, flags);
  355. goto out_put;
  356. }
  357. if (!aer_mask_override && einj->uncor_status &&
  358. !(einj->uncor_status & ~uncor_mask)) {
  359. ret = -EINVAL;
  360. pci_warn(dev, "The uncorrectable error(s) is masked by device\n");
  361. spin_unlock_irqrestore(&inject_lock, flags);
  362. goto out_put;
  363. }
  364. rperr = __find_aer_error_by_dev(rpdev);
  365. if (!rperr) {
  366. rperr = rperr_alloc;
  367. rperr_alloc = NULL;
  368. aer_error_init(rperr, pci_domain_nr(rpdev->bus),
  369. rpdev->bus->number, rpdev->devfn,
  370. rp_pos_cap_err);
  371. list_add(&rperr->list, &einjected);
  372. }
  373. if (einj->cor_status) {
  374. if (rperr->root_status & PCI_ERR_ROOT_COR_RCV)
  375. rperr->root_status |= PCI_ERR_ROOT_MULTI_COR_RCV;
  376. else
  377. rperr->root_status |= PCI_ERR_ROOT_COR_RCV;
  378. rperr->source_id &= 0xffff0000;
  379. rperr->source_id |= (einj->bus << 8) | devfn;
  380. }
  381. if (einj->uncor_status) {
  382. if (rperr->root_status & PCI_ERR_ROOT_UNCOR_RCV)
  383. rperr->root_status |= PCI_ERR_ROOT_MULTI_UNCOR_RCV;
  384. if (sever & einj->uncor_status) {
  385. rperr->root_status |= PCI_ERR_ROOT_FATAL_RCV;
  386. if (!(rperr->root_status & PCI_ERR_ROOT_UNCOR_RCV))
  387. rperr->root_status |= PCI_ERR_ROOT_FIRST_FATAL;
  388. } else
  389. rperr->root_status |= PCI_ERR_ROOT_NONFATAL_RCV;
  390. rperr->root_status |= PCI_ERR_ROOT_UNCOR_RCV;
  391. rperr->source_id &= 0x0000ffff;
  392. rperr->source_id |= ((einj->bus << 8) | devfn) << 16;
  393. }
  394. spin_unlock_irqrestore(&inject_lock, flags);
  395. if (aer_mask_override) {
  396. pci_write_config_dword(dev, pos_cap_err + PCI_ERR_COR_MASK,
  397. cor_mask_orig);
  398. pci_write_config_dword(dev, pos_cap_err + PCI_ERR_UNCOR_MASK,
  399. uncor_mask_orig);
  400. }
  401. ret = pci_bus_set_aer_ops(dev->bus);
  402. if (ret)
  403. goto out_put;
  404. ret = pci_bus_set_aer_ops(rpdev->bus);
  405. if (ret)
  406. goto out_put;
  407. device = pcie_port_find_device(rpdev, PCIE_PORT_SERVICE_AER);
  408. if (device) {
  409. edev = to_pcie_device(device);
  410. if (!get_service_data(edev)) {
  411. pci_warn(edev->port, "AER service is not initialized\n");
  412. ret = -EPROTONOSUPPORT;
  413. goto out_put;
  414. }
  415. pci_info(edev->port, "Injecting errors %08x/%08x into device %s\n",
  416. einj->cor_status, einj->uncor_status, pci_name(dev));
  417. ret = irq_inject_interrupt(edev->irq);
  418. } else {
  419. pci_err(rpdev, "AER device not found\n");
  420. ret = -ENODEV;
  421. }
  422. out_put:
  423. kfree(err_alloc);
  424. kfree(rperr_alloc);
  425. pci_dev_put(dev);
  426. return ret;
  427. }
  428. static ssize_t aer_inject_write(struct file *filp, const char __user *ubuf,
  429. size_t usize, loff_t *off)
  430. {
  431. struct aer_error_inj einj;
  432. int ret;
  433. if (!capable(CAP_SYS_ADMIN))
  434. return -EPERM;
  435. if (usize < offsetof(struct aer_error_inj, domain) ||
  436. usize > sizeof(einj))
  437. return -EINVAL;
  438. memset(&einj, 0, sizeof(einj));
  439. if (copy_from_user(&einj, ubuf, usize))
  440. return -EFAULT;
  441. ret = aer_inject(&einj);
  442. return ret ? ret : usize;
  443. }
  444. static const struct file_operations aer_inject_fops = {
  445. .write = aer_inject_write,
  446. .owner = THIS_MODULE,
  447. .llseek = noop_llseek,
  448. };
  449. static struct miscdevice aer_inject_device = {
  450. .minor = MISC_DYNAMIC_MINOR,
  451. .name = "aer_inject",
  452. .fops = &aer_inject_fops,
  453. };
  454. static int __init aer_inject_init(void)
  455. {
  456. return misc_register(&aer_inject_device);
  457. }
  458. static void __exit aer_inject_exit(void)
  459. {
  460. struct aer_error *err, *err_next;
  461. unsigned long flags;
  462. struct pci_bus_ops *bus_ops;
  463. misc_deregister(&aer_inject_device);
  464. while ((bus_ops = pci_bus_ops_pop())) {
  465. pci_bus_set_ops(bus_ops->bus, bus_ops->ops);
  466. kfree(bus_ops);
  467. }
  468. spin_lock_irqsave(&inject_lock, flags);
  469. list_for_each_entry_safe(err, err_next, &einjected, list) {
  470. list_del(&err->list);
  471. kfree(err);
  472. }
  473. spin_unlock_irqrestore(&inject_lock, flags);
  474. }
  475. module_init(aer_inject_init);
  476. module_exit(aer_inject_exit);
  477. MODULE_DESCRIPTION("PCIe AER software error injector");
  478. MODULE_LICENSE("GPL");