aer.c 38 KB

123456789101112131415161718192021222324252627282930313233343536373839404142434445464748495051525354555657585960616263646566676869707172737475767778798081828384858687888990919293949596979899100101102103104105106107108109110111112113114115116117118119120121122123124125126127128129130131132133134135136137138139140141142143144145146147148149150151152153154155156157158159160161162163164165166167168169170171172173174175176177178179180181182183184185186187188189190191192193194195196197198199200201202203204205206207208209210211212213214215216217218219220221222223224225226227228229230231232233234235236237238239240241242243244245246247248249250251252253254255256257258259260261262263264265266267268269270271272273274275276277278279280281282283284285286287288289290291292293294295296297298299300301302303304305306307308309310311312313314315316317318319320321322323324325326327328329330331332333334335336337338339340341342343344345346347348349350351352353354355356357358359360361362363364365366367368369370371372373374375376377378379380381382383384385386387388389390391392393394395396397398399400401402403404405406407408409410411412413414415416417418419420421422423424425426427428429430431432433434435436437438439440441442443444445446447448449450451452453454455456457458459460461462463464465466467468469470471472473474475476477478479480481482483484485486487488489490491492493494495496497498499500501502503504505506507508509510511512513514515516517518519520521522523524525526527528529530531532533534535536537538539540541542543544545546547548549550551552553554555556557558559560561562563564565566567568569570571572573574575576577578579580581582583584585586587588589590591592593594595596597598599600601602603604605606607608609610611612613614615616617618619620621622623624625626627628629630631632633634635636637638639640641642643644645646647648649650651652653654655656657658659660661662663664665666667668669670671672673674675676677678679680681682683684685686687688689690691692693694695696697698699700701702703704705706707708709710711712713714715716717718719720721722723724725726727728729730731732733734735736737738739740741742743744745746747748749750751752753754755756757758759760761762763764765766767768769770771772773774775776777778779780781782783784785786787788789790791792793794795796797798799800801802803804805806807808809810811812813814815816817818819820821822823824825826827828829830831832833834835836837838839840841842843844845846847848849850851852853854855856857858859860861862863864865866867868869870871872873874875876877878879880881882883884885886887888889890891892893894895896897898899900901902903904905906907908909910911912913914915916917918919920921922923924925926927928929930931932933934935936937938939940941942943944945946947948949950951952953954955956957958959960961962963964965966967968969970971972973974975976977978979980981982983984985986987988989990991992993994995996997998999100010011002100310041005100610071008100910101011101210131014101510161017101810191020102110221023102410251026102710281029103010311032103310341035103610371038103910401041104210431044104510461047104810491050105110521053105410551056105710581059106010611062106310641065106610671068106910701071107210731074107510761077107810791080108110821083108410851086108710881089109010911092109310941095109610971098109911001101110211031104110511061107110811091110111111121113111411151116111711181119112011211122112311241125112611271128112911301131113211331134113511361137113811391140114111421143114411451146114711481149115011511152115311541155115611571158115911601161116211631164116511661167116811691170117111721173117411751176117711781179118011811182118311841185118611871188118911901191119211931194119511961197119811991200120112021203120412051206120712081209121012111212121312141215121612171218121912201221122212231224122512261227122812291230123112321233123412351236123712381239124012411242124312441245124612471248124912501251125212531254125512561257125812591260126112621263126412651266126712681269127012711272127312741275127612771278127912801281128212831284128512861287128812891290129112921293129412951296129712981299130013011302130313041305130613071308130913101311131213131314131513161317131813191320132113221323132413251326132713281329133013311332133313341335133613371338133913401341134213431344134513461347134813491350135113521353135413551356135713581359136013611362136313641365136613671368136913701371137213731374137513761377137813791380138113821383138413851386138713881389139013911392139313941395139613971398139914001401140214031404
  1. // SPDX-License-Identifier: GPL-2.0
  2. /*
  3. * Implement the AER root port service driver. The driver registers an IRQ
  4. * handler. When a root port triggers an AER interrupt, the IRQ handler
  5. * collects root port status and schedules work.
  6. *
  7. * Copyright (C) 2006 Intel Corp.
  8. * Tom Long Nguyen (tom.l.nguyen@intel.com)
  9. * Zhang Yanmin (yanmin.zhang@intel.com)
  10. *
  11. * (C) Copyright 2009 Hewlett-Packard Development Company, L.P.
  12. * Andrew Patterson <andrew.patterson@hp.com>
  13. */
  14. #define pr_fmt(fmt) "AER: " fmt
  15. #define dev_fmt pr_fmt
  16. #include <linux/bitops.h>
  17. #include <linux/cper.h>
  18. #include <linux/pci.h>
  19. #include <linux/pci-acpi.h>
  20. #include <linux/sched.h>
  21. #include <linux/kernel.h>
  22. #include <linux/errno.h>
  23. #include <linux/pm.h>
  24. #include <linux/init.h>
  25. #include <linux/interrupt.h>
  26. #include <linux/delay.h>
  27. #include <linux/kfifo.h>
  28. #include <linux/slab.h>
  29. #include <acpi/apei.h>
  30. #include <ras/ras_event.h>
  31. #include "../pci.h"
  32. #include "portdrv.h"
  33. #define AER_ERROR_SOURCES_MAX 128
  34. #define AER_MAX_TYPEOF_COR_ERRS 16 /* as per PCI_ERR_COR_STATUS */
  35. #define AER_MAX_TYPEOF_UNCOR_ERRS 27 /* as per PCI_ERR_UNCOR_STATUS*/
  36. struct aer_err_source {
  37. unsigned int status;
  38. unsigned int id;
  39. };
  40. struct aer_rpc {
  41. struct pci_dev *rpd; /* Root Port device */
  42. DECLARE_KFIFO(aer_fifo, struct aer_err_source, AER_ERROR_SOURCES_MAX);
  43. };
  44. /* AER stats for the device */
  45. struct aer_stats {
  46. /*
  47. * Fields for all AER capable devices. They indicate the errors
  48. * "as seen by this device". Note that this may mean that if an
  49. * end point is causing problems, the AER counters may increment
  50. * at its link partner (e.g. root port) because the errors will be
  51. * "seen" by the link partner and not the the problematic end point
  52. * itself (which may report all counters as 0 as it never saw any
  53. * problems).
  54. */
  55. /* Counters for different type of correctable errors */
  56. u64 dev_cor_errs[AER_MAX_TYPEOF_COR_ERRS];
  57. /* Counters for different type of fatal uncorrectable errors */
  58. u64 dev_fatal_errs[AER_MAX_TYPEOF_UNCOR_ERRS];
  59. /* Counters for different type of nonfatal uncorrectable errors */
  60. u64 dev_nonfatal_errs[AER_MAX_TYPEOF_UNCOR_ERRS];
  61. /* Total number of ERR_COR sent by this device */
  62. u64 dev_total_cor_errs;
  63. /* Total number of ERR_FATAL sent by this device */
  64. u64 dev_total_fatal_errs;
  65. /* Total number of ERR_NONFATAL sent by this device */
  66. u64 dev_total_nonfatal_errs;
  67. /*
  68. * Fields for Root ports & root complex event collectors only, these
  69. * indicate the total number of ERR_COR, ERR_FATAL, and ERR_NONFATAL
  70. * messages received by the root port / event collector, INCLUDING the
  71. * ones that are generated internally (by the rootport itself)
  72. */
  73. u64 rootport_total_cor_errs;
  74. u64 rootport_total_fatal_errs;
  75. u64 rootport_total_nonfatal_errs;
  76. };
  77. #define AER_LOG_TLP_MASKS (PCI_ERR_UNC_POISON_TLP| \
  78. PCI_ERR_UNC_ECRC| \
  79. PCI_ERR_UNC_UNSUP| \
  80. PCI_ERR_UNC_COMP_ABORT| \
  81. PCI_ERR_UNC_UNX_COMP| \
  82. PCI_ERR_UNC_MALF_TLP)
  83. #define SYSTEM_ERROR_INTR_ON_MESG_MASK (PCI_EXP_RTCTL_SECEE| \
  84. PCI_EXP_RTCTL_SENFEE| \
  85. PCI_EXP_RTCTL_SEFEE)
  86. #define ROOT_PORT_INTR_ON_MESG_MASK (PCI_ERR_ROOT_CMD_COR_EN| \
  87. PCI_ERR_ROOT_CMD_NONFATAL_EN| \
  88. PCI_ERR_ROOT_CMD_FATAL_EN)
  89. #define ERR_COR_ID(d) (d & 0xffff)
  90. #define ERR_UNCOR_ID(d) (d >> 16)
  91. static int pcie_aer_disable;
  92. static pci_ers_result_t aer_root_reset(struct pci_dev *dev);
  93. void pci_no_aer(void)
  94. {
  95. pcie_aer_disable = 1;
  96. }
  97. bool pci_aer_available(void)
  98. {
  99. return !pcie_aer_disable && pci_msi_enabled();
  100. }
  101. #ifdef CONFIG_PCIE_ECRC
  102. #define ECRC_POLICY_DEFAULT 0 /* ECRC set by BIOS */
  103. #define ECRC_POLICY_OFF 1 /* ECRC off for performance */
  104. #define ECRC_POLICY_ON 2 /* ECRC on for data integrity */
  105. static int ecrc_policy = ECRC_POLICY_DEFAULT;
  106. static const char * const ecrc_policy_str[] = {
  107. [ECRC_POLICY_DEFAULT] = "bios",
  108. [ECRC_POLICY_OFF] = "off",
  109. [ECRC_POLICY_ON] = "on"
  110. };
  111. /**
  112. * enable_ercr_checking - enable PCIe ECRC checking for a device
  113. * @dev: the PCI device
  114. *
  115. * Returns 0 on success, or negative on failure.
  116. */
  117. static int enable_ecrc_checking(struct pci_dev *dev)
  118. {
  119. int aer = dev->aer_cap;
  120. u32 reg32;
  121. if (!aer)
  122. return -ENODEV;
  123. pci_read_config_dword(dev, aer + PCI_ERR_CAP, &reg32);
  124. if (reg32 & PCI_ERR_CAP_ECRC_GENC)
  125. reg32 |= PCI_ERR_CAP_ECRC_GENE;
  126. if (reg32 & PCI_ERR_CAP_ECRC_CHKC)
  127. reg32 |= PCI_ERR_CAP_ECRC_CHKE;
  128. pci_write_config_dword(dev, aer + PCI_ERR_CAP, reg32);
  129. return 0;
  130. }
  131. /**
  132. * disable_ercr_checking - disables PCIe ECRC checking for a device
  133. * @dev: the PCI device
  134. *
  135. * Returns 0 on success, or negative on failure.
  136. */
  137. static int disable_ecrc_checking(struct pci_dev *dev)
  138. {
  139. int aer = dev->aer_cap;
  140. u32 reg32;
  141. if (!aer)
  142. return -ENODEV;
  143. pci_read_config_dword(dev, aer + PCI_ERR_CAP, &reg32);
  144. reg32 &= ~(PCI_ERR_CAP_ECRC_GENE | PCI_ERR_CAP_ECRC_CHKE);
  145. pci_write_config_dword(dev, aer + PCI_ERR_CAP, reg32);
  146. return 0;
  147. }
  148. /**
  149. * pcie_set_ecrc_checking - set/unset PCIe ECRC checking for a device based on global policy
  150. * @dev: the PCI device
  151. */
  152. void pcie_set_ecrc_checking(struct pci_dev *dev)
  153. {
  154. switch (ecrc_policy) {
  155. case ECRC_POLICY_DEFAULT:
  156. return;
  157. case ECRC_POLICY_OFF:
  158. disable_ecrc_checking(dev);
  159. break;
  160. case ECRC_POLICY_ON:
  161. enable_ecrc_checking(dev);
  162. break;
  163. default:
  164. return;
  165. }
  166. }
  167. /**
  168. * pcie_ecrc_get_policy - parse kernel command-line ecrc option
  169. * @str: ECRC policy from kernel command line to use
  170. */
  171. void pcie_ecrc_get_policy(char *str)
  172. {
  173. int i;
  174. i = match_string(ecrc_policy_str, ARRAY_SIZE(ecrc_policy_str), str);
  175. if (i < 0)
  176. return;
  177. ecrc_policy = i;
  178. }
  179. #endif /* CONFIG_PCIE_ECRC */
  180. #define PCI_EXP_AER_FLAGS (PCI_EXP_DEVCTL_CERE | PCI_EXP_DEVCTL_NFERE | \
  181. PCI_EXP_DEVCTL_FERE | PCI_EXP_DEVCTL_URRE)
  182. int pcie_aer_is_native(struct pci_dev *dev)
  183. {
  184. struct pci_host_bridge *host = pci_find_host_bridge(dev->bus);
  185. if (!dev->aer_cap)
  186. return 0;
  187. return pcie_ports_native || host->native_aer;
  188. }
  189. int pci_enable_pcie_error_reporting(struct pci_dev *dev)
  190. {
  191. int rc;
  192. if (!pcie_aer_is_native(dev))
  193. return -EIO;
  194. rc = pcie_capability_set_word(dev, PCI_EXP_DEVCTL, PCI_EXP_AER_FLAGS);
  195. return pcibios_err_to_errno(rc);
  196. }
  197. EXPORT_SYMBOL_GPL(pci_enable_pcie_error_reporting);
  198. int pci_disable_pcie_error_reporting(struct pci_dev *dev)
  199. {
  200. int rc;
  201. if (!pcie_aer_is_native(dev))
  202. return -EIO;
  203. rc = pcie_capability_clear_word(dev, PCI_EXP_DEVCTL, PCI_EXP_AER_FLAGS);
  204. return pcibios_err_to_errno(rc);
  205. }
  206. EXPORT_SYMBOL_GPL(pci_disable_pcie_error_reporting);
  207. int pci_aer_clear_nonfatal_status(struct pci_dev *dev)
  208. {
  209. int aer = dev->aer_cap;
  210. u32 status, sev;
  211. if (!pcie_aer_is_native(dev))
  212. return -EIO;
  213. /* Clear status bits for ERR_NONFATAL errors only */
  214. pci_read_config_dword(dev, aer + PCI_ERR_UNCOR_STATUS, &status);
  215. pci_read_config_dword(dev, aer + PCI_ERR_UNCOR_SEVER, &sev);
  216. status &= ~sev;
  217. if (status)
  218. pci_write_config_dword(dev, aer + PCI_ERR_UNCOR_STATUS, status);
  219. return 0;
  220. }
  221. EXPORT_SYMBOL_GPL(pci_aer_clear_nonfatal_status);
  222. void pci_aer_clear_fatal_status(struct pci_dev *dev)
  223. {
  224. int aer = dev->aer_cap;
  225. u32 status, sev;
  226. if (!pcie_aer_is_native(dev))
  227. return;
  228. /* Clear status bits for ERR_FATAL errors only */
  229. pci_read_config_dword(dev, aer + PCI_ERR_UNCOR_STATUS, &status);
  230. pci_read_config_dword(dev, aer + PCI_ERR_UNCOR_SEVER, &sev);
  231. status &= sev;
  232. if (status)
  233. pci_write_config_dword(dev, aer + PCI_ERR_UNCOR_STATUS, status);
  234. }
  235. /**
  236. * pci_aer_raw_clear_status - Clear AER error registers.
  237. * @dev: the PCI device
  238. *
  239. * Clearing AER error status registers unconditionally, regardless of
  240. * whether they're owned by firmware or the OS.
  241. *
  242. * Returns 0 on success, or negative on failure.
  243. */
  244. int pci_aer_raw_clear_status(struct pci_dev *dev)
  245. {
  246. int aer = dev->aer_cap;
  247. u32 status;
  248. int port_type;
  249. if (!aer)
  250. return -EIO;
  251. port_type = pci_pcie_type(dev);
  252. if (port_type == PCI_EXP_TYPE_ROOT_PORT) {
  253. pci_read_config_dword(dev, aer + PCI_ERR_ROOT_STATUS, &status);
  254. pci_write_config_dword(dev, aer + PCI_ERR_ROOT_STATUS, status);
  255. }
  256. pci_read_config_dword(dev, aer + PCI_ERR_COR_STATUS, &status);
  257. pci_write_config_dword(dev, aer + PCI_ERR_COR_STATUS, status);
  258. pci_read_config_dword(dev, aer + PCI_ERR_UNCOR_STATUS, &status);
  259. pci_write_config_dword(dev, aer + PCI_ERR_UNCOR_STATUS, status);
  260. return 0;
  261. }
  262. int pci_aer_clear_status(struct pci_dev *dev)
  263. {
  264. if (!pcie_aer_is_native(dev))
  265. return -EIO;
  266. return pci_aer_raw_clear_status(dev);
  267. }
  268. void pci_save_aer_state(struct pci_dev *dev)
  269. {
  270. int aer = dev->aer_cap;
  271. struct pci_cap_saved_state *save_state;
  272. u32 *cap;
  273. if (!aer)
  274. return;
  275. save_state = pci_find_saved_ext_cap(dev, PCI_EXT_CAP_ID_ERR);
  276. if (!save_state)
  277. return;
  278. cap = &save_state->cap.data[0];
  279. pci_read_config_dword(dev, aer + PCI_ERR_UNCOR_MASK, cap++);
  280. pci_read_config_dword(dev, aer + PCI_ERR_UNCOR_SEVER, cap++);
  281. pci_read_config_dword(dev, aer + PCI_ERR_COR_MASK, cap++);
  282. pci_read_config_dword(dev, aer + PCI_ERR_CAP, cap++);
  283. if (pcie_cap_has_rtctl(dev))
  284. pci_read_config_dword(dev, aer + PCI_ERR_ROOT_COMMAND, cap++);
  285. }
  286. void pci_restore_aer_state(struct pci_dev *dev)
  287. {
  288. int aer = dev->aer_cap;
  289. struct pci_cap_saved_state *save_state;
  290. u32 *cap;
  291. if (!aer)
  292. return;
  293. save_state = pci_find_saved_ext_cap(dev, PCI_EXT_CAP_ID_ERR);
  294. if (!save_state)
  295. return;
  296. cap = &save_state->cap.data[0];
  297. pci_write_config_dword(dev, aer + PCI_ERR_UNCOR_MASK, *cap++);
  298. pci_write_config_dword(dev, aer + PCI_ERR_UNCOR_SEVER, *cap++);
  299. pci_write_config_dword(dev, aer + PCI_ERR_COR_MASK, *cap++);
  300. pci_write_config_dword(dev, aer + PCI_ERR_CAP, *cap++);
  301. if (pcie_cap_has_rtctl(dev))
  302. pci_write_config_dword(dev, aer + PCI_ERR_ROOT_COMMAND, *cap++);
  303. }
  304. void pci_aer_init(struct pci_dev *dev)
  305. {
  306. int n;
  307. dev->aer_cap = pci_find_ext_capability(dev, PCI_EXT_CAP_ID_ERR);
  308. if (!dev->aer_cap)
  309. return;
  310. dev->aer_stats = kzalloc(sizeof(struct aer_stats), GFP_KERNEL);
  311. /*
  312. * We save/restore PCI_ERR_UNCOR_MASK, PCI_ERR_UNCOR_SEVER,
  313. * PCI_ERR_COR_MASK, and PCI_ERR_CAP. Root and Root Complex Event
  314. * Collectors also implement PCI_ERR_ROOT_COMMAND (PCIe r5.0, sec
  315. * 7.8.4).
  316. */
  317. n = pcie_cap_has_rtctl(dev) ? 5 : 4;
  318. pci_add_ext_cap_save_buffer(dev, PCI_EXT_CAP_ID_ERR, sizeof(u32) * n);
  319. pci_aer_clear_status(dev);
  320. }
  321. void pci_aer_exit(struct pci_dev *dev)
  322. {
  323. kfree(dev->aer_stats);
  324. dev->aer_stats = NULL;
  325. }
  326. #define AER_AGENT_RECEIVER 0
  327. #define AER_AGENT_REQUESTER 1
  328. #define AER_AGENT_COMPLETER 2
  329. #define AER_AGENT_TRANSMITTER 3
  330. #define AER_AGENT_REQUESTER_MASK(t) ((t == AER_CORRECTABLE) ? \
  331. 0 : (PCI_ERR_UNC_COMP_TIME|PCI_ERR_UNC_UNSUP))
  332. #define AER_AGENT_COMPLETER_MASK(t) ((t == AER_CORRECTABLE) ? \
  333. 0 : PCI_ERR_UNC_COMP_ABORT)
  334. #define AER_AGENT_TRANSMITTER_MASK(t) ((t == AER_CORRECTABLE) ? \
  335. (PCI_ERR_COR_REP_ROLL|PCI_ERR_COR_REP_TIMER) : 0)
  336. #define AER_GET_AGENT(t, e) \
  337. ((e & AER_AGENT_COMPLETER_MASK(t)) ? AER_AGENT_COMPLETER : \
  338. (e & AER_AGENT_REQUESTER_MASK(t)) ? AER_AGENT_REQUESTER : \
  339. (e & AER_AGENT_TRANSMITTER_MASK(t)) ? AER_AGENT_TRANSMITTER : \
  340. AER_AGENT_RECEIVER)
  341. #define AER_PHYSICAL_LAYER_ERROR 0
  342. #define AER_DATA_LINK_LAYER_ERROR 1
  343. #define AER_TRANSACTION_LAYER_ERROR 2
  344. #define AER_PHYSICAL_LAYER_ERROR_MASK(t) ((t == AER_CORRECTABLE) ? \
  345. PCI_ERR_COR_RCVR : 0)
  346. #define AER_DATA_LINK_LAYER_ERROR_MASK(t) ((t == AER_CORRECTABLE) ? \
  347. (PCI_ERR_COR_BAD_TLP| \
  348. PCI_ERR_COR_BAD_DLLP| \
  349. PCI_ERR_COR_REP_ROLL| \
  350. PCI_ERR_COR_REP_TIMER) : PCI_ERR_UNC_DLP)
  351. #define AER_GET_LAYER_ERROR(t, e) \
  352. ((e & AER_PHYSICAL_LAYER_ERROR_MASK(t)) ? AER_PHYSICAL_LAYER_ERROR : \
  353. (e & AER_DATA_LINK_LAYER_ERROR_MASK(t)) ? AER_DATA_LINK_LAYER_ERROR : \
  354. AER_TRANSACTION_LAYER_ERROR)
  355. /*
  356. * AER error strings
  357. */
  358. static const char *aer_error_severity_string[] = {
  359. "Uncorrected (Non-Fatal)",
  360. "Uncorrected (Fatal)",
  361. "Corrected"
  362. };
  363. static const char *aer_error_layer[] = {
  364. "Physical Layer",
  365. "Data Link Layer",
  366. "Transaction Layer"
  367. };
  368. static const char *aer_correctable_error_string[] = {
  369. "RxErr", /* Bit Position 0 */
  370. NULL,
  371. NULL,
  372. NULL,
  373. NULL,
  374. NULL,
  375. "BadTLP", /* Bit Position 6 */
  376. "BadDLLP", /* Bit Position 7 */
  377. "Rollover", /* Bit Position 8 */
  378. NULL,
  379. NULL,
  380. NULL,
  381. "Timeout", /* Bit Position 12 */
  382. "NonFatalErr", /* Bit Position 13 */
  383. "CorrIntErr", /* Bit Position 14 */
  384. "HeaderOF", /* Bit Position 15 */
  385. NULL, /* Bit Position 16 */
  386. NULL, /* Bit Position 17 */
  387. NULL, /* Bit Position 18 */
  388. NULL, /* Bit Position 19 */
  389. NULL, /* Bit Position 20 */
  390. NULL, /* Bit Position 21 */
  391. NULL, /* Bit Position 22 */
  392. NULL, /* Bit Position 23 */
  393. NULL, /* Bit Position 24 */
  394. NULL, /* Bit Position 25 */
  395. NULL, /* Bit Position 26 */
  396. NULL, /* Bit Position 27 */
  397. NULL, /* Bit Position 28 */
  398. NULL, /* Bit Position 29 */
  399. NULL, /* Bit Position 30 */
  400. NULL, /* Bit Position 31 */
  401. };
  402. static const char *aer_uncorrectable_error_string[] = {
  403. "Undefined", /* Bit Position 0 */
  404. NULL,
  405. NULL,
  406. NULL,
  407. "DLP", /* Bit Position 4 */
  408. "SDES", /* Bit Position 5 */
  409. NULL,
  410. NULL,
  411. NULL,
  412. NULL,
  413. NULL,
  414. NULL,
  415. "TLP", /* Bit Position 12 */
  416. "FCP", /* Bit Position 13 */
  417. "CmpltTO", /* Bit Position 14 */
  418. "CmpltAbrt", /* Bit Position 15 */
  419. "UnxCmplt", /* Bit Position 16 */
  420. "RxOF", /* Bit Position 17 */
  421. "MalfTLP", /* Bit Position 18 */
  422. "ECRC", /* Bit Position 19 */
  423. "UnsupReq", /* Bit Position 20 */
  424. "ACSViol", /* Bit Position 21 */
  425. "UncorrIntErr", /* Bit Position 22 */
  426. "BlockedTLP", /* Bit Position 23 */
  427. "AtomicOpBlocked", /* Bit Position 24 */
  428. "TLPBlockedErr", /* Bit Position 25 */
  429. "PoisonTLPBlocked", /* Bit Position 26 */
  430. NULL, /* Bit Position 27 */
  431. NULL, /* Bit Position 28 */
  432. NULL, /* Bit Position 29 */
  433. NULL, /* Bit Position 30 */
  434. NULL, /* Bit Position 31 */
  435. };
  436. static const char *aer_agent_string[] = {
  437. "Receiver ID",
  438. "Requester ID",
  439. "Completer ID",
  440. "Transmitter ID"
  441. };
  442. #define aer_stats_dev_attr(name, stats_array, strings_array, \
  443. total_string, total_field) \
  444. static ssize_t \
  445. name##_show(struct device *dev, struct device_attribute *attr, \
  446. char *buf) \
  447. { \
  448. unsigned int i; \
  449. char *str = buf; \
  450. struct pci_dev *pdev = to_pci_dev(dev); \
  451. u64 *stats = pdev->aer_stats->stats_array; \
  452. \
  453. for (i = 0; i < ARRAY_SIZE(strings_array); i++) { \
  454. if (strings_array[i]) \
  455. str += sprintf(str, "%s %llu\n", \
  456. strings_array[i], stats[i]); \
  457. else if (stats[i]) \
  458. str += sprintf(str, #stats_array "_bit[%d] %llu\n",\
  459. i, stats[i]); \
  460. } \
  461. str += sprintf(str, "TOTAL_%s %llu\n", total_string, \
  462. pdev->aer_stats->total_field); \
  463. return str-buf; \
  464. } \
  465. static DEVICE_ATTR_RO(name)
  466. aer_stats_dev_attr(aer_dev_correctable, dev_cor_errs,
  467. aer_correctable_error_string, "ERR_COR",
  468. dev_total_cor_errs);
  469. aer_stats_dev_attr(aer_dev_fatal, dev_fatal_errs,
  470. aer_uncorrectable_error_string, "ERR_FATAL",
  471. dev_total_fatal_errs);
  472. aer_stats_dev_attr(aer_dev_nonfatal, dev_nonfatal_errs,
  473. aer_uncorrectable_error_string, "ERR_NONFATAL",
  474. dev_total_nonfatal_errs);
  475. #define aer_stats_rootport_attr(name, field) \
  476. static ssize_t \
  477. name##_show(struct device *dev, struct device_attribute *attr, \
  478. char *buf) \
  479. { \
  480. struct pci_dev *pdev = to_pci_dev(dev); \
  481. return sprintf(buf, "%llu\n", pdev->aer_stats->field); \
  482. } \
  483. static DEVICE_ATTR_RO(name)
  484. aer_stats_rootport_attr(aer_rootport_total_err_cor,
  485. rootport_total_cor_errs);
  486. aer_stats_rootport_attr(aer_rootport_total_err_fatal,
  487. rootport_total_fatal_errs);
  488. aer_stats_rootport_attr(aer_rootport_total_err_nonfatal,
  489. rootport_total_nonfatal_errs);
  490. static struct attribute *aer_stats_attrs[] __ro_after_init = {
  491. &dev_attr_aer_dev_correctable.attr,
  492. &dev_attr_aer_dev_fatal.attr,
  493. &dev_attr_aer_dev_nonfatal.attr,
  494. &dev_attr_aer_rootport_total_err_cor.attr,
  495. &dev_attr_aer_rootport_total_err_fatal.attr,
  496. &dev_attr_aer_rootport_total_err_nonfatal.attr,
  497. NULL
  498. };
  499. static umode_t aer_stats_attrs_are_visible(struct kobject *kobj,
  500. struct attribute *a, int n)
  501. {
  502. struct device *dev = kobj_to_dev(kobj);
  503. struct pci_dev *pdev = to_pci_dev(dev);
  504. if (!pdev->aer_stats)
  505. return 0;
  506. if ((a == &dev_attr_aer_rootport_total_err_cor.attr ||
  507. a == &dev_attr_aer_rootport_total_err_fatal.attr ||
  508. a == &dev_attr_aer_rootport_total_err_nonfatal.attr) &&
  509. pci_pcie_type(pdev) != PCI_EXP_TYPE_ROOT_PORT)
  510. return 0;
  511. return a->mode;
  512. }
  513. const struct attribute_group aer_stats_attr_group = {
  514. .attrs = aer_stats_attrs,
  515. .is_visible = aer_stats_attrs_are_visible,
  516. };
  517. static void pci_dev_aer_stats_incr(struct pci_dev *pdev,
  518. struct aer_err_info *info)
  519. {
  520. unsigned long status = info->status & ~info->mask;
  521. int i, max = -1;
  522. u64 *counter = NULL;
  523. struct aer_stats *aer_stats = pdev->aer_stats;
  524. if (!aer_stats)
  525. return;
  526. switch (info->severity) {
  527. case AER_CORRECTABLE:
  528. aer_stats->dev_total_cor_errs++;
  529. counter = &aer_stats->dev_cor_errs[0];
  530. max = AER_MAX_TYPEOF_COR_ERRS;
  531. break;
  532. case AER_NONFATAL:
  533. aer_stats->dev_total_nonfatal_errs++;
  534. counter = &aer_stats->dev_nonfatal_errs[0];
  535. max = AER_MAX_TYPEOF_UNCOR_ERRS;
  536. break;
  537. case AER_FATAL:
  538. aer_stats->dev_total_fatal_errs++;
  539. counter = &aer_stats->dev_fatal_errs[0];
  540. max = AER_MAX_TYPEOF_UNCOR_ERRS;
  541. break;
  542. }
  543. for_each_set_bit(i, &status, max)
  544. counter[i]++;
  545. }
  546. static void pci_rootport_aer_stats_incr(struct pci_dev *pdev,
  547. struct aer_err_source *e_src)
  548. {
  549. struct aer_stats *aer_stats = pdev->aer_stats;
  550. if (!aer_stats)
  551. return;
  552. if (e_src->status & PCI_ERR_ROOT_COR_RCV)
  553. aer_stats->rootport_total_cor_errs++;
  554. if (e_src->status & PCI_ERR_ROOT_UNCOR_RCV) {
  555. if (e_src->status & PCI_ERR_ROOT_FATAL_RCV)
  556. aer_stats->rootport_total_fatal_errs++;
  557. else
  558. aer_stats->rootport_total_nonfatal_errs++;
  559. }
  560. }
  561. static void __print_tlp_header(struct pci_dev *dev,
  562. struct aer_header_log_regs *t)
  563. {
  564. pci_err(dev, " TLP Header: %08x %08x %08x %08x\n",
  565. t->dw0, t->dw1, t->dw2, t->dw3);
  566. }
  567. static void __aer_print_error(struct pci_dev *dev,
  568. struct aer_err_info *info)
  569. {
  570. const char **strings;
  571. unsigned long status = info->status & ~info->mask;
  572. const char *level, *errmsg;
  573. int i;
  574. if (info->severity == AER_CORRECTABLE) {
  575. strings = aer_correctable_error_string;
  576. level = KERN_WARNING;
  577. } else {
  578. strings = aer_uncorrectable_error_string;
  579. level = KERN_ERR;
  580. }
  581. for_each_set_bit(i, &status, 32) {
  582. errmsg = strings[i];
  583. if (!errmsg)
  584. errmsg = "Unknown Error Bit";
  585. pci_printk(level, dev, " [%2d] %-22s%s\n", i, errmsg,
  586. info->first_error == i ? " (First)" : "");
  587. }
  588. pci_dev_aer_stats_incr(dev, info);
  589. }
  590. void aer_print_error(struct pci_dev *dev, struct aer_err_info *info)
  591. {
  592. int layer, agent;
  593. int id = ((dev->bus->number << 8) | dev->devfn);
  594. const char *level;
  595. if (!info->status) {
  596. pci_err(dev, "PCIe Bus Error: severity=%s, type=Inaccessible, (Unregistered Agent ID)\n",
  597. aer_error_severity_string[info->severity]);
  598. goto out;
  599. }
  600. layer = AER_GET_LAYER_ERROR(info->severity, info->status);
  601. agent = AER_GET_AGENT(info->severity, info->status);
  602. level = (info->severity == AER_CORRECTABLE) ? KERN_WARNING : KERN_ERR;
  603. pci_printk(level, dev, "PCIe Bus Error: severity=%s, type=%s, (%s)\n",
  604. aer_error_severity_string[info->severity],
  605. aer_error_layer[layer], aer_agent_string[agent]);
  606. pci_printk(level, dev, " device [%04x:%04x] error status/mask=%08x/%08x\n",
  607. dev->vendor, dev->device, info->status, info->mask);
  608. __aer_print_error(dev, info);
  609. if (info->tlp_header_valid)
  610. __print_tlp_header(dev, &info->tlp);
  611. out:
  612. if (info->id && info->error_dev_num > 1 && info->id == id)
  613. pci_err(dev, " Error of this Agent is reported first\n");
  614. trace_aer_event(dev_name(&dev->dev), (info->status & ~info->mask),
  615. info->severity, info->tlp_header_valid, &info->tlp);
  616. }
  617. static void aer_print_port_info(struct pci_dev *dev, struct aer_err_info *info)
  618. {
  619. u8 bus = info->id >> 8;
  620. u8 devfn = info->id & 0xff;
  621. pci_info(dev, "%s%s error received: %04x:%02x:%02x.%d\n",
  622. info->multi_error_valid ? "Multiple " : "",
  623. aer_error_severity_string[info->severity],
  624. pci_domain_nr(dev->bus), bus, PCI_SLOT(devfn),
  625. PCI_FUNC(devfn));
  626. }
  627. #ifdef CONFIG_ACPI_APEI_PCIEAER
  628. int cper_severity_to_aer(int cper_severity)
  629. {
  630. switch (cper_severity) {
  631. case CPER_SEV_RECOVERABLE:
  632. return AER_NONFATAL;
  633. case CPER_SEV_FATAL:
  634. return AER_FATAL;
  635. default:
  636. return AER_CORRECTABLE;
  637. }
  638. }
  639. EXPORT_SYMBOL_GPL(cper_severity_to_aer);
  640. void cper_print_aer(struct pci_dev *dev, int aer_severity,
  641. struct aer_capability_regs *aer)
  642. {
  643. int layer, agent, tlp_header_valid = 0;
  644. u32 status, mask;
  645. struct aer_err_info info;
  646. if (aer_severity == AER_CORRECTABLE) {
  647. status = aer->cor_status;
  648. mask = aer->cor_mask;
  649. } else {
  650. status = aer->uncor_status;
  651. mask = aer->uncor_mask;
  652. tlp_header_valid = status & AER_LOG_TLP_MASKS;
  653. }
  654. layer = AER_GET_LAYER_ERROR(aer_severity, status);
  655. agent = AER_GET_AGENT(aer_severity, status);
  656. memset(&info, 0, sizeof(info));
  657. info.severity = aer_severity;
  658. info.status = status;
  659. info.mask = mask;
  660. info.first_error = PCI_ERR_CAP_FEP(aer->cap_control);
  661. pci_err(dev, "aer_status: 0x%08x, aer_mask: 0x%08x\n", status, mask);
  662. __aer_print_error(dev, &info);
  663. pci_err(dev, "aer_layer=%s, aer_agent=%s\n",
  664. aer_error_layer[layer], aer_agent_string[agent]);
  665. if (aer_severity != AER_CORRECTABLE)
  666. pci_err(dev, "aer_uncor_severity: 0x%08x\n",
  667. aer->uncor_severity);
  668. if (tlp_header_valid)
  669. __print_tlp_header(dev, &aer->header_log);
  670. trace_aer_event(dev_name(&dev->dev), (status & ~mask),
  671. aer_severity, tlp_header_valid, &aer->header_log);
  672. }
  673. #endif
  674. /**
  675. * add_error_device - list device to be handled
  676. * @e_info: pointer to error info
  677. * @dev: pointer to pci_dev to be added
  678. */
  679. static int add_error_device(struct aer_err_info *e_info, struct pci_dev *dev)
  680. {
  681. if (e_info->error_dev_num < AER_MAX_MULTI_ERR_DEVICES) {
  682. e_info->dev[e_info->error_dev_num] = pci_dev_get(dev);
  683. e_info->error_dev_num++;
  684. return 0;
  685. }
  686. return -ENOSPC;
  687. }
  688. /**
  689. * is_error_source - check whether the device is source of reported error
  690. * @dev: pointer to pci_dev to be checked
  691. * @e_info: pointer to reported error info
  692. */
  693. static bool is_error_source(struct pci_dev *dev, struct aer_err_info *e_info)
  694. {
  695. int aer = dev->aer_cap;
  696. u32 status, mask;
  697. u16 reg16;
  698. /*
  699. * When bus id is equal to 0, it might be a bad id
  700. * reported by root port.
  701. */
  702. if ((PCI_BUS_NUM(e_info->id) != 0) &&
  703. !(dev->bus->bus_flags & PCI_BUS_FLAGS_NO_AERSID)) {
  704. /* Device ID match? */
  705. if (e_info->id == ((dev->bus->number << 8) | dev->devfn))
  706. return true;
  707. /* Continue id comparing if there is no multiple error */
  708. if (!e_info->multi_error_valid)
  709. return false;
  710. }
  711. /*
  712. * When either
  713. * 1) bus id is equal to 0. Some ports might lose the bus
  714. * id of error source id;
  715. * 2) bus flag PCI_BUS_FLAGS_NO_AERSID is set
  716. * 3) There are multiple errors and prior ID comparing fails;
  717. * We check AER status registers to find possible reporter.
  718. */
  719. if (atomic_read(&dev->enable_cnt) == 0)
  720. return false;
  721. /* Check if AER is enabled */
  722. pcie_capability_read_word(dev, PCI_EXP_DEVCTL, &reg16);
  723. if (!(reg16 & PCI_EXP_AER_FLAGS))
  724. return false;
  725. if (!aer)
  726. return false;
  727. /* Check if error is recorded */
  728. if (e_info->severity == AER_CORRECTABLE) {
  729. pci_read_config_dword(dev, aer + PCI_ERR_COR_STATUS, &status);
  730. pci_read_config_dword(dev, aer + PCI_ERR_COR_MASK, &mask);
  731. } else {
  732. pci_read_config_dword(dev, aer + PCI_ERR_UNCOR_STATUS, &status);
  733. pci_read_config_dword(dev, aer + PCI_ERR_UNCOR_MASK, &mask);
  734. }
  735. if (status & ~mask)
  736. return true;
  737. return false;
  738. }
  739. static int find_device_iter(struct pci_dev *dev, void *data)
  740. {
  741. struct aer_err_info *e_info = (struct aer_err_info *)data;
  742. if (is_error_source(dev, e_info)) {
  743. /* List this device */
  744. if (add_error_device(e_info, dev)) {
  745. /* We cannot handle more... Stop iteration */
  746. /* TODO: Should print error message here? */
  747. return 1;
  748. }
  749. /* If there is only a single error, stop iteration */
  750. if (!e_info->multi_error_valid)
  751. return 1;
  752. }
  753. return 0;
  754. }
  755. /**
  756. * find_source_device - search through device hierarchy for source device
  757. * @parent: pointer to Root Port pci_dev data structure
  758. * @e_info: including detailed error information such like id
  759. *
  760. * Return true if found.
  761. *
  762. * Invoked by DPC when error is detected at the Root Port.
  763. * Caller of this function must set id, severity, and multi_error_valid of
  764. * struct aer_err_info pointed by @e_info properly. This function must fill
  765. * e_info->error_dev_num and e_info->dev[], based on the given information.
  766. */
  767. static bool find_source_device(struct pci_dev *parent,
  768. struct aer_err_info *e_info)
  769. {
  770. struct pci_dev *dev = parent;
  771. int result;
  772. /* Must reset in this function */
  773. e_info->error_dev_num = 0;
  774. /* Is Root Port an agent that sends error message? */
  775. result = find_device_iter(dev, e_info);
  776. if (result)
  777. return true;
  778. pci_walk_bus(parent->subordinate, find_device_iter, e_info);
  779. if (!e_info->error_dev_num) {
  780. pci_info(parent, "can't find device of ID%04x\n", e_info->id);
  781. return false;
  782. }
  783. return true;
  784. }
  785. /**
  786. * handle_error_source - handle logging error into an event log
  787. * @dev: pointer to pci_dev data structure of error source device
  788. * @info: comprehensive error information
  789. *
  790. * Invoked when an error being detected by Root Port.
  791. */
  792. static void handle_error_source(struct pci_dev *dev, struct aer_err_info *info)
  793. {
  794. int aer = dev->aer_cap;
  795. if (info->severity == AER_CORRECTABLE) {
  796. /*
  797. * Correctable error does not need software intervention.
  798. * No need to go through error recovery process.
  799. */
  800. if (aer)
  801. pci_write_config_dword(dev, aer + PCI_ERR_COR_STATUS,
  802. info->status);
  803. if (pcie_aer_is_native(dev))
  804. pcie_clear_device_status(dev);
  805. } else if (info->severity == AER_NONFATAL)
  806. pcie_do_recovery(dev, pci_channel_io_normal, aer_root_reset);
  807. else if (info->severity == AER_FATAL)
  808. pcie_do_recovery(dev, pci_channel_io_frozen, aer_root_reset);
  809. pci_dev_put(dev);
  810. }
  811. #ifdef CONFIG_ACPI_APEI_PCIEAER
  812. #define AER_RECOVER_RING_ORDER 4
  813. #define AER_RECOVER_RING_SIZE (1 << AER_RECOVER_RING_ORDER)
  814. struct aer_recover_entry {
  815. u8 bus;
  816. u8 devfn;
  817. u16 domain;
  818. int severity;
  819. struct aer_capability_regs *regs;
  820. };
  821. static DEFINE_KFIFO(aer_recover_ring, struct aer_recover_entry,
  822. AER_RECOVER_RING_SIZE);
  823. static void aer_recover_work_func(struct work_struct *work)
  824. {
  825. struct aer_recover_entry entry;
  826. struct pci_dev *pdev;
  827. while (kfifo_get(&aer_recover_ring, &entry)) {
  828. pdev = pci_get_domain_bus_and_slot(entry.domain, entry.bus,
  829. entry.devfn);
  830. if (!pdev) {
  831. pr_err("AER recover: Can not find pci_dev for %04x:%02x:%02x:%x\n",
  832. entry.domain, entry.bus,
  833. PCI_SLOT(entry.devfn), PCI_FUNC(entry.devfn));
  834. continue;
  835. }
  836. cper_print_aer(pdev, entry.severity, entry.regs);
  837. if (entry.severity == AER_NONFATAL)
  838. pcie_do_recovery(pdev, pci_channel_io_normal,
  839. aer_root_reset);
  840. else if (entry.severity == AER_FATAL)
  841. pcie_do_recovery(pdev, pci_channel_io_frozen,
  842. aer_root_reset);
  843. pci_dev_put(pdev);
  844. }
  845. }
  846. /*
  847. * Mutual exclusion for writers of aer_recover_ring, reader side don't
  848. * need lock, because there is only one reader and lock is not needed
  849. * between reader and writer.
  850. */
  851. static DEFINE_SPINLOCK(aer_recover_ring_lock);
  852. static DECLARE_WORK(aer_recover_work, aer_recover_work_func);
  853. void aer_recover_queue(int domain, unsigned int bus, unsigned int devfn,
  854. int severity, struct aer_capability_regs *aer_regs)
  855. {
  856. struct aer_recover_entry entry = {
  857. .bus = bus,
  858. .devfn = devfn,
  859. .domain = domain,
  860. .severity = severity,
  861. .regs = aer_regs,
  862. };
  863. if (kfifo_in_spinlocked(&aer_recover_ring, &entry, 1,
  864. &aer_recover_ring_lock))
  865. schedule_work(&aer_recover_work);
  866. else
  867. pr_err("AER recover: Buffer overflow when recovering AER for %04x:%02x:%02x:%x\n",
  868. domain, bus, PCI_SLOT(devfn), PCI_FUNC(devfn));
  869. }
  870. EXPORT_SYMBOL_GPL(aer_recover_queue);
  871. #endif
  872. /**
  873. * aer_get_device_error_info - read error status from dev and store it to info
  874. * @dev: pointer to the device expected to have a error record
  875. * @info: pointer to structure to store the error record
  876. *
  877. * Return 1 on success, 0 on error.
  878. *
  879. * Note that @info is reused among all error devices. Clear fields properly.
  880. */
  881. int aer_get_device_error_info(struct pci_dev *dev, struct aer_err_info *info)
  882. {
  883. int aer = dev->aer_cap;
  884. int temp;
  885. /* Must reset in this function */
  886. info->status = 0;
  887. info->tlp_header_valid = 0;
  888. /* The device might not support AER */
  889. if (!aer)
  890. return 0;
  891. if (info->severity == AER_CORRECTABLE) {
  892. pci_read_config_dword(dev, aer + PCI_ERR_COR_STATUS,
  893. &info->status);
  894. pci_read_config_dword(dev, aer + PCI_ERR_COR_MASK,
  895. &info->mask);
  896. if (!(info->status & ~info->mask))
  897. return 0;
  898. } else if (pci_pcie_type(dev) == PCI_EXP_TYPE_ROOT_PORT ||
  899. pci_pcie_type(dev) == PCI_EXP_TYPE_DOWNSTREAM ||
  900. info->severity == AER_NONFATAL) {
  901. /* Link is still healthy for IO reads */
  902. pci_read_config_dword(dev, aer + PCI_ERR_UNCOR_STATUS,
  903. &info->status);
  904. pci_read_config_dword(dev, aer + PCI_ERR_UNCOR_MASK,
  905. &info->mask);
  906. if (!(info->status & ~info->mask))
  907. return 0;
  908. /* Get First Error Pointer */
  909. pci_read_config_dword(dev, aer + PCI_ERR_CAP, &temp);
  910. info->first_error = PCI_ERR_CAP_FEP(temp);
  911. if (info->status & AER_LOG_TLP_MASKS) {
  912. info->tlp_header_valid = 1;
  913. pci_read_config_dword(dev,
  914. aer + PCI_ERR_HEADER_LOG, &info->tlp.dw0);
  915. pci_read_config_dword(dev,
  916. aer + PCI_ERR_HEADER_LOG + 4, &info->tlp.dw1);
  917. pci_read_config_dword(dev,
  918. aer + PCI_ERR_HEADER_LOG + 8, &info->tlp.dw2);
  919. pci_read_config_dword(dev,
  920. aer + PCI_ERR_HEADER_LOG + 12, &info->tlp.dw3);
  921. }
  922. }
  923. return 1;
  924. }
  925. static inline void aer_process_err_devices(struct aer_err_info *e_info)
  926. {
  927. int i;
  928. /* Report all before handle them, not to lost records by reset etc. */
  929. for (i = 0; i < e_info->error_dev_num && e_info->dev[i]; i++) {
  930. if (aer_get_device_error_info(e_info->dev[i], e_info))
  931. aer_print_error(e_info->dev[i], e_info);
  932. }
  933. for (i = 0; i < e_info->error_dev_num && e_info->dev[i]; i++) {
  934. if (aer_get_device_error_info(e_info->dev[i], e_info))
  935. handle_error_source(e_info->dev[i], e_info);
  936. }
  937. }
  938. /**
  939. * aer_isr_one_error - consume an error detected by root port
  940. * @rpc: pointer to the root port which holds an error
  941. * @e_src: pointer to an error source
  942. */
  943. static void aer_isr_one_error(struct aer_rpc *rpc,
  944. struct aer_err_source *e_src)
  945. {
  946. struct pci_dev *pdev = rpc->rpd;
  947. struct aer_err_info e_info;
  948. pci_rootport_aer_stats_incr(pdev, e_src);
  949. /*
  950. * There is a possibility that both correctable error and
  951. * uncorrectable error being logged. Report correctable error first.
  952. */
  953. if (e_src->status & PCI_ERR_ROOT_COR_RCV) {
  954. e_info.id = ERR_COR_ID(e_src->id);
  955. e_info.severity = AER_CORRECTABLE;
  956. if (e_src->status & PCI_ERR_ROOT_MULTI_COR_RCV)
  957. e_info.multi_error_valid = 1;
  958. else
  959. e_info.multi_error_valid = 0;
  960. aer_print_port_info(pdev, &e_info);
  961. if (find_source_device(pdev, &e_info))
  962. aer_process_err_devices(&e_info);
  963. }
  964. if (e_src->status & PCI_ERR_ROOT_UNCOR_RCV) {
  965. e_info.id = ERR_UNCOR_ID(e_src->id);
  966. if (e_src->status & PCI_ERR_ROOT_FATAL_RCV)
  967. e_info.severity = AER_FATAL;
  968. else
  969. e_info.severity = AER_NONFATAL;
  970. if (e_src->status & PCI_ERR_ROOT_MULTI_UNCOR_RCV)
  971. e_info.multi_error_valid = 1;
  972. else
  973. e_info.multi_error_valid = 0;
  974. aer_print_port_info(pdev, &e_info);
  975. if (find_source_device(pdev, &e_info))
  976. aer_process_err_devices(&e_info);
  977. }
  978. }
  979. /**
  980. * aer_isr - consume errors detected by root port
  981. * @irq: IRQ assigned to Root Port
  982. * @context: pointer to Root Port data structure
  983. *
  984. * Invoked, as DPC, when root port records new detected error
  985. */
  986. static irqreturn_t aer_isr(int irq, void *context)
  987. {
  988. struct pcie_device *dev = (struct pcie_device *)context;
  989. struct aer_rpc *rpc = get_service_data(dev);
  990. struct aer_err_source e_src;
  991. if (kfifo_is_empty(&rpc->aer_fifo))
  992. return IRQ_NONE;
  993. while (kfifo_get(&rpc->aer_fifo, &e_src))
  994. aer_isr_one_error(rpc, &e_src);
  995. return IRQ_HANDLED;
  996. }
  997. /**
  998. * aer_irq - Root Port's ISR
  999. * @irq: IRQ assigned to Root Port
  1000. * @context: pointer to Root Port data structure
  1001. *
  1002. * Invoked when Root Port detects AER messages.
  1003. */
  1004. static irqreturn_t aer_irq(int irq, void *context)
  1005. {
  1006. struct pcie_device *pdev = (struct pcie_device *)context;
  1007. struct aer_rpc *rpc = get_service_data(pdev);
  1008. struct pci_dev *rp = rpc->rpd;
  1009. int aer = rp->aer_cap;
  1010. struct aer_err_source e_src = {};
  1011. pci_read_config_dword(rp, aer + PCI_ERR_ROOT_STATUS, &e_src.status);
  1012. if (!(e_src.status & (PCI_ERR_ROOT_UNCOR_RCV|PCI_ERR_ROOT_COR_RCV)))
  1013. return IRQ_NONE;
  1014. pci_read_config_dword(rp, aer + PCI_ERR_ROOT_ERR_SRC, &e_src.id);
  1015. pci_write_config_dword(rp, aer + PCI_ERR_ROOT_STATUS, e_src.status);
  1016. if (!kfifo_put(&rpc->aer_fifo, e_src))
  1017. return IRQ_HANDLED;
  1018. return IRQ_WAKE_THREAD;
  1019. }
  1020. static int set_device_error_reporting(struct pci_dev *dev, void *data)
  1021. {
  1022. bool enable = *((bool *)data);
  1023. int type = pci_pcie_type(dev);
  1024. if ((type == PCI_EXP_TYPE_ROOT_PORT) ||
  1025. (type == PCI_EXP_TYPE_UPSTREAM) ||
  1026. (type == PCI_EXP_TYPE_DOWNSTREAM)) {
  1027. if (enable)
  1028. pci_enable_pcie_error_reporting(dev);
  1029. else
  1030. pci_disable_pcie_error_reporting(dev);
  1031. }
  1032. if (enable)
  1033. pcie_set_ecrc_checking(dev);
  1034. return 0;
  1035. }
  1036. /**
  1037. * set_downstream_devices_error_reporting - enable/disable the error reporting bits on the root port and its downstream ports.
  1038. * @dev: pointer to root port's pci_dev data structure
  1039. * @enable: true = enable error reporting, false = disable error reporting.
  1040. */
  1041. static void set_downstream_devices_error_reporting(struct pci_dev *dev,
  1042. bool enable)
  1043. {
  1044. set_device_error_reporting(dev, &enable);
  1045. if (!dev->subordinate)
  1046. return;
  1047. pci_walk_bus(dev->subordinate, set_device_error_reporting, &enable);
  1048. }
  1049. /**
  1050. * aer_enable_rootport - enable Root Port's interrupts when receiving messages
  1051. * @rpc: pointer to a Root Port data structure
  1052. *
  1053. * Invoked when PCIe bus loads AER service driver.
  1054. */
  1055. static void aer_enable_rootport(struct aer_rpc *rpc)
  1056. {
  1057. struct pci_dev *pdev = rpc->rpd;
  1058. int aer = pdev->aer_cap;
  1059. u16 reg16;
  1060. u32 reg32;
  1061. /* Clear PCIe Capability's Device Status */
  1062. pcie_capability_read_word(pdev, PCI_EXP_DEVSTA, &reg16);
  1063. pcie_capability_write_word(pdev, PCI_EXP_DEVSTA, reg16);
  1064. /* Disable system error generation in response to error messages */
  1065. pcie_capability_clear_word(pdev, PCI_EXP_RTCTL,
  1066. SYSTEM_ERROR_INTR_ON_MESG_MASK);
  1067. /* Clear error status */
  1068. pci_read_config_dword(pdev, aer + PCI_ERR_ROOT_STATUS, &reg32);
  1069. pci_write_config_dword(pdev, aer + PCI_ERR_ROOT_STATUS, reg32);
  1070. pci_read_config_dword(pdev, aer + PCI_ERR_COR_STATUS, &reg32);
  1071. pci_write_config_dword(pdev, aer + PCI_ERR_COR_STATUS, reg32);
  1072. pci_read_config_dword(pdev, aer + PCI_ERR_UNCOR_STATUS, &reg32);
  1073. pci_write_config_dword(pdev, aer + PCI_ERR_UNCOR_STATUS, reg32);
  1074. /*
  1075. * Enable error reporting for the root port device and downstream port
  1076. * devices.
  1077. */
  1078. set_downstream_devices_error_reporting(pdev, true);
  1079. /* Enable Root Port's interrupt in response to error messages */
  1080. pci_read_config_dword(pdev, aer + PCI_ERR_ROOT_COMMAND, &reg32);
  1081. reg32 |= ROOT_PORT_INTR_ON_MESG_MASK;
  1082. pci_write_config_dword(pdev, aer + PCI_ERR_ROOT_COMMAND, reg32);
  1083. }
  1084. /**
  1085. * aer_disable_rootport - disable Root Port's interrupts when receiving messages
  1086. * @rpc: pointer to a Root Port data structure
  1087. *
  1088. * Invoked when PCIe bus unloads AER service driver.
  1089. */
  1090. static void aer_disable_rootport(struct aer_rpc *rpc)
  1091. {
  1092. struct pci_dev *pdev = rpc->rpd;
  1093. int aer = pdev->aer_cap;
  1094. u32 reg32;
  1095. /*
  1096. * Disable error reporting for the root port device and downstream port
  1097. * devices.
  1098. */
  1099. set_downstream_devices_error_reporting(pdev, false);
  1100. /* Disable Root's interrupt in response to error messages */
  1101. pci_read_config_dword(pdev, aer + PCI_ERR_ROOT_COMMAND, &reg32);
  1102. reg32 &= ~ROOT_PORT_INTR_ON_MESG_MASK;
  1103. pci_write_config_dword(pdev, aer + PCI_ERR_ROOT_COMMAND, reg32);
  1104. /* Clear Root's error status reg */
  1105. pci_read_config_dword(pdev, aer + PCI_ERR_ROOT_STATUS, &reg32);
  1106. pci_write_config_dword(pdev, aer + PCI_ERR_ROOT_STATUS, reg32);
  1107. }
  1108. /**
  1109. * aer_remove - clean up resources
  1110. * @dev: pointer to the pcie_dev data structure
  1111. *
  1112. * Invoked when PCI Express bus unloads or AER probe fails.
  1113. */
  1114. static void aer_remove(struct pcie_device *dev)
  1115. {
  1116. struct aer_rpc *rpc = get_service_data(dev);
  1117. aer_disable_rootport(rpc);
  1118. }
  1119. /**
  1120. * aer_probe - initialize resources
  1121. * @dev: pointer to the pcie_dev data structure
  1122. *
  1123. * Invoked when PCI Express bus loads AER service driver.
  1124. */
  1125. static int aer_probe(struct pcie_device *dev)
  1126. {
  1127. int status;
  1128. struct aer_rpc *rpc;
  1129. struct device *device = &dev->device;
  1130. struct pci_dev *port = dev->port;
  1131. rpc = devm_kzalloc(device, sizeof(struct aer_rpc), GFP_KERNEL);
  1132. if (!rpc)
  1133. return -ENOMEM;
  1134. rpc->rpd = port;
  1135. INIT_KFIFO(rpc->aer_fifo);
  1136. set_service_data(dev, rpc);
  1137. status = devm_request_threaded_irq(device, dev->irq, aer_irq, aer_isr,
  1138. IRQF_SHARED, "aerdrv", dev);
  1139. if (status) {
  1140. pci_err(port, "request AER IRQ %d failed\n", dev->irq);
  1141. return status;
  1142. }
  1143. aer_enable_rootport(rpc);
  1144. pci_info(port, "enabled with IRQ %d\n", dev->irq);
  1145. return 0;
  1146. }
  1147. /**
  1148. * aer_root_reset - reset link on Root Port
  1149. * @dev: pointer to Root Port's pci_dev data structure
  1150. *
  1151. * Invoked by Port Bus driver when performing link reset at Root Port.
  1152. */
  1153. static pci_ers_result_t aer_root_reset(struct pci_dev *dev)
  1154. {
  1155. int aer = dev->aer_cap;
  1156. u32 reg32;
  1157. int rc;
  1158. /* Disable Root's interrupt in response to error messages */
  1159. pci_read_config_dword(dev, aer + PCI_ERR_ROOT_COMMAND, &reg32);
  1160. reg32 &= ~ROOT_PORT_INTR_ON_MESG_MASK;
  1161. pci_write_config_dword(dev, aer + PCI_ERR_ROOT_COMMAND, reg32);
  1162. rc = pci_bus_error_reset(dev);
  1163. pci_info(dev, "Root Port link has been reset\n");
  1164. /* Clear Root Error Status */
  1165. pci_read_config_dword(dev, aer + PCI_ERR_ROOT_STATUS, &reg32);
  1166. pci_write_config_dword(dev, aer + PCI_ERR_ROOT_STATUS, reg32);
  1167. /* Enable Root Port's interrupt in response to error messages */
  1168. pci_read_config_dword(dev, aer + PCI_ERR_ROOT_COMMAND, &reg32);
  1169. reg32 |= ROOT_PORT_INTR_ON_MESG_MASK;
  1170. pci_write_config_dword(dev, aer + PCI_ERR_ROOT_COMMAND, reg32);
  1171. return rc ? PCI_ERS_RESULT_DISCONNECT : PCI_ERS_RESULT_RECOVERED;
  1172. }
  1173. static struct pcie_port_service_driver aerdriver = {
  1174. .name = "aer",
  1175. .port_type = PCI_EXP_TYPE_ROOT_PORT,
  1176. .service = PCIE_PORT_SERVICE_AER,
  1177. .probe = aer_probe,
  1178. .remove = aer_remove,
  1179. };
  1180. /**
  1181. * aer_service_init - register AER root service driver
  1182. *
  1183. * Invoked when AER root service driver is loaded.
  1184. */
  1185. int __init pcie_aer_init(void)
  1186. {
  1187. if (!pci_aer_available())
  1188. return -ENXIO;
  1189. return pcie_port_service_register(&aerdriver);
  1190. }