pci.h 22 KB

123456789101112131415161718192021222324252627282930313233343536373839404142434445464748495051525354555657585960616263646566676869707172737475767778798081828384858687888990919293949596979899100101102103104105106107108109110111112113114115116117118119120121122123124125126127128129130131132133134135136137138139140141142143144145146147148149150151152153154155156157158159160161162163164165166167168169170171172173174175176177178179180181182183184185186187188189190191192193194195196197198199200201202203204205206207208209210211212213214215216217218219220221222223224225226227228229230231232233234235236237238239240241242243244245246247248249250251252253254255256257258259260261262263264265266267268269270271272273274275276277278279280281282283284285286287288289290291292293294295296297298299300301302303304305306307308309310311312313314315316317318319320321322323324325326327328329330331332333334335336337338339340341342343344345346347348349350351352353354355356357358359360361362363364365366367368369370371372373374375376377378379380381382383384385386387388389390391392393394395396397398399400401402403404405406407408409410411412413414415416417418419420421422423424425426427428429430431432433434435436437438439440441442443444445446447448449450451452453454455456457458459460461462463464465466467468469470471472473474475476477478479480481482483484485486487488489490491492493494495496497498499500501502503504505506507508509510511512513514515516517518519520521522523524525526527528529530531532533534535536537538539540541542543544545546547548549550551552553554555556557558559560561562563564565566567568569570571572573574575576577578579580581582583584585586587588589590591592593594595596597598599600601602603604605606607608609610611612613614615616617618619620621622623624625626627628629630631632633634635636637638639640641642643644645646647648649650651652653654655656657658659660661662663664665666667668669670671672673674675676677678679680681682683684685686687688689690691692693694695696697698699700701702703704705706707708709
  1. /* SPDX-License-Identifier: GPL-2.0 */
  2. #ifndef DRIVERS_PCI_H
  3. #define DRIVERS_PCI_H
  4. #include <linux/pci.h>
  5. #include <linux/android_kabi.h>
  6. /* Number of possible devfns: 0.0 to 1f.7 inclusive */
  7. #define MAX_NR_DEVFNS 256
  8. #define PCI_FIND_CAP_TTL 48
  9. #define PCI_VSEC_ID_INTEL_TBT 0x1234 /* Thunderbolt */
  10. extern const unsigned char pcie_link_speed[];
  11. extern bool pci_early_dump;
  12. bool pcie_cap_has_lnkctl(const struct pci_dev *dev);
  13. bool pcie_cap_has_rtctl(const struct pci_dev *dev);
  14. /* Functions internal to the PCI core code */
  15. int pci_create_sysfs_dev_files(struct pci_dev *pdev);
  16. void pci_remove_sysfs_dev_files(struct pci_dev *pdev);
  17. #if !defined(CONFIG_DMI) && !defined(CONFIG_ACPI)
  18. static inline void pci_create_firmware_label_files(struct pci_dev *pdev)
  19. { return; }
  20. static inline void pci_remove_firmware_label_files(struct pci_dev *pdev)
  21. { return; }
  22. #else
  23. void pci_create_firmware_label_files(struct pci_dev *pdev);
  24. void pci_remove_firmware_label_files(struct pci_dev *pdev);
  25. #endif
  26. void pci_cleanup_rom(struct pci_dev *dev);
  27. enum pci_mmap_api {
  28. PCI_MMAP_SYSFS, /* mmap on /sys/bus/pci/devices/<BDF>/resource<N> */
  29. PCI_MMAP_PROCFS /* mmap on /proc/bus/pci/<BDF> */
  30. };
  31. int pci_mmap_fits(struct pci_dev *pdev, int resno, struct vm_area_struct *vmai,
  32. enum pci_mmap_api mmap_api);
  33. int pci_probe_reset_function(struct pci_dev *dev);
  34. int pci_bridge_secondary_bus_reset(struct pci_dev *dev);
  35. int pci_bus_error_reset(struct pci_dev *dev);
  36. #define PCI_PM_D2_DELAY 200 /* usec; see PCIe r4.0, sec 5.9.1 */
  37. #define PCI_PM_D3HOT_WAIT 10 /* msec */
  38. #define PCI_PM_D3COLD_WAIT 100 /* msec */
  39. /**
  40. * struct pci_platform_pm_ops - Firmware PM callbacks
  41. *
  42. * @bridge_d3: Does the bridge allow entering into D3
  43. *
  44. * @is_manageable: returns 'true' if given device is power manageable by the
  45. * platform firmware
  46. *
  47. * @set_state: invokes the platform firmware to set the device's power state
  48. *
  49. * @get_state: queries the platform firmware for a device's current power state
  50. *
  51. * @refresh_state: asks the platform to refresh the device's power state data
  52. *
  53. * @choose_state: returns PCI power state of given device preferred by the
  54. * platform; to be used during system-wide transitions from a
  55. * sleeping state to the working state and vice versa
  56. *
  57. * @set_wakeup: enables/disables wakeup capability for the device
  58. *
  59. * @need_resume: returns 'true' if the given device (which is currently
  60. * suspended) needs to be resumed to be configured for system
  61. * wakeup.
  62. *
  63. * If given platform is generally capable of power managing PCI devices, all of
  64. * these callbacks are mandatory.
  65. */
  66. struct pci_platform_pm_ops {
  67. bool (*bridge_d3)(struct pci_dev *dev);
  68. bool (*is_manageable)(struct pci_dev *dev);
  69. int (*set_state)(struct pci_dev *dev, pci_power_t state);
  70. pci_power_t (*get_state)(struct pci_dev *dev);
  71. void (*refresh_state)(struct pci_dev *dev);
  72. pci_power_t (*choose_state)(struct pci_dev *dev);
  73. int (*set_wakeup)(struct pci_dev *dev, bool enable);
  74. bool (*need_resume)(struct pci_dev *dev);
  75. };
  76. int pci_set_platform_pm(const struct pci_platform_pm_ops *ops);
  77. void pci_update_current_state(struct pci_dev *dev, pci_power_t state);
  78. void pci_refresh_power_state(struct pci_dev *dev);
  79. int pci_power_up(struct pci_dev *dev);
  80. void pci_disable_enabled_device(struct pci_dev *dev);
  81. int pci_finish_runtime_suspend(struct pci_dev *dev);
  82. void pcie_clear_device_status(struct pci_dev *dev);
  83. void pcie_clear_root_pme_status(struct pci_dev *dev);
  84. bool pci_check_pme_status(struct pci_dev *dev);
  85. void pci_pme_wakeup_bus(struct pci_bus *bus);
  86. int __pci_pme_wakeup(struct pci_dev *dev, void *ign);
  87. void pci_pme_restore(struct pci_dev *dev);
  88. bool pci_dev_need_resume(struct pci_dev *dev);
  89. void pci_dev_adjust_pme(struct pci_dev *dev);
  90. void pci_dev_complete_resume(struct pci_dev *pci_dev);
  91. void pci_config_pm_runtime_get(struct pci_dev *dev);
  92. void pci_config_pm_runtime_put(struct pci_dev *dev);
  93. void pci_pm_init(struct pci_dev *dev);
  94. void pci_ea_init(struct pci_dev *dev);
  95. void pci_allocate_cap_save_buffers(struct pci_dev *dev);
  96. void pci_free_cap_save_buffers(struct pci_dev *dev);
  97. bool pci_bridge_d3_possible(struct pci_dev *dev);
  98. void pci_bridge_d3_update(struct pci_dev *dev);
  99. void pci_bridge_wait_for_secondary_bus(struct pci_dev *dev);
  100. static inline void pci_wakeup_event(struct pci_dev *dev)
  101. {
  102. /* Wait 100 ms before the system can be put into a sleep state. */
  103. pm_wakeup_event(&dev->dev, 100);
  104. }
  105. static inline bool pci_has_subordinate(struct pci_dev *pci_dev)
  106. {
  107. return !!(pci_dev->subordinate);
  108. }
  109. static inline bool pci_power_manageable(struct pci_dev *pci_dev)
  110. {
  111. /*
  112. * Currently we allow normal PCI devices and PCI bridges transition
  113. * into D3 if their bridge_d3 is set.
  114. */
  115. return !pci_has_subordinate(pci_dev) || pci_dev->bridge_d3;
  116. }
  117. static inline bool pcie_downstream_port(const struct pci_dev *dev)
  118. {
  119. int type = pci_pcie_type(dev);
  120. return type == PCI_EXP_TYPE_ROOT_PORT ||
  121. type == PCI_EXP_TYPE_DOWNSTREAM ||
  122. type == PCI_EXP_TYPE_PCIE_BRIDGE;
  123. }
  124. int pci_vpd_init(struct pci_dev *dev);
  125. void pci_vpd_release(struct pci_dev *dev);
  126. void pcie_vpd_create_sysfs_dev_files(struct pci_dev *dev);
  127. void pcie_vpd_remove_sysfs_dev_files(struct pci_dev *dev);
  128. /* PCI Virtual Channel */
  129. int pci_save_vc_state(struct pci_dev *dev);
  130. void pci_restore_vc_state(struct pci_dev *dev);
  131. void pci_allocate_vc_save_buffers(struct pci_dev *dev);
  132. /* PCI /proc functions */
  133. #ifdef CONFIG_PROC_FS
  134. int pci_proc_attach_device(struct pci_dev *dev);
  135. int pci_proc_detach_device(struct pci_dev *dev);
  136. int pci_proc_detach_bus(struct pci_bus *bus);
  137. #else
  138. static inline int pci_proc_attach_device(struct pci_dev *dev) { return 0; }
  139. static inline int pci_proc_detach_device(struct pci_dev *dev) { return 0; }
  140. static inline int pci_proc_detach_bus(struct pci_bus *bus) { return 0; }
  141. #endif
  142. /* Functions for PCI Hotplug drivers to use */
  143. int pci_hp_add_bridge(struct pci_dev *dev);
  144. #ifdef HAVE_PCI_LEGACY
  145. void pci_create_legacy_files(struct pci_bus *bus);
  146. void pci_remove_legacy_files(struct pci_bus *bus);
  147. #else
  148. static inline void pci_create_legacy_files(struct pci_bus *bus) { return; }
  149. static inline void pci_remove_legacy_files(struct pci_bus *bus) { return; }
  150. #endif
  151. /* Lock for read/write access to pci device and bus lists */
  152. extern struct rw_semaphore pci_bus_sem;
  153. extern struct mutex pci_slot_mutex;
  154. extern raw_spinlock_t pci_lock;
  155. extern unsigned int pci_pm_d3hot_delay;
  156. #ifdef CONFIG_PCI_MSI
  157. void pci_no_msi(void);
  158. #else
  159. static inline void pci_no_msi(void) { }
  160. #endif
  161. static inline void pci_msi_set_enable(struct pci_dev *dev, int enable)
  162. {
  163. u16 control;
  164. pci_read_config_word(dev, dev->msi_cap + PCI_MSI_FLAGS, &control);
  165. control &= ~PCI_MSI_FLAGS_ENABLE;
  166. if (enable)
  167. control |= PCI_MSI_FLAGS_ENABLE;
  168. pci_write_config_word(dev, dev->msi_cap + PCI_MSI_FLAGS, control);
  169. }
  170. static inline void pci_msix_clear_and_set_ctrl(struct pci_dev *dev, u16 clear, u16 set)
  171. {
  172. u16 ctrl;
  173. pci_read_config_word(dev, dev->msix_cap + PCI_MSIX_FLAGS, &ctrl);
  174. ctrl &= ~clear;
  175. ctrl |= set;
  176. pci_write_config_word(dev, dev->msix_cap + PCI_MSIX_FLAGS, ctrl);
  177. }
  178. void pci_realloc_get_opt(char *);
  179. static inline int pci_no_d1d2(struct pci_dev *dev)
  180. {
  181. unsigned int parent_dstates = 0;
  182. if (dev->bus->self)
  183. parent_dstates = dev->bus->self->no_d1d2;
  184. return (dev->no_d1d2 || parent_dstates);
  185. }
  186. extern const struct attribute_group *pci_dev_groups[];
  187. extern const struct attribute_group *pcibus_groups[];
  188. extern const struct device_type pci_dev_type;
  189. extern const struct attribute_group *pci_bus_groups[];
  190. extern unsigned long pci_hotplug_io_size;
  191. extern unsigned long pci_hotplug_mmio_size;
  192. extern unsigned long pci_hotplug_mmio_pref_size;
  193. extern unsigned long pci_hotplug_bus_size;
  194. /**
  195. * pci_match_one_device - Tell if a PCI device structure has a matching
  196. * PCI device id structure
  197. * @id: single PCI device id structure to match
  198. * @dev: the PCI device structure to match against
  199. *
  200. * Returns the matching pci_device_id structure or %NULL if there is no match.
  201. */
  202. static inline const struct pci_device_id *
  203. pci_match_one_device(const struct pci_device_id *id, const struct pci_dev *dev)
  204. {
  205. if ((id->vendor == PCI_ANY_ID || id->vendor == dev->vendor) &&
  206. (id->device == PCI_ANY_ID || id->device == dev->device) &&
  207. (id->subvendor == PCI_ANY_ID || id->subvendor == dev->subsystem_vendor) &&
  208. (id->subdevice == PCI_ANY_ID || id->subdevice == dev->subsystem_device) &&
  209. !((id->class ^ dev->class) & id->class_mask))
  210. return id;
  211. return NULL;
  212. }
  213. /* PCI slot sysfs helper code */
  214. #define to_pci_slot(s) container_of(s, struct pci_slot, kobj)
  215. extern struct kset *pci_slots_kset;
  216. struct pci_slot_attribute {
  217. struct attribute attr;
  218. ssize_t (*show)(struct pci_slot *, char *);
  219. ssize_t (*store)(struct pci_slot *, const char *, size_t);
  220. };
  221. #define to_pci_slot_attr(s) container_of(s, struct pci_slot_attribute, attr)
  222. enum pci_bar_type {
  223. pci_bar_unknown, /* Standard PCI BAR probe */
  224. pci_bar_io, /* An I/O port BAR */
  225. pci_bar_mem32, /* A 32-bit memory BAR */
  226. pci_bar_mem64, /* A 64-bit memory BAR */
  227. };
  228. struct device *pci_get_host_bridge_device(struct pci_dev *dev);
  229. void pci_put_host_bridge_device(struct device *dev);
  230. int pci_configure_extended_tags(struct pci_dev *dev, void *ign);
  231. bool pci_bus_read_dev_vendor_id(struct pci_bus *bus, int devfn, u32 *pl,
  232. int crs_timeout);
  233. bool pci_bus_generic_read_dev_vendor_id(struct pci_bus *bus, int devfn, u32 *pl,
  234. int crs_timeout);
  235. int pci_idt_bus_quirk(struct pci_bus *bus, int devfn, u32 *pl, int crs_timeout);
  236. int pci_setup_device(struct pci_dev *dev);
  237. int __pci_read_base(struct pci_dev *dev, enum pci_bar_type type,
  238. struct resource *res, unsigned int reg);
  239. void pci_configure_ari(struct pci_dev *dev);
  240. void __pci_bus_size_bridges(struct pci_bus *bus,
  241. struct list_head *realloc_head);
  242. void __pci_bus_assign_resources(const struct pci_bus *bus,
  243. struct list_head *realloc_head,
  244. struct list_head *fail_head);
  245. bool pci_bus_clip_resource(struct pci_dev *dev, int idx);
  246. void pci_reassigndev_resource_alignment(struct pci_dev *dev);
  247. void pci_disable_bridge_window(struct pci_dev *dev);
  248. struct pci_bus *pci_bus_get(struct pci_bus *bus);
  249. void pci_bus_put(struct pci_bus *bus);
  250. /* PCIe link information from Link Capabilities 2 */
  251. #define PCIE_LNKCAP2_SLS2SPEED(lnkcap2) \
  252. ((lnkcap2) & PCI_EXP_LNKCAP2_SLS_32_0GB ? PCIE_SPEED_32_0GT : \
  253. (lnkcap2) & PCI_EXP_LNKCAP2_SLS_16_0GB ? PCIE_SPEED_16_0GT : \
  254. (lnkcap2) & PCI_EXP_LNKCAP2_SLS_8_0GB ? PCIE_SPEED_8_0GT : \
  255. (lnkcap2) & PCI_EXP_LNKCAP2_SLS_5_0GB ? PCIE_SPEED_5_0GT : \
  256. (lnkcap2) & PCI_EXP_LNKCAP2_SLS_2_5GB ? PCIE_SPEED_2_5GT : \
  257. PCI_SPEED_UNKNOWN)
  258. /* PCIe speed to Mb/s reduced by encoding overhead */
  259. #define PCIE_SPEED2MBS_ENC(speed) \
  260. ((speed) == PCIE_SPEED_32_0GT ? 32000*128/130 : \
  261. (speed) == PCIE_SPEED_16_0GT ? 16000*128/130 : \
  262. (speed) == PCIE_SPEED_8_0GT ? 8000*128/130 : \
  263. (speed) == PCIE_SPEED_5_0GT ? 5000*8/10 : \
  264. (speed) == PCIE_SPEED_2_5GT ? 2500*8/10 : \
  265. 0)
  266. const char *pci_speed_string(enum pci_bus_speed speed);
  267. enum pci_bus_speed pcie_get_speed_cap(struct pci_dev *dev);
  268. enum pcie_link_width pcie_get_width_cap(struct pci_dev *dev);
  269. u32 pcie_bandwidth_capable(struct pci_dev *dev, enum pci_bus_speed *speed,
  270. enum pcie_link_width *width);
  271. void __pcie_print_link_status(struct pci_dev *dev, bool verbose);
  272. void pcie_report_downtraining(struct pci_dev *dev);
  273. void pcie_update_link_speed(struct pci_bus *bus, u16 link_status);
  274. /* Single Root I/O Virtualization */
  275. struct pci_sriov {
  276. int pos; /* Capability position */
  277. int nres; /* Number of resources */
  278. u32 cap; /* SR-IOV Capabilities */
  279. u16 ctrl; /* SR-IOV Control */
  280. u16 total_VFs; /* Total VFs associated with the PF */
  281. u16 initial_VFs; /* Initial VFs associated with the PF */
  282. u16 num_VFs; /* Number of VFs available */
  283. u16 offset; /* First VF Routing ID offset */
  284. u16 stride; /* Following VF stride */
  285. u16 vf_device; /* VF device ID */
  286. u32 pgsz; /* Page size for BAR alignment */
  287. u8 link; /* Function Dependency Link */
  288. u8 max_VF_buses; /* Max buses consumed by VFs */
  289. u16 driver_max_VFs; /* Max num VFs driver supports */
  290. struct pci_dev *dev; /* Lowest numbered PF */
  291. struct pci_dev *self; /* This PF */
  292. u32 class; /* VF device */
  293. u8 hdr_type; /* VF header type */
  294. u16 subsystem_vendor; /* VF subsystem vendor */
  295. u16 subsystem_device; /* VF subsystem device */
  296. resource_size_t barsz[PCI_SRIOV_NUM_BARS]; /* VF BAR size */
  297. bool drivers_autoprobe; /* Auto probing of VFs by driver */
  298. ANDROID_KABI_RESERVE(1);
  299. ANDROID_KABI_RESERVE(2);
  300. ANDROID_KABI_RESERVE(3);
  301. ANDROID_KABI_RESERVE(4);
  302. };
  303. /**
  304. * pci_dev_set_io_state - Set the new error state if possible.
  305. *
  306. * @dev - pci device to set new error_state
  307. * @new - the state we want dev to be in
  308. *
  309. * Must be called with device_lock held.
  310. *
  311. * Returns true if state has been changed to the requested state.
  312. */
  313. static inline bool pci_dev_set_io_state(struct pci_dev *dev,
  314. pci_channel_state_t new)
  315. {
  316. bool changed = false;
  317. device_lock_assert(&dev->dev);
  318. switch (new) {
  319. case pci_channel_io_perm_failure:
  320. switch (dev->error_state) {
  321. case pci_channel_io_frozen:
  322. case pci_channel_io_normal:
  323. case pci_channel_io_perm_failure:
  324. changed = true;
  325. break;
  326. }
  327. break;
  328. case pci_channel_io_frozen:
  329. switch (dev->error_state) {
  330. case pci_channel_io_frozen:
  331. case pci_channel_io_normal:
  332. changed = true;
  333. break;
  334. }
  335. break;
  336. case pci_channel_io_normal:
  337. switch (dev->error_state) {
  338. case pci_channel_io_frozen:
  339. case pci_channel_io_normal:
  340. changed = true;
  341. break;
  342. }
  343. break;
  344. }
  345. if (changed)
  346. dev->error_state = new;
  347. return changed;
  348. }
  349. static inline int pci_dev_set_disconnected(struct pci_dev *dev, void *unused)
  350. {
  351. device_lock(&dev->dev);
  352. pci_dev_set_io_state(dev, pci_channel_io_perm_failure);
  353. device_unlock(&dev->dev);
  354. return 0;
  355. }
  356. static inline bool pci_dev_is_disconnected(const struct pci_dev *dev)
  357. {
  358. return dev->error_state == pci_channel_io_perm_failure;
  359. }
  360. /* pci_dev priv_flags */
  361. #define PCI_DEV_ADDED 0
  362. #define PCI_DPC_RECOVERED 1
  363. #define PCI_DPC_RECOVERING 2
  364. static inline void pci_dev_assign_added(struct pci_dev *dev, bool added)
  365. {
  366. assign_bit(PCI_DEV_ADDED, &dev->priv_flags, added);
  367. }
  368. static inline bool pci_dev_is_added(const struct pci_dev *dev)
  369. {
  370. return test_bit(PCI_DEV_ADDED, &dev->priv_flags);
  371. }
  372. #ifdef CONFIG_PCIEAER
  373. #include <linux/aer.h>
  374. #define AER_MAX_MULTI_ERR_DEVICES 5 /* Not likely to have more */
  375. struct aer_err_info {
  376. struct pci_dev *dev[AER_MAX_MULTI_ERR_DEVICES];
  377. int error_dev_num;
  378. unsigned int id:16;
  379. unsigned int severity:2; /* 0:NONFATAL | 1:FATAL | 2:COR */
  380. unsigned int __pad1:5;
  381. unsigned int multi_error_valid:1;
  382. unsigned int first_error:5;
  383. unsigned int __pad2:2;
  384. unsigned int tlp_header_valid:1;
  385. unsigned int status; /* COR/UNCOR Error Status */
  386. unsigned int mask; /* COR/UNCOR Error Mask */
  387. struct aer_header_log_regs tlp; /* TLP Header */
  388. };
  389. int aer_get_device_error_info(struct pci_dev *dev, struct aer_err_info *info);
  390. void aer_print_error(struct pci_dev *dev, struct aer_err_info *info);
  391. #endif /* CONFIG_PCIEAER */
  392. #ifdef CONFIG_PCIE_DPC
  393. void pci_save_dpc_state(struct pci_dev *dev);
  394. void pci_restore_dpc_state(struct pci_dev *dev);
  395. void pci_dpc_init(struct pci_dev *pdev);
  396. void dpc_process_error(struct pci_dev *pdev);
  397. pci_ers_result_t dpc_reset_link(struct pci_dev *pdev);
  398. bool pci_dpc_recovered(struct pci_dev *pdev);
  399. #else
  400. static inline void pci_save_dpc_state(struct pci_dev *dev) {}
  401. static inline void pci_restore_dpc_state(struct pci_dev *dev) {}
  402. static inline void pci_dpc_init(struct pci_dev *pdev) {}
  403. static inline bool pci_dpc_recovered(struct pci_dev *pdev) { return false; }
  404. #endif
  405. #ifdef CONFIG_PCI_ATS
  406. /* Address Translation Service */
  407. void pci_ats_init(struct pci_dev *dev);
  408. void pci_restore_ats_state(struct pci_dev *dev);
  409. #else
  410. static inline void pci_ats_init(struct pci_dev *d) { }
  411. static inline void pci_restore_ats_state(struct pci_dev *dev) { }
  412. #endif /* CONFIG_PCI_ATS */
  413. #ifdef CONFIG_PCI_PRI
  414. void pci_pri_init(struct pci_dev *dev);
  415. void pci_restore_pri_state(struct pci_dev *pdev);
  416. #else
  417. static inline void pci_pri_init(struct pci_dev *dev) { }
  418. static inline void pci_restore_pri_state(struct pci_dev *pdev) { }
  419. #endif
  420. #ifdef CONFIG_PCI_PASID
  421. void pci_pasid_init(struct pci_dev *dev);
  422. void pci_restore_pasid_state(struct pci_dev *pdev);
  423. #else
  424. static inline void pci_pasid_init(struct pci_dev *dev) { }
  425. static inline void pci_restore_pasid_state(struct pci_dev *pdev) { }
  426. #endif
  427. #ifdef CONFIG_PCI_IOV
  428. int pci_iov_init(struct pci_dev *dev);
  429. void pci_iov_release(struct pci_dev *dev);
  430. void pci_iov_remove(struct pci_dev *dev);
  431. void pci_iov_update_resource(struct pci_dev *dev, int resno);
  432. resource_size_t pci_sriov_resource_alignment(struct pci_dev *dev, int resno);
  433. void pci_restore_iov_state(struct pci_dev *dev);
  434. int pci_iov_bus_range(struct pci_bus *bus);
  435. extern const struct attribute_group sriov_dev_attr_group;
  436. #else
  437. static inline int pci_iov_init(struct pci_dev *dev)
  438. {
  439. return -ENODEV;
  440. }
  441. static inline void pci_iov_release(struct pci_dev *dev)
  442. {
  443. }
  444. static inline void pci_iov_remove(struct pci_dev *dev)
  445. {
  446. }
  447. static inline void pci_restore_iov_state(struct pci_dev *dev)
  448. {
  449. }
  450. static inline int pci_iov_bus_range(struct pci_bus *bus)
  451. {
  452. return 0;
  453. }
  454. #endif /* CONFIG_PCI_IOV */
  455. unsigned long pci_cardbus_resource_alignment(struct resource *);
  456. static inline resource_size_t pci_resource_alignment(struct pci_dev *dev,
  457. struct resource *res)
  458. {
  459. #ifdef CONFIG_PCI_IOV
  460. int resno = res - dev->resource;
  461. if (resno >= PCI_IOV_RESOURCES && resno <= PCI_IOV_RESOURCE_END)
  462. return pci_sriov_resource_alignment(dev, resno);
  463. #endif
  464. if (dev->class >> 8 == PCI_CLASS_BRIDGE_CARDBUS)
  465. return pci_cardbus_resource_alignment(res);
  466. return resource_alignment(res);
  467. }
  468. void pci_acs_init(struct pci_dev *dev);
  469. #ifdef CONFIG_PCI_QUIRKS
  470. int pci_dev_specific_acs_enabled(struct pci_dev *dev, u16 acs_flags);
  471. int pci_dev_specific_enable_acs(struct pci_dev *dev);
  472. int pci_dev_specific_disable_acs_redir(struct pci_dev *dev);
  473. #else
  474. static inline int pci_dev_specific_acs_enabled(struct pci_dev *dev,
  475. u16 acs_flags)
  476. {
  477. return -ENOTTY;
  478. }
  479. static inline int pci_dev_specific_enable_acs(struct pci_dev *dev)
  480. {
  481. return -ENOTTY;
  482. }
  483. static inline int pci_dev_specific_disable_acs_redir(struct pci_dev *dev)
  484. {
  485. return -ENOTTY;
  486. }
  487. #endif
  488. /* PCI error reporting and recovery */
  489. pci_ers_result_t pcie_do_recovery(struct pci_dev *dev,
  490. pci_channel_state_t state,
  491. pci_ers_result_t (*reset_link)(struct pci_dev *pdev));
  492. bool pcie_wait_for_link(struct pci_dev *pdev, bool active);
  493. #ifdef CONFIG_PCIEASPM
  494. void pcie_aspm_init_link_state(struct pci_dev *pdev);
  495. void pcie_aspm_exit_link_state(struct pci_dev *pdev);
  496. void pcie_aspm_pm_state_change(struct pci_dev *pdev);
  497. void pcie_aspm_powersave_config_link(struct pci_dev *pdev);
  498. #else
  499. static inline void pcie_aspm_init_link_state(struct pci_dev *pdev) { }
  500. static inline void pcie_aspm_exit_link_state(struct pci_dev *pdev) { }
  501. static inline void pcie_aspm_pm_state_change(struct pci_dev *pdev) { }
  502. static inline void pcie_aspm_powersave_config_link(struct pci_dev *pdev) { }
  503. #endif
  504. #ifdef CONFIG_PCIE_ECRC
  505. void pcie_set_ecrc_checking(struct pci_dev *dev);
  506. void pcie_ecrc_get_policy(char *str);
  507. #else
  508. static inline void pcie_set_ecrc_checking(struct pci_dev *dev) { }
  509. static inline void pcie_ecrc_get_policy(char *str) { }
  510. #endif
  511. #ifdef CONFIG_PCIE_PTM
  512. void pci_ptm_init(struct pci_dev *dev);
  513. int pci_enable_ptm(struct pci_dev *dev, u8 *granularity);
  514. #else
  515. static inline void pci_ptm_init(struct pci_dev *dev) { }
  516. static inline int pci_enable_ptm(struct pci_dev *dev, u8 *granularity)
  517. { return -EINVAL; }
  518. #endif
  519. struct pci_dev_reset_methods {
  520. u16 vendor;
  521. u16 device;
  522. int (*reset)(struct pci_dev *dev, int probe);
  523. };
  524. #ifdef CONFIG_PCI_QUIRKS
  525. int pci_dev_specific_reset(struct pci_dev *dev, int probe);
  526. #else
  527. static inline int pci_dev_specific_reset(struct pci_dev *dev, int probe)
  528. {
  529. return -ENOTTY;
  530. }
  531. #endif
  532. #if defined(CONFIG_PCI_QUIRKS) && defined(CONFIG_ARM64)
  533. int acpi_get_rc_resources(struct device *dev, const char *hid, u16 segment,
  534. struct resource *res);
  535. #else
  536. static inline int acpi_get_rc_resources(struct device *dev, const char *hid,
  537. u16 segment, struct resource *res)
  538. {
  539. return -ENODEV;
  540. }
  541. #endif
  542. u32 pci_rebar_get_possible_sizes(struct pci_dev *pdev, int bar);
  543. int pci_rebar_get_current_size(struct pci_dev *pdev, int bar);
  544. int pci_rebar_set_size(struct pci_dev *pdev, int bar, int size);
  545. static inline u64 pci_rebar_size_to_bytes(int size)
  546. {
  547. return 1ULL << (size + 20);
  548. }
  549. struct device_node;
  550. #ifdef CONFIG_OF
  551. int of_pci_parse_bus_range(struct device_node *node, struct resource *res);
  552. int of_get_pci_domain_nr(struct device_node *node);
  553. int of_pci_get_max_link_speed(struct device_node *node);
  554. void pci_set_of_node(struct pci_dev *dev);
  555. void pci_release_of_node(struct pci_dev *dev);
  556. void pci_set_bus_of_node(struct pci_bus *bus);
  557. void pci_release_bus_of_node(struct pci_bus *bus);
  558. int devm_of_pci_bridge_init(struct device *dev, struct pci_host_bridge *bridge);
  559. #else
  560. static inline int
  561. of_pci_parse_bus_range(struct device_node *node, struct resource *res)
  562. {
  563. return -EINVAL;
  564. }
  565. static inline int
  566. of_get_pci_domain_nr(struct device_node *node)
  567. {
  568. return -1;
  569. }
  570. static inline int
  571. of_pci_get_max_link_speed(struct device_node *node)
  572. {
  573. return -EINVAL;
  574. }
  575. static inline void pci_set_of_node(struct pci_dev *dev) { }
  576. static inline void pci_release_of_node(struct pci_dev *dev) { }
  577. static inline void pci_set_bus_of_node(struct pci_bus *bus) { }
  578. static inline void pci_release_bus_of_node(struct pci_bus *bus) { }
  579. static inline int devm_of_pci_bridge_init(struct device *dev, struct pci_host_bridge *bridge)
  580. {
  581. return 0;
  582. }
  583. #endif /* CONFIG_OF */
  584. #ifdef CONFIG_PCIEAER
  585. void pci_no_aer(void);
  586. void pci_aer_init(struct pci_dev *dev);
  587. void pci_aer_exit(struct pci_dev *dev);
  588. extern const struct attribute_group aer_stats_attr_group;
  589. void pci_aer_clear_fatal_status(struct pci_dev *dev);
  590. int pci_aer_clear_status(struct pci_dev *dev);
  591. int pci_aer_raw_clear_status(struct pci_dev *dev);
  592. #else
  593. static inline void pci_no_aer(void) { }
  594. static inline void pci_aer_init(struct pci_dev *d) { }
  595. static inline void pci_aer_exit(struct pci_dev *d) { }
  596. static inline void pci_aer_clear_fatal_status(struct pci_dev *dev) { }
  597. static inline int pci_aer_clear_status(struct pci_dev *dev) { return -EINVAL; }
  598. static inline int pci_aer_raw_clear_status(struct pci_dev *dev) { return -EINVAL; }
  599. #endif
  600. #ifdef CONFIG_ACPI
  601. int pci_acpi_program_hp_params(struct pci_dev *dev);
  602. #else
  603. static inline int pci_acpi_program_hp_params(struct pci_dev *dev)
  604. {
  605. return -ENODEV;
  606. }
  607. #endif
  608. #ifdef CONFIG_PCIEASPM
  609. extern const struct attribute_group aspm_ctrl_attr_group;
  610. #endif
  611. #endif /* DRIVERS_PCI_H */