pci-bridge-emul.h 3.3 KB

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  1. /* SPDX-License-Identifier: GPL-2.0 */
  2. #ifndef __PCI_BRIDGE_EMUL_H__
  3. #define __PCI_BRIDGE_EMUL_H__
  4. #include <linux/kernel.h>
  5. /* PCI configuration space of a PCI-to-PCI bridge. */
  6. struct pci_bridge_emul_conf {
  7. __le16 vendor;
  8. __le16 device;
  9. __le16 command;
  10. __le16 status;
  11. __le32 class_revision;
  12. u8 cache_line_size;
  13. u8 latency_timer;
  14. u8 header_type;
  15. u8 bist;
  16. __le32 bar[2];
  17. u8 primary_bus;
  18. u8 secondary_bus;
  19. u8 subordinate_bus;
  20. u8 secondary_latency_timer;
  21. u8 iobase;
  22. u8 iolimit;
  23. __le16 secondary_status;
  24. __le16 membase;
  25. __le16 memlimit;
  26. __le16 pref_mem_base;
  27. __le16 pref_mem_limit;
  28. __le32 prefbaseupper;
  29. __le32 preflimitupper;
  30. __le16 iobaseupper;
  31. __le16 iolimitupper;
  32. u8 capabilities_pointer;
  33. u8 reserve[3];
  34. __le32 romaddr;
  35. u8 intline;
  36. u8 intpin;
  37. __le16 bridgectrl;
  38. };
  39. /* PCI configuration space of the PCIe capabilities */
  40. struct pci_bridge_emul_pcie_conf {
  41. u8 cap_id;
  42. u8 next;
  43. __le16 cap;
  44. __le32 devcap;
  45. __le16 devctl;
  46. __le16 devsta;
  47. __le32 lnkcap;
  48. __le16 lnkctl;
  49. __le16 lnksta;
  50. __le32 slotcap;
  51. __le16 slotctl;
  52. __le16 slotsta;
  53. __le16 rootctl;
  54. __le16 rootcap;
  55. __le32 rootsta;
  56. __le32 devcap2;
  57. __le16 devctl2;
  58. __le16 devsta2;
  59. __le32 lnkcap2;
  60. __le16 lnkctl2;
  61. __le16 lnksta2;
  62. __le32 slotcap2;
  63. __le16 slotctl2;
  64. __le16 slotsta2;
  65. };
  66. struct pci_bridge_emul;
  67. typedef enum { PCI_BRIDGE_EMUL_HANDLED,
  68. PCI_BRIDGE_EMUL_NOT_HANDLED } pci_bridge_emul_read_status_t;
  69. struct pci_bridge_emul_ops {
  70. /*
  71. * Called when reading from the regular PCI bridge
  72. * configuration space. Return PCI_BRIDGE_EMUL_HANDLED when the
  73. * operation has handled the read operation and filled in the
  74. * *value, or PCI_BRIDGE_EMUL_NOT_HANDLED when the read should
  75. * be emulated by the common code by reading from the
  76. * in-memory copy of the configuration space.
  77. */
  78. pci_bridge_emul_read_status_t (*read_base)(struct pci_bridge_emul *bridge,
  79. int reg, u32 *value);
  80. /*
  81. * Same as ->read_base(), except it is for reading from the
  82. * PCIe capability configuration space.
  83. */
  84. pci_bridge_emul_read_status_t (*read_pcie)(struct pci_bridge_emul *bridge,
  85. int reg, u32 *value);
  86. /*
  87. * Called when writing to the regular PCI bridge configuration
  88. * space. old is the current value, new is the new value being
  89. * written, and mask indicates which parts of the value are
  90. * being changed.
  91. */
  92. void (*write_base)(struct pci_bridge_emul *bridge, int reg,
  93. u32 old, u32 new, u32 mask);
  94. /*
  95. * Same as ->write_base(), except it is for writing from the
  96. * PCIe capability configuration space.
  97. */
  98. void (*write_pcie)(struct pci_bridge_emul *bridge, int reg,
  99. u32 old, u32 new, u32 mask);
  100. };
  101. struct pci_bridge_reg_behavior;
  102. struct pci_bridge_emul {
  103. struct pci_bridge_emul_conf conf;
  104. struct pci_bridge_emul_pcie_conf pcie_conf;
  105. struct pci_bridge_emul_ops *ops;
  106. struct pci_bridge_reg_behavior *pci_regs_behavior;
  107. struct pci_bridge_reg_behavior *pcie_cap_regs_behavior;
  108. void *data;
  109. bool has_pcie;
  110. };
  111. enum {
  112. PCI_BRIDGE_EMUL_NO_PREFETCHABLE_BAR = BIT(0),
  113. };
  114. int pci_bridge_emul_init(struct pci_bridge_emul *bridge,
  115. unsigned int flags);
  116. void pci_bridge_emul_cleanup(struct pci_bridge_emul *bridge);
  117. int pci_bridge_emul_conf_read(struct pci_bridge_emul *bridge, int where,
  118. int size, u32 *value);
  119. int pci_bridge_emul_conf_write(struct pci_bridge_emul *bridge, int where,
  120. int size, u32 value);
  121. #endif /* __PCI_BRIDGE_EMUL_H__ */