msi.c 41 KB

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  1. // SPDX-License-Identifier: GPL-2.0
  2. /*
  3. * PCI Message Signaled Interrupt (MSI)
  4. *
  5. * Copyright (C) 2003-2004 Intel
  6. * Copyright (C) Tom Long Nguyen (tom.l.nguyen@intel.com)
  7. * Copyright (C) 2016 Christoph Hellwig.
  8. */
  9. #include <linux/err.h>
  10. #include <linux/mm.h>
  11. #include <linux/irq.h>
  12. #include <linux/interrupt.h>
  13. #include <linux/export.h>
  14. #include <linux/ioport.h>
  15. #include <linux/pci.h>
  16. #include <linux/proc_fs.h>
  17. #include <linux/msi.h>
  18. #include <linux/smp.h>
  19. #include <linux/errno.h>
  20. #include <linux/io.h>
  21. #include <linux/acpi_iort.h>
  22. #include <linux/slab.h>
  23. #include <linux/irqdomain.h>
  24. #include <linux/of_irq.h>
  25. #include "pci.h"
  26. static int pci_msi_enable = 1;
  27. int pci_msi_ignore_mask;
  28. #define msix_table_size(flags) ((flags & PCI_MSIX_FLAGS_QSIZE) + 1)
  29. #ifdef CONFIG_PCI_MSI_IRQ_DOMAIN
  30. static int pci_msi_setup_msi_irqs(struct pci_dev *dev, int nvec, int type)
  31. {
  32. struct irq_domain *domain;
  33. domain = dev_get_msi_domain(&dev->dev);
  34. if (domain && irq_domain_is_hierarchy(domain))
  35. return msi_domain_alloc_irqs(domain, &dev->dev, nvec);
  36. return arch_setup_msi_irqs(dev, nvec, type);
  37. }
  38. static void pci_msi_teardown_msi_irqs(struct pci_dev *dev)
  39. {
  40. struct irq_domain *domain;
  41. domain = dev_get_msi_domain(&dev->dev);
  42. if (domain && irq_domain_is_hierarchy(domain))
  43. msi_domain_free_irqs(domain, &dev->dev);
  44. else
  45. arch_teardown_msi_irqs(dev);
  46. }
  47. #else
  48. #define pci_msi_setup_msi_irqs arch_setup_msi_irqs
  49. #define pci_msi_teardown_msi_irqs arch_teardown_msi_irqs
  50. #endif
  51. #ifdef CONFIG_PCI_MSI_ARCH_FALLBACKS
  52. /* Arch hooks */
  53. int __weak arch_setup_msi_irq(struct pci_dev *dev, struct msi_desc *desc)
  54. {
  55. struct msi_controller *chip = dev->bus->msi;
  56. int err;
  57. if (!chip || !chip->setup_irq)
  58. return -EINVAL;
  59. err = chip->setup_irq(chip, dev, desc);
  60. if (err < 0)
  61. return err;
  62. irq_set_chip_data(desc->irq, chip);
  63. return 0;
  64. }
  65. void __weak arch_teardown_msi_irq(unsigned int irq)
  66. {
  67. struct msi_controller *chip = irq_get_chip_data(irq);
  68. if (!chip || !chip->teardown_irq)
  69. return;
  70. chip->teardown_irq(chip, irq);
  71. }
  72. int __weak arch_setup_msi_irqs(struct pci_dev *dev, int nvec, int type)
  73. {
  74. struct msi_controller *chip = dev->bus->msi;
  75. struct msi_desc *entry;
  76. int ret;
  77. if (chip && chip->setup_irqs)
  78. return chip->setup_irqs(chip, dev, nvec, type);
  79. /*
  80. * If an architecture wants to support multiple MSI, it needs to
  81. * override arch_setup_msi_irqs()
  82. */
  83. if (type == PCI_CAP_ID_MSI && nvec > 1)
  84. return 1;
  85. for_each_pci_msi_entry(entry, dev) {
  86. ret = arch_setup_msi_irq(dev, entry);
  87. if (ret < 0)
  88. return ret;
  89. if (ret > 0)
  90. return -ENOSPC;
  91. }
  92. return 0;
  93. }
  94. /*
  95. * We have a default implementation available as a separate non-weak
  96. * function, as it is used by the Xen x86 PCI code
  97. */
  98. void default_teardown_msi_irqs(struct pci_dev *dev)
  99. {
  100. int i;
  101. struct msi_desc *entry;
  102. for_each_pci_msi_entry(entry, dev)
  103. if (entry->irq)
  104. for (i = 0; i < entry->nvec_used; i++)
  105. arch_teardown_msi_irq(entry->irq + i);
  106. }
  107. void __weak arch_teardown_msi_irqs(struct pci_dev *dev)
  108. {
  109. return default_teardown_msi_irqs(dev);
  110. }
  111. #endif /* CONFIG_PCI_MSI_ARCH_FALLBACKS */
  112. static void default_restore_msi_irq(struct pci_dev *dev, int irq)
  113. {
  114. struct msi_desc *entry;
  115. entry = NULL;
  116. if (dev->msix_enabled) {
  117. for_each_pci_msi_entry(entry, dev) {
  118. if (irq == entry->irq)
  119. break;
  120. }
  121. } else if (dev->msi_enabled) {
  122. entry = irq_get_msi_desc(irq);
  123. }
  124. if (entry)
  125. __pci_write_msi_msg(entry, &entry->msg);
  126. }
  127. void __weak arch_restore_msi_irqs(struct pci_dev *dev)
  128. {
  129. return default_restore_msi_irqs(dev);
  130. }
  131. static inline __attribute_const__ u32 msi_mask(unsigned x)
  132. {
  133. /* Don't shift by >= width of type */
  134. if (x >= 5)
  135. return 0xffffffff;
  136. return (1 << (1 << x)) - 1;
  137. }
  138. /*
  139. * PCI 2.3 does not specify mask bits for each MSI interrupt. Attempting to
  140. * mask all MSI interrupts by clearing the MSI enable bit does not work
  141. * reliably as devices without an INTx disable bit will then generate a
  142. * level IRQ which will never be cleared.
  143. */
  144. u32 __pci_msi_desc_mask_irq(struct msi_desc *desc, u32 mask, u32 flag)
  145. {
  146. u32 mask_bits = desc->masked;
  147. if (pci_msi_ignore_mask || !desc->msi_attrib.maskbit)
  148. return 0;
  149. mask_bits &= ~mask;
  150. mask_bits |= flag;
  151. pci_write_config_dword(msi_desc_to_pci_dev(desc), desc->mask_pos,
  152. mask_bits);
  153. return mask_bits;
  154. }
  155. static void msi_mask_irq(struct msi_desc *desc, u32 mask, u32 flag)
  156. {
  157. desc->masked = __pci_msi_desc_mask_irq(desc, mask, flag);
  158. }
  159. static void __iomem *pci_msix_desc_addr(struct msi_desc *desc)
  160. {
  161. if (desc->msi_attrib.is_virtual)
  162. return NULL;
  163. return desc->mask_base +
  164. desc->msi_attrib.entry_nr * PCI_MSIX_ENTRY_SIZE;
  165. }
  166. /*
  167. * This internal function does not flush PCI writes to the device.
  168. * All users must ensure that they read from the device before either
  169. * assuming that the device state is up to date, or returning out of this
  170. * file. This saves a few milliseconds when initialising devices with lots
  171. * of MSI-X interrupts.
  172. */
  173. u32 __pci_msix_desc_mask_irq(struct msi_desc *desc, u32 flag)
  174. {
  175. u32 mask_bits = desc->masked;
  176. void __iomem *desc_addr;
  177. if (pci_msi_ignore_mask)
  178. return 0;
  179. desc_addr = pci_msix_desc_addr(desc);
  180. if (!desc_addr)
  181. return 0;
  182. mask_bits &= ~PCI_MSIX_ENTRY_CTRL_MASKBIT;
  183. if (flag & PCI_MSIX_ENTRY_CTRL_MASKBIT)
  184. mask_bits |= PCI_MSIX_ENTRY_CTRL_MASKBIT;
  185. writel(mask_bits, desc_addr + PCI_MSIX_ENTRY_VECTOR_CTRL);
  186. return mask_bits;
  187. }
  188. static void msix_mask_irq(struct msi_desc *desc, u32 flag)
  189. {
  190. desc->masked = __pci_msix_desc_mask_irq(desc, flag);
  191. }
  192. static void msi_set_mask_bit(struct irq_data *data, u32 flag)
  193. {
  194. struct msi_desc *desc = irq_data_get_msi_desc(data);
  195. if (desc->msi_attrib.is_msix) {
  196. msix_mask_irq(desc, flag);
  197. readl(desc->mask_base); /* Flush write to device */
  198. } else {
  199. unsigned offset = data->irq - desc->irq;
  200. msi_mask_irq(desc, 1 << offset, flag << offset);
  201. }
  202. }
  203. /**
  204. * pci_msi_mask_irq - Generic IRQ chip callback to mask PCI/MSI interrupts
  205. * @data: pointer to irqdata associated to that interrupt
  206. */
  207. void pci_msi_mask_irq(struct irq_data *data)
  208. {
  209. msi_set_mask_bit(data, 1);
  210. }
  211. EXPORT_SYMBOL_GPL(pci_msi_mask_irq);
  212. /**
  213. * pci_msi_unmask_irq - Generic IRQ chip callback to unmask PCI/MSI interrupts
  214. * @data: pointer to irqdata associated to that interrupt
  215. */
  216. void pci_msi_unmask_irq(struct irq_data *data)
  217. {
  218. msi_set_mask_bit(data, 0);
  219. }
  220. EXPORT_SYMBOL_GPL(pci_msi_unmask_irq);
  221. void default_restore_msi_irqs(struct pci_dev *dev)
  222. {
  223. struct msi_desc *entry;
  224. for_each_pci_msi_entry(entry, dev)
  225. default_restore_msi_irq(dev, entry->irq);
  226. }
  227. void __pci_read_msi_msg(struct msi_desc *entry, struct msi_msg *msg)
  228. {
  229. struct pci_dev *dev = msi_desc_to_pci_dev(entry);
  230. BUG_ON(dev->current_state != PCI_D0);
  231. if (entry->msi_attrib.is_msix) {
  232. void __iomem *base = pci_msix_desc_addr(entry);
  233. if (!base) {
  234. WARN_ON(1);
  235. return;
  236. }
  237. msg->address_lo = readl(base + PCI_MSIX_ENTRY_LOWER_ADDR);
  238. msg->address_hi = readl(base + PCI_MSIX_ENTRY_UPPER_ADDR);
  239. msg->data = readl(base + PCI_MSIX_ENTRY_DATA);
  240. } else {
  241. int pos = dev->msi_cap;
  242. u16 data;
  243. pci_read_config_dword(dev, pos + PCI_MSI_ADDRESS_LO,
  244. &msg->address_lo);
  245. if (entry->msi_attrib.is_64) {
  246. pci_read_config_dword(dev, pos + PCI_MSI_ADDRESS_HI,
  247. &msg->address_hi);
  248. pci_read_config_word(dev, pos + PCI_MSI_DATA_64, &data);
  249. } else {
  250. msg->address_hi = 0;
  251. pci_read_config_word(dev, pos + PCI_MSI_DATA_32, &data);
  252. }
  253. msg->data = data;
  254. }
  255. }
  256. void __pci_write_msi_msg(struct msi_desc *entry, struct msi_msg *msg)
  257. {
  258. struct pci_dev *dev = msi_desc_to_pci_dev(entry);
  259. if (dev->current_state != PCI_D0 || pci_dev_is_disconnected(dev)) {
  260. /* Don't touch the hardware now */
  261. } else if (entry->msi_attrib.is_msix) {
  262. void __iomem *base = pci_msix_desc_addr(entry);
  263. bool unmasked = !(entry->masked & PCI_MSIX_ENTRY_CTRL_MASKBIT);
  264. if (!base)
  265. goto skip;
  266. /*
  267. * The specification mandates that the entry is masked
  268. * when the message is modified:
  269. *
  270. * "If software changes the Address or Data value of an
  271. * entry while the entry is unmasked, the result is
  272. * undefined."
  273. */
  274. if (unmasked)
  275. __pci_msix_desc_mask_irq(entry, PCI_MSIX_ENTRY_CTRL_MASKBIT);
  276. writel(msg->address_lo, base + PCI_MSIX_ENTRY_LOWER_ADDR);
  277. writel(msg->address_hi, base + PCI_MSIX_ENTRY_UPPER_ADDR);
  278. writel(msg->data, base + PCI_MSIX_ENTRY_DATA);
  279. if (unmasked)
  280. __pci_msix_desc_mask_irq(entry, 0);
  281. /* Ensure that the writes are visible in the device */
  282. readl(base + PCI_MSIX_ENTRY_DATA);
  283. } else {
  284. int pos = dev->msi_cap;
  285. u16 msgctl;
  286. pci_read_config_word(dev, pos + PCI_MSI_FLAGS, &msgctl);
  287. msgctl &= ~PCI_MSI_FLAGS_QSIZE;
  288. msgctl |= entry->msi_attrib.multiple << 4;
  289. pci_write_config_word(dev, pos + PCI_MSI_FLAGS, msgctl);
  290. pci_write_config_dword(dev, pos + PCI_MSI_ADDRESS_LO,
  291. msg->address_lo);
  292. if (entry->msi_attrib.is_64) {
  293. pci_write_config_dword(dev, pos + PCI_MSI_ADDRESS_HI,
  294. msg->address_hi);
  295. pci_write_config_word(dev, pos + PCI_MSI_DATA_64,
  296. msg->data);
  297. } else {
  298. pci_write_config_word(dev, pos + PCI_MSI_DATA_32,
  299. msg->data);
  300. }
  301. /* Ensure that the writes are visible in the device */
  302. pci_read_config_word(dev, pos + PCI_MSI_FLAGS, &msgctl);
  303. }
  304. skip:
  305. entry->msg = *msg;
  306. if (entry->write_msi_msg)
  307. entry->write_msi_msg(entry, entry->write_msi_msg_data);
  308. }
  309. void pci_write_msi_msg(unsigned int irq, struct msi_msg *msg)
  310. {
  311. struct msi_desc *entry = irq_get_msi_desc(irq);
  312. __pci_write_msi_msg(entry, msg);
  313. }
  314. EXPORT_SYMBOL_GPL(pci_write_msi_msg);
  315. static void free_msi_irqs(struct pci_dev *dev)
  316. {
  317. struct list_head *msi_list = dev_to_msi_list(&dev->dev);
  318. struct msi_desc *entry, *tmp;
  319. struct attribute **msi_attrs;
  320. struct device_attribute *dev_attr;
  321. int i, count = 0;
  322. for_each_pci_msi_entry(entry, dev)
  323. if (entry->irq)
  324. for (i = 0; i < entry->nvec_used; i++)
  325. BUG_ON(irq_has_action(entry->irq + i));
  326. if (dev->msi_irq_groups) {
  327. sysfs_remove_groups(&dev->dev.kobj, dev->msi_irq_groups);
  328. msi_attrs = dev->msi_irq_groups[0]->attrs;
  329. while (msi_attrs[count]) {
  330. dev_attr = container_of(msi_attrs[count],
  331. struct device_attribute, attr);
  332. kfree(dev_attr->attr.name);
  333. kfree(dev_attr);
  334. ++count;
  335. }
  336. kfree(msi_attrs);
  337. kfree(dev->msi_irq_groups[0]);
  338. kfree(dev->msi_irq_groups);
  339. dev->msi_irq_groups = NULL;
  340. }
  341. pci_msi_teardown_msi_irqs(dev);
  342. list_for_each_entry_safe(entry, tmp, msi_list, list) {
  343. if (entry->msi_attrib.is_msix) {
  344. if (list_is_last(&entry->list, msi_list))
  345. iounmap(entry->mask_base);
  346. }
  347. list_del(&entry->list);
  348. free_msi_entry(entry);
  349. }
  350. }
  351. static void pci_intx_for_msi(struct pci_dev *dev, int enable)
  352. {
  353. if (!(dev->dev_flags & PCI_DEV_FLAGS_MSI_INTX_DISABLE_BUG))
  354. pci_intx(dev, enable);
  355. }
  356. static void __pci_restore_msi_state(struct pci_dev *dev)
  357. {
  358. u16 control;
  359. struct msi_desc *entry;
  360. if (!dev->msi_enabled)
  361. return;
  362. entry = irq_get_msi_desc(dev->irq);
  363. pci_intx_for_msi(dev, 0);
  364. pci_msi_set_enable(dev, 0);
  365. arch_restore_msi_irqs(dev);
  366. pci_read_config_word(dev, dev->msi_cap + PCI_MSI_FLAGS, &control);
  367. msi_mask_irq(entry, msi_mask(entry->msi_attrib.multi_cap),
  368. entry->masked);
  369. control &= ~PCI_MSI_FLAGS_QSIZE;
  370. control |= (entry->msi_attrib.multiple << 4) | PCI_MSI_FLAGS_ENABLE;
  371. pci_write_config_word(dev, dev->msi_cap + PCI_MSI_FLAGS, control);
  372. }
  373. static void __pci_restore_msix_state(struct pci_dev *dev)
  374. {
  375. struct msi_desc *entry;
  376. if (!dev->msix_enabled)
  377. return;
  378. BUG_ON(list_empty(dev_to_msi_list(&dev->dev)));
  379. /* route the table */
  380. pci_intx_for_msi(dev, 0);
  381. pci_msix_clear_and_set_ctrl(dev, 0,
  382. PCI_MSIX_FLAGS_ENABLE | PCI_MSIX_FLAGS_MASKALL);
  383. arch_restore_msi_irqs(dev);
  384. for_each_pci_msi_entry(entry, dev)
  385. msix_mask_irq(entry, entry->masked);
  386. pci_msix_clear_and_set_ctrl(dev, PCI_MSIX_FLAGS_MASKALL, 0);
  387. }
  388. void pci_restore_msi_state(struct pci_dev *dev)
  389. {
  390. __pci_restore_msi_state(dev);
  391. __pci_restore_msix_state(dev);
  392. }
  393. EXPORT_SYMBOL_GPL(pci_restore_msi_state);
  394. static ssize_t msi_mode_show(struct device *dev, struct device_attribute *attr,
  395. char *buf)
  396. {
  397. struct msi_desc *entry;
  398. unsigned long irq;
  399. int retval;
  400. retval = kstrtoul(attr->attr.name, 10, &irq);
  401. if (retval)
  402. return retval;
  403. entry = irq_get_msi_desc(irq);
  404. if (entry)
  405. return sprintf(buf, "%s\n",
  406. entry->msi_attrib.is_msix ? "msix" : "msi");
  407. return -ENODEV;
  408. }
  409. static int populate_msi_sysfs(struct pci_dev *pdev)
  410. {
  411. struct attribute **msi_attrs;
  412. struct attribute *msi_attr;
  413. struct device_attribute *msi_dev_attr;
  414. struct attribute_group *msi_irq_group;
  415. const struct attribute_group **msi_irq_groups;
  416. struct msi_desc *entry;
  417. int ret = -ENOMEM;
  418. int num_msi = 0;
  419. int count = 0;
  420. int i;
  421. /* Determine how many msi entries we have */
  422. for_each_pci_msi_entry(entry, pdev)
  423. num_msi += entry->nvec_used;
  424. if (!num_msi)
  425. return 0;
  426. /* Dynamically create the MSI attributes for the PCI device */
  427. msi_attrs = kcalloc(num_msi + 1, sizeof(void *), GFP_KERNEL);
  428. if (!msi_attrs)
  429. return -ENOMEM;
  430. for_each_pci_msi_entry(entry, pdev) {
  431. for (i = 0; i < entry->nvec_used; i++) {
  432. msi_dev_attr = kzalloc(sizeof(*msi_dev_attr), GFP_KERNEL);
  433. if (!msi_dev_attr)
  434. goto error_attrs;
  435. msi_attrs[count] = &msi_dev_attr->attr;
  436. sysfs_attr_init(&msi_dev_attr->attr);
  437. msi_dev_attr->attr.name = kasprintf(GFP_KERNEL, "%d",
  438. entry->irq + i);
  439. if (!msi_dev_attr->attr.name)
  440. goto error_attrs;
  441. msi_dev_attr->attr.mode = S_IRUGO;
  442. msi_dev_attr->show = msi_mode_show;
  443. ++count;
  444. }
  445. }
  446. msi_irq_group = kzalloc(sizeof(*msi_irq_group), GFP_KERNEL);
  447. if (!msi_irq_group)
  448. goto error_attrs;
  449. msi_irq_group->name = "msi_irqs";
  450. msi_irq_group->attrs = msi_attrs;
  451. msi_irq_groups = kcalloc(2, sizeof(void *), GFP_KERNEL);
  452. if (!msi_irq_groups)
  453. goto error_irq_group;
  454. msi_irq_groups[0] = msi_irq_group;
  455. ret = sysfs_create_groups(&pdev->dev.kobj, msi_irq_groups);
  456. if (ret)
  457. goto error_irq_groups;
  458. pdev->msi_irq_groups = msi_irq_groups;
  459. return 0;
  460. error_irq_groups:
  461. kfree(msi_irq_groups);
  462. error_irq_group:
  463. kfree(msi_irq_group);
  464. error_attrs:
  465. count = 0;
  466. msi_attr = msi_attrs[count];
  467. while (msi_attr) {
  468. msi_dev_attr = container_of(msi_attr, struct device_attribute, attr);
  469. kfree(msi_attr->name);
  470. kfree(msi_dev_attr);
  471. ++count;
  472. msi_attr = msi_attrs[count];
  473. }
  474. kfree(msi_attrs);
  475. return ret;
  476. }
  477. static struct msi_desc *
  478. msi_setup_entry(struct pci_dev *dev, int nvec, struct irq_affinity *affd)
  479. {
  480. struct irq_affinity_desc *masks = NULL;
  481. struct msi_desc *entry;
  482. u16 control;
  483. if (affd)
  484. masks = irq_create_affinity_masks(nvec, affd);
  485. /* MSI Entry Initialization */
  486. entry = alloc_msi_entry(&dev->dev, nvec, masks);
  487. if (!entry)
  488. goto out;
  489. pci_read_config_word(dev, dev->msi_cap + PCI_MSI_FLAGS, &control);
  490. /* Lies, damned lies, and MSIs */
  491. if (dev->dev_flags & PCI_DEV_FLAGS_HAS_MSI_MASKING)
  492. control |= PCI_MSI_FLAGS_MASKBIT;
  493. entry->msi_attrib.is_msix = 0;
  494. entry->msi_attrib.is_64 = !!(control & PCI_MSI_FLAGS_64BIT);
  495. entry->msi_attrib.is_virtual = 0;
  496. entry->msi_attrib.entry_nr = 0;
  497. entry->msi_attrib.maskbit = !!(control & PCI_MSI_FLAGS_MASKBIT);
  498. entry->msi_attrib.default_irq = dev->irq; /* Save IOAPIC IRQ */
  499. entry->msi_attrib.multi_cap = (control & PCI_MSI_FLAGS_QMASK) >> 1;
  500. entry->msi_attrib.multiple = ilog2(__roundup_pow_of_two(nvec));
  501. if (control & PCI_MSI_FLAGS_64BIT)
  502. entry->mask_pos = dev->msi_cap + PCI_MSI_MASK_64;
  503. else
  504. entry->mask_pos = dev->msi_cap + PCI_MSI_MASK_32;
  505. /* Save the initial mask status */
  506. if (entry->msi_attrib.maskbit)
  507. pci_read_config_dword(dev, entry->mask_pos, &entry->masked);
  508. out:
  509. kfree(masks);
  510. return entry;
  511. }
  512. static int msi_verify_entries(struct pci_dev *dev)
  513. {
  514. struct msi_desc *entry;
  515. for_each_pci_msi_entry(entry, dev) {
  516. if (!dev->no_64bit_msi || !entry->msg.address_hi)
  517. continue;
  518. pci_err(dev, "Device has broken 64-bit MSI but arch"
  519. " tried to assign one above 4G\n");
  520. return -EIO;
  521. }
  522. return 0;
  523. }
  524. /**
  525. * msi_capability_init - configure device's MSI capability structure
  526. * @dev: pointer to the pci_dev data structure of MSI device function
  527. * @nvec: number of interrupts to allocate
  528. * @affd: description of automatic IRQ affinity assignments (may be %NULL)
  529. *
  530. * Setup the MSI capability structure of the device with the requested
  531. * number of interrupts. A return value of zero indicates the successful
  532. * setup of an entry with the new MSI IRQ. A negative return value indicates
  533. * an error, and a positive return value indicates the number of interrupts
  534. * which could have been allocated.
  535. */
  536. static int msi_capability_init(struct pci_dev *dev, int nvec,
  537. struct irq_affinity *affd)
  538. {
  539. struct msi_desc *entry;
  540. int ret;
  541. unsigned mask;
  542. pci_msi_set_enable(dev, 0); /* Disable MSI during set up */
  543. entry = msi_setup_entry(dev, nvec, affd);
  544. if (!entry)
  545. return -ENOMEM;
  546. /* All MSIs are unmasked by default; mask them all */
  547. mask = msi_mask(entry->msi_attrib.multi_cap);
  548. msi_mask_irq(entry, mask, mask);
  549. list_add_tail(&entry->list, dev_to_msi_list(&dev->dev));
  550. /* Configure MSI capability structure */
  551. ret = pci_msi_setup_msi_irqs(dev, nvec, PCI_CAP_ID_MSI);
  552. if (ret) {
  553. msi_mask_irq(entry, mask, 0);
  554. free_msi_irqs(dev);
  555. return ret;
  556. }
  557. ret = msi_verify_entries(dev);
  558. if (ret) {
  559. msi_mask_irq(entry, mask, 0);
  560. free_msi_irqs(dev);
  561. return ret;
  562. }
  563. ret = populate_msi_sysfs(dev);
  564. if (ret) {
  565. msi_mask_irq(entry, mask, 0);
  566. free_msi_irqs(dev);
  567. return ret;
  568. }
  569. /* Set MSI enabled bits */
  570. pci_intx_for_msi(dev, 0);
  571. pci_msi_set_enable(dev, 1);
  572. dev->msi_enabled = 1;
  573. pcibios_free_irq(dev);
  574. dev->irq = entry->irq;
  575. return 0;
  576. }
  577. static void __iomem *msix_map_region(struct pci_dev *dev, unsigned nr_entries)
  578. {
  579. resource_size_t phys_addr;
  580. u32 table_offset;
  581. unsigned long flags;
  582. u8 bir;
  583. pci_read_config_dword(dev, dev->msix_cap + PCI_MSIX_TABLE,
  584. &table_offset);
  585. bir = (u8)(table_offset & PCI_MSIX_TABLE_BIR);
  586. flags = pci_resource_flags(dev, bir);
  587. if (!flags || (flags & IORESOURCE_UNSET))
  588. return NULL;
  589. table_offset &= PCI_MSIX_TABLE_OFFSET;
  590. phys_addr = pci_resource_start(dev, bir) + table_offset;
  591. return ioremap(phys_addr, nr_entries * PCI_MSIX_ENTRY_SIZE);
  592. }
  593. static int msix_setup_entries(struct pci_dev *dev, void __iomem *base,
  594. struct msix_entry *entries, int nvec,
  595. struct irq_affinity *affd)
  596. {
  597. struct irq_affinity_desc *curmsk, *masks = NULL;
  598. struct msi_desc *entry;
  599. void __iomem *addr;
  600. int ret, i;
  601. int vec_count = pci_msix_vec_count(dev);
  602. if (affd)
  603. masks = irq_create_affinity_masks(nvec, affd);
  604. for (i = 0, curmsk = masks; i < nvec; i++) {
  605. entry = alloc_msi_entry(&dev->dev, 1, curmsk);
  606. if (!entry) {
  607. if (!i)
  608. iounmap(base);
  609. else
  610. free_msi_irqs(dev);
  611. /* No enough memory. Don't try again */
  612. ret = -ENOMEM;
  613. goto out;
  614. }
  615. entry->msi_attrib.is_msix = 1;
  616. entry->msi_attrib.is_64 = 1;
  617. if (entries)
  618. entry->msi_attrib.entry_nr = entries[i].entry;
  619. else
  620. entry->msi_attrib.entry_nr = i;
  621. entry->msi_attrib.is_virtual =
  622. entry->msi_attrib.entry_nr >= vec_count;
  623. entry->msi_attrib.default_irq = dev->irq;
  624. entry->mask_base = base;
  625. addr = pci_msix_desc_addr(entry);
  626. if (addr)
  627. entry->masked = readl(addr + PCI_MSIX_ENTRY_VECTOR_CTRL);
  628. list_add_tail(&entry->list, dev_to_msi_list(&dev->dev));
  629. if (masks)
  630. curmsk++;
  631. }
  632. ret = 0;
  633. out:
  634. kfree(masks);
  635. return ret;
  636. }
  637. static void msix_update_entries(struct pci_dev *dev, struct msix_entry *entries)
  638. {
  639. struct msi_desc *entry;
  640. for_each_pci_msi_entry(entry, dev) {
  641. if (entries) {
  642. entries->vector = entry->irq;
  643. entries++;
  644. }
  645. }
  646. }
  647. static void msix_mask_all(void __iomem *base, int tsize)
  648. {
  649. u32 ctrl = PCI_MSIX_ENTRY_CTRL_MASKBIT;
  650. int i;
  651. if (pci_msi_ignore_mask)
  652. return;
  653. for (i = 0; i < tsize; i++, base += PCI_MSIX_ENTRY_SIZE)
  654. writel(ctrl, base + PCI_MSIX_ENTRY_VECTOR_CTRL);
  655. }
  656. /**
  657. * msix_capability_init - configure device's MSI-X capability
  658. * @dev: pointer to the pci_dev data structure of MSI-X device function
  659. * @entries: pointer to an array of struct msix_entry entries
  660. * @nvec: number of @entries
  661. * @affd: Optional pointer to enable automatic affinity assignment
  662. *
  663. * Setup the MSI-X capability structure of device function with a
  664. * single MSI-X IRQ. A return of zero indicates the successful setup of
  665. * requested MSI-X entries with allocated IRQs or non-zero for otherwise.
  666. **/
  667. static int msix_capability_init(struct pci_dev *dev, struct msix_entry *entries,
  668. int nvec, struct irq_affinity *affd)
  669. {
  670. void __iomem *base;
  671. int ret, tsize;
  672. u16 control;
  673. /*
  674. * Some devices require MSI-X to be enabled before the MSI-X
  675. * registers can be accessed. Mask all the vectors to prevent
  676. * interrupts coming in before they're fully set up.
  677. */
  678. pci_msix_clear_and_set_ctrl(dev, 0, PCI_MSIX_FLAGS_MASKALL |
  679. PCI_MSIX_FLAGS_ENABLE);
  680. pci_read_config_word(dev, dev->msix_cap + PCI_MSIX_FLAGS, &control);
  681. /* Request & Map MSI-X table region */
  682. tsize = msix_table_size(control);
  683. base = msix_map_region(dev, tsize);
  684. if (!base) {
  685. ret = -ENOMEM;
  686. goto out_disable;
  687. }
  688. ret = msix_setup_entries(dev, base, entries, nvec, affd);
  689. if (ret)
  690. goto out_disable;
  691. ret = pci_msi_setup_msi_irqs(dev, nvec, PCI_CAP_ID_MSIX);
  692. if (ret)
  693. goto out_avail;
  694. /* Check if all MSI entries honor device restrictions */
  695. ret = msi_verify_entries(dev);
  696. if (ret)
  697. goto out_free;
  698. msix_update_entries(dev, entries);
  699. ret = populate_msi_sysfs(dev);
  700. if (ret)
  701. goto out_free;
  702. /* Set MSI-X enabled bits and unmask the function */
  703. pci_intx_for_msi(dev, 0);
  704. dev->msix_enabled = 1;
  705. /*
  706. * Ensure that all table entries are masked to prevent
  707. * stale entries from firing in a crash kernel.
  708. *
  709. * Done late to deal with a broken Marvell NVME device
  710. * which takes the MSI-X mask bits into account even
  711. * when MSI-X is disabled, which prevents MSI delivery.
  712. */
  713. msix_mask_all(base, tsize);
  714. pci_msix_clear_and_set_ctrl(dev, PCI_MSIX_FLAGS_MASKALL, 0);
  715. pcibios_free_irq(dev);
  716. return 0;
  717. out_avail:
  718. if (ret < 0) {
  719. /*
  720. * If we had some success, report the number of IRQs
  721. * we succeeded in setting up.
  722. */
  723. struct msi_desc *entry;
  724. int avail = 0;
  725. for_each_pci_msi_entry(entry, dev) {
  726. if (entry->irq != 0)
  727. avail++;
  728. }
  729. if (avail != 0)
  730. ret = avail;
  731. }
  732. out_free:
  733. free_msi_irqs(dev);
  734. out_disable:
  735. pci_msix_clear_and_set_ctrl(dev, PCI_MSIX_FLAGS_MASKALL | PCI_MSIX_FLAGS_ENABLE, 0);
  736. return ret;
  737. }
  738. /**
  739. * pci_msi_supported - check whether MSI may be enabled on a device
  740. * @dev: pointer to the pci_dev data structure of MSI device function
  741. * @nvec: how many MSIs have been requested?
  742. *
  743. * Look at global flags, the device itself, and its parent buses
  744. * to determine if MSI/-X are supported for the device. If MSI/-X is
  745. * supported return 1, else return 0.
  746. **/
  747. static int pci_msi_supported(struct pci_dev *dev, int nvec)
  748. {
  749. struct pci_bus *bus;
  750. /* MSI must be globally enabled and supported by the device */
  751. if (!pci_msi_enable)
  752. return 0;
  753. if (!dev || dev->no_msi)
  754. return 0;
  755. /*
  756. * You can't ask to have 0 or less MSIs configured.
  757. * a) it's stupid ..
  758. * b) the list manipulation code assumes nvec >= 1.
  759. */
  760. if (nvec < 1)
  761. return 0;
  762. /*
  763. * Any bridge which does NOT route MSI transactions from its
  764. * secondary bus to its primary bus must set NO_MSI flag on
  765. * the secondary pci_bus.
  766. * We expect only arch-specific PCI host bus controller driver
  767. * or quirks for specific PCI bridges to be setting NO_MSI.
  768. */
  769. for (bus = dev->bus; bus; bus = bus->parent)
  770. if (bus->bus_flags & PCI_BUS_FLAGS_NO_MSI)
  771. return 0;
  772. return 1;
  773. }
  774. /**
  775. * pci_msi_vec_count - Return the number of MSI vectors a device can send
  776. * @dev: device to report about
  777. *
  778. * This function returns the number of MSI vectors a device requested via
  779. * Multiple Message Capable register. It returns a negative errno if the
  780. * device is not capable sending MSI interrupts. Otherwise, the call succeeds
  781. * and returns a power of two, up to a maximum of 2^5 (32), according to the
  782. * MSI specification.
  783. **/
  784. int pci_msi_vec_count(struct pci_dev *dev)
  785. {
  786. int ret;
  787. u16 msgctl;
  788. if (!dev->msi_cap)
  789. return -EINVAL;
  790. pci_read_config_word(dev, dev->msi_cap + PCI_MSI_FLAGS, &msgctl);
  791. ret = 1 << ((msgctl & PCI_MSI_FLAGS_QMASK) >> 1);
  792. return ret;
  793. }
  794. EXPORT_SYMBOL(pci_msi_vec_count);
  795. static void pci_msi_shutdown(struct pci_dev *dev)
  796. {
  797. struct msi_desc *desc;
  798. u32 mask;
  799. if (!pci_msi_enable || !dev || !dev->msi_enabled)
  800. return;
  801. BUG_ON(list_empty(dev_to_msi_list(&dev->dev)));
  802. desc = first_pci_msi_entry(dev);
  803. pci_msi_set_enable(dev, 0);
  804. pci_intx_for_msi(dev, 1);
  805. dev->msi_enabled = 0;
  806. /* Return the device with MSI unmasked as initial states */
  807. mask = msi_mask(desc->msi_attrib.multi_cap);
  808. msi_mask_irq(desc, mask, 0);
  809. /* Restore dev->irq to its default pin-assertion IRQ */
  810. dev->irq = desc->msi_attrib.default_irq;
  811. pcibios_alloc_irq(dev);
  812. }
  813. void pci_disable_msi(struct pci_dev *dev)
  814. {
  815. if (!pci_msi_enable || !dev || !dev->msi_enabled)
  816. return;
  817. pci_msi_shutdown(dev);
  818. free_msi_irqs(dev);
  819. }
  820. EXPORT_SYMBOL(pci_disable_msi);
  821. /**
  822. * pci_msix_vec_count - return the number of device's MSI-X table entries
  823. * @dev: pointer to the pci_dev data structure of MSI-X device function
  824. * This function returns the number of device's MSI-X table entries and
  825. * therefore the number of MSI-X vectors device is capable of sending.
  826. * It returns a negative errno if the device is not capable of sending MSI-X
  827. * interrupts.
  828. **/
  829. int pci_msix_vec_count(struct pci_dev *dev)
  830. {
  831. u16 control;
  832. if (!dev->msix_cap)
  833. return -EINVAL;
  834. pci_read_config_word(dev, dev->msix_cap + PCI_MSIX_FLAGS, &control);
  835. return msix_table_size(control);
  836. }
  837. EXPORT_SYMBOL(pci_msix_vec_count);
  838. static int __pci_enable_msix(struct pci_dev *dev, struct msix_entry *entries,
  839. int nvec, struct irq_affinity *affd, int flags)
  840. {
  841. int nr_entries;
  842. int i, j;
  843. if (!pci_msi_supported(dev, nvec) || dev->current_state != PCI_D0)
  844. return -EINVAL;
  845. nr_entries = pci_msix_vec_count(dev);
  846. if (nr_entries < 0)
  847. return nr_entries;
  848. if (nvec > nr_entries && !(flags & PCI_IRQ_VIRTUAL))
  849. return nr_entries;
  850. if (entries) {
  851. /* Check for any invalid entries */
  852. for (i = 0; i < nvec; i++) {
  853. if (entries[i].entry >= nr_entries)
  854. return -EINVAL; /* invalid entry */
  855. for (j = i + 1; j < nvec; j++) {
  856. if (entries[i].entry == entries[j].entry)
  857. return -EINVAL; /* duplicate entry */
  858. }
  859. }
  860. }
  861. /* Check whether driver already requested for MSI IRQ */
  862. if (dev->msi_enabled) {
  863. pci_info(dev, "can't enable MSI-X (MSI IRQ already assigned)\n");
  864. return -EINVAL;
  865. }
  866. return msix_capability_init(dev, entries, nvec, affd);
  867. }
  868. static void pci_msix_shutdown(struct pci_dev *dev)
  869. {
  870. struct msi_desc *entry;
  871. if (!pci_msi_enable || !dev || !dev->msix_enabled)
  872. return;
  873. if (pci_dev_is_disconnected(dev)) {
  874. dev->msix_enabled = 0;
  875. return;
  876. }
  877. /* Return the device with MSI-X masked as initial states */
  878. for_each_pci_msi_entry(entry, dev)
  879. __pci_msix_desc_mask_irq(entry, 1);
  880. pci_msix_clear_and_set_ctrl(dev, PCI_MSIX_FLAGS_ENABLE, 0);
  881. pci_intx_for_msi(dev, 1);
  882. dev->msix_enabled = 0;
  883. pcibios_alloc_irq(dev);
  884. }
  885. void pci_disable_msix(struct pci_dev *dev)
  886. {
  887. if (!pci_msi_enable || !dev || !dev->msix_enabled)
  888. return;
  889. pci_msix_shutdown(dev);
  890. free_msi_irqs(dev);
  891. }
  892. EXPORT_SYMBOL(pci_disable_msix);
  893. void pci_no_msi(void)
  894. {
  895. pci_msi_enable = 0;
  896. }
  897. /**
  898. * pci_msi_enabled - is MSI enabled?
  899. *
  900. * Returns true if MSI has not been disabled by the command-line option
  901. * pci=nomsi.
  902. **/
  903. int pci_msi_enabled(void)
  904. {
  905. return pci_msi_enable;
  906. }
  907. EXPORT_SYMBOL(pci_msi_enabled);
  908. static int __pci_enable_msi_range(struct pci_dev *dev, int minvec, int maxvec,
  909. struct irq_affinity *affd)
  910. {
  911. int nvec;
  912. int rc;
  913. if (!pci_msi_supported(dev, minvec) || dev->current_state != PCI_D0)
  914. return -EINVAL;
  915. /* Check whether driver already requested MSI-X IRQs */
  916. if (dev->msix_enabled) {
  917. pci_info(dev, "can't enable MSI (MSI-X already enabled)\n");
  918. return -EINVAL;
  919. }
  920. if (maxvec < minvec)
  921. return -ERANGE;
  922. if (WARN_ON_ONCE(dev->msi_enabled))
  923. return -EINVAL;
  924. nvec = pci_msi_vec_count(dev);
  925. if (nvec < 0)
  926. return nvec;
  927. if (nvec < minvec)
  928. return -ENOSPC;
  929. if (nvec > maxvec)
  930. nvec = maxvec;
  931. for (;;) {
  932. if (affd) {
  933. nvec = irq_calc_affinity_vectors(minvec, nvec, affd);
  934. if (nvec < minvec)
  935. return -ENOSPC;
  936. }
  937. rc = msi_capability_init(dev, nvec, affd);
  938. if (rc == 0)
  939. return nvec;
  940. if (rc < 0)
  941. return rc;
  942. if (rc < minvec)
  943. return -ENOSPC;
  944. nvec = rc;
  945. }
  946. }
  947. /* deprecated, don't use */
  948. int pci_enable_msi(struct pci_dev *dev)
  949. {
  950. int rc = __pci_enable_msi_range(dev, 1, 1, NULL);
  951. if (rc < 0)
  952. return rc;
  953. return 0;
  954. }
  955. EXPORT_SYMBOL(pci_enable_msi);
  956. static int __pci_enable_msix_range(struct pci_dev *dev,
  957. struct msix_entry *entries, int minvec,
  958. int maxvec, struct irq_affinity *affd,
  959. int flags)
  960. {
  961. int rc, nvec = maxvec;
  962. if (maxvec < minvec)
  963. return -ERANGE;
  964. if (WARN_ON_ONCE(dev->msix_enabled))
  965. return -EINVAL;
  966. for (;;) {
  967. if (affd) {
  968. nvec = irq_calc_affinity_vectors(minvec, nvec, affd);
  969. if (nvec < minvec)
  970. return -ENOSPC;
  971. }
  972. rc = __pci_enable_msix(dev, entries, nvec, affd, flags);
  973. if (rc == 0)
  974. return nvec;
  975. if (rc < 0)
  976. return rc;
  977. if (rc < minvec)
  978. return -ENOSPC;
  979. nvec = rc;
  980. }
  981. }
  982. /**
  983. * pci_enable_msix_range - configure device's MSI-X capability structure
  984. * @dev: pointer to the pci_dev data structure of MSI-X device function
  985. * @entries: pointer to an array of MSI-X entries
  986. * @minvec: minimum number of MSI-X IRQs requested
  987. * @maxvec: maximum number of MSI-X IRQs requested
  988. *
  989. * Setup the MSI-X capability structure of device function with a maximum
  990. * possible number of interrupts in the range between @minvec and @maxvec
  991. * upon its software driver call to request for MSI-X mode enabled on its
  992. * hardware device function. It returns a negative errno if an error occurs.
  993. * If it succeeds, it returns the actual number of interrupts allocated and
  994. * indicates the successful configuration of MSI-X capability structure
  995. * with new allocated MSI-X interrupts.
  996. **/
  997. int pci_enable_msix_range(struct pci_dev *dev, struct msix_entry *entries,
  998. int minvec, int maxvec)
  999. {
  1000. return __pci_enable_msix_range(dev, entries, minvec, maxvec, NULL, 0);
  1001. }
  1002. EXPORT_SYMBOL(pci_enable_msix_range);
  1003. /**
  1004. * pci_alloc_irq_vectors_affinity - allocate multiple IRQs for a device
  1005. * @dev: PCI device to operate on
  1006. * @min_vecs: minimum number of vectors required (must be >= 1)
  1007. * @max_vecs: maximum (desired) number of vectors
  1008. * @flags: flags or quirks for the allocation
  1009. * @affd: optional description of the affinity requirements
  1010. *
  1011. * Allocate up to @max_vecs interrupt vectors for @dev, using MSI-X or MSI
  1012. * vectors if available, and fall back to a single legacy vector
  1013. * if neither is available. Return the number of vectors allocated,
  1014. * (which might be smaller than @max_vecs) if successful, or a negative
  1015. * error code on error. If less than @min_vecs interrupt vectors are
  1016. * available for @dev the function will fail with -ENOSPC.
  1017. *
  1018. * To get the Linux IRQ number used for a vector that can be passed to
  1019. * request_irq() use the pci_irq_vector() helper.
  1020. */
  1021. int pci_alloc_irq_vectors_affinity(struct pci_dev *dev, unsigned int min_vecs,
  1022. unsigned int max_vecs, unsigned int flags,
  1023. struct irq_affinity *affd)
  1024. {
  1025. struct irq_affinity msi_default_affd = {0};
  1026. int nvecs = -ENOSPC;
  1027. if (flags & PCI_IRQ_AFFINITY) {
  1028. if (!affd)
  1029. affd = &msi_default_affd;
  1030. } else {
  1031. if (WARN_ON(affd))
  1032. affd = NULL;
  1033. }
  1034. if (flags & PCI_IRQ_MSIX) {
  1035. nvecs = __pci_enable_msix_range(dev, NULL, min_vecs, max_vecs,
  1036. affd, flags);
  1037. if (nvecs > 0)
  1038. return nvecs;
  1039. }
  1040. if (flags & PCI_IRQ_MSI) {
  1041. nvecs = __pci_enable_msi_range(dev, min_vecs, max_vecs, affd);
  1042. if (nvecs > 0)
  1043. return nvecs;
  1044. }
  1045. /* use legacy IRQ if allowed */
  1046. if (flags & PCI_IRQ_LEGACY) {
  1047. if (min_vecs == 1 && dev->irq) {
  1048. /*
  1049. * Invoke the affinity spreading logic to ensure that
  1050. * the device driver can adjust queue configuration
  1051. * for the single interrupt case.
  1052. */
  1053. if (affd)
  1054. irq_create_affinity_masks(1, affd);
  1055. pci_intx(dev, 1);
  1056. return 1;
  1057. }
  1058. }
  1059. return nvecs;
  1060. }
  1061. EXPORT_SYMBOL(pci_alloc_irq_vectors_affinity);
  1062. /**
  1063. * pci_free_irq_vectors - free previously allocated IRQs for a device
  1064. * @dev: PCI device to operate on
  1065. *
  1066. * Undoes the allocations and enabling in pci_alloc_irq_vectors().
  1067. */
  1068. void pci_free_irq_vectors(struct pci_dev *dev)
  1069. {
  1070. pci_disable_msix(dev);
  1071. pci_disable_msi(dev);
  1072. }
  1073. EXPORT_SYMBOL(pci_free_irq_vectors);
  1074. /**
  1075. * pci_irq_vector - return Linux IRQ number of a device vector
  1076. * @dev: PCI device to operate on
  1077. * @nr: Interrupt vector index (0-based)
  1078. *
  1079. * @nr has the following meanings depending on the interrupt mode:
  1080. * MSI-X: The index in the MSI-X vector table
  1081. * MSI: The index of the enabled MSI vectors
  1082. * INTx: Must be 0
  1083. *
  1084. * Return: The Linux interrupt number or -EINVAl if @nr is out of range.
  1085. */
  1086. int pci_irq_vector(struct pci_dev *dev, unsigned int nr)
  1087. {
  1088. if (dev->msix_enabled) {
  1089. struct msi_desc *entry;
  1090. for_each_pci_msi_entry(entry, dev) {
  1091. if (entry->msi_attrib.entry_nr == nr)
  1092. return entry->irq;
  1093. }
  1094. WARN_ON_ONCE(1);
  1095. return -EINVAL;
  1096. }
  1097. if (dev->msi_enabled) {
  1098. struct msi_desc *entry = first_pci_msi_entry(dev);
  1099. if (WARN_ON_ONCE(nr >= entry->nvec_used))
  1100. return -EINVAL;
  1101. } else {
  1102. if (WARN_ON_ONCE(nr > 0))
  1103. return -EINVAL;
  1104. }
  1105. return dev->irq + nr;
  1106. }
  1107. EXPORT_SYMBOL(pci_irq_vector);
  1108. /**
  1109. * pci_irq_get_affinity - return the affinity of a particular MSI vector
  1110. * @dev: PCI device to operate on
  1111. * @nr: device-relative interrupt vector index (0-based).
  1112. *
  1113. * @nr has the following meanings depending on the interrupt mode:
  1114. * MSI-X: The index in the MSI-X vector table
  1115. * MSI: The index of the enabled MSI vectors
  1116. * INTx: Must be 0
  1117. *
  1118. * Return: A cpumask pointer or NULL if @nr is out of range
  1119. */
  1120. const struct cpumask *pci_irq_get_affinity(struct pci_dev *dev, int nr)
  1121. {
  1122. if (dev->msix_enabled) {
  1123. struct msi_desc *entry;
  1124. for_each_pci_msi_entry(entry, dev) {
  1125. if (entry->msi_attrib.entry_nr == nr)
  1126. return &entry->affinity->mask;
  1127. }
  1128. WARN_ON_ONCE(1);
  1129. return NULL;
  1130. } else if (dev->msi_enabled) {
  1131. struct msi_desc *entry = first_pci_msi_entry(dev);
  1132. if (WARN_ON_ONCE(!entry || !entry->affinity ||
  1133. nr >= entry->nvec_used))
  1134. return NULL;
  1135. return &entry->affinity[nr].mask;
  1136. } else {
  1137. return cpu_possible_mask;
  1138. }
  1139. }
  1140. EXPORT_SYMBOL(pci_irq_get_affinity);
  1141. struct pci_dev *msi_desc_to_pci_dev(struct msi_desc *desc)
  1142. {
  1143. return to_pci_dev(desc->dev);
  1144. }
  1145. EXPORT_SYMBOL(msi_desc_to_pci_dev);
  1146. void *msi_desc_to_pci_sysdata(struct msi_desc *desc)
  1147. {
  1148. struct pci_dev *dev = msi_desc_to_pci_dev(desc);
  1149. return dev->bus->sysdata;
  1150. }
  1151. EXPORT_SYMBOL_GPL(msi_desc_to_pci_sysdata);
  1152. #ifdef CONFIG_PCI_MSI_IRQ_DOMAIN
  1153. /**
  1154. * pci_msi_domain_write_msg - Helper to write MSI message to PCI config space
  1155. * @irq_data: Pointer to interrupt data of the MSI interrupt
  1156. * @msg: Pointer to the message
  1157. */
  1158. void pci_msi_domain_write_msg(struct irq_data *irq_data, struct msi_msg *msg)
  1159. {
  1160. struct msi_desc *desc = irq_data_get_msi_desc(irq_data);
  1161. /*
  1162. * For MSI-X desc->irq is always equal to irq_data->irq. For
  1163. * MSI only the first interrupt of MULTI MSI passes the test.
  1164. */
  1165. if (desc->irq == irq_data->irq)
  1166. __pci_write_msi_msg(desc, msg);
  1167. }
  1168. /**
  1169. * pci_msi_domain_calc_hwirq - Generate a unique ID for an MSI source
  1170. * @desc: Pointer to the MSI descriptor
  1171. *
  1172. * The ID number is only used within the irqdomain.
  1173. */
  1174. static irq_hw_number_t pci_msi_domain_calc_hwirq(struct msi_desc *desc)
  1175. {
  1176. struct pci_dev *dev = msi_desc_to_pci_dev(desc);
  1177. return (irq_hw_number_t)desc->msi_attrib.entry_nr |
  1178. pci_dev_id(dev) << 11 |
  1179. (pci_domain_nr(dev->bus) & 0xFFFFFFFF) << 27;
  1180. }
  1181. static inline bool pci_msi_desc_is_multi_msi(struct msi_desc *desc)
  1182. {
  1183. return !desc->msi_attrib.is_msix && desc->nvec_used > 1;
  1184. }
  1185. /**
  1186. * pci_msi_domain_check_cap - Verify that @domain supports the capabilities
  1187. * for @dev
  1188. * @domain: The interrupt domain to check
  1189. * @info: The domain info for verification
  1190. * @dev: The device to check
  1191. *
  1192. * Returns:
  1193. * 0 if the functionality is supported
  1194. * 1 if Multi MSI is requested, but the domain does not support it
  1195. * -ENOTSUPP otherwise
  1196. */
  1197. int pci_msi_domain_check_cap(struct irq_domain *domain,
  1198. struct msi_domain_info *info, struct device *dev)
  1199. {
  1200. struct msi_desc *desc = first_pci_msi_entry(to_pci_dev(dev));
  1201. /* Special handling to support __pci_enable_msi_range() */
  1202. if (pci_msi_desc_is_multi_msi(desc) &&
  1203. !(info->flags & MSI_FLAG_MULTI_PCI_MSI))
  1204. return 1;
  1205. else if (desc->msi_attrib.is_msix && !(info->flags & MSI_FLAG_PCI_MSIX))
  1206. return -ENOTSUPP;
  1207. return 0;
  1208. }
  1209. static int pci_msi_domain_handle_error(struct irq_domain *domain,
  1210. struct msi_desc *desc, int error)
  1211. {
  1212. /* Special handling to support __pci_enable_msi_range() */
  1213. if (pci_msi_desc_is_multi_msi(desc) && error == -ENOSPC)
  1214. return 1;
  1215. return error;
  1216. }
  1217. static void pci_msi_domain_set_desc(msi_alloc_info_t *arg,
  1218. struct msi_desc *desc)
  1219. {
  1220. arg->desc = desc;
  1221. arg->hwirq = pci_msi_domain_calc_hwirq(desc);
  1222. }
  1223. static struct msi_domain_ops pci_msi_domain_ops_default = {
  1224. .set_desc = pci_msi_domain_set_desc,
  1225. .msi_check = pci_msi_domain_check_cap,
  1226. .handle_error = pci_msi_domain_handle_error,
  1227. };
  1228. static void pci_msi_domain_update_dom_ops(struct msi_domain_info *info)
  1229. {
  1230. struct msi_domain_ops *ops = info->ops;
  1231. if (ops == NULL) {
  1232. info->ops = &pci_msi_domain_ops_default;
  1233. } else {
  1234. if (ops->set_desc == NULL)
  1235. ops->set_desc = pci_msi_domain_set_desc;
  1236. if (ops->msi_check == NULL)
  1237. ops->msi_check = pci_msi_domain_check_cap;
  1238. if (ops->handle_error == NULL)
  1239. ops->handle_error = pci_msi_domain_handle_error;
  1240. }
  1241. }
  1242. static void pci_msi_domain_update_chip_ops(struct msi_domain_info *info)
  1243. {
  1244. struct irq_chip *chip = info->chip;
  1245. BUG_ON(!chip);
  1246. if (!chip->irq_write_msi_msg)
  1247. chip->irq_write_msi_msg = pci_msi_domain_write_msg;
  1248. if (!chip->irq_mask)
  1249. chip->irq_mask = pci_msi_mask_irq;
  1250. if (!chip->irq_unmask)
  1251. chip->irq_unmask = pci_msi_unmask_irq;
  1252. }
  1253. /**
  1254. * pci_msi_create_irq_domain - Create a MSI interrupt domain
  1255. * @fwnode: Optional fwnode of the interrupt controller
  1256. * @info: MSI domain info
  1257. * @parent: Parent irq domain
  1258. *
  1259. * Updates the domain and chip ops and creates a MSI interrupt domain.
  1260. *
  1261. * Returns:
  1262. * A domain pointer or NULL in case of failure.
  1263. */
  1264. struct irq_domain *pci_msi_create_irq_domain(struct fwnode_handle *fwnode,
  1265. struct msi_domain_info *info,
  1266. struct irq_domain *parent)
  1267. {
  1268. struct irq_domain *domain;
  1269. if (WARN_ON(info->flags & MSI_FLAG_LEVEL_CAPABLE))
  1270. info->flags &= ~MSI_FLAG_LEVEL_CAPABLE;
  1271. if (info->flags & MSI_FLAG_USE_DEF_DOM_OPS)
  1272. pci_msi_domain_update_dom_ops(info);
  1273. if (info->flags & MSI_FLAG_USE_DEF_CHIP_OPS)
  1274. pci_msi_domain_update_chip_ops(info);
  1275. info->flags |= MSI_FLAG_ACTIVATE_EARLY;
  1276. if (IS_ENABLED(CONFIG_GENERIC_IRQ_RESERVATION_MODE))
  1277. info->flags |= MSI_FLAG_MUST_REACTIVATE;
  1278. /* PCI-MSI is oneshot-safe */
  1279. info->chip->flags |= IRQCHIP_ONESHOT_SAFE;
  1280. domain = msi_create_irq_domain(fwnode, info, parent);
  1281. if (!domain)
  1282. return NULL;
  1283. irq_domain_update_bus_token(domain, DOMAIN_BUS_PCI_MSI);
  1284. return domain;
  1285. }
  1286. EXPORT_SYMBOL_GPL(pci_msi_create_irq_domain);
  1287. /*
  1288. * Users of the generic MSI infrastructure expect a device to have a single ID,
  1289. * so with DMA aliases we have to pick the least-worst compromise. Devices with
  1290. * DMA phantom functions tend to still emit MSIs from the real function number,
  1291. * so we ignore those and only consider topological aliases where either the
  1292. * alias device or RID appears on a different bus number. We also make the
  1293. * reasonable assumption that bridges are walked in an upstream direction (so
  1294. * the last one seen wins), and the much braver assumption that the most likely
  1295. * case is that of PCI->PCIe so we should always use the alias RID. This echoes
  1296. * the logic from intel_irq_remapping's set_msi_sid(), which presumably works
  1297. * well enough in practice; in the face of the horrible PCIe<->PCI-X conditions
  1298. * for taking ownership all we can really do is close our eyes and hope...
  1299. */
  1300. static int get_msi_id_cb(struct pci_dev *pdev, u16 alias, void *data)
  1301. {
  1302. u32 *pa = data;
  1303. u8 bus = PCI_BUS_NUM(*pa);
  1304. if (pdev->bus->number != bus || PCI_BUS_NUM(alias) != bus)
  1305. *pa = alias;
  1306. return 0;
  1307. }
  1308. /**
  1309. * pci_msi_domain_get_msi_rid - Get the MSI requester id (RID)
  1310. * @domain: The interrupt domain
  1311. * @pdev: The PCI device.
  1312. *
  1313. * The RID for a device is formed from the alias, with a firmware
  1314. * supplied mapping applied
  1315. *
  1316. * Returns: The RID.
  1317. */
  1318. u32 pci_msi_domain_get_msi_rid(struct irq_domain *domain, struct pci_dev *pdev)
  1319. {
  1320. struct device_node *of_node;
  1321. u32 rid = pci_dev_id(pdev);
  1322. pci_for_each_dma_alias(pdev, get_msi_id_cb, &rid);
  1323. of_node = irq_domain_get_of_node(domain);
  1324. rid = of_node ? of_msi_map_id(&pdev->dev, of_node, rid) :
  1325. iort_msi_map_id(&pdev->dev, rid);
  1326. return rid;
  1327. }
  1328. /**
  1329. * pci_msi_get_device_domain - Get the MSI domain for a given PCI device
  1330. * @pdev: The PCI device
  1331. *
  1332. * Use the firmware data to find a device-specific MSI domain
  1333. * (i.e. not one that is set as a default).
  1334. *
  1335. * Returns: The corresponding MSI domain or NULL if none has been found.
  1336. */
  1337. struct irq_domain *pci_msi_get_device_domain(struct pci_dev *pdev)
  1338. {
  1339. struct irq_domain *dom;
  1340. u32 rid = pci_dev_id(pdev);
  1341. pci_for_each_dma_alias(pdev, get_msi_id_cb, &rid);
  1342. dom = of_msi_map_get_device_domain(&pdev->dev, rid, DOMAIN_BUS_PCI_MSI);
  1343. if (!dom)
  1344. dom = iort_get_device_domain(&pdev->dev, rid,
  1345. DOMAIN_BUS_PCI_MSI);
  1346. return dom;
  1347. }
  1348. /**
  1349. * pci_dev_has_special_msi_domain - Check whether the device is handled by
  1350. * a non-standard PCI-MSI domain
  1351. * @pdev: The PCI device to check.
  1352. *
  1353. * Returns: True if the device irqdomain or the bus irqdomain is
  1354. * non-standard PCI/MSI.
  1355. */
  1356. bool pci_dev_has_special_msi_domain(struct pci_dev *pdev)
  1357. {
  1358. struct irq_domain *dom = dev_get_msi_domain(&pdev->dev);
  1359. if (!dom)
  1360. dom = dev_get_msi_domain(&pdev->bus->dev);
  1361. if (!dom)
  1362. return true;
  1363. return dom->bus_token != DOMAIN_BUS_PCI_MSI;
  1364. }
  1365. #endif /* CONFIG_PCI_MSI_IRQ_DOMAIN */