vmd.c 21 KB

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  1. // SPDX-License-Identifier: GPL-2.0
  2. /*
  3. * Volume Management Device driver
  4. * Copyright (c) 2015, Intel Corporation.
  5. */
  6. #include <linux/device.h>
  7. #include <linux/interrupt.h>
  8. #include <linux/irq.h>
  9. #include <linux/kernel.h>
  10. #include <linux/module.h>
  11. #include <linux/msi.h>
  12. #include <linux/pci.h>
  13. #include <linux/srcu.h>
  14. #include <linux/rculist.h>
  15. #include <linux/rcupdate.h>
  16. #include <asm/irqdomain.h>
  17. #include <asm/device.h>
  18. #include <asm/msi.h>
  19. #include <asm/msidef.h>
  20. #define VMD_CFGBAR 0
  21. #define VMD_MEMBAR1 2
  22. #define VMD_MEMBAR2 4
  23. #define PCI_REG_VMCAP 0x40
  24. #define BUS_RESTRICT_CAP(vmcap) (vmcap & 0x1)
  25. #define PCI_REG_VMCONFIG 0x44
  26. #define BUS_RESTRICT_CFG(vmcfg) ((vmcfg >> 8) & 0x3)
  27. #define PCI_REG_VMLOCK 0x70
  28. #define MB2_SHADOW_EN(vmlock) (vmlock & 0x2)
  29. #define MB2_SHADOW_OFFSET 0x2000
  30. #define MB2_SHADOW_SIZE 16
  31. enum vmd_features {
  32. /*
  33. * Device may contain registers which hint the physical location of the
  34. * membars, in order to allow proper address translation during
  35. * resource assignment to enable guest virtualization
  36. */
  37. VMD_FEAT_HAS_MEMBAR_SHADOW = (1 << 0),
  38. /*
  39. * Device may provide root port configuration information which limits
  40. * bus numbering
  41. */
  42. VMD_FEAT_HAS_BUS_RESTRICTIONS = (1 << 1),
  43. /*
  44. * Device contains physical location shadow registers in
  45. * vendor-specific capability space
  46. */
  47. VMD_FEAT_HAS_MEMBAR_SHADOW_VSCAP = (1 << 2),
  48. };
  49. /*
  50. * Lock for manipulating VMD IRQ lists.
  51. */
  52. static DEFINE_RAW_SPINLOCK(list_lock);
  53. /**
  54. * struct vmd_irq - private data to map driver IRQ to the VMD shared vector
  55. * @node: list item for parent traversal.
  56. * @irq: back pointer to parent.
  57. * @enabled: true if driver enabled IRQ
  58. * @virq: the virtual IRQ value provided to the requesting driver.
  59. *
  60. * Every MSI/MSI-X IRQ requested for a device in a VMD domain will be mapped to
  61. * a VMD IRQ using this structure.
  62. */
  63. struct vmd_irq {
  64. struct list_head node;
  65. struct vmd_irq_list *irq;
  66. bool enabled;
  67. unsigned int virq;
  68. };
  69. /**
  70. * struct vmd_irq_list - list of driver requested IRQs mapping to a VMD vector
  71. * @irq_list: the list of irq's the VMD one demuxes to.
  72. * @srcu: SRCU struct for local synchronization.
  73. * @count: number of child IRQs assigned to this vector; used to track
  74. * sharing.
  75. */
  76. struct vmd_irq_list {
  77. struct list_head irq_list;
  78. struct srcu_struct srcu;
  79. unsigned int count;
  80. };
  81. struct vmd_dev {
  82. struct pci_dev *dev;
  83. spinlock_t cfg_lock;
  84. char __iomem *cfgbar;
  85. int msix_count;
  86. struct vmd_irq_list *irqs;
  87. struct pci_sysdata sysdata;
  88. struct resource resources[3];
  89. struct irq_domain *irq_domain;
  90. struct pci_bus *bus;
  91. u8 busn_start;
  92. };
  93. static inline struct vmd_dev *vmd_from_bus(struct pci_bus *bus)
  94. {
  95. return container_of(bus->sysdata, struct vmd_dev, sysdata);
  96. }
  97. static inline unsigned int index_from_irqs(struct vmd_dev *vmd,
  98. struct vmd_irq_list *irqs)
  99. {
  100. return irqs - vmd->irqs;
  101. }
  102. /*
  103. * Drivers managing a device in a VMD domain allocate their own IRQs as before,
  104. * but the MSI entry for the hardware it's driving will be programmed with a
  105. * destination ID for the VMD MSI-X table. The VMD muxes interrupts in its
  106. * domain into one of its own, and the VMD driver de-muxes these for the
  107. * handlers sharing that VMD IRQ. The vmd irq_domain provides the operations
  108. * and irq_chip to set this up.
  109. */
  110. static void vmd_compose_msi_msg(struct irq_data *data, struct msi_msg *msg)
  111. {
  112. struct vmd_irq *vmdirq = data->chip_data;
  113. struct vmd_irq_list *irq = vmdirq->irq;
  114. struct vmd_dev *vmd = irq_data_get_irq_handler_data(data);
  115. msg->address_hi = MSI_ADDR_BASE_HI;
  116. msg->address_lo = MSI_ADDR_BASE_LO |
  117. MSI_ADDR_DEST_ID(index_from_irqs(vmd, irq));
  118. msg->data = 0;
  119. }
  120. /*
  121. * We rely on MSI_FLAG_USE_DEF_CHIP_OPS to set the IRQ mask/unmask ops.
  122. */
  123. static void vmd_irq_enable(struct irq_data *data)
  124. {
  125. struct vmd_irq *vmdirq = data->chip_data;
  126. unsigned long flags;
  127. raw_spin_lock_irqsave(&list_lock, flags);
  128. WARN_ON(vmdirq->enabled);
  129. list_add_tail_rcu(&vmdirq->node, &vmdirq->irq->irq_list);
  130. vmdirq->enabled = true;
  131. raw_spin_unlock_irqrestore(&list_lock, flags);
  132. data->chip->irq_unmask(data);
  133. }
  134. static void vmd_irq_disable(struct irq_data *data)
  135. {
  136. struct vmd_irq *vmdirq = data->chip_data;
  137. unsigned long flags;
  138. data->chip->irq_mask(data);
  139. raw_spin_lock_irqsave(&list_lock, flags);
  140. if (vmdirq->enabled) {
  141. list_del_rcu(&vmdirq->node);
  142. vmdirq->enabled = false;
  143. }
  144. raw_spin_unlock_irqrestore(&list_lock, flags);
  145. }
  146. /*
  147. * XXX: Stubbed until we develop acceptable way to not create conflicts with
  148. * other devices sharing the same vector.
  149. */
  150. static int vmd_irq_set_affinity(struct irq_data *data,
  151. const struct cpumask *dest, bool force)
  152. {
  153. return -EINVAL;
  154. }
  155. static struct irq_chip vmd_msi_controller = {
  156. .name = "VMD-MSI",
  157. .irq_enable = vmd_irq_enable,
  158. .irq_disable = vmd_irq_disable,
  159. .irq_compose_msi_msg = vmd_compose_msi_msg,
  160. .irq_set_affinity = vmd_irq_set_affinity,
  161. };
  162. static irq_hw_number_t vmd_get_hwirq(struct msi_domain_info *info,
  163. msi_alloc_info_t *arg)
  164. {
  165. return 0;
  166. }
  167. /*
  168. * XXX: We can be even smarter selecting the best IRQ once we solve the
  169. * affinity problem.
  170. */
  171. static struct vmd_irq_list *vmd_next_irq(struct vmd_dev *vmd, struct msi_desc *desc)
  172. {
  173. int i, best = 1;
  174. unsigned long flags;
  175. if (vmd->msix_count == 1)
  176. return &vmd->irqs[0];
  177. /*
  178. * White list for fast-interrupt handlers. All others will share the
  179. * "slow" interrupt vector.
  180. */
  181. switch (msi_desc_to_pci_dev(desc)->class) {
  182. case PCI_CLASS_STORAGE_EXPRESS:
  183. break;
  184. default:
  185. return &vmd->irqs[0];
  186. }
  187. raw_spin_lock_irqsave(&list_lock, flags);
  188. for (i = 1; i < vmd->msix_count; i++)
  189. if (vmd->irqs[i].count < vmd->irqs[best].count)
  190. best = i;
  191. vmd->irqs[best].count++;
  192. raw_spin_unlock_irqrestore(&list_lock, flags);
  193. return &vmd->irqs[best];
  194. }
  195. static int vmd_msi_init(struct irq_domain *domain, struct msi_domain_info *info,
  196. unsigned int virq, irq_hw_number_t hwirq,
  197. msi_alloc_info_t *arg)
  198. {
  199. struct msi_desc *desc = arg->desc;
  200. struct vmd_dev *vmd = vmd_from_bus(msi_desc_to_pci_dev(desc)->bus);
  201. struct vmd_irq *vmdirq = kzalloc(sizeof(*vmdirq), GFP_KERNEL);
  202. unsigned int index, vector;
  203. if (!vmdirq)
  204. return -ENOMEM;
  205. INIT_LIST_HEAD(&vmdirq->node);
  206. vmdirq->irq = vmd_next_irq(vmd, desc);
  207. vmdirq->virq = virq;
  208. index = index_from_irqs(vmd, vmdirq->irq);
  209. vector = pci_irq_vector(vmd->dev, index);
  210. irq_domain_set_info(domain, virq, vector, info->chip, vmdirq,
  211. handle_untracked_irq, vmd, NULL);
  212. return 0;
  213. }
  214. static void vmd_msi_free(struct irq_domain *domain,
  215. struct msi_domain_info *info, unsigned int virq)
  216. {
  217. struct vmd_irq *vmdirq = irq_get_chip_data(virq);
  218. unsigned long flags;
  219. synchronize_srcu(&vmdirq->irq->srcu);
  220. /* XXX: Potential optimization to rebalance */
  221. raw_spin_lock_irqsave(&list_lock, flags);
  222. vmdirq->irq->count--;
  223. raw_spin_unlock_irqrestore(&list_lock, flags);
  224. kfree(vmdirq);
  225. }
  226. static int vmd_msi_prepare(struct irq_domain *domain, struct device *dev,
  227. int nvec, msi_alloc_info_t *arg)
  228. {
  229. struct pci_dev *pdev = to_pci_dev(dev);
  230. struct vmd_dev *vmd = vmd_from_bus(pdev->bus);
  231. if (nvec > vmd->msix_count)
  232. return vmd->msix_count;
  233. memset(arg, 0, sizeof(*arg));
  234. return 0;
  235. }
  236. static void vmd_set_desc(msi_alloc_info_t *arg, struct msi_desc *desc)
  237. {
  238. arg->desc = desc;
  239. }
  240. static struct msi_domain_ops vmd_msi_domain_ops = {
  241. .get_hwirq = vmd_get_hwirq,
  242. .msi_init = vmd_msi_init,
  243. .msi_free = vmd_msi_free,
  244. .msi_prepare = vmd_msi_prepare,
  245. .set_desc = vmd_set_desc,
  246. };
  247. static struct msi_domain_info vmd_msi_domain_info = {
  248. .flags = MSI_FLAG_USE_DEF_DOM_OPS | MSI_FLAG_USE_DEF_CHIP_OPS |
  249. MSI_FLAG_PCI_MSIX,
  250. .ops = &vmd_msi_domain_ops,
  251. .chip = &vmd_msi_controller,
  252. };
  253. static int vmd_create_irq_domain(struct vmd_dev *vmd)
  254. {
  255. struct fwnode_handle *fn;
  256. fn = irq_domain_alloc_named_id_fwnode("VMD-MSI", vmd->sysdata.domain);
  257. if (!fn)
  258. return -ENODEV;
  259. vmd->irq_domain = pci_msi_create_irq_domain(fn, &vmd_msi_domain_info, NULL);
  260. if (!vmd->irq_domain) {
  261. irq_domain_free_fwnode(fn);
  262. return -ENODEV;
  263. }
  264. return 0;
  265. }
  266. static void vmd_remove_irq_domain(struct vmd_dev *vmd)
  267. {
  268. if (vmd->irq_domain) {
  269. struct fwnode_handle *fn = vmd->irq_domain->fwnode;
  270. irq_domain_remove(vmd->irq_domain);
  271. irq_domain_free_fwnode(fn);
  272. }
  273. }
  274. static char __iomem *vmd_cfg_addr(struct vmd_dev *vmd, struct pci_bus *bus,
  275. unsigned int devfn, int reg, int len)
  276. {
  277. char __iomem *addr = vmd->cfgbar +
  278. ((bus->number - vmd->busn_start) << 20) +
  279. (devfn << 12) + reg;
  280. if ((addr - vmd->cfgbar) + len >=
  281. resource_size(&vmd->dev->resource[VMD_CFGBAR]))
  282. return NULL;
  283. return addr;
  284. }
  285. /*
  286. * CPU may deadlock if config space is not serialized on some versions of this
  287. * hardware, so all config space access is done under a spinlock.
  288. */
  289. static int vmd_pci_read(struct pci_bus *bus, unsigned int devfn, int reg,
  290. int len, u32 *value)
  291. {
  292. struct vmd_dev *vmd = vmd_from_bus(bus);
  293. char __iomem *addr = vmd_cfg_addr(vmd, bus, devfn, reg, len);
  294. unsigned long flags;
  295. int ret = 0;
  296. if (!addr)
  297. return -EFAULT;
  298. spin_lock_irqsave(&vmd->cfg_lock, flags);
  299. switch (len) {
  300. case 1:
  301. *value = readb(addr);
  302. break;
  303. case 2:
  304. *value = readw(addr);
  305. break;
  306. case 4:
  307. *value = readl(addr);
  308. break;
  309. default:
  310. ret = -EINVAL;
  311. break;
  312. }
  313. spin_unlock_irqrestore(&vmd->cfg_lock, flags);
  314. return ret;
  315. }
  316. /*
  317. * VMD h/w converts non-posted config writes to posted memory writes. The
  318. * read-back in this function forces the completion so it returns only after
  319. * the config space was written, as expected.
  320. */
  321. static int vmd_pci_write(struct pci_bus *bus, unsigned int devfn, int reg,
  322. int len, u32 value)
  323. {
  324. struct vmd_dev *vmd = vmd_from_bus(bus);
  325. char __iomem *addr = vmd_cfg_addr(vmd, bus, devfn, reg, len);
  326. unsigned long flags;
  327. int ret = 0;
  328. if (!addr)
  329. return -EFAULT;
  330. spin_lock_irqsave(&vmd->cfg_lock, flags);
  331. switch (len) {
  332. case 1:
  333. writeb(value, addr);
  334. readb(addr);
  335. break;
  336. case 2:
  337. writew(value, addr);
  338. readw(addr);
  339. break;
  340. case 4:
  341. writel(value, addr);
  342. readl(addr);
  343. break;
  344. default:
  345. ret = -EINVAL;
  346. break;
  347. }
  348. spin_unlock_irqrestore(&vmd->cfg_lock, flags);
  349. return ret;
  350. }
  351. static struct pci_ops vmd_ops = {
  352. .read = vmd_pci_read,
  353. .write = vmd_pci_write,
  354. };
  355. static void vmd_attach_resources(struct vmd_dev *vmd)
  356. {
  357. vmd->dev->resource[VMD_MEMBAR1].child = &vmd->resources[1];
  358. vmd->dev->resource[VMD_MEMBAR2].child = &vmd->resources[2];
  359. }
  360. static void vmd_detach_resources(struct vmd_dev *vmd)
  361. {
  362. vmd->dev->resource[VMD_MEMBAR1].child = NULL;
  363. vmd->dev->resource[VMD_MEMBAR2].child = NULL;
  364. }
  365. /*
  366. * VMD domains start at 0x10000 to not clash with ACPI _SEG domains.
  367. * Per ACPI r6.0, sec 6.5.6, _SEG returns an integer, of which the lower
  368. * 16 bits are the PCI Segment Group (domain) number. Other bits are
  369. * currently reserved.
  370. */
  371. static int vmd_find_free_domain(void)
  372. {
  373. int domain = 0xffff;
  374. struct pci_bus *bus = NULL;
  375. while ((bus = pci_find_next_bus(bus)) != NULL)
  376. domain = max_t(int, domain, pci_domain_nr(bus));
  377. return domain + 1;
  378. }
  379. static int vmd_get_phys_offsets(struct vmd_dev *vmd, bool native_hint,
  380. resource_size_t *offset1,
  381. resource_size_t *offset2)
  382. {
  383. struct pci_dev *dev = vmd->dev;
  384. u64 phys1, phys2;
  385. if (native_hint) {
  386. u32 vmlock;
  387. int ret;
  388. ret = pci_read_config_dword(dev, PCI_REG_VMLOCK, &vmlock);
  389. if (ret || vmlock == ~0)
  390. return -ENODEV;
  391. if (MB2_SHADOW_EN(vmlock)) {
  392. void __iomem *membar2;
  393. membar2 = pci_iomap(dev, VMD_MEMBAR2, 0);
  394. if (!membar2)
  395. return -ENOMEM;
  396. phys1 = readq(membar2 + MB2_SHADOW_OFFSET);
  397. phys2 = readq(membar2 + MB2_SHADOW_OFFSET + 8);
  398. pci_iounmap(dev, membar2);
  399. } else
  400. return 0;
  401. } else {
  402. /* Hypervisor-Emulated Vendor-Specific Capability */
  403. int pos = pci_find_capability(dev, PCI_CAP_ID_VNDR);
  404. u32 reg, regu;
  405. pci_read_config_dword(dev, pos + 4, &reg);
  406. /* "SHDW" */
  407. if (pos && reg == 0x53484457) {
  408. pci_read_config_dword(dev, pos + 8, &reg);
  409. pci_read_config_dword(dev, pos + 12, &regu);
  410. phys1 = (u64) regu << 32 | reg;
  411. pci_read_config_dword(dev, pos + 16, &reg);
  412. pci_read_config_dword(dev, pos + 20, &regu);
  413. phys2 = (u64) regu << 32 | reg;
  414. } else
  415. return 0;
  416. }
  417. *offset1 = dev->resource[VMD_MEMBAR1].start -
  418. (phys1 & PCI_BASE_ADDRESS_MEM_MASK);
  419. *offset2 = dev->resource[VMD_MEMBAR2].start -
  420. (phys2 & PCI_BASE_ADDRESS_MEM_MASK);
  421. return 0;
  422. }
  423. static int vmd_get_bus_number_start(struct vmd_dev *vmd)
  424. {
  425. struct pci_dev *dev = vmd->dev;
  426. u16 reg;
  427. pci_read_config_word(dev, PCI_REG_VMCAP, &reg);
  428. if (BUS_RESTRICT_CAP(reg)) {
  429. pci_read_config_word(dev, PCI_REG_VMCONFIG, &reg);
  430. switch (BUS_RESTRICT_CFG(reg)) {
  431. case 0:
  432. vmd->busn_start = 0;
  433. break;
  434. case 1:
  435. vmd->busn_start = 128;
  436. break;
  437. case 2:
  438. vmd->busn_start = 224;
  439. break;
  440. default:
  441. pci_err(dev, "Unknown Bus Offset Setting (%d)\n",
  442. BUS_RESTRICT_CFG(reg));
  443. return -ENODEV;
  444. }
  445. }
  446. return 0;
  447. }
  448. static irqreturn_t vmd_irq(int irq, void *data)
  449. {
  450. struct vmd_irq_list *irqs = data;
  451. struct vmd_irq *vmdirq;
  452. int idx;
  453. idx = srcu_read_lock(&irqs->srcu);
  454. list_for_each_entry_rcu(vmdirq, &irqs->irq_list, node)
  455. generic_handle_irq(vmdirq->virq);
  456. srcu_read_unlock(&irqs->srcu, idx);
  457. return IRQ_HANDLED;
  458. }
  459. static int vmd_alloc_irqs(struct vmd_dev *vmd)
  460. {
  461. struct pci_dev *dev = vmd->dev;
  462. int i, err;
  463. vmd->msix_count = pci_msix_vec_count(dev);
  464. if (vmd->msix_count < 0)
  465. return -ENODEV;
  466. vmd->msix_count = pci_alloc_irq_vectors(dev, 1, vmd->msix_count,
  467. PCI_IRQ_MSIX);
  468. if (vmd->msix_count < 0)
  469. return vmd->msix_count;
  470. vmd->irqs = devm_kcalloc(&dev->dev, vmd->msix_count, sizeof(*vmd->irqs),
  471. GFP_KERNEL);
  472. if (!vmd->irqs)
  473. return -ENOMEM;
  474. for (i = 0; i < vmd->msix_count; i++) {
  475. err = init_srcu_struct(&vmd->irqs[i].srcu);
  476. if (err)
  477. return err;
  478. INIT_LIST_HEAD(&vmd->irqs[i].irq_list);
  479. err = devm_request_irq(&dev->dev, pci_irq_vector(dev, i),
  480. vmd_irq, IRQF_NO_THREAD,
  481. "vmd", &vmd->irqs[i]);
  482. if (err)
  483. return err;
  484. }
  485. return 0;
  486. }
  487. static int vmd_enable_domain(struct vmd_dev *vmd, unsigned long features)
  488. {
  489. struct pci_sysdata *sd = &vmd->sysdata;
  490. struct resource *res;
  491. u32 upper_bits;
  492. unsigned long flags;
  493. LIST_HEAD(resources);
  494. resource_size_t offset[2] = {0};
  495. resource_size_t membar2_offset = 0x2000;
  496. struct pci_bus *child;
  497. int ret;
  498. /*
  499. * Shadow registers may exist in certain VMD device ids which allow
  500. * guests to correctly assign host physical addresses to the root ports
  501. * and child devices. These registers will either return the host value
  502. * or 0, depending on an enable bit in the VMD device.
  503. */
  504. if (features & VMD_FEAT_HAS_MEMBAR_SHADOW) {
  505. membar2_offset = MB2_SHADOW_OFFSET + MB2_SHADOW_SIZE;
  506. ret = vmd_get_phys_offsets(vmd, true, &offset[0], &offset[1]);
  507. if (ret)
  508. return ret;
  509. } else if (features & VMD_FEAT_HAS_MEMBAR_SHADOW_VSCAP) {
  510. ret = vmd_get_phys_offsets(vmd, false, &offset[0], &offset[1]);
  511. if (ret)
  512. return ret;
  513. }
  514. /*
  515. * Certain VMD devices may have a root port configuration option which
  516. * limits the bus range to between 0-127, 128-255, or 224-255
  517. */
  518. if (features & VMD_FEAT_HAS_BUS_RESTRICTIONS) {
  519. ret = vmd_get_bus_number_start(vmd);
  520. if (ret)
  521. return ret;
  522. }
  523. res = &vmd->dev->resource[VMD_CFGBAR];
  524. vmd->resources[0] = (struct resource) {
  525. .name = "VMD CFGBAR",
  526. .start = vmd->busn_start,
  527. .end = vmd->busn_start + (resource_size(res) >> 20) - 1,
  528. .flags = IORESOURCE_BUS | IORESOURCE_PCI_FIXED,
  529. };
  530. /*
  531. * If the window is below 4GB, clear IORESOURCE_MEM_64 so we can
  532. * put 32-bit resources in the window.
  533. *
  534. * There's no hardware reason why a 64-bit window *couldn't*
  535. * contain a 32-bit resource, but pbus_size_mem() computes the
  536. * bridge window size assuming a 64-bit window will contain no
  537. * 32-bit resources. __pci_assign_resource() enforces that
  538. * artificial restriction to make sure everything will fit.
  539. *
  540. * The only way we could use a 64-bit non-prefetchable MEMBAR is
  541. * if its address is <4GB so that we can convert it to a 32-bit
  542. * resource. To be visible to the host OS, all VMD endpoints must
  543. * be initially configured by platform BIOS, which includes setting
  544. * up these resources. We can assume the device is configured
  545. * according to the platform needs.
  546. */
  547. res = &vmd->dev->resource[VMD_MEMBAR1];
  548. upper_bits = upper_32_bits(res->end);
  549. flags = res->flags & ~IORESOURCE_SIZEALIGN;
  550. if (!upper_bits)
  551. flags &= ~IORESOURCE_MEM_64;
  552. vmd->resources[1] = (struct resource) {
  553. .name = "VMD MEMBAR1",
  554. .start = res->start,
  555. .end = res->end,
  556. .flags = flags,
  557. .parent = res,
  558. };
  559. res = &vmd->dev->resource[VMD_MEMBAR2];
  560. upper_bits = upper_32_bits(res->end);
  561. flags = res->flags & ~IORESOURCE_SIZEALIGN;
  562. if (!upper_bits)
  563. flags &= ~IORESOURCE_MEM_64;
  564. vmd->resources[2] = (struct resource) {
  565. .name = "VMD MEMBAR2",
  566. .start = res->start + membar2_offset,
  567. .end = res->end,
  568. .flags = flags,
  569. .parent = res,
  570. };
  571. sd->vmd_dev = vmd->dev;
  572. sd->domain = vmd_find_free_domain();
  573. if (sd->domain < 0)
  574. return sd->domain;
  575. sd->node = pcibus_to_node(vmd->dev->bus);
  576. ret = vmd_create_irq_domain(vmd);
  577. if (ret)
  578. return ret;
  579. /*
  580. * Override the irq domain bus token so the domain can be distinguished
  581. * from a regular PCI/MSI domain.
  582. */
  583. irq_domain_update_bus_token(vmd->irq_domain, DOMAIN_BUS_VMD_MSI);
  584. pci_add_resource(&resources, &vmd->resources[0]);
  585. pci_add_resource_offset(&resources, &vmd->resources[1], offset[0]);
  586. pci_add_resource_offset(&resources, &vmd->resources[2], offset[1]);
  587. vmd->bus = pci_create_root_bus(&vmd->dev->dev, vmd->busn_start,
  588. &vmd_ops, sd, &resources);
  589. if (!vmd->bus) {
  590. pci_free_resource_list(&resources);
  591. vmd_remove_irq_domain(vmd);
  592. return -ENODEV;
  593. }
  594. vmd_attach_resources(vmd);
  595. if (vmd->irq_domain)
  596. dev_set_msi_domain(&vmd->bus->dev, vmd->irq_domain);
  597. pci_scan_child_bus(vmd->bus);
  598. pci_assign_unassigned_bus_resources(vmd->bus);
  599. /*
  600. * VMD root buses are virtual and don't return true on pci_is_pcie()
  601. * and will fail pcie_bus_configure_settings() early. It can instead be
  602. * run on each of the real root ports.
  603. */
  604. list_for_each_entry(child, &vmd->bus->children, node)
  605. pcie_bus_configure_settings(child);
  606. pci_bus_add_devices(vmd->bus);
  607. WARN(sysfs_create_link(&vmd->dev->dev.kobj, &vmd->bus->dev.kobj,
  608. "domain"), "Can't create symlink to domain\n");
  609. return 0;
  610. }
  611. static int vmd_probe(struct pci_dev *dev, const struct pci_device_id *id)
  612. {
  613. struct vmd_dev *vmd;
  614. int err;
  615. if (resource_size(&dev->resource[VMD_CFGBAR]) < (1 << 20))
  616. return -ENOMEM;
  617. vmd = devm_kzalloc(&dev->dev, sizeof(*vmd), GFP_KERNEL);
  618. if (!vmd)
  619. return -ENOMEM;
  620. vmd->dev = dev;
  621. err = pcim_enable_device(dev);
  622. if (err < 0)
  623. return err;
  624. vmd->cfgbar = pcim_iomap(dev, VMD_CFGBAR, 0);
  625. if (!vmd->cfgbar)
  626. return -ENOMEM;
  627. pci_set_master(dev);
  628. if (dma_set_mask_and_coherent(&dev->dev, DMA_BIT_MASK(64)) &&
  629. dma_set_mask_and_coherent(&dev->dev, DMA_BIT_MASK(32)))
  630. return -ENODEV;
  631. err = vmd_alloc_irqs(vmd);
  632. if (err)
  633. return err;
  634. spin_lock_init(&vmd->cfg_lock);
  635. pci_set_drvdata(dev, vmd);
  636. err = vmd_enable_domain(vmd, (unsigned long) id->driver_data);
  637. if (err)
  638. return err;
  639. dev_info(&vmd->dev->dev, "Bound to PCI domain %04x\n",
  640. vmd->sysdata.domain);
  641. return 0;
  642. }
  643. static void vmd_cleanup_srcu(struct vmd_dev *vmd)
  644. {
  645. int i;
  646. for (i = 0; i < vmd->msix_count; i++)
  647. cleanup_srcu_struct(&vmd->irqs[i].srcu);
  648. }
  649. static void vmd_remove(struct pci_dev *dev)
  650. {
  651. struct vmd_dev *vmd = pci_get_drvdata(dev);
  652. sysfs_remove_link(&vmd->dev->dev.kobj, "domain");
  653. pci_stop_root_bus(vmd->bus);
  654. pci_remove_root_bus(vmd->bus);
  655. vmd_cleanup_srcu(vmd);
  656. vmd_detach_resources(vmd);
  657. vmd_remove_irq_domain(vmd);
  658. }
  659. #ifdef CONFIG_PM_SLEEP
  660. static int vmd_suspend(struct device *dev)
  661. {
  662. struct pci_dev *pdev = to_pci_dev(dev);
  663. struct vmd_dev *vmd = pci_get_drvdata(pdev);
  664. int i;
  665. for (i = 0; i < vmd->msix_count; i++)
  666. devm_free_irq(dev, pci_irq_vector(pdev, i), &vmd->irqs[i]);
  667. return 0;
  668. }
  669. static int vmd_resume(struct device *dev)
  670. {
  671. struct pci_dev *pdev = to_pci_dev(dev);
  672. struct vmd_dev *vmd = pci_get_drvdata(pdev);
  673. int err, i;
  674. for (i = 0; i < vmd->msix_count; i++) {
  675. err = devm_request_irq(dev, pci_irq_vector(pdev, i),
  676. vmd_irq, IRQF_NO_THREAD,
  677. "vmd", &vmd->irqs[i]);
  678. if (err)
  679. return err;
  680. }
  681. return 0;
  682. }
  683. #endif
  684. static SIMPLE_DEV_PM_OPS(vmd_dev_pm_ops, vmd_suspend, vmd_resume);
  685. static const struct pci_device_id vmd_ids[] = {
  686. {PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_VMD_201D),
  687. .driver_data = VMD_FEAT_HAS_MEMBAR_SHADOW_VSCAP,},
  688. {PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_VMD_28C0),
  689. .driver_data = VMD_FEAT_HAS_MEMBAR_SHADOW |
  690. VMD_FEAT_HAS_BUS_RESTRICTIONS,},
  691. {PCI_DEVICE(PCI_VENDOR_ID_INTEL, 0x467f),
  692. .driver_data = VMD_FEAT_HAS_MEMBAR_SHADOW_VSCAP |
  693. VMD_FEAT_HAS_BUS_RESTRICTIONS,},
  694. {PCI_DEVICE(PCI_VENDOR_ID_INTEL, 0x4c3d),
  695. .driver_data = VMD_FEAT_HAS_MEMBAR_SHADOW_VSCAP |
  696. VMD_FEAT_HAS_BUS_RESTRICTIONS,},
  697. {PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_VMD_9A0B),
  698. .driver_data = VMD_FEAT_HAS_MEMBAR_SHADOW_VSCAP |
  699. VMD_FEAT_HAS_BUS_RESTRICTIONS,},
  700. {0,}
  701. };
  702. MODULE_DEVICE_TABLE(pci, vmd_ids);
  703. static struct pci_driver vmd_drv = {
  704. .name = "vmd",
  705. .id_table = vmd_ids,
  706. .probe = vmd_probe,
  707. .remove = vmd_remove,
  708. .driver = {
  709. .pm = &vmd_dev_pm_ops,
  710. },
  711. };
  712. module_pci_driver(vmd_drv);
  713. MODULE_AUTHOR("Intel Corporation");
  714. MODULE_LICENSE("GPL v2");
  715. MODULE_VERSION("0.6");