pcie-mediatek.c 32 KB

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  1. // SPDX-License-Identifier: GPL-2.0
  2. /*
  3. * MediaTek PCIe host controller driver.
  4. *
  5. * Copyright (c) 2017 MediaTek Inc.
  6. * Author: Ryder Lee <ryder.lee@mediatek.com>
  7. * Honghui Zhang <honghui.zhang@mediatek.com>
  8. */
  9. #include <linux/clk.h>
  10. #include <linux/delay.h>
  11. #include <linux/iopoll.h>
  12. #include <linux/irq.h>
  13. #include <linux/irqchip/chained_irq.h>
  14. #include <linux/irqdomain.h>
  15. #include <linux/kernel.h>
  16. #include <linux/msi.h>
  17. #include <linux/module.h>
  18. #include <linux/of_address.h>
  19. #include <linux/of_pci.h>
  20. #include <linux/of_platform.h>
  21. #include <linux/pci.h>
  22. #include <linux/phy/phy.h>
  23. #include <linux/platform_device.h>
  24. #include <linux/pm_runtime.h>
  25. #include <linux/reset.h>
  26. #include "../pci.h"
  27. /* PCIe shared registers */
  28. #define PCIE_SYS_CFG 0x00
  29. #define PCIE_INT_ENABLE 0x0c
  30. #define PCIE_CFG_ADDR 0x20
  31. #define PCIE_CFG_DATA 0x24
  32. /* PCIe per port registers */
  33. #define PCIE_BAR0_SETUP 0x10
  34. #define PCIE_CLASS 0x34
  35. #define PCIE_LINK_STATUS 0x50
  36. #define PCIE_PORT_INT_EN(x) BIT(20 + (x))
  37. #define PCIE_PORT_PERST(x) BIT(1 + (x))
  38. #define PCIE_PORT_LINKUP BIT(0)
  39. #define PCIE_BAR_MAP_MAX GENMASK(31, 16)
  40. #define PCIE_BAR_ENABLE BIT(0)
  41. #define PCIE_REVISION_ID BIT(0)
  42. #define PCIE_CLASS_CODE (0x60400 << 8)
  43. #define PCIE_CONF_REG(regn) (((regn) & GENMASK(7, 2)) | \
  44. ((((regn) >> 8) & GENMASK(3, 0)) << 24))
  45. #define PCIE_CONF_FUN(fun) (((fun) << 8) & GENMASK(10, 8))
  46. #define PCIE_CONF_DEV(dev) (((dev) << 11) & GENMASK(15, 11))
  47. #define PCIE_CONF_BUS(bus) (((bus) << 16) & GENMASK(23, 16))
  48. #define PCIE_CONF_ADDR(regn, fun, dev, bus) \
  49. (PCIE_CONF_REG(regn) | PCIE_CONF_FUN(fun) | \
  50. PCIE_CONF_DEV(dev) | PCIE_CONF_BUS(bus))
  51. /* MediaTek specific configuration registers */
  52. #define PCIE_FTS_NUM 0x70c
  53. #define PCIE_FTS_NUM_MASK GENMASK(15, 8)
  54. #define PCIE_FTS_NUM_L0(x) ((x) & 0xff << 8)
  55. #define PCIE_FC_CREDIT 0x73c
  56. #define PCIE_FC_CREDIT_MASK (GENMASK(31, 31) | GENMASK(28, 16))
  57. #define PCIE_FC_CREDIT_VAL(x) ((x) << 16)
  58. /* PCIe V2 share registers */
  59. #define PCIE_SYS_CFG_V2 0x0
  60. #define PCIE_CSR_LTSSM_EN(x) BIT(0 + (x) * 8)
  61. #define PCIE_CSR_ASPM_L1_EN(x) BIT(1 + (x) * 8)
  62. /* PCIe V2 per-port registers */
  63. #define PCIE_MSI_VECTOR 0x0c0
  64. #define PCIE_CONF_VEND_ID 0x100
  65. #define PCIE_CONF_DEVICE_ID 0x102
  66. #define PCIE_CONF_CLASS_ID 0x106
  67. #define PCIE_INT_MASK 0x420
  68. #define INTX_MASK GENMASK(19, 16)
  69. #define INTX_SHIFT 16
  70. #define PCIE_INT_STATUS 0x424
  71. #define MSI_STATUS BIT(23)
  72. #define PCIE_IMSI_STATUS 0x42c
  73. #define PCIE_IMSI_ADDR 0x430
  74. #define MSI_MASK BIT(23)
  75. #define MTK_MSI_IRQS_NUM 32
  76. #define PCIE_AHB_TRANS_BASE0_L 0x438
  77. #define PCIE_AHB_TRANS_BASE0_H 0x43c
  78. #define AHB2PCIE_SIZE(x) ((x) & GENMASK(4, 0))
  79. #define PCIE_AXI_WINDOW0 0x448
  80. #define WIN_ENABLE BIT(7)
  81. /*
  82. * Define PCIe to AHB window size as 2^33 to support max 8GB address space
  83. * translate, support least 4GB DRAM size access from EP DMA(physical DRAM
  84. * start from 0x40000000).
  85. */
  86. #define PCIE2AHB_SIZE 0x21
  87. /* PCIe V2 configuration transaction header */
  88. #define PCIE_CFG_HEADER0 0x460
  89. #define PCIE_CFG_HEADER1 0x464
  90. #define PCIE_CFG_HEADER2 0x468
  91. #define PCIE_CFG_WDATA 0x470
  92. #define PCIE_APP_TLP_REQ 0x488
  93. #define PCIE_CFG_RDATA 0x48c
  94. #define APP_CFG_REQ BIT(0)
  95. #define APP_CPL_STATUS GENMASK(7, 5)
  96. #define CFG_WRRD_TYPE_0 4
  97. #define CFG_WR_FMT 2
  98. #define CFG_RD_FMT 0
  99. #define CFG_DW0_LENGTH(length) ((length) & GENMASK(9, 0))
  100. #define CFG_DW0_TYPE(type) (((type) << 24) & GENMASK(28, 24))
  101. #define CFG_DW0_FMT(fmt) (((fmt) << 29) & GENMASK(31, 29))
  102. #define CFG_DW2_REGN(regn) ((regn) & GENMASK(11, 2))
  103. #define CFG_DW2_FUN(fun) (((fun) << 16) & GENMASK(18, 16))
  104. #define CFG_DW2_DEV(dev) (((dev) << 19) & GENMASK(23, 19))
  105. #define CFG_DW2_BUS(bus) (((bus) << 24) & GENMASK(31, 24))
  106. #define CFG_HEADER_DW0(type, fmt) \
  107. (CFG_DW0_LENGTH(1) | CFG_DW0_TYPE(type) | CFG_DW0_FMT(fmt))
  108. #define CFG_HEADER_DW1(where, size) \
  109. (GENMASK(((size) - 1), 0) << ((where) & 0x3))
  110. #define CFG_HEADER_DW2(regn, fun, dev, bus) \
  111. (CFG_DW2_REGN(regn) | CFG_DW2_FUN(fun) | \
  112. CFG_DW2_DEV(dev) | CFG_DW2_BUS(bus))
  113. #define PCIE_RST_CTRL 0x510
  114. #define PCIE_PHY_RSTB BIT(0)
  115. #define PCIE_PIPE_SRSTB BIT(1)
  116. #define PCIE_MAC_SRSTB BIT(2)
  117. #define PCIE_CRSTB BIT(3)
  118. #define PCIE_PERSTB BIT(8)
  119. #define PCIE_LINKDOWN_RST_EN GENMASK(15, 13)
  120. #define PCIE_LINK_STATUS_V2 0x804
  121. #define PCIE_PORT_LINKUP_V2 BIT(10)
  122. struct mtk_pcie_port;
  123. /**
  124. * struct mtk_pcie_soc - differentiate between host generations
  125. * @need_fix_class_id: whether this host's class ID needed to be fixed or not
  126. * @need_fix_device_id: whether this host's device ID needed to be fixed or not
  127. * @device_id: device ID which this host need to be fixed
  128. * @ops: pointer to configuration access functions
  129. * @startup: pointer to controller setting functions
  130. * @setup_irq: pointer to initialize IRQ functions
  131. */
  132. struct mtk_pcie_soc {
  133. bool need_fix_class_id;
  134. bool need_fix_device_id;
  135. unsigned int device_id;
  136. struct pci_ops *ops;
  137. int (*startup)(struct mtk_pcie_port *port);
  138. int (*setup_irq)(struct mtk_pcie_port *port, struct device_node *node);
  139. };
  140. /**
  141. * struct mtk_pcie_port - PCIe port information
  142. * @base: IO mapped register base
  143. * @list: port list
  144. * @pcie: pointer to PCIe host info
  145. * @reset: pointer to port reset control
  146. * @sys_ck: pointer to transaction/data link layer clock
  147. * @ahb_ck: pointer to AHB slave interface operating clock for CSR access
  148. * and RC initiated MMIO access
  149. * @axi_ck: pointer to application layer MMIO channel operating clock
  150. * @aux_ck: pointer to pe2_mac_bridge and pe2_mac_core operating clock
  151. * when pcie_mac_ck/pcie_pipe_ck is turned off
  152. * @obff_ck: pointer to OBFF functional block operating clock
  153. * @pipe_ck: pointer to LTSSM and PHY/MAC layer operating clock
  154. * @phy: pointer to PHY control block
  155. * @slot: port slot
  156. * @irq: GIC irq
  157. * @irq_domain: legacy INTx IRQ domain
  158. * @inner_domain: inner IRQ domain
  159. * @msi_domain: MSI IRQ domain
  160. * @lock: protect the msi_irq_in_use bitmap
  161. * @msi_irq_in_use: bit map for assigned MSI IRQ
  162. */
  163. struct mtk_pcie_port {
  164. void __iomem *base;
  165. struct list_head list;
  166. struct mtk_pcie *pcie;
  167. struct reset_control *reset;
  168. struct clk *sys_ck;
  169. struct clk *ahb_ck;
  170. struct clk *axi_ck;
  171. struct clk *aux_ck;
  172. struct clk *obff_ck;
  173. struct clk *pipe_ck;
  174. struct phy *phy;
  175. u32 slot;
  176. int irq;
  177. struct irq_domain *irq_domain;
  178. struct irq_domain *inner_domain;
  179. struct irq_domain *msi_domain;
  180. struct mutex lock;
  181. DECLARE_BITMAP(msi_irq_in_use, MTK_MSI_IRQS_NUM);
  182. };
  183. /**
  184. * struct mtk_pcie - PCIe host information
  185. * @dev: pointer to PCIe device
  186. * @base: IO mapped register base
  187. * @free_ck: free-run reference clock
  188. * @mem: non-prefetchable memory resource
  189. * @ports: pointer to PCIe port information
  190. * @soc: pointer to SoC-dependent operations
  191. */
  192. struct mtk_pcie {
  193. struct device *dev;
  194. void __iomem *base;
  195. struct clk *free_ck;
  196. struct list_head ports;
  197. const struct mtk_pcie_soc *soc;
  198. };
  199. static void mtk_pcie_subsys_powerdown(struct mtk_pcie *pcie)
  200. {
  201. struct device *dev = pcie->dev;
  202. clk_disable_unprepare(pcie->free_ck);
  203. pm_runtime_put_sync(dev);
  204. pm_runtime_disable(dev);
  205. }
  206. static void mtk_pcie_port_free(struct mtk_pcie_port *port)
  207. {
  208. struct mtk_pcie *pcie = port->pcie;
  209. struct device *dev = pcie->dev;
  210. devm_iounmap(dev, port->base);
  211. list_del(&port->list);
  212. devm_kfree(dev, port);
  213. }
  214. static void mtk_pcie_put_resources(struct mtk_pcie *pcie)
  215. {
  216. struct mtk_pcie_port *port, *tmp;
  217. list_for_each_entry_safe(port, tmp, &pcie->ports, list) {
  218. phy_power_off(port->phy);
  219. phy_exit(port->phy);
  220. clk_disable_unprepare(port->pipe_ck);
  221. clk_disable_unprepare(port->obff_ck);
  222. clk_disable_unprepare(port->axi_ck);
  223. clk_disable_unprepare(port->aux_ck);
  224. clk_disable_unprepare(port->ahb_ck);
  225. clk_disable_unprepare(port->sys_ck);
  226. mtk_pcie_port_free(port);
  227. }
  228. mtk_pcie_subsys_powerdown(pcie);
  229. }
  230. static int mtk_pcie_check_cfg_cpld(struct mtk_pcie_port *port)
  231. {
  232. u32 val;
  233. int err;
  234. err = readl_poll_timeout_atomic(port->base + PCIE_APP_TLP_REQ, val,
  235. !(val & APP_CFG_REQ), 10,
  236. 100 * USEC_PER_MSEC);
  237. if (err)
  238. return PCIBIOS_SET_FAILED;
  239. if (readl(port->base + PCIE_APP_TLP_REQ) & APP_CPL_STATUS)
  240. return PCIBIOS_SET_FAILED;
  241. return PCIBIOS_SUCCESSFUL;
  242. }
  243. static int mtk_pcie_hw_rd_cfg(struct mtk_pcie_port *port, u32 bus, u32 devfn,
  244. int where, int size, u32 *val)
  245. {
  246. u32 tmp;
  247. /* Write PCIe configuration transaction header for Cfgrd */
  248. writel(CFG_HEADER_DW0(CFG_WRRD_TYPE_0, CFG_RD_FMT),
  249. port->base + PCIE_CFG_HEADER0);
  250. writel(CFG_HEADER_DW1(where, size), port->base + PCIE_CFG_HEADER1);
  251. writel(CFG_HEADER_DW2(where, PCI_FUNC(devfn), PCI_SLOT(devfn), bus),
  252. port->base + PCIE_CFG_HEADER2);
  253. /* Trigger h/w to transmit Cfgrd TLP */
  254. tmp = readl(port->base + PCIE_APP_TLP_REQ);
  255. tmp |= APP_CFG_REQ;
  256. writel(tmp, port->base + PCIE_APP_TLP_REQ);
  257. /* Check completion status */
  258. if (mtk_pcie_check_cfg_cpld(port))
  259. return PCIBIOS_SET_FAILED;
  260. /* Read cpld payload of Cfgrd */
  261. *val = readl(port->base + PCIE_CFG_RDATA);
  262. if (size == 1)
  263. *val = (*val >> (8 * (where & 3))) & 0xff;
  264. else if (size == 2)
  265. *val = (*val >> (8 * (where & 3))) & 0xffff;
  266. return PCIBIOS_SUCCESSFUL;
  267. }
  268. static int mtk_pcie_hw_wr_cfg(struct mtk_pcie_port *port, u32 bus, u32 devfn,
  269. int where, int size, u32 val)
  270. {
  271. /* Write PCIe configuration transaction header for Cfgwr */
  272. writel(CFG_HEADER_DW0(CFG_WRRD_TYPE_0, CFG_WR_FMT),
  273. port->base + PCIE_CFG_HEADER0);
  274. writel(CFG_HEADER_DW1(where, size), port->base + PCIE_CFG_HEADER1);
  275. writel(CFG_HEADER_DW2(where, PCI_FUNC(devfn), PCI_SLOT(devfn), bus),
  276. port->base + PCIE_CFG_HEADER2);
  277. /* Write Cfgwr data */
  278. val = val << 8 * (where & 3);
  279. writel(val, port->base + PCIE_CFG_WDATA);
  280. /* Trigger h/w to transmit Cfgwr TLP */
  281. val = readl(port->base + PCIE_APP_TLP_REQ);
  282. val |= APP_CFG_REQ;
  283. writel(val, port->base + PCIE_APP_TLP_REQ);
  284. /* Check completion status */
  285. return mtk_pcie_check_cfg_cpld(port);
  286. }
  287. static struct mtk_pcie_port *mtk_pcie_find_port(struct pci_bus *bus,
  288. unsigned int devfn)
  289. {
  290. struct mtk_pcie *pcie = bus->sysdata;
  291. struct mtk_pcie_port *port;
  292. struct pci_dev *dev = NULL;
  293. /*
  294. * Walk the bus hierarchy to get the devfn value
  295. * of the port in the root bus.
  296. */
  297. while (bus && bus->number) {
  298. dev = bus->self;
  299. bus = dev->bus;
  300. devfn = dev->devfn;
  301. }
  302. list_for_each_entry(port, &pcie->ports, list)
  303. if (port->slot == PCI_SLOT(devfn))
  304. return port;
  305. return NULL;
  306. }
  307. static int mtk_pcie_config_read(struct pci_bus *bus, unsigned int devfn,
  308. int where, int size, u32 *val)
  309. {
  310. struct mtk_pcie_port *port;
  311. u32 bn = bus->number;
  312. int ret;
  313. port = mtk_pcie_find_port(bus, devfn);
  314. if (!port) {
  315. *val = ~0;
  316. return PCIBIOS_DEVICE_NOT_FOUND;
  317. }
  318. ret = mtk_pcie_hw_rd_cfg(port, bn, devfn, where, size, val);
  319. if (ret)
  320. *val = ~0;
  321. return ret;
  322. }
  323. static int mtk_pcie_config_write(struct pci_bus *bus, unsigned int devfn,
  324. int where, int size, u32 val)
  325. {
  326. struct mtk_pcie_port *port;
  327. u32 bn = bus->number;
  328. port = mtk_pcie_find_port(bus, devfn);
  329. if (!port)
  330. return PCIBIOS_DEVICE_NOT_FOUND;
  331. return mtk_pcie_hw_wr_cfg(port, bn, devfn, where, size, val);
  332. }
  333. static struct pci_ops mtk_pcie_ops_v2 = {
  334. .read = mtk_pcie_config_read,
  335. .write = mtk_pcie_config_write,
  336. };
  337. static void mtk_compose_msi_msg(struct irq_data *data, struct msi_msg *msg)
  338. {
  339. struct mtk_pcie_port *port = irq_data_get_irq_chip_data(data);
  340. phys_addr_t addr;
  341. /* MT2712/MT7622 only support 32-bit MSI addresses */
  342. addr = virt_to_phys(port->base + PCIE_MSI_VECTOR);
  343. msg->address_hi = 0;
  344. msg->address_lo = lower_32_bits(addr);
  345. msg->data = data->hwirq;
  346. dev_dbg(port->pcie->dev, "msi#%d address_hi %#x address_lo %#x\n",
  347. (int)data->hwirq, msg->address_hi, msg->address_lo);
  348. }
  349. static int mtk_msi_set_affinity(struct irq_data *irq_data,
  350. const struct cpumask *mask, bool force)
  351. {
  352. return -EINVAL;
  353. }
  354. static void mtk_msi_ack_irq(struct irq_data *data)
  355. {
  356. struct mtk_pcie_port *port = irq_data_get_irq_chip_data(data);
  357. u32 hwirq = data->hwirq;
  358. writel(1 << hwirq, port->base + PCIE_IMSI_STATUS);
  359. }
  360. static struct irq_chip mtk_msi_bottom_irq_chip = {
  361. .name = "MTK MSI",
  362. .irq_compose_msi_msg = mtk_compose_msi_msg,
  363. .irq_set_affinity = mtk_msi_set_affinity,
  364. .irq_ack = mtk_msi_ack_irq,
  365. };
  366. static int mtk_pcie_irq_domain_alloc(struct irq_domain *domain, unsigned int virq,
  367. unsigned int nr_irqs, void *args)
  368. {
  369. struct mtk_pcie_port *port = domain->host_data;
  370. unsigned long bit;
  371. WARN_ON(nr_irqs != 1);
  372. mutex_lock(&port->lock);
  373. bit = find_first_zero_bit(port->msi_irq_in_use, MTK_MSI_IRQS_NUM);
  374. if (bit >= MTK_MSI_IRQS_NUM) {
  375. mutex_unlock(&port->lock);
  376. return -ENOSPC;
  377. }
  378. __set_bit(bit, port->msi_irq_in_use);
  379. mutex_unlock(&port->lock);
  380. irq_domain_set_info(domain, virq, bit, &mtk_msi_bottom_irq_chip,
  381. domain->host_data, handle_edge_irq,
  382. NULL, NULL);
  383. return 0;
  384. }
  385. static void mtk_pcie_irq_domain_free(struct irq_domain *domain,
  386. unsigned int virq, unsigned int nr_irqs)
  387. {
  388. struct irq_data *d = irq_domain_get_irq_data(domain, virq);
  389. struct mtk_pcie_port *port = irq_data_get_irq_chip_data(d);
  390. mutex_lock(&port->lock);
  391. if (!test_bit(d->hwirq, port->msi_irq_in_use))
  392. dev_err(port->pcie->dev, "trying to free unused MSI#%lu\n",
  393. d->hwirq);
  394. else
  395. __clear_bit(d->hwirq, port->msi_irq_in_use);
  396. mutex_unlock(&port->lock);
  397. irq_domain_free_irqs_parent(domain, virq, nr_irqs);
  398. }
  399. static const struct irq_domain_ops msi_domain_ops = {
  400. .alloc = mtk_pcie_irq_domain_alloc,
  401. .free = mtk_pcie_irq_domain_free,
  402. };
  403. static struct irq_chip mtk_msi_irq_chip = {
  404. .name = "MTK PCIe MSI",
  405. .irq_ack = irq_chip_ack_parent,
  406. .irq_mask = pci_msi_mask_irq,
  407. .irq_unmask = pci_msi_unmask_irq,
  408. };
  409. static struct msi_domain_info mtk_msi_domain_info = {
  410. .flags = (MSI_FLAG_USE_DEF_DOM_OPS | MSI_FLAG_USE_DEF_CHIP_OPS |
  411. MSI_FLAG_PCI_MSIX),
  412. .chip = &mtk_msi_irq_chip,
  413. };
  414. static int mtk_pcie_allocate_msi_domains(struct mtk_pcie_port *port)
  415. {
  416. struct fwnode_handle *fwnode = of_node_to_fwnode(port->pcie->dev->of_node);
  417. mutex_init(&port->lock);
  418. port->inner_domain = irq_domain_create_linear(fwnode, MTK_MSI_IRQS_NUM,
  419. &msi_domain_ops, port);
  420. if (!port->inner_domain) {
  421. dev_err(port->pcie->dev, "failed to create IRQ domain\n");
  422. return -ENOMEM;
  423. }
  424. port->msi_domain = pci_msi_create_irq_domain(fwnode, &mtk_msi_domain_info,
  425. port->inner_domain);
  426. if (!port->msi_domain) {
  427. dev_err(port->pcie->dev, "failed to create MSI domain\n");
  428. irq_domain_remove(port->inner_domain);
  429. return -ENOMEM;
  430. }
  431. return 0;
  432. }
  433. static void mtk_pcie_enable_msi(struct mtk_pcie_port *port)
  434. {
  435. u32 val;
  436. phys_addr_t msg_addr;
  437. msg_addr = virt_to_phys(port->base + PCIE_MSI_VECTOR);
  438. val = lower_32_bits(msg_addr);
  439. writel(val, port->base + PCIE_IMSI_ADDR);
  440. val = readl(port->base + PCIE_INT_MASK);
  441. val &= ~MSI_MASK;
  442. writel(val, port->base + PCIE_INT_MASK);
  443. }
  444. static void mtk_pcie_irq_teardown(struct mtk_pcie *pcie)
  445. {
  446. struct mtk_pcie_port *port, *tmp;
  447. list_for_each_entry_safe(port, tmp, &pcie->ports, list) {
  448. irq_set_chained_handler_and_data(port->irq, NULL, NULL);
  449. if (port->irq_domain)
  450. irq_domain_remove(port->irq_domain);
  451. if (IS_ENABLED(CONFIG_PCI_MSI)) {
  452. if (port->msi_domain)
  453. irq_domain_remove(port->msi_domain);
  454. if (port->inner_domain)
  455. irq_domain_remove(port->inner_domain);
  456. }
  457. irq_dispose_mapping(port->irq);
  458. }
  459. }
  460. static int mtk_pcie_intx_map(struct irq_domain *domain, unsigned int irq,
  461. irq_hw_number_t hwirq)
  462. {
  463. irq_set_chip_and_handler(irq, &dummy_irq_chip, handle_simple_irq);
  464. irq_set_chip_data(irq, domain->host_data);
  465. return 0;
  466. }
  467. static const struct irq_domain_ops intx_domain_ops = {
  468. .map = mtk_pcie_intx_map,
  469. };
  470. static int mtk_pcie_init_irq_domain(struct mtk_pcie_port *port,
  471. struct device_node *node)
  472. {
  473. struct device *dev = port->pcie->dev;
  474. struct device_node *pcie_intc_node;
  475. int ret;
  476. /* Setup INTx */
  477. pcie_intc_node = of_get_next_child(node, NULL);
  478. if (!pcie_intc_node) {
  479. dev_err(dev, "no PCIe Intc node found\n");
  480. return -ENODEV;
  481. }
  482. port->irq_domain = irq_domain_add_linear(pcie_intc_node, PCI_NUM_INTX,
  483. &intx_domain_ops, port);
  484. of_node_put(pcie_intc_node);
  485. if (!port->irq_domain) {
  486. dev_err(dev, "failed to get INTx IRQ domain\n");
  487. return -ENODEV;
  488. }
  489. if (IS_ENABLED(CONFIG_PCI_MSI)) {
  490. ret = mtk_pcie_allocate_msi_domains(port);
  491. if (ret)
  492. return ret;
  493. }
  494. return 0;
  495. }
  496. static void mtk_pcie_intr_handler(struct irq_desc *desc)
  497. {
  498. struct mtk_pcie_port *port = irq_desc_get_handler_data(desc);
  499. struct irq_chip *irqchip = irq_desc_get_chip(desc);
  500. unsigned long status;
  501. u32 virq;
  502. u32 bit = INTX_SHIFT;
  503. chained_irq_enter(irqchip, desc);
  504. status = readl(port->base + PCIE_INT_STATUS);
  505. if (status & INTX_MASK) {
  506. for_each_set_bit_from(bit, &status, PCI_NUM_INTX + INTX_SHIFT) {
  507. /* Clear the INTx */
  508. writel(1 << bit, port->base + PCIE_INT_STATUS);
  509. virq = irq_find_mapping(port->irq_domain,
  510. bit - INTX_SHIFT);
  511. generic_handle_irq(virq);
  512. }
  513. }
  514. if (IS_ENABLED(CONFIG_PCI_MSI)) {
  515. if (status & MSI_STATUS){
  516. unsigned long imsi_status;
  517. while ((imsi_status = readl(port->base + PCIE_IMSI_STATUS))) {
  518. for_each_set_bit(bit, &imsi_status, MTK_MSI_IRQS_NUM) {
  519. virq = irq_find_mapping(port->inner_domain, bit);
  520. generic_handle_irq(virq);
  521. }
  522. }
  523. /* Clear MSI interrupt status */
  524. writel(MSI_STATUS, port->base + PCIE_INT_STATUS);
  525. }
  526. }
  527. chained_irq_exit(irqchip, desc);
  528. }
  529. static int mtk_pcie_setup_irq(struct mtk_pcie_port *port,
  530. struct device_node *node)
  531. {
  532. struct mtk_pcie *pcie = port->pcie;
  533. struct device *dev = pcie->dev;
  534. struct platform_device *pdev = to_platform_device(dev);
  535. int err;
  536. err = mtk_pcie_init_irq_domain(port, node);
  537. if (err) {
  538. dev_err(dev, "failed to init PCIe IRQ domain\n");
  539. return err;
  540. }
  541. port->irq = platform_get_irq(pdev, port->slot);
  542. if (port->irq < 0)
  543. return port->irq;
  544. irq_set_chained_handler_and_data(port->irq,
  545. mtk_pcie_intr_handler, port);
  546. return 0;
  547. }
  548. static int mtk_pcie_startup_port_v2(struct mtk_pcie_port *port)
  549. {
  550. struct mtk_pcie *pcie = port->pcie;
  551. struct pci_host_bridge *host = pci_host_bridge_from_priv(pcie);
  552. struct resource *mem = NULL;
  553. struct resource_entry *entry;
  554. const struct mtk_pcie_soc *soc = port->pcie->soc;
  555. u32 val;
  556. int err;
  557. entry = resource_list_first_type(&host->windows, IORESOURCE_MEM);
  558. if (entry)
  559. mem = entry->res;
  560. if (!mem)
  561. return -EINVAL;
  562. /* MT7622 platforms need to enable LTSSM and ASPM from PCIe subsys */
  563. if (pcie->base) {
  564. val = readl(pcie->base + PCIE_SYS_CFG_V2);
  565. val |= PCIE_CSR_LTSSM_EN(port->slot) |
  566. PCIE_CSR_ASPM_L1_EN(port->slot);
  567. writel(val, pcie->base + PCIE_SYS_CFG_V2);
  568. }
  569. /* Assert all reset signals */
  570. writel(0, port->base + PCIE_RST_CTRL);
  571. /*
  572. * Enable PCIe link down reset, if link status changed from link up to
  573. * link down, this will reset MAC control registers and configuration
  574. * space.
  575. */
  576. writel(PCIE_LINKDOWN_RST_EN, port->base + PCIE_RST_CTRL);
  577. /* De-assert PHY, PE, PIPE, MAC and configuration reset */
  578. val = readl(port->base + PCIE_RST_CTRL);
  579. val |= PCIE_PHY_RSTB | PCIE_PERSTB | PCIE_PIPE_SRSTB |
  580. PCIE_MAC_SRSTB | PCIE_CRSTB;
  581. writel(val, port->base + PCIE_RST_CTRL);
  582. /* Set up vendor ID and class code */
  583. if (soc->need_fix_class_id) {
  584. val = PCI_VENDOR_ID_MEDIATEK;
  585. writew(val, port->base + PCIE_CONF_VEND_ID);
  586. val = PCI_CLASS_BRIDGE_PCI;
  587. writew(val, port->base + PCIE_CONF_CLASS_ID);
  588. }
  589. if (soc->need_fix_device_id)
  590. writew(soc->device_id, port->base + PCIE_CONF_DEVICE_ID);
  591. /* 100ms timeout value should be enough for Gen1/2 training */
  592. err = readl_poll_timeout(port->base + PCIE_LINK_STATUS_V2, val,
  593. !!(val & PCIE_PORT_LINKUP_V2), 20,
  594. 100 * USEC_PER_MSEC);
  595. if (err)
  596. return -ETIMEDOUT;
  597. /* Set INTx mask */
  598. val = readl(port->base + PCIE_INT_MASK);
  599. val &= ~INTX_MASK;
  600. writel(val, port->base + PCIE_INT_MASK);
  601. if (IS_ENABLED(CONFIG_PCI_MSI))
  602. mtk_pcie_enable_msi(port);
  603. /* Set AHB to PCIe translation windows */
  604. val = lower_32_bits(mem->start) |
  605. AHB2PCIE_SIZE(fls(resource_size(mem)));
  606. writel(val, port->base + PCIE_AHB_TRANS_BASE0_L);
  607. val = upper_32_bits(mem->start);
  608. writel(val, port->base + PCIE_AHB_TRANS_BASE0_H);
  609. /* Set PCIe to AXI translation memory space.*/
  610. val = PCIE2AHB_SIZE | WIN_ENABLE;
  611. writel(val, port->base + PCIE_AXI_WINDOW0);
  612. return 0;
  613. }
  614. static void __iomem *mtk_pcie_map_bus(struct pci_bus *bus,
  615. unsigned int devfn, int where)
  616. {
  617. struct mtk_pcie *pcie = bus->sysdata;
  618. writel(PCIE_CONF_ADDR(where, PCI_FUNC(devfn), PCI_SLOT(devfn),
  619. bus->number), pcie->base + PCIE_CFG_ADDR);
  620. return pcie->base + PCIE_CFG_DATA + (where & 3);
  621. }
  622. static struct pci_ops mtk_pcie_ops = {
  623. .map_bus = mtk_pcie_map_bus,
  624. .read = pci_generic_config_read,
  625. .write = pci_generic_config_write,
  626. };
  627. static int mtk_pcie_startup_port(struct mtk_pcie_port *port)
  628. {
  629. struct mtk_pcie *pcie = port->pcie;
  630. u32 func = PCI_FUNC(port->slot << 3);
  631. u32 slot = PCI_SLOT(port->slot << 3);
  632. u32 val;
  633. int err;
  634. /* assert port PERST_N */
  635. val = readl(pcie->base + PCIE_SYS_CFG);
  636. val |= PCIE_PORT_PERST(port->slot);
  637. writel(val, pcie->base + PCIE_SYS_CFG);
  638. /* de-assert port PERST_N */
  639. val = readl(pcie->base + PCIE_SYS_CFG);
  640. val &= ~PCIE_PORT_PERST(port->slot);
  641. writel(val, pcie->base + PCIE_SYS_CFG);
  642. /* 100ms timeout value should be enough for Gen1/2 training */
  643. err = readl_poll_timeout(port->base + PCIE_LINK_STATUS, val,
  644. !!(val & PCIE_PORT_LINKUP), 20,
  645. 100 * USEC_PER_MSEC);
  646. if (err)
  647. return -ETIMEDOUT;
  648. /* enable interrupt */
  649. val = readl(pcie->base + PCIE_INT_ENABLE);
  650. val |= PCIE_PORT_INT_EN(port->slot);
  651. writel(val, pcie->base + PCIE_INT_ENABLE);
  652. /* map to all DDR region. We need to set it before cfg operation. */
  653. writel(PCIE_BAR_MAP_MAX | PCIE_BAR_ENABLE,
  654. port->base + PCIE_BAR0_SETUP);
  655. /* configure class code and revision ID */
  656. writel(PCIE_CLASS_CODE | PCIE_REVISION_ID, port->base + PCIE_CLASS);
  657. /* configure FC credit */
  658. writel(PCIE_CONF_ADDR(PCIE_FC_CREDIT, func, slot, 0),
  659. pcie->base + PCIE_CFG_ADDR);
  660. val = readl(pcie->base + PCIE_CFG_DATA);
  661. val &= ~PCIE_FC_CREDIT_MASK;
  662. val |= PCIE_FC_CREDIT_VAL(0x806c);
  663. writel(PCIE_CONF_ADDR(PCIE_FC_CREDIT, func, slot, 0),
  664. pcie->base + PCIE_CFG_ADDR);
  665. writel(val, pcie->base + PCIE_CFG_DATA);
  666. /* configure RC FTS number to 250 when it leaves L0s */
  667. writel(PCIE_CONF_ADDR(PCIE_FTS_NUM, func, slot, 0),
  668. pcie->base + PCIE_CFG_ADDR);
  669. val = readl(pcie->base + PCIE_CFG_DATA);
  670. val &= ~PCIE_FTS_NUM_MASK;
  671. val |= PCIE_FTS_NUM_L0(0x50);
  672. writel(PCIE_CONF_ADDR(PCIE_FTS_NUM, func, slot, 0),
  673. pcie->base + PCIE_CFG_ADDR);
  674. writel(val, pcie->base + PCIE_CFG_DATA);
  675. return 0;
  676. }
  677. static void mtk_pcie_enable_port(struct mtk_pcie_port *port)
  678. {
  679. struct mtk_pcie *pcie = port->pcie;
  680. struct device *dev = pcie->dev;
  681. int err;
  682. err = clk_prepare_enable(port->sys_ck);
  683. if (err) {
  684. dev_err(dev, "failed to enable sys_ck%d clock\n", port->slot);
  685. goto err_sys_clk;
  686. }
  687. err = clk_prepare_enable(port->ahb_ck);
  688. if (err) {
  689. dev_err(dev, "failed to enable ahb_ck%d\n", port->slot);
  690. goto err_ahb_clk;
  691. }
  692. err = clk_prepare_enable(port->aux_ck);
  693. if (err) {
  694. dev_err(dev, "failed to enable aux_ck%d\n", port->slot);
  695. goto err_aux_clk;
  696. }
  697. err = clk_prepare_enable(port->axi_ck);
  698. if (err) {
  699. dev_err(dev, "failed to enable axi_ck%d\n", port->slot);
  700. goto err_axi_clk;
  701. }
  702. err = clk_prepare_enable(port->obff_ck);
  703. if (err) {
  704. dev_err(dev, "failed to enable obff_ck%d\n", port->slot);
  705. goto err_obff_clk;
  706. }
  707. err = clk_prepare_enable(port->pipe_ck);
  708. if (err) {
  709. dev_err(dev, "failed to enable pipe_ck%d\n", port->slot);
  710. goto err_pipe_clk;
  711. }
  712. reset_control_assert(port->reset);
  713. reset_control_deassert(port->reset);
  714. err = phy_init(port->phy);
  715. if (err) {
  716. dev_err(dev, "failed to initialize port%d phy\n", port->slot);
  717. goto err_phy_init;
  718. }
  719. err = phy_power_on(port->phy);
  720. if (err) {
  721. dev_err(dev, "failed to power on port%d phy\n", port->slot);
  722. goto err_phy_on;
  723. }
  724. if (!pcie->soc->startup(port))
  725. return;
  726. dev_info(dev, "Port%d link down\n", port->slot);
  727. phy_power_off(port->phy);
  728. err_phy_on:
  729. phy_exit(port->phy);
  730. err_phy_init:
  731. clk_disable_unprepare(port->pipe_ck);
  732. err_pipe_clk:
  733. clk_disable_unprepare(port->obff_ck);
  734. err_obff_clk:
  735. clk_disable_unprepare(port->axi_ck);
  736. err_axi_clk:
  737. clk_disable_unprepare(port->aux_ck);
  738. err_aux_clk:
  739. clk_disable_unprepare(port->ahb_ck);
  740. err_ahb_clk:
  741. clk_disable_unprepare(port->sys_ck);
  742. err_sys_clk:
  743. mtk_pcie_port_free(port);
  744. }
  745. static int mtk_pcie_parse_port(struct mtk_pcie *pcie,
  746. struct device_node *node,
  747. int slot)
  748. {
  749. struct mtk_pcie_port *port;
  750. struct device *dev = pcie->dev;
  751. struct platform_device *pdev = to_platform_device(dev);
  752. char name[10];
  753. int err;
  754. port = devm_kzalloc(dev, sizeof(*port), GFP_KERNEL);
  755. if (!port)
  756. return -ENOMEM;
  757. snprintf(name, sizeof(name), "port%d", slot);
  758. port->base = devm_platform_ioremap_resource_byname(pdev, name);
  759. if (IS_ERR(port->base)) {
  760. dev_err(dev, "failed to map port%d base\n", slot);
  761. return PTR_ERR(port->base);
  762. }
  763. snprintf(name, sizeof(name), "sys_ck%d", slot);
  764. port->sys_ck = devm_clk_get(dev, name);
  765. if (IS_ERR(port->sys_ck)) {
  766. dev_err(dev, "failed to get sys_ck%d clock\n", slot);
  767. return PTR_ERR(port->sys_ck);
  768. }
  769. /* sys_ck might be divided into the following parts in some chips */
  770. snprintf(name, sizeof(name), "ahb_ck%d", slot);
  771. port->ahb_ck = devm_clk_get_optional(dev, name);
  772. if (IS_ERR(port->ahb_ck))
  773. return PTR_ERR(port->ahb_ck);
  774. snprintf(name, sizeof(name), "axi_ck%d", slot);
  775. port->axi_ck = devm_clk_get_optional(dev, name);
  776. if (IS_ERR(port->axi_ck))
  777. return PTR_ERR(port->axi_ck);
  778. snprintf(name, sizeof(name), "aux_ck%d", slot);
  779. port->aux_ck = devm_clk_get_optional(dev, name);
  780. if (IS_ERR(port->aux_ck))
  781. return PTR_ERR(port->aux_ck);
  782. snprintf(name, sizeof(name), "obff_ck%d", slot);
  783. port->obff_ck = devm_clk_get_optional(dev, name);
  784. if (IS_ERR(port->obff_ck))
  785. return PTR_ERR(port->obff_ck);
  786. snprintf(name, sizeof(name), "pipe_ck%d", slot);
  787. port->pipe_ck = devm_clk_get_optional(dev, name);
  788. if (IS_ERR(port->pipe_ck))
  789. return PTR_ERR(port->pipe_ck);
  790. snprintf(name, sizeof(name), "pcie-rst%d", slot);
  791. port->reset = devm_reset_control_get_optional_exclusive(dev, name);
  792. if (PTR_ERR(port->reset) == -EPROBE_DEFER)
  793. return PTR_ERR(port->reset);
  794. /* some platforms may use default PHY setting */
  795. snprintf(name, sizeof(name), "pcie-phy%d", slot);
  796. port->phy = devm_phy_optional_get(dev, name);
  797. if (IS_ERR(port->phy))
  798. return PTR_ERR(port->phy);
  799. port->slot = slot;
  800. port->pcie = pcie;
  801. if (pcie->soc->setup_irq) {
  802. err = pcie->soc->setup_irq(port, node);
  803. if (err)
  804. return err;
  805. }
  806. INIT_LIST_HEAD(&port->list);
  807. list_add_tail(&port->list, &pcie->ports);
  808. return 0;
  809. }
  810. static int mtk_pcie_subsys_powerup(struct mtk_pcie *pcie)
  811. {
  812. struct device *dev = pcie->dev;
  813. struct platform_device *pdev = to_platform_device(dev);
  814. struct resource *regs;
  815. int err;
  816. /* get shared registers, which are optional */
  817. regs = platform_get_resource_byname(pdev, IORESOURCE_MEM, "subsys");
  818. if (regs) {
  819. pcie->base = devm_ioremap_resource(dev, regs);
  820. if (IS_ERR(pcie->base)) {
  821. dev_err(dev, "failed to map shared register\n");
  822. return PTR_ERR(pcie->base);
  823. }
  824. }
  825. pcie->free_ck = devm_clk_get(dev, "free_ck");
  826. if (IS_ERR(pcie->free_ck)) {
  827. if (PTR_ERR(pcie->free_ck) == -EPROBE_DEFER)
  828. return -EPROBE_DEFER;
  829. pcie->free_ck = NULL;
  830. }
  831. pm_runtime_enable(dev);
  832. pm_runtime_get_sync(dev);
  833. /* enable top level clock */
  834. err = clk_prepare_enable(pcie->free_ck);
  835. if (err) {
  836. dev_err(dev, "failed to enable free_ck\n");
  837. goto err_free_ck;
  838. }
  839. return 0;
  840. err_free_ck:
  841. pm_runtime_put_sync(dev);
  842. pm_runtime_disable(dev);
  843. return err;
  844. }
  845. static int mtk_pcie_setup(struct mtk_pcie *pcie)
  846. {
  847. struct device *dev = pcie->dev;
  848. struct device_node *node = dev->of_node, *child;
  849. struct mtk_pcie_port *port, *tmp;
  850. int err;
  851. for_each_available_child_of_node(node, child) {
  852. int slot;
  853. err = of_pci_get_devfn(child);
  854. if (err < 0) {
  855. dev_err(dev, "failed to parse devfn: %d\n", err);
  856. goto error_put_node;
  857. }
  858. slot = PCI_SLOT(err);
  859. err = mtk_pcie_parse_port(pcie, child, slot);
  860. if (err)
  861. goto error_put_node;
  862. }
  863. err = mtk_pcie_subsys_powerup(pcie);
  864. if (err)
  865. return err;
  866. /* enable each port, and then check link status */
  867. list_for_each_entry_safe(port, tmp, &pcie->ports, list)
  868. mtk_pcie_enable_port(port);
  869. /* power down PCIe subsys if slots are all empty (link down) */
  870. if (list_empty(&pcie->ports))
  871. mtk_pcie_subsys_powerdown(pcie);
  872. return 0;
  873. error_put_node:
  874. of_node_put(child);
  875. return err;
  876. }
  877. static int mtk_pcie_probe(struct platform_device *pdev)
  878. {
  879. struct device *dev = &pdev->dev;
  880. struct mtk_pcie *pcie;
  881. struct pci_host_bridge *host;
  882. int err;
  883. host = devm_pci_alloc_host_bridge(dev, sizeof(*pcie));
  884. if (!host)
  885. return -ENOMEM;
  886. pcie = pci_host_bridge_priv(host);
  887. pcie->dev = dev;
  888. pcie->soc = of_device_get_match_data(dev);
  889. platform_set_drvdata(pdev, pcie);
  890. INIT_LIST_HEAD(&pcie->ports);
  891. err = mtk_pcie_setup(pcie);
  892. if (err)
  893. return err;
  894. host->ops = pcie->soc->ops;
  895. host->sysdata = pcie;
  896. err = pci_host_probe(host);
  897. if (err)
  898. goto put_resources;
  899. return 0;
  900. put_resources:
  901. if (!list_empty(&pcie->ports))
  902. mtk_pcie_put_resources(pcie);
  903. return err;
  904. }
  905. static void mtk_pcie_free_resources(struct mtk_pcie *pcie)
  906. {
  907. struct pci_host_bridge *host = pci_host_bridge_from_priv(pcie);
  908. struct list_head *windows = &host->windows;
  909. pci_free_resource_list(windows);
  910. }
  911. static int mtk_pcie_remove(struct platform_device *pdev)
  912. {
  913. struct mtk_pcie *pcie = platform_get_drvdata(pdev);
  914. struct pci_host_bridge *host = pci_host_bridge_from_priv(pcie);
  915. pci_stop_root_bus(host->bus);
  916. pci_remove_root_bus(host->bus);
  917. mtk_pcie_free_resources(pcie);
  918. mtk_pcie_irq_teardown(pcie);
  919. mtk_pcie_put_resources(pcie);
  920. return 0;
  921. }
  922. static int __maybe_unused mtk_pcie_suspend_noirq(struct device *dev)
  923. {
  924. struct mtk_pcie *pcie = dev_get_drvdata(dev);
  925. struct mtk_pcie_port *port;
  926. if (list_empty(&pcie->ports))
  927. return 0;
  928. list_for_each_entry(port, &pcie->ports, list) {
  929. clk_disable_unprepare(port->pipe_ck);
  930. clk_disable_unprepare(port->obff_ck);
  931. clk_disable_unprepare(port->axi_ck);
  932. clk_disable_unprepare(port->aux_ck);
  933. clk_disable_unprepare(port->ahb_ck);
  934. clk_disable_unprepare(port->sys_ck);
  935. phy_power_off(port->phy);
  936. phy_exit(port->phy);
  937. }
  938. clk_disable_unprepare(pcie->free_ck);
  939. return 0;
  940. }
  941. static int __maybe_unused mtk_pcie_resume_noirq(struct device *dev)
  942. {
  943. struct mtk_pcie *pcie = dev_get_drvdata(dev);
  944. struct mtk_pcie_port *port, *tmp;
  945. if (list_empty(&pcie->ports))
  946. return 0;
  947. clk_prepare_enable(pcie->free_ck);
  948. list_for_each_entry_safe(port, tmp, &pcie->ports, list)
  949. mtk_pcie_enable_port(port);
  950. /* In case of EP was removed while system suspend. */
  951. if (list_empty(&pcie->ports))
  952. clk_disable_unprepare(pcie->free_ck);
  953. return 0;
  954. }
  955. static const struct dev_pm_ops mtk_pcie_pm_ops = {
  956. SET_NOIRQ_SYSTEM_SLEEP_PM_OPS(mtk_pcie_suspend_noirq,
  957. mtk_pcie_resume_noirq)
  958. };
  959. static const struct mtk_pcie_soc mtk_pcie_soc_v1 = {
  960. .ops = &mtk_pcie_ops,
  961. .startup = mtk_pcie_startup_port,
  962. };
  963. static const struct mtk_pcie_soc mtk_pcie_soc_mt2712 = {
  964. .ops = &mtk_pcie_ops_v2,
  965. .startup = mtk_pcie_startup_port_v2,
  966. .setup_irq = mtk_pcie_setup_irq,
  967. };
  968. static const struct mtk_pcie_soc mtk_pcie_soc_mt7622 = {
  969. .need_fix_class_id = true,
  970. .ops = &mtk_pcie_ops_v2,
  971. .startup = mtk_pcie_startup_port_v2,
  972. .setup_irq = mtk_pcie_setup_irq,
  973. };
  974. static const struct mtk_pcie_soc mtk_pcie_soc_mt7629 = {
  975. .need_fix_class_id = true,
  976. .need_fix_device_id = true,
  977. .device_id = PCI_DEVICE_ID_MEDIATEK_7629,
  978. .ops = &mtk_pcie_ops_v2,
  979. .startup = mtk_pcie_startup_port_v2,
  980. .setup_irq = mtk_pcie_setup_irq,
  981. };
  982. static const struct of_device_id mtk_pcie_ids[] = {
  983. { .compatible = "mediatek,mt2701-pcie", .data = &mtk_pcie_soc_v1 },
  984. { .compatible = "mediatek,mt7623-pcie", .data = &mtk_pcie_soc_v1 },
  985. { .compatible = "mediatek,mt2712-pcie", .data = &mtk_pcie_soc_mt2712 },
  986. { .compatible = "mediatek,mt7622-pcie", .data = &mtk_pcie_soc_mt7622 },
  987. { .compatible = "mediatek,mt7629-pcie", .data = &mtk_pcie_soc_mt7629 },
  988. {},
  989. };
  990. static struct platform_driver mtk_pcie_driver = {
  991. .probe = mtk_pcie_probe,
  992. .remove = mtk_pcie_remove,
  993. .driver = {
  994. .name = "mtk-pcie",
  995. .of_match_table = mtk_pcie_ids,
  996. .suppress_bind_attrs = true,
  997. .pm = &mtk_pcie_pm_ops,
  998. },
  999. };
  1000. module_platform_driver(mtk_pcie_driver);
  1001. MODULE_LICENSE("GPL v2");