pcie-brcmstb.c 38 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /* Copyright (C) 2009 - 2019 Broadcom */
  3. #include <linux/bitfield.h>
  4. #include <linux/bitops.h>
  5. #include <linux/clk.h>
  6. #include <linux/compiler.h>
  7. #include <linux/delay.h>
  8. #include <linux/init.h>
  9. #include <linux/interrupt.h>
  10. #include <linux/io.h>
  11. #include <linux/ioport.h>
  12. #include <linux/irqchip/chained_irq.h>
  13. #include <linux/irqdomain.h>
  14. #include <linux/kernel.h>
  15. #include <linux/list.h>
  16. #include <linux/log2.h>
  17. #include <linux/module.h>
  18. #include <linux/msi.h>
  19. #include <linux/of_address.h>
  20. #include <linux/of_irq.h>
  21. #include <linux/of_pci.h>
  22. #include <linux/of_platform.h>
  23. #include <linux/pci.h>
  24. #include <linux/printk.h>
  25. #include <linux/reset.h>
  26. #include <linux/sizes.h>
  27. #include <linux/slab.h>
  28. #include <linux/string.h>
  29. #include <linux/types.h>
  30. #include "../pci.h"
  31. /* BRCM_PCIE_CAP_REGS - Offset for the mandatory capability config regs */
  32. #define BRCM_PCIE_CAP_REGS 0x00ac
  33. /* Broadcom STB PCIe Register Offsets */
  34. #define PCIE_RC_CFG_VENDOR_VENDOR_SPECIFIC_REG1 0x0188
  35. #define PCIE_RC_CFG_VENDOR_VENDOR_SPECIFIC_REG1_ENDIAN_MODE_BAR2_MASK 0xc
  36. #define PCIE_RC_CFG_VENDOR_SPCIFIC_REG1_LITTLE_ENDIAN 0x0
  37. #define PCIE_RC_CFG_PRIV1_ID_VAL3 0x043c
  38. #define PCIE_RC_CFG_PRIV1_ID_VAL3_CLASS_CODE_MASK 0xffffff
  39. #define PCIE_RC_CFG_PRIV1_LINK_CAPABILITY 0x04dc
  40. #define PCIE_RC_CFG_PRIV1_LINK_CAPABILITY_ASPM_SUPPORT_MASK 0xc00
  41. #define PCIE_RC_DL_MDIO_ADDR 0x1100
  42. #define PCIE_RC_DL_MDIO_WR_DATA 0x1104
  43. #define PCIE_RC_DL_MDIO_RD_DATA 0x1108
  44. #define PCIE_MISC_MISC_CTRL 0x4008
  45. #define PCIE_MISC_MISC_CTRL_SCB_ACCESS_EN_MASK 0x1000
  46. #define PCIE_MISC_MISC_CTRL_CFG_READ_UR_MODE_MASK 0x2000
  47. #define PCIE_MISC_MISC_CTRL_MAX_BURST_SIZE_MASK 0x300000
  48. #define PCIE_MISC_MISC_CTRL_SCB0_SIZE_MASK 0xf8000000
  49. #define PCIE_MISC_MISC_CTRL_SCB1_SIZE_MASK 0x07c00000
  50. #define PCIE_MISC_MISC_CTRL_SCB2_SIZE_MASK 0x0000001f
  51. #define SCB_SIZE_MASK(x) PCIE_MISC_MISC_CTRL_SCB ## x ## _SIZE_MASK
  52. #define PCIE_MISC_CPU_2_PCIE_MEM_WIN0_LO 0x400c
  53. #define PCIE_MEM_WIN0_LO(win) \
  54. PCIE_MISC_CPU_2_PCIE_MEM_WIN0_LO + ((win) * 8)
  55. #define PCIE_MISC_CPU_2_PCIE_MEM_WIN0_HI 0x4010
  56. #define PCIE_MEM_WIN0_HI(win) \
  57. PCIE_MISC_CPU_2_PCIE_MEM_WIN0_HI + ((win) * 8)
  58. #define PCIE_MISC_RC_BAR1_CONFIG_LO 0x402c
  59. #define PCIE_MISC_RC_BAR1_CONFIG_LO_SIZE_MASK 0x1f
  60. #define PCIE_MISC_RC_BAR2_CONFIG_LO 0x4034
  61. #define PCIE_MISC_RC_BAR2_CONFIG_LO_SIZE_MASK 0x1f
  62. #define PCIE_MISC_RC_BAR2_CONFIG_HI 0x4038
  63. #define PCIE_MISC_RC_BAR3_CONFIG_LO 0x403c
  64. #define PCIE_MISC_RC_BAR3_CONFIG_LO_SIZE_MASK 0x1f
  65. #define PCIE_MISC_MSI_BAR_CONFIG_LO 0x4044
  66. #define PCIE_MISC_MSI_BAR_CONFIG_HI 0x4048
  67. #define PCIE_MISC_MSI_DATA_CONFIG 0x404c
  68. #define PCIE_MISC_MSI_DATA_CONFIG_VAL_32 0xffe06540
  69. #define PCIE_MISC_MSI_DATA_CONFIG_VAL_8 0xfff86540
  70. #define PCIE_MISC_PCIE_CTRL 0x4064
  71. #define PCIE_MISC_PCIE_CTRL_PCIE_L23_REQUEST_MASK 0x1
  72. #define PCIE_MISC_PCIE_CTRL_PCIE_PERSTB_MASK 0x4
  73. #define PCIE_MISC_PCIE_STATUS 0x4068
  74. #define PCIE_MISC_PCIE_STATUS_PCIE_PORT_MASK 0x80
  75. #define PCIE_MISC_PCIE_STATUS_PCIE_DL_ACTIVE_MASK 0x20
  76. #define PCIE_MISC_PCIE_STATUS_PCIE_PHYLINKUP_MASK 0x10
  77. #define PCIE_MISC_PCIE_STATUS_PCIE_LINK_IN_L23_MASK 0x40
  78. #define PCIE_MISC_REVISION 0x406c
  79. #define BRCM_PCIE_HW_REV_33 0x0303
  80. #define PCIE_MISC_CPU_2_PCIE_MEM_WIN0_BASE_LIMIT 0x4070
  81. #define PCIE_MISC_CPU_2_PCIE_MEM_WIN0_BASE_LIMIT_LIMIT_MASK 0xfff00000
  82. #define PCIE_MISC_CPU_2_PCIE_MEM_WIN0_BASE_LIMIT_BASE_MASK 0xfff0
  83. #define PCIE_MEM_WIN0_BASE_LIMIT(win) \
  84. PCIE_MISC_CPU_2_PCIE_MEM_WIN0_BASE_LIMIT + ((win) * 4)
  85. #define PCIE_MISC_CPU_2_PCIE_MEM_WIN0_BASE_HI 0x4080
  86. #define PCIE_MISC_CPU_2_PCIE_MEM_WIN0_BASE_HI_BASE_MASK 0xff
  87. #define PCIE_MEM_WIN0_BASE_HI(win) \
  88. PCIE_MISC_CPU_2_PCIE_MEM_WIN0_BASE_HI + ((win) * 8)
  89. #define PCIE_MISC_CPU_2_PCIE_MEM_WIN0_LIMIT_HI 0x4084
  90. #define PCIE_MISC_CPU_2_PCIE_MEM_WIN0_LIMIT_HI_LIMIT_MASK 0xff
  91. #define PCIE_MEM_WIN0_LIMIT_HI(win) \
  92. PCIE_MISC_CPU_2_PCIE_MEM_WIN0_LIMIT_HI + ((win) * 8)
  93. #define PCIE_MISC_HARD_PCIE_HARD_DEBUG 0x4204
  94. #define PCIE_MISC_HARD_PCIE_HARD_DEBUG_CLKREQ_DEBUG_ENABLE_MASK 0x2
  95. #define PCIE_MISC_HARD_PCIE_HARD_DEBUG_SERDES_IDDQ_MASK 0x08000000
  96. #define PCIE_INTR2_CPU_BASE 0x4300
  97. #define PCIE_MSI_INTR2_BASE 0x4500
  98. /* Offsets from PCIE_INTR2_CPU_BASE and PCIE_MSI_INTR2_BASE */
  99. #define MSI_INT_STATUS 0x0
  100. #define MSI_INT_CLR 0x8
  101. #define MSI_INT_MASK_SET 0x10
  102. #define MSI_INT_MASK_CLR 0x14
  103. #define PCIE_EXT_CFG_DATA 0x8000
  104. #define PCIE_EXT_CFG_INDEX 0x9000
  105. #define PCIE_EXT_BUSNUM_SHIFT 20
  106. #define PCIE_EXT_SLOT_SHIFT 15
  107. #define PCIE_EXT_FUNC_SHIFT 12
  108. #define PCIE_RGR1_SW_INIT_1_PERST_MASK 0x1
  109. #define PCIE_RGR1_SW_INIT_1_PERST_SHIFT 0x0
  110. #define RGR1_SW_INIT_1_INIT_GENERIC_MASK 0x2
  111. #define RGR1_SW_INIT_1_INIT_GENERIC_SHIFT 0x1
  112. #define RGR1_SW_INIT_1_INIT_7278_MASK 0x1
  113. #define RGR1_SW_INIT_1_INIT_7278_SHIFT 0x0
  114. /* PCIe parameters */
  115. #define BRCM_NUM_PCIE_OUT_WINS 0x4
  116. #define BRCM_INT_PCI_MSI_NR 32
  117. #define BRCM_INT_PCI_MSI_LEGACY_NR 8
  118. #define BRCM_INT_PCI_MSI_SHIFT 0
  119. /* MSI target adresses */
  120. #define BRCM_MSI_TARGET_ADDR_LT_4GB 0x0fffffffcULL
  121. #define BRCM_MSI_TARGET_ADDR_GT_4GB 0xffffffffcULL
  122. /* MDIO registers */
  123. #define MDIO_PORT0 0x0
  124. #define MDIO_DATA_MASK 0x7fffffff
  125. #define MDIO_PORT_MASK 0xf0000
  126. #define MDIO_REGAD_MASK 0xffff
  127. #define MDIO_CMD_MASK 0xfff00000
  128. #define MDIO_CMD_READ 0x1
  129. #define MDIO_CMD_WRITE 0x0
  130. #define MDIO_DATA_DONE_MASK 0x80000000
  131. #define MDIO_RD_DONE(x) (((x) & MDIO_DATA_DONE_MASK) ? 1 : 0)
  132. #define MDIO_WT_DONE(x) (((x) & MDIO_DATA_DONE_MASK) ? 0 : 1)
  133. #define SSC_REGS_ADDR 0x1100
  134. #define SET_ADDR_OFFSET 0x1f
  135. #define SSC_CNTL_OFFSET 0x2
  136. #define SSC_CNTL_OVRD_EN_MASK 0x8000
  137. #define SSC_CNTL_OVRD_VAL_MASK 0x4000
  138. #define SSC_STATUS_OFFSET 0x1
  139. #define SSC_STATUS_SSC_MASK 0x400
  140. #define SSC_STATUS_PLL_LOCK_MASK 0x800
  141. #define PCIE_BRCM_MAX_MEMC 3
  142. #define IDX_ADDR(pcie) (pcie->reg_offsets[EXT_CFG_INDEX])
  143. #define DATA_ADDR(pcie) (pcie->reg_offsets[EXT_CFG_DATA])
  144. #define PCIE_RGR1_SW_INIT_1(pcie) (pcie->reg_offsets[RGR1_SW_INIT_1])
  145. /* Rescal registers */
  146. #define PCIE_DVT_PMU_PCIE_PHY_CTRL 0xc700
  147. #define PCIE_DVT_PMU_PCIE_PHY_CTRL_DAST_NFLDS 0x3
  148. #define PCIE_DVT_PMU_PCIE_PHY_CTRL_DAST_DIG_RESET_MASK 0x4
  149. #define PCIE_DVT_PMU_PCIE_PHY_CTRL_DAST_DIG_RESET_SHIFT 0x2
  150. #define PCIE_DVT_PMU_PCIE_PHY_CTRL_DAST_RESET_MASK 0x2
  151. #define PCIE_DVT_PMU_PCIE_PHY_CTRL_DAST_RESET_SHIFT 0x1
  152. #define PCIE_DVT_PMU_PCIE_PHY_CTRL_DAST_PWRDN_MASK 0x1
  153. #define PCIE_DVT_PMU_PCIE_PHY_CTRL_DAST_PWRDN_SHIFT 0x0
  154. /* Forward declarations */
  155. struct brcm_pcie;
  156. static inline void brcm_pcie_bridge_sw_init_set_7278(struct brcm_pcie *pcie, u32 val);
  157. static inline void brcm_pcie_bridge_sw_init_set_generic(struct brcm_pcie *pcie, u32 val);
  158. static inline void brcm_pcie_perst_set_7278(struct brcm_pcie *pcie, u32 val);
  159. static inline void brcm_pcie_perst_set_generic(struct brcm_pcie *pcie, u32 val);
  160. enum {
  161. RGR1_SW_INIT_1,
  162. EXT_CFG_INDEX,
  163. EXT_CFG_DATA,
  164. };
  165. enum {
  166. RGR1_SW_INIT_1_INIT_MASK,
  167. RGR1_SW_INIT_1_INIT_SHIFT,
  168. };
  169. enum pcie_type {
  170. GENERIC,
  171. BCM7278,
  172. BCM2711,
  173. };
  174. struct pcie_cfg_data {
  175. const int *offsets;
  176. const enum pcie_type type;
  177. void (*perst_set)(struct brcm_pcie *pcie, u32 val);
  178. void (*bridge_sw_init_set)(struct brcm_pcie *pcie, u32 val);
  179. };
  180. static const int pcie_offsets[] = {
  181. [RGR1_SW_INIT_1] = 0x9210,
  182. [EXT_CFG_INDEX] = 0x9000,
  183. [EXT_CFG_DATA] = 0x9004,
  184. };
  185. static const struct pcie_cfg_data generic_cfg = {
  186. .offsets = pcie_offsets,
  187. .type = GENERIC,
  188. .perst_set = brcm_pcie_perst_set_generic,
  189. .bridge_sw_init_set = brcm_pcie_bridge_sw_init_set_generic,
  190. };
  191. static const int pcie_offset_bcm7278[] = {
  192. [RGR1_SW_INIT_1] = 0xc010,
  193. [EXT_CFG_INDEX] = 0x9000,
  194. [EXT_CFG_DATA] = 0x9004,
  195. };
  196. static const struct pcie_cfg_data bcm7278_cfg = {
  197. .offsets = pcie_offset_bcm7278,
  198. .type = BCM7278,
  199. .perst_set = brcm_pcie_perst_set_7278,
  200. .bridge_sw_init_set = brcm_pcie_bridge_sw_init_set_7278,
  201. };
  202. static const struct pcie_cfg_data bcm2711_cfg = {
  203. .offsets = pcie_offsets,
  204. .type = BCM2711,
  205. .perst_set = brcm_pcie_perst_set_generic,
  206. .bridge_sw_init_set = brcm_pcie_bridge_sw_init_set_generic,
  207. };
  208. struct brcm_msi {
  209. struct device *dev;
  210. void __iomem *base;
  211. struct device_node *np;
  212. struct irq_domain *msi_domain;
  213. struct irq_domain *inner_domain;
  214. struct mutex lock; /* guards the alloc/free operations */
  215. u64 target_addr;
  216. int irq;
  217. /* used indicates which MSI interrupts have been alloc'd */
  218. unsigned long used;
  219. bool legacy;
  220. /* Some chips have MSIs in bits [31..24] of a shared register. */
  221. int legacy_shift;
  222. int nr; /* No. of MSI available, depends on chip */
  223. /* This is the base pointer for interrupt status/set/clr regs */
  224. void __iomem *intr_base;
  225. };
  226. /* Internal PCIe Host Controller Information.*/
  227. struct brcm_pcie {
  228. struct device *dev;
  229. void __iomem *base;
  230. struct clk *clk;
  231. struct device_node *np;
  232. bool ssc;
  233. int gen;
  234. u64 msi_target_addr;
  235. struct brcm_msi *msi;
  236. const int *reg_offsets;
  237. enum pcie_type type;
  238. struct reset_control *rescal;
  239. int num_memc;
  240. u64 memc_size[PCIE_BRCM_MAX_MEMC];
  241. u32 hw_rev;
  242. void (*perst_set)(struct brcm_pcie *pcie, u32 val);
  243. void (*bridge_sw_init_set)(struct brcm_pcie *pcie, u32 val);
  244. };
  245. /*
  246. * This is to convert the size of the inbound "BAR" region to the
  247. * non-linear values of PCIE_X_MISC_RC_BAR[123]_CONFIG_LO.SIZE
  248. */
  249. static int brcm_pcie_encode_ibar_size(u64 size)
  250. {
  251. int log2_in = ilog2(size);
  252. if (log2_in >= 12 && log2_in <= 15)
  253. /* Covers 4KB to 32KB (inclusive) */
  254. return (log2_in - 12) + 0x1c;
  255. else if (log2_in >= 16 && log2_in <= 35)
  256. /* Covers 64KB to 32GB, (inclusive) */
  257. return log2_in - 15;
  258. /* Something is awry so disable */
  259. return 0;
  260. }
  261. static u32 brcm_pcie_mdio_form_pkt(int port, int regad, int cmd)
  262. {
  263. u32 pkt = 0;
  264. pkt |= FIELD_PREP(MDIO_PORT_MASK, port);
  265. pkt |= FIELD_PREP(MDIO_REGAD_MASK, regad);
  266. pkt |= FIELD_PREP(MDIO_CMD_MASK, cmd);
  267. return pkt;
  268. }
  269. /* negative return value indicates error */
  270. static int brcm_pcie_mdio_read(void __iomem *base, u8 port, u8 regad, u32 *val)
  271. {
  272. int tries;
  273. u32 data;
  274. writel(brcm_pcie_mdio_form_pkt(port, regad, MDIO_CMD_READ),
  275. base + PCIE_RC_DL_MDIO_ADDR);
  276. readl(base + PCIE_RC_DL_MDIO_ADDR);
  277. data = readl(base + PCIE_RC_DL_MDIO_RD_DATA);
  278. for (tries = 0; !MDIO_RD_DONE(data) && tries < 10; tries++) {
  279. udelay(10);
  280. data = readl(base + PCIE_RC_DL_MDIO_RD_DATA);
  281. }
  282. *val = FIELD_GET(MDIO_DATA_MASK, data);
  283. return MDIO_RD_DONE(data) ? 0 : -EIO;
  284. }
  285. /* negative return value indicates error */
  286. static int brcm_pcie_mdio_write(void __iomem *base, u8 port,
  287. u8 regad, u16 wrdata)
  288. {
  289. int tries;
  290. u32 data;
  291. writel(brcm_pcie_mdio_form_pkt(port, regad, MDIO_CMD_WRITE),
  292. base + PCIE_RC_DL_MDIO_ADDR);
  293. readl(base + PCIE_RC_DL_MDIO_ADDR);
  294. writel(MDIO_DATA_DONE_MASK | wrdata, base + PCIE_RC_DL_MDIO_WR_DATA);
  295. data = readl(base + PCIE_RC_DL_MDIO_WR_DATA);
  296. for (tries = 0; !MDIO_WT_DONE(data) && tries < 10; tries++) {
  297. udelay(10);
  298. data = readl(base + PCIE_RC_DL_MDIO_WR_DATA);
  299. }
  300. return MDIO_WT_DONE(data) ? 0 : -EIO;
  301. }
  302. /*
  303. * Configures device for Spread Spectrum Clocking (SSC) mode; a negative
  304. * return value indicates error.
  305. */
  306. static int brcm_pcie_set_ssc(struct brcm_pcie *pcie)
  307. {
  308. int pll, ssc;
  309. int ret;
  310. u32 tmp;
  311. ret = brcm_pcie_mdio_write(pcie->base, MDIO_PORT0, SET_ADDR_OFFSET,
  312. SSC_REGS_ADDR);
  313. if (ret < 0)
  314. return ret;
  315. ret = brcm_pcie_mdio_read(pcie->base, MDIO_PORT0,
  316. SSC_CNTL_OFFSET, &tmp);
  317. if (ret < 0)
  318. return ret;
  319. u32p_replace_bits(&tmp, 1, SSC_CNTL_OVRD_EN_MASK);
  320. u32p_replace_bits(&tmp, 1, SSC_CNTL_OVRD_VAL_MASK);
  321. ret = brcm_pcie_mdio_write(pcie->base, MDIO_PORT0,
  322. SSC_CNTL_OFFSET, tmp);
  323. if (ret < 0)
  324. return ret;
  325. usleep_range(1000, 2000);
  326. ret = brcm_pcie_mdio_read(pcie->base, MDIO_PORT0,
  327. SSC_STATUS_OFFSET, &tmp);
  328. if (ret < 0)
  329. return ret;
  330. ssc = FIELD_GET(SSC_STATUS_SSC_MASK, tmp);
  331. pll = FIELD_GET(SSC_STATUS_PLL_LOCK_MASK, tmp);
  332. return ssc && pll ? 0 : -EIO;
  333. }
  334. /* Limits operation to a specific generation (1, 2, or 3) */
  335. static void brcm_pcie_set_gen(struct brcm_pcie *pcie, int gen)
  336. {
  337. u16 lnkctl2 = readw(pcie->base + BRCM_PCIE_CAP_REGS + PCI_EXP_LNKCTL2);
  338. u32 lnkcap = readl(pcie->base + BRCM_PCIE_CAP_REGS + PCI_EXP_LNKCAP);
  339. lnkcap = (lnkcap & ~PCI_EXP_LNKCAP_SLS) | gen;
  340. writel(lnkcap, pcie->base + BRCM_PCIE_CAP_REGS + PCI_EXP_LNKCAP);
  341. lnkctl2 = (lnkctl2 & ~0xf) | gen;
  342. writew(lnkctl2, pcie->base + BRCM_PCIE_CAP_REGS + PCI_EXP_LNKCTL2);
  343. }
  344. static void brcm_pcie_set_outbound_win(struct brcm_pcie *pcie,
  345. unsigned int win, u64 cpu_addr,
  346. u64 pcie_addr, u64 size)
  347. {
  348. u32 cpu_addr_mb_high, limit_addr_mb_high;
  349. phys_addr_t cpu_addr_mb, limit_addr_mb;
  350. int high_addr_shift;
  351. u32 tmp;
  352. /* Set the base of the pcie_addr window */
  353. writel(lower_32_bits(pcie_addr), pcie->base + PCIE_MEM_WIN0_LO(win));
  354. writel(upper_32_bits(pcie_addr), pcie->base + PCIE_MEM_WIN0_HI(win));
  355. /* Write the addr base & limit lower bits (in MBs) */
  356. cpu_addr_mb = cpu_addr / SZ_1M;
  357. limit_addr_mb = (cpu_addr + size - 1) / SZ_1M;
  358. tmp = readl(pcie->base + PCIE_MEM_WIN0_BASE_LIMIT(win));
  359. u32p_replace_bits(&tmp, cpu_addr_mb,
  360. PCIE_MISC_CPU_2_PCIE_MEM_WIN0_BASE_LIMIT_BASE_MASK);
  361. u32p_replace_bits(&tmp, limit_addr_mb,
  362. PCIE_MISC_CPU_2_PCIE_MEM_WIN0_BASE_LIMIT_LIMIT_MASK);
  363. writel(tmp, pcie->base + PCIE_MEM_WIN0_BASE_LIMIT(win));
  364. /* Write the cpu & limit addr upper bits */
  365. high_addr_shift =
  366. HWEIGHT32(PCIE_MISC_CPU_2_PCIE_MEM_WIN0_BASE_LIMIT_BASE_MASK);
  367. cpu_addr_mb_high = cpu_addr_mb >> high_addr_shift;
  368. tmp = readl(pcie->base + PCIE_MEM_WIN0_BASE_HI(win));
  369. u32p_replace_bits(&tmp, cpu_addr_mb_high,
  370. PCIE_MISC_CPU_2_PCIE_MEM_WIN0_BASE_HI_BASE_MASK);
  371. writel(tmp, pcie->base + PCIE_MEM_WIN0_BASE_HI(win));
  372. limit_addr_mb_high = limit_addr_mb >> high_addr_shift;
  373. tmp = readl(pcie->base + PCIE_MEM_WIN0_LIMIT_HI(win));
  374. u32p_replace_bits(&tmp, limit_addr_mb_high,
  375. PCIE_MISC_CPU_2_PCIE_MEM_WIN0_LIMIT_HI_LIMIT_MASK);
  376. writel(tmp, pcie->base + PCIE_MEM_WIN0_LIMIT_HI(win));
  377. }
  378. static struct irq_chip brcm_msi_irq_chip = {
  379. .name = "BRCM STB PCIe MSI",
  380. .irq_ack = irq_chip_ack_parent,
  381. .irq_mask = pci_msi_mask_irq,
  382. .irq_unmask = pci_msi_unmask_irq,
  383. };
  384. static struct msi_domain_info brcm_msi_domain_info = {
  385. /* Multi MSI is supported by the controller, but not by this driver */
  386. .flags = (MSI_FLAG_USE_DEF_DOM_OPS | MSI_FLAG_USE_DEF_CHIP_OPS),
  387. .chip = &brcm_msi_irq_chip,
  388. };
  389. static void brcm_pcie_msi_isr(struct irq_desc *desc)
  390. {
  391. struct irq_chip *chip = irq_desc_get_chip(desc);
  392. unsigned long status, virq;
  393. struct brcm_msi *msi;
  394. struct device *dev;
  395. u32 bit;
  396. chained_irq_enter(chip, desc);
  397. msi = irq_desc_get_handler_data(desc);
  398. dev = msi->dev;
  399. status = readl(msi->intr_base + MSI_INT_STATUS);
  400. status >>= msi->legacy_shift;
  401. for_each_set_bit(bit, &status, msi->nr) {
  402. virq = irq_find_mapping(msi->inner_domain, bit);
  403. if (virq)
  404. generic_handle_irq(virq);
  405. else
  406. dev_dbg(dev, "unexpected MSI\n");
  407. }
  408. chained_irq_exit(chip, desc);
  409. }
  410. static void brcm_msi_compose_msi_msg(struct irq_data *data, struct msi_msg *msg)
  411. {
  412. struct brcm_msi *msi = irq_data_get_irq_chip_data(data);
  413. msg->address_lo = lower_32_bits(msi->target_addr);
  414. msg->address_hi = upper_32_bits(msi->target_addr);
  415. msg->data = (0xffff & PCIE_MISC_MSI_DATA_CONFIG_VAL_32) | data->hwirq;
  416. }
  417. static int brcm_msi_set_affinity(struct irq_data *irq_data,
  418. const struct cpumask *mask, bool force)
  419. {
  420. return -EINVAL;
  421. }
  422. static void brcm_msi_ack_irq(struct irq_data *data)
  423. {
  424. struct brcm_msi *msi = irq_data_get_irq_chip_data(data);
  425. const int shift_amt = data->hwirq + msi->legacy_shift;
  426. writel(1 << shift_amt, msi->intr_base + MSI_INT_CLR);
  427. }
  428. static struct irq_chip brcm_msi_bottom_irq_chip = {
  429. .name = "BRCM STB MSI",
  430. .irq_compose_msi_msg = brcm_msi_compose_msi_msg,
  431. .irq_set_affinity = brcm_msi_set_affinity,
  432. .irq_ack = brcm_msi_ack_irq,
  433. };
  434. static int brcm_msi_alloc(struct brcm_msi *msi)
  435. {
  436. int hwirq;
  437. mutex_lock(&msi->lock);
  438. hwirq = bitmap_find_free_region(&msi->used, msi->nr, 0);
  439. mutex_unlock(&msi->lock);
  440. return hwirq;
  441. }
  442. static void brcm_msi_free(struct brcm_msi *msi, unsigned long hwirq)
  443. {
  444. mutex_lock(&msi->lock);
  445. bitmap_release_region(&msi->used, hwirq, 0);
  446. mutex_unlock(&msi->lock);
  447. }
  448. static int brcm_irq_domain_alloc(struct irq_domain *domain, unsigned int virq,
  449. unsigned int nr_irqs, void *args)
  450. {
  451. struct brcm_msi *msi = domain->host_data;
  452. int hwirq;
  453. hwirq = brcm_msi_alloc(msi);
  454. if (hwirq < 0)
  455. return hwirq;
  456. irq_domain_set_info(domain, virq, (irq_hw_number_t)hwirq,
  457. &brcm_msi_bottom_irq_chip, domain->host_data,
  458. handle_edge_irq, NULL, NULL);
  459. return 0;
  460. }
  461. static void brcm_irq_domain_free(struct irq_domain *domain,
  462. unsigned int virq, unsigned int nr_irqs)
  463. {
  464. struct irq_data *d = irq_domain_get_irq_data(domain, virq);
  465. struct brcm_msi *msi = irq_data_get_irq_chip_data(d);
  466. brcm_msi_free(msi, d->hwirq);
  467. }
  468. static const struct irq_domain_ops msi_domain_ops = {
  469. .alloc = brcm_irq_domain_alloc,
  470. .free = brcm_irq_domain_free,
  471. };
  472. static int brcm_allocate_domains(struct brcm_msi *msi)
  473. {
  474. struct fwnode_handle *fwnode = of_node_to_fwnode(msi->np);
  475. struct device *dev = msi->dev;
  476. msi->inner_domain = irq_domain_add_linear(NULL, msi->nr, &msi_domain_ops, msi);
  477. if (!msi->inner_domain) {
  478. dev_err(dev, "failed to create IRQ domain\n");
  479. return -ENOMEM;
  480. }
  481. msi->msi_domain = pci_msi_create_irq_domain(fwnode,
  482. &brcm_msi_domain_info,
  483. msi->inner_domain);
  484. if (!msi->msi_domain) {
  485. dev_err(dev, "failed to create MSI domain\n");
  486. irq_domain_remove(msi->inner_domain);
  487. return -ENOMEM;
  488. }
  489. return 0;
  490. }
  491. static void brcm_free_domains(struct brcm_msi *msi)
  492. {
  493. irq_domain_remove(msi->msi_domain);
  494. irq_domain_remove(msi->inner_domain);
  495. }
  496. static void brcm_msi_remove(struct brcm_pcie *pcie)
  497. {
  498. struct brcm_msi *msi = pcie->msi;
  499. if (!msi)
  500. return;
  501. irq_set_chained_handler(msi->irq, NULL);
  502. irq_set_handler_data(msi->irq, NULL);
  503. brcm_free_domains(msi);
  504. }
  505. static void brcm_msi_set_regs(struct brcm_msi *msi)
  506. {
  507. u32 val = __GENMASK(31, msi->legacy_shift);
  508. writel(val, msi->intr_base + MSI_INT_MASK_CLR);
  509. writel(val, msi->intr_base + MSI_INT_CLR);
  510. /*
  511. * The 0 bit of PCIE_MISC_MSI_BAR_CONFIG_LO is repurposed to MSI
  512. * enable, which we set to 1.
  513. */
  514. writel(lower_32_bits(msi->target_addr) | 0x1,
  515. msi->base + PCIE_MISC_MSI_BAR_CONFIG_LO);
  516. writel(upper_32_bits(msi->target_addr),
  517. msi->base + PCIE_MISC_MSI_BAR_CONFIG_HI);
  518. val = msi->legacy ? PCIE_MISC_MSI_DATA_CONFIG_VAL_8 : PCIE_MISC_MSI_DATA_CONFIG_VAL_32;
  519. writel(val, msi->base + PCIE_MISC_MSI_DATA_CONFIG);
  520. }
  521. static int brcm_pcie_enable_msi(struct brcm_pcie *pcie)
  522. {
  523. struct brcm_msi *msi;
  524. int irq, ret;
  525. struct device *dev = pcie->dev;
  526. irq = irq_of_parse_and_map(dev->of_node, 1);
  527. if (irq <= 0) {
  528. dev_err(dev, "cannot map MSI interrupt\n");
  529. return -ENODEV;
  530. }
  531. msi = devm_kzalloc(dev, sizeof(struct brcm_msi), GFP_KERNEL);
  532. if (!msi)
  533. return -ENOMEM;
  534. mutex_init(&msi->lock);
  535. msi->dev = dev;
  536. msi->base = pcie->base;
  537. msi->np = pcie->np;
  538. msi->target_addr = pcie->msi_target_addr;
  539. msi->irq = irq;
  540. msi->legacy = pcie->hw_rev < BRCM_PCIE_HW_REV_33;
  541. if (msi->legacy) {
  542. msi->intr_base = msi->base + PCIE_INTR2_CPU_BASE;
  543. msi->nr = BRCM_INT_PCI_MSI_LEGACY_NR;
  544. msi->legacy_shift = 24;
  545. } else {
  546. msi->intr_base = msi->base + PCIE_MSI_INTR2_BASE;
  547. msi->nr = BRCM_INT_PCI_MSI_NR;
  548. msi->legacy_shift = 0;
  549. }
  550. ret = brcm_allocate_domains(msi);
  551. if (ret)
  552. return ret;
  553. irq_set_chained_handler_and_data(msi->irq, brcm_pcie_msi_isr, msi);
  554. brcm_msi_set_regs(msi);
  555. pcie->msi = msi;
  556. return 0;
  557. }
  558. /* The controller is capable of serving in both RC and EP roles */
  559. static bool brcm_pcie_rc_mode(struct brcm_pcie *pcie)
  560. {
  561. void __iomem *base = pcie->base;
  562. u32 val = readl(base + PCIE_MISC_PCIE_STATUS);
  563. return !!FIELD_GET(PCIE_MISC_PCIE_STATUS_PCIE_PORT_MASK, val);
  564. }
  565. static bool brcm_pcie_link_up(struct brcm_pcie *pcie)
  566. {
  567. u32 val = readl(pcie->base + PCIE_MISC_PCIE_STATUS);
  568. u32 dla = FIELD_GET(PCIE_MISC_PCIE_STATUS_PCIE_DL_ACTIVE_MASK, val);
  569. u32 plu = FIELD_GET(PCIE_MISC_PCIE_STATUS_PCIE_PHYLINKUP_MASK, val);
  570. return dla && plu;
  571. }
  572. /* Configuration space read/write support */
  573. static inline int brcm_pcie_cfg_index(int busnr, int devfn, int reg)
  574. {
  575. return ((PCI_SLOT(devfn) & 0x1f) << PCIE_EXT_SLOT_SHIFT)
  576. | ((PCI_FUNC(devfn) & 0x07) << PCIE_EXT_FUNC_SHIFT)
  577. | (busnr << PCIE_EXT_BUSNUM_SHIFT)
  578. | (reg & ~3);
  579. }
  580. static void __iomem *brcm_pcie_map_conf(struct pci_bus *bus, unsigned int devfn,
  581. int where)
  582. {
  583. struct brcm_pcie *pcie = bus->sysdata;
  584. void __iomem *base = pcie->base;
  585. int idx;
  586. /* Accesses to the RC go right to the RC registers if slot==0 */
  587. if (pci_is_root_bus(bus))
  588. return PCI_SLOT(devfn) ? NULL : base + where;
  589. /* For devices, write to the config space index register */
  590. idx = brcm_pcie_cfg_index(bus->number, devfn, 0);
  591. writel(idx, pcie->base + PCIE_EXT_CFG_INDEX);
  592. return base + PCIE_EXT_CFG_DATA + where;
  593. }
  594. static struct pci_ops brcm_pcie_ops = {
  595. .map_bus = brcm_pcie_map_conf,
  596. .read = pci_generic_config_read,
  597. .write = pci_generic_config_write,
  598. };
  599. static inline void brcm_pcie_bridge_sw_init_set_generic(struct brcm_pcie *pcie, u32 val)
  600. {
  601. u32 tmp, mask = RGR1_SW_INIT_1_INIT_GENERIC_MASK;
  602. u32 shift = RGR1_SW_INIT_1_INIT_GENERIC_SHIFT;
  603. tmp = readl(pcie->base + PCIE_RGR1_SW_INIT_1(pcie));
  604. tmp = (tmp & ~mask) | ((val << shift) & mask);
  605. writel(tmp, pcie->base + PCIE_RGR1_SW_INIT_1(pcie));
  606. }
  607. static inline void brcm_pcie_bridge_sw_init_set_7278(struct brcm_pcie *pcie, u32 val)
  608. {
  609. u32 tmp, mask = RGR1_SW_INIT_1_INIT_7278_MASK;
  610. u32 shift = RGR1_SW_INIT_1_INIT_7278_SHIFT;
  611. tmp = readl(pcie->base + PCIE_RGR1_SW_INIT_1(pcie));
  612. tmp = (tmp & ~mask) | ((val << shift) & mask);
  613. writel(tmp, pcie->base + PCIE_RGR1_SW_INIT_1(pcie));
  614. }
  615. static inline void brcm_pcie_perst_set_7278(struct brcm_pcie *pcie, u32 val)
  616. {
  617. u32 tmp;
  618. /* Perst bit has moved and assert value is 0 */
  619. tmp = readl(pcie->base + PCIE_MISC_PCIE_CTRL);
  620. u32p_replace_bits(&tmp, !val, PCIE_MISC_PCIE_CTRL_PCIE_PERSTB_MASK);
  621. writel(tmp, pcie->base + PCIE_MISC_PCIE_CTRL);
  622. }
  623. static inline void brcm_pcie_perst_set_generic(struct brcm_pcie *pcie, u32 val)
  624. {
  625. u32 tmp;
  626. tmp = readl(pcie->base + PCIE_RGR1_SW_INIT_1(pcie));
  627. u32p_replace_bits(&tmp, val, PCIE_RGR1_SW_INIT_1_PERST_MASK);
  628. writel(tmp, pcie->base + PCIE_RGR1_SW_INIT_1(pcie));
  629. }
  630. static inline int brcm_pcie_get_rc_bar2_size_and_offset(struct brcm_pcie *pcie,
  631. u64 *rc_bar2_size,
  632. u64 *rc_bar2_offset)
  633. {
  634. struct pci_host_bridge *bridge = pci_host_bridge_from_priv(pcie);
  635. struct resource_entry *entry;
  636. struct device *dev = pcie->dev;
  637. u64 lowest_pcie_addr = ~(u64)0;
  638. int ret, i = 0;
  639. u64 size = 0;
  640. resource_list_for_each_entry(entry, &bridge->dma_ranges) {
  641. u64 pcie_beg = entry->res->start - entry->offset;
  642. size += entry->res->end - entry->res->start + 1;
  643. if (pcie_beg < lowest_pcie_addr)
  644. lowest_pcie_addr = pcie_beg;
  645. }
  646. if (lowest_pcie_addr == ~(u64)0) {
  647. dev_err(dev, "DT node has no dma-ranges\n");
  648. return -EINVAL;
  649. }
  650. ret = of_property_read_variable_u64_array(pcie->np, "brcm,scb-sizes", pcie->memc_size, 1,
  651. PCIE_BRCM_MAX_MEMC);
  652. if (ret <= 0) {
  653. /* Make an educated guess */
  654. pcie->num_memc = 1;
  655. pcie->memc_size[0] = 1ULL << fls64(size - 1);
  656. } else {
  657. pcie->num_memc = ret;
  658. }
  659. /* Each memc is viewed through a "port" that is a power of 2 */
  660. for (i = 0, size = 0; i < pcie->num_memc; i++)
  661. size += pcie->memc_size[i];
  662. /* System memory starts at this address in PCIe-space */
  663. *rc_bar2_offset = lowest_pcie_addr;
  664. /* The sum of all memc views must also be a power of 2 */
  665. *rc_bar2_size = 1ULL << fls64(size - 1);
  666. /*
  667. * We validate the inbound memory view even though we should trust
  668. * whatever the device-tree provides. This is because of an HW issue on
  669. * early Raspberry Pi 4's revisions (bcm2711). It turns out its
  670. * firmware has to dynamically edit dma-ranges due to a bug on the
  671. * PCIe controller integration, which prohibits any access above the
  672. * lower 3GB of memory. Given this, we decided to keep the dma-ranges
  673. * in check, avoiding hard to debug device-tree related issues in the
  674. * future:
  675. *
  676. * The PCIe host controller by design must set the inbound viewport to
  677. * be a contiguous arrangement of all of the system's memory. In
  678. * addition, its size mut be a power of two. To further complicate
  679. * matters, the viewport must start on a pcie-address that is aligned
  680. * on a multiple of its size. If a portion of the viewport does not
  681. * represent system memory -- e.g. 3GB of memory requires a 4GB
  682. * viewport -- we can map the outbound memory in or after 3GB and even
  683. * though the viewport will overlap the outbound memory the controller
  684. * will know to send outbound memory downstream and everything else
  685. * upstream.
  686. *
  687. * For example:
  688. *
  689. * - The best-case scenario, memory up to 3GB, is to place the inbound
  690. * region in the first 4GB of pcie-space, as some legacy devices can
  691. * only address 32bits. We would also like to put the MSI under 4GB
  692. * as well, since some devices require a 32bit MSI target address.
  693. *
  694. * - If the system memory is 4GB or larger we cannot start the inbound
  695. * region at location 0 (since we have to allow some space for
  696. * outbound memory @ 3GB). So instead it will start at the 1x
  697. * multiple of its size
  698. */
  699. if (!*rc_bar2_size || (*rc_bar2_offset & (*rc_bar2_size - 1)) ||
  700. (*rc_bar2_offset < SZ_4G && *rc_bar2_offset > SZ_2G)) {
  701. dev_err(dev, "Invalid rc_bar2_offset/size: size 0x%llx, off 0x%llx\n",
  702. *rc_bar2_size, *rc_bar2_offset);
  703. return -EINVAL;
  704. }
  705. return 0;
  706. }
  707. static int brcm_pcie_setup(struct brcm_pcie *pcie)
  708. {
  709. struct pci_host_bridge *bridge = pci_host_bridge_from_priv(pcie);
  710. u64 rc_bar2_offset, rc_bar2_size;
  711. void __iomem *base = pcie->base;
  712. struct device *dev = pcie->dev;
  713. struct resource_entry *entry;
  714. bool ssc_good = false;
  715. struct resource *res;
  716. int num_out_wins = 0;
  717. u16 nlw, cls, lnksta;
  718. int i, ret, memc;
  719. u32 tmp, burst, aspm_support;
  720. /* Reset the bridge */
  721. pcie->bridge_sw_init_set(pcie, 1);
  722. usleep_range(100, 200);
  723. /* Take the bridge out of reset */
  724. pcie->bridge_sw_init_set(pcie, 0);
  725. tmp = readl(base + PCIE_MISC_HARD_PCIE_HARD_DEBUG);
  726. tmp &= ~PCIE_MISC_HARD_PCIE_HARD_DEBUG_SERDES_IDDQ_MASK;
  727. writel(tmp, base + PCIE_MISC_HARD_PCIE_HARD_DEBUG);
  728. /* Wait for SerDes to be stable */
  729. usleep_range(100, 200);
  730. /*
  731. * SCB_MAX_BURST_SIZE is a two bit field. For GENERIC chips it
  732. * is encoded as 0=128, 1=256, 2=512, 3=Rsvd, for BCM7278 it
  733. * is encoded as 0=Rsvd, 1=128, 2=256, 3=512.
  734. */
  735. if (pcie->type == BCM2711)
  736. burst = 0x0; /* 128B */
  737. else if (pcie->type == BCM7278)
  738. burst = 0x3; /* 512 bytes */
  739. else
  740. burst = 0x2; /* 512 bytes */
  741. /* Set SCB_MAX_BURST_SIZE, CFG_READ_UR_MODE, SCB_ACCESS_EN */
  742. tmp = readl(base + PCIE_MISC_MISC_CTRL);
  743. u32p_replace_bits(&tmp, 1, PCIE_MISC_MISC_CTRL_SCB_ACCESS_EN_MASK);
  744. u32p_replace_bits(&tmp, 1, PCIE_MISC_MISC_CTRL_CFG_READ_UR_MODE_MASK);
  745. u32p_replace_bits(&tmp, burst, PCIE_MISC_MISC_CTRL_MAX_BURST_SIZE_MASK);
  746. writel(tmp, base + PCIE_MISC_MISC_CTRL);
  747. ret = brcm_pcie_get_rc_bar2_size_and_offset(pcie, &rc_bar2_size,
  748. &rc_bar2_offset);
  749. if (ret)
  750. return ret;
  751. tmp = lower_32_bits(rc_bar2_offset);
  752. u32p_replace_bits(&tmp, brcm_pcie_encode_ibar_size(rc_bar2_size),
  753. PCIE_MISC_RC_BAR2_CONFIG_LO_SIZE_MASK);
  754. writel(tmp, base + PCIE_MISC_RC_BAR2_CONFIG_LO);
  755. writel(upper_32_bits(rc_bar2_offset),
  756. base + PCIE_MISC_RC_BAR2_CONFIG_HI);
  757. tmp = readl(base + PCIE_MISC_MISC_CTRL);
  758. for (memc = 0; memc < pcie->num_memc; memc++) {
  759. u32 scb_size_val = ilog2(pcie->memc_size[memc]) - 15;
  760. if (memc == 0)
  761. u32p_replace_bits(&tmp, scb_size_val, SCB_SIZE_MASK(0));
  762. else if (memc == 1)
  763. u32p_replace_bits(&tmp, scb_size_val, SCB_SIZE_MASK(1));
  764. else if (memc == 2)
  765. u32p_replace_bits(&tmp, scb_size_val, SCB_SIZE_MASK(2));
  766. }
  767. writel(tmp, base + PCIE_MISC_MISC_CTRL);
  768. /*
  769. * We ideally want the MSI target address to be located in the 32bit
  770. * addressable memory area. Some devices might depend on it. This is
  771. * possible either when the inbound window is located above the lower
  772. * 4GB or when the inbound area is smaller than 4GB (taking into
  773. * account the rounding-up we're forced to perform).
  774. */
  775. if (rc_bar2_offset >= SZ_4G || (rc_bar2_size + rc_bar2_offset) < SZ_4G)
  776. pcie->msi_target_addr = BRCM_MSI_TARGET_ADDR_LT_4GB;
  777. else
  778. pcie->msi_target_addr = BRCM_MSI_TARGET_ADDR_GT_4GB;
  779. /* disable the PCIe->GISB memory window (RC_BAR1) */
  780. tmp = readl(base + PCIE_MISC_RC_BAR1_CONFIG_LO);
  781. tmp &= ~PCIE_MISC_RC_BAR1_CONFIG_LO_SIZE_MASK;
  782. writel(tmp, base + PCIE_MISC_RC_BAR1_CONFIG_LO);
  783. /* disable the PCIe->SCB memory window (RC_BAR3) */
  784. tmp = readl(base + PCIE_MISC_RC_BAR3_CONFIG_LO);
  785. tmp &= ~PCIE_MISC_RC_BAR3_CONFIG_LO_SIZE_MASK;
  786. writel(tmp, base + PCIE_MISC_RC_BAR3_CONFIG_LO);
  787. if (pcie->gen)
  788. brcm_pcie_set_gen(pcie, pcie->gen);
  789. /* Unassert the fundamental reset */
  790. pcie->perst_set(pcie, 0);
  791. /*
  792. * Give the RC/EP time to wake up, before trying to configure RC.
  793. * Intermittently check status for link-up, up to a total of 100ms.
  794. */
  795. for (i = 0; i < 100 && !brcm_pcie_link_up(pcie); i += 5)
  796. msleep(5);
  797. if (!brcm_pcie_link_up(pcie)) {
  798. dev_err(dev, "link down\n");
  799. return -ENODEV;
  800. }
  801. if (!brcm_pcie_rc_mode(pcie)) {
  802. dev_err(dev, "PCIe misconfigured; is in EP mode\n");
  803. return -EINVAL;
  804. }
  805. resource_list_for_each_entry(entry, &bridge->windows) {
  806. res = entry->res;
  807. if (resource_type(res) != IORESOURCE_MEM)
  808. continue;
  809. if (num_out_wins >= BRCM_NUM_PCIE_OUT_WINS) {
  810. dev_err(pcie->dev, "too many outbound wins\n");
  811. return -EINVAL;
  812. }
  813. brcm_pcie_set_outbound_win(pcie, num_out_wins, res->start,
  814. res->start - entry->offset,
  815. resource_size(res));
  816. num_out_wins++;
  817. }
  818. /* Don't advertise L0s capability if 'aspm-no-l0s' */
  819. aspm_support = PCIE_LINK_STATE_L1;
  820. if (!of_property_read_bool(pcie->np, "aspm-no-l0s"))
  821. aspm_support |= PCIE_LINK_STATE_L0S;
  822. tmp = readl(base + PCIE_RC_CFG_PRIV1_LINK_CAPABILITY);
  823. u32p_replace_bits(&tmp, aspm_support,
  824. PCIE_RC_CFG_PRIV1_LINK_CAPABILITY_ASPM_SUPPORT_MASK);
  825. writel(tmp, base + PCIE_RC_CFG_PRIV1_LINK_CAPABILITY);
  826. /*
  827. * For config space accesses on the RC, show the right class for
  828. * a PCIe-PCIe bridge (the default setting is to be EP mode).
  829. */
  830. tmp = readl(base + PCIE_RC_CFG_PRIV1_ID_VAL3);
  831. u32p_replace_bits(&tmp, 0x060400,
  832. PCIE_RC_CFG_PRIV1_ID_VAL3_CLASS_CODE_MASK);
  833. writel(tmp, base + PCIE_RC_CFG_PRIV1_ID_VAL3);
  834. if (pcie->ssc) {
  835. ret = brcm_pcie_set_ssc(pcie);
  836. if (ret == 0)
  837. ssc_good = true;
  838. else
  839. dev_err(dev, "failed attempt to enter ssc mode\n");
  840. }
  841. lnksta = readw(base + BRCM_PCIE_CAP_REGS + PCI_EXP_LNKSTA);
  842. cls = FIELD_GET(PCI_EXP_LNKSTA_CLS, lnksta);
  843. nlw = FIELD_GET(PCI_EXP_LNKSTA_NLW, lnksta);
  844. dev_info(dev, "link up, %s x%u %s\n",
  845. pci_speed_string(pcie_link_speed[cls]), nlw,
  846. ssc_good ? "(SSC)" : "(!SSC)");
  847. /* PCIe->SCB endian mode for BAR */
  848. tmp = readl(base + PCIE_RC_CFG_VENDOR_VENDOR_SPECIFIC_REG1);
  849. u32p_replace_bits(&tmp, PCIE_RC_CFG_VENDOR_SPCIFIC_REG1_LITTLE_ENDIAN,
  850. PCIE_RC_CFG_VENDOR_VENDOR_SPECIFIC_REG1_ENDIAN_MODE_BAR2_MASK);
  851. writel(tmp, base + PCIE_RC_CFG_VENDOR_VENDOR_SPECIFIC_REG1);
  852. /*
  853. * Refclk from RC should be gated with CLKREQ# input when ASPM L0s,L1
  854. * is enabled => setting the CLKREQ_DEBUG_ENABLE field to 1.
  855. */
  856. tmp = readl(base + PCIE_MISC_HARD_PCIE_HARD_DEBUG);
  857. tmp |= PCIE_MISC_HARD_PCIE_HARD_DEBUG_CLKREQ_DEBUG_ENABLE_MASK;
  858. writel(tmp, base + PCIE_MISC_HARD_PCIE_HARD_DEBUG);
  859. return 0;
  860. }
  861. /* L23 is a low-power PCIe link state */
  862. static void brcm_pcie_enter_l23(struct brcm_pcie *pcie)
  863. {
  864. void __iomem *base = pcie->base;
  865. int l23, i;
  866. u32 tmp;
  867. /* Assert request for L23 */
  868. tmp = readl(base + PCIE_MISC_PCIE_CTRL);
  869. u32p_replace_bits(&tmp, 1, PCIE_MISC_PCIE_CTRL_PCIE_L23_REQUEST_MASK);
  870. writel(tmp, base + PCIE_MISC_PCIE_CTRL);
  871. /* Wait up to 36 msec for L23 */
  872. tmp = readl(base + PCIE_MISC_PCIE_STATUS);
  873. l23 = FIELD_GET(PCIE_MISC_PCIE_STATUS_PCIE_LINK_IN_L23_MASK, tmp);
  874. for (i = 0; i < 15 && !l23; i++) {
  875. usleep_range(2000, 2400);
  876. tmp = readl(base + PCIE_MISC_PCIE_STATUS);
  877. l23 = FIELD_GET(PCIE_MISC_PCIE_STATUS_PCIE_LINK_IN_L23_MASK,
  878. tmp);
  879. }
  880. if (!l23)
  881. dev_err(pcie->dev, "failed to enter low-power link state\n");
  882. }
  883. static int brcm_phy_cntl(struct brcm_pcie *pcie, const int start)
  884. {
  885. static const u32 shifts[PCIE_DVT_PMU_PCIE_PHY_CTRL_DAST_NFLDS] = {
  886. PCIE_DVT_PMU_PCIE_PHY_CTRL_DAST_PWRDN_SHIFT,
  887. PCIE_DVT_PMU_PCIE_PHY_CTRL_DAST_RESET_SHIFT,
  888. PCIE_DVT_PMU_PCIE_PHY_CTRL_DAST_DIG_RESET_SHIFT,};
  889. static const u32 masks[PCIE_DVT_PMU_PCIE_PHY_CTRL_DAST_NFLDS] = {
  890. PCIE_DVT_PMU_PCIE_PHY_CTRL_DAST_PWRDN_MASK,
  891. PCIE_DVT_PMU_PCIE_PHY_CTRL_DAST_RESET_MASK,
  892. PCIE_DVT_PMU_PCIE_PHY_CTRL_DAST_DIG_RESET_MASK,};
  893. const int beg = start ? 0 : PCIE_DVT_PMU_PCIE_PHY_CTRL_DAST_NFLDS - 1;
  894. const int end = start ? PCIE_DVT_PMU_PCIE_PHY_CTRL_DAST_NFLDS : -1;
  895. u32 tmp, combined_mask = 0;
  896. u32 val;
  897. void __iomem *base = pcie->base;
  898. int i, ret;
  899. for (i = beg; i != end; start ? i++ : i--) {
  900. val = start ? BIT_MASK(shifts[i]) : 0;
  901. tmp = readl(base + PCIE_DVT_PMU_PCIE_PHY_CTRL);
  902. tmp = (tmp & ~masks[i]) | (val & masks[i]);
  903. writel(tmp, base + PCIE_DVT_PMU_PCIE_PHY_CTRL);
  904. usleep_range(50, 200);
  905. combined_mask |= masks[i];
  906. }
  907. tmp = readl(base + PCIE_DVT_PMU_PCIE_PHY_CTRL);
  908. val = start ? combined_mask : 0;
  909. ret = (tmp & combined_mask) == val ? 0 : -EIO;
  910. if (ret)
  911. dev_err(pcie->dev, "failed to %s phy\n", (start ? "start" : "stop"));
  912. return ret;
  913. }
  914. static inline int brcm_phy_start(struct brcm_pcie *pcie)
  915. {
  916. return pcie->rescal ? brcm_phy_cntl(pcie, 1) : 0;
  917. }
  918. static inline int brcm_phy_stop(struct brcm_pcie *pcie)
  919. {
  920. return pcie->rescal ? brcm_phy_cntl(pcie, 0) : 0;
  921. }
  922. static void brcm_pcie_turn_off(struct brcm_pcie *pcie)
  923. {
  924. void __iomem *base = pcie->base;
  925. int tmp;
  926. if (brcm_pcie_link_up(pcie))
  927. brcm_pcie_enter_l23(pcie);
  928. /* Assert fundamental reset */
  929. pcie->perst_set(pcie, 1);
  930. /* Deassert request for L23 in case it was asserted */
  931. tmp = readl(base + PCIE_MISC_PCIE_CTRL);
  932. u32p_replace_bits(&tmp, 0, PCIE_MISC_PCIE_CTRL_PCIE_L23_REQUEST_MASK);
  933. writel(tmp, base + PCIE_MISC_PCIE_CTRL);
  934. /* Turn off SerDes */
  935. tmp = readl(base + PCIE_MISC_HARD_PCIE_HARD_DEBUG);
  936. u32p_replace_bits(&tmp, 1, PCIE_MISC_HARD_PCIE_HARD_DEBUG_SERDES_IDDQ_MASK);
  937. writel(tmp, base + PCIE_MISC_HARD_PCIE_HARD_DEBUG);
  938. /* Shutdown PCIe bridge */
  939. pcie->bridge_sw_init_set(pcie, 1);
  940. }
  941. static int brcm_pcie_suspend(struct device *dev)
  942. {
  943. struct brcm_pcie *pcie = dev_get_drvdata(dev);
  944. int ret;
  945. brcm_pcie_turn_off(pcie);
  946. ret = brcm_phy_stop(pcie);
  947. clk_disable_unprepare(pcie->clk);
  948. return ret;
  949. }
  950. static int brcm_pcie_resume(struct device *dev)
  951. {
  952. struct brcm_pcie *pcie = dev_get_drvdata(dev);
  953. void __iomem *base;
  954. u32 tmp;
  955. int ret;
  956. base = pcie->base;
  957. clk_prepare_enable(pcie->clk);
  958. ret = brcm_phy_start(pcie);
  959. if (ret)
  960. goto err;
  961. /* Take bridge out of reset so we can access the SERDES reg */
  962. pcie->bridge_sw_init_set(pcie, 0);
  963. /* SERDES_IDDQ = 0 */
  964. tmp = readl(base + PCIE_MISC_HARD_PCIE_HARD_DEBUG);
  965. u32p_replace_bits(&tmp, 0, PCIE_MISC_HARD_PCIE_HARD_DEBUG_SERDES_IDDQ_MASK);
  966. writel(tmp, base + PCIE_MISC_HARD_PCIE_HARD_DEBUG);
  967. /* wait for serdes to be stable */
  968. udelay(100);
  969. ret = brcm_pcie_setup(pcie);
  970. if (ret)
  971. goto err;
  972. if (pcie->msi)
  973. brcm_msi_set_regs(pcie->msi);
  974. return 0;
  975. err:
  976. clk_disable_unprepare(pcie->clk);
  977. return ret;
  978. }
  979. static void __brcm_pcie_remove(struct brcm_pcie *pcie)
  980. {
  981. brcm_msi_remove(pcie);
  982. brcm_pcie_turn_off(pcie);
  983. brcm_phy_stop(pcie);
  984. reset_control_assert(pcie->rescal);
  985. clk_disable_unprepare(pcie->clk);
  986. }
  987. static int brcm_pcie_remove(struct platform_device *pdev)
  988. {
  989. struct brcm_pcie *pcie = platform_get_drvdata(pdev);
  990. struct pci_host_bridge *bridge = pci_host_bridge_from_priv(pcie);
  991. pci_stop_root_bus(bridge->bus);
  992. pci_remove_root_bus(bridge->bus);
  993. __brcm_pcie_remove(pcie);
  994. return 0;
  995. }
  996. static const struct of_device_id brcm_pcie_match[] = {
  997. { .compatible = "brcm,bcm2711-pcie", .data = &bcm2711_cfg },
  998. { .compatible = "brcm,bcm7211-pcie", .data = &generic_cfg },
  999. { .compatible = "brcm,bcm7278-pcie", .data = &bcm7278_cfg },
  1000. { .compatible = "brcm,bcm7216-pcie", .data = &bcm7278_cfg },
  1001. { .compatible = "brcm,bcm7445-pcie", .data = &generic_cfg },
  1002. {},
  1003. };
  1004. static int brcm_pcie_probe(struct platform_device *pdev)
  1005. {
  1006. struct device_node *np = pdev->dev.of_node, *msi_np;
  1007. struct pci_host_bridge *bridge;
  1008. const struct pcie_cfg_data *data;
  1009. struct brcm_pcie *pcie;
  1010. int ret;
  1011. bridge = devm_pci_alloc_host_bridge(&pdev->dev, sizeof(*pcie));
  1012. if (!bridge)
  1013. return -ENOMEM;
  1014. data = of_device_get_match_data(&pdev->dev);
  1015. if (!data) {
  1016. pr_err("failed to look up compatible string\n");
  1017. return -EINVAL;
  1018. }
  1019. pcie = pci_host_bridge_priv(bridge);
  1020. pcie->dev = &pdev->dev;
  1021. pcie->np = np;
  1022. pcie->reg_offsets = data->offsets;
  1023. pcie->type = data->type;
  1024. pcie->perst_set = data->perst_set;
  1025. pcie->bridge_sw_init_set = data->bridge_sw_init_set;
  1026. pcie->base = devm_platform_ioremap_resource(pdev, 0);
  1027. if (IS_ERR(pcie->base))
  1028. return PTR_ERR(pcie->base);
  1029. pcie->clk = devm_clk_get_optional(&pdev->dev, "sw_pcie");
  1030. if (IS_ERR(pcie->clk))
  1031. return PTR_ERR(pcie->clk);
  1032. ret = of_pci_get_max_link_speed(np);
  1033. pcie->gen = (ret < 0) ? 0 : ret;
  1034. pcie->ssc = of_property_read_bool(np, "brcm,enable-ssc");
  1035. ret = clk_prepare_enable(pcie->clk);
  1036. if (ret) {
  1037. dev_err(&pdev->dev, "could not enable clock\n");
  1038. return ret;
  1039. }
  1040. pcie->rescal = devm_reset_control_get_optional_shared(&pdev->dev, "rescal");
  1041. if (IS_ERR(pcie->rescal)) {
  1042. clk_disable_unprepare(pcie->clk);
  1043. return PTR_ERR(pcie->rescal);
  1044. }
  1045. ret = reset_control_deassert(pcie->rescal);
  1046. if (ret)
  1047. dev_err(&pdev->dev, "failed to deassert 'rescal'\n");
  1048. ret = brcm_phy_start(pcie);
  1049. if (ret) {
  1050. reset_control_assert(pcie->rescal);
  1051. clk_disable_unprepare(pcie->clk);
  1052. return ret;
  1053. }
  1054. ret = brcm_pcie_setup(pcie);
  1055. if (ret)
  1056. goto fail;
  1057. pcie->hw_rev = readl(pcie->base + PCIE_MISC_REVISION);
  1058. msi_np = of_parse_phandle(pcie->np, "msi-parent", 0);
  1059. if (pci_msi_enabled() && msi_np == pcie->np) {
  1060. ret = brcm_pcie_enable_msi(pcie);
  1061. if (ret) {
  1062. dev_err(pcie->dev, "probe of internal MSI failed");
  1063. goto fail;
  1064. }
  1065. }
  1066. bridge->ops = &brcm_pcie_ops;
  1067. bridge->sysdata = pcie;
  1068. platform_set_drvdata(pdev, pcie);
  1069. return pci_host_probe(bridge);
  1070. fail:
  1071. __brcm_pcie_remove(pcie);
  1072. return ret;
  1073. }
  1074. MODULE_DEVICE_TABLE(of, brcm_pcie_match);
  1075. static const struct dev_pm_ops brcm_pcie_pm_ops = {
  1076. .suspend = brcm_pcie_suspend,
  1077. .resume = brcm_pcie_resume,
  1078. };
  1079. static struct platform_driver brcm_pcie_driver = {
  1080. .probe = brcm_pcie_probe,
  1081. .remove = brcm_pcie_remove,
  1082. .driver = {
  1083. .name = "brcm-pcie",
  1084. .of_match_table = brcm_pcie_match,
  1085. .pm = &brcm_pcie_pm_ops,
  1086. },
  1087. };
  1088. module_platform_driver(brcm_pcie_driver);
  1089. MODULE_LICENSE("GPL");
  1090. MODULE_DESCRIPTION("Broadcom STB PCIe RC driver");
  1091. MODULE_AUTHOR("Broadcom");