pci-mvebu.c 29 KB

1234567891011121314151617181920212223242526272829303132333435363738394041424344454647484950515253545556575859606162636465666768697071727374757677787980818283848586878889909192939495969798991001011021031041051061071081091101111121131141151161171181191201211221231241251261271281291301311321331341351361371381391401411421431441451461471481491501511521531541551561571581591601611621631641651661671681691701711721731741751761771781791801811821831841851861871881891901911921931941951961971981992002012022032042052062072082092102112122132142152162172182192202212222232242252262272282292302312322332342352362372382392402412422432442452462472482492502512522532542552562572582592602612622632642652662672682692702712722732742752762772782792802812822832842852862872882892902912922932942952962972982993003013023033043053063073083093103113123133143153163173183193203213223233243253263273283293303313323333343353363373383393403413423433443453463473483493503513523533543553563573583593603613623633643653663673683693703713723733743753763773783793803813823833843853863873883893903913923933943953963973983994004014024034044054064074084094104114124134144154164174184194204214224234244254264274284294304314324334344354364374384394404414424434444454464474484494504514524534544554564574584594604614624634644654664674684694704714724734744754764774784794804814824834844854864874884894904914924934944954964974984995005015025035045055065075085095105115125135145155165175185195205215225235245255265275285295305315325335345355365375385395405415425435445455465475485495505515525535545555565575585595605615625635645655665675685695705715725735745755765775785795805815825835845855865875885895905915925935945955965975985996006016026036046056066076086096106116126136146156166176186196206216226236246256266276286296306316326336346356366376386396406416426436446456466476486496506516526536546556566576586596606616626636646656666676686696706716726736746756766776786796806816826836846856866876886896906916926936946956966976986997007017027037047057067077087097107117127137147157167177187197207217227237247257267277287297307317327337347357367377387397407417427437447457467477487497507517527537547557567577587597607617627637647657667677687697707717727737747757767777787797807817827837847857867877887897907917927937947957967977987998008018028038048058068078088098108118128138148158168178188198208218228238248258268278288298308318328338348358368378388398408418428438448458468478488498508518528538548558568578588598608618628638648658668678688698708718728738748758768778788798808818828838848858868878888898908918928938948958968978988999009019029039049059069079089099109119129139149159169179189199209219229239249259269279289299309319329339349359369379389399409419429439449459469479489499509519529539549559569579589599609619629639649659669679689699709719729739749759769779789799809819829839849859869879889899909919929939949959969979989991000100110021003100410051006100710081009101010111012101310141015101610171018101910201021102210231024102510261027102810291030103110321033103410351036103710381039104010411042104310441045104610471048104910501051105210531054105510561057105810591060106110621063106410651066106710681069107010711072107310741075107610771078107910801081108210831084108510861087108810891090109110921093109410951096109710981099110011011102110311041105110611071108110911101111111211131114111511161117111811191120112111221123112411251126112711281129113011311132113311341135113611371138113911401141114211431144114511461147114811491150115111521153115411551156115711581159
  1. // SPDX-License-Identifier: GPL-2.0
  2. /*
  3. * PCIe driver for Marvell Armada 370 and Armada XP SoCs
  4. *
  5. * Author: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
  6. */
  7. #include <linux/kernel.h>
  8. #include <linux/pci.h>
  9. #include <linux/clk.h>
  10. #include <linux/delay.h>
  11. #include <linux/gpio.h>
  12. #include <linux/init.h>
  13. #include <linux/mbus.h>
  14. #include <linux/slab.h>
  15. #include <linux/platform_device.h>
  16. #include <linux/of_address.h>
  17. #include <linux/of_irq.h>
  18. #include <linux/of_gpio.h>
  19. #include <linux/of_pci.h>
  20. #include <linux/of_platform.h>
  21. #include "../pci.h"
  22. #include "../pci-bridge-emul.h"
  23. /*
  24. * PCIe unit register offsets.
  25. */
  26. #define PCIE_DEV_ID_OFF 0x0000
  27. #define PCIE_CMD_OFF 0x0004
  28. #define PCIE_DEV_REV_OFF 0x0008
  29. #define PCIE_BAR_LO_OFF(n) (0x0010 + ((n) << 3))
  30. #define PCIE_BAR_HI_OFF(n) (0x0014 + ((n) << 3))
  31. #define PCIE_CAP_PCIEXP 0x0060
  32. #define PCIE_HEADER_LOG_4_OFF 0x0128
  33. #define PCIE_BAR_CTRL_OFF(n) (0x1804 + (((n) - 1) * 4))
  34. #define PCIE_WIN04_CTRL_OFF(n) (0x1820 + ((n) << 4))
  35. #define PCIE_WIN04_BASE_OFF(n) (0x1824 + ((n) << 4))
  36. #define PCIE_WIN04_REMAP_OFF(n) (0x182c + ((n) << 4))
  37. #define PCIE_WIN5_CTRL_OFF 0x1880
  38. #define PCIE_WIN5_BASE_OFF 0x1884
  39. #define PCIE_WIN5_REMAP_OFF 0x188c
  40. #define PCIE_CONF_ADDR_OFF 0x18f8
  41. #define PCIE_CONF_ADDR_EN 0x80000000
  42. #define PCIE_CONF_REG(r) ((((r) & 0xf00) << 16) | ((r) & 0xfc))
  43. #define PCIE_CONF_BUS(b) (((b) & 0xff) << 16)
  44. #define PCIE_CONF_DEV(d) (((d) & 0x1f) << 11)
  45. #define PCIE_CONF_FUNC(f) (((f) & 0x7) << 8)
  46. #define PCIE_CONF_ADDR(bus, devfn, where) \
  47. (PCIE_CONF_BUS(bus) | PCIE_CONF_DEV(PCI_SLOT(devfn)) | \
  48. PCIE_CONF_FUNC(PCI_FUNC(devfn)) | PCIE_CONF_REG(where) | \
  49. PCIE_CONF_ADDR_EN)
  50. #define PCIE_CONF_DATA_OFF 0x18fc
  51. #define PCIE_MASK_OFF 0x1910
  52. #define PCIE_MASK_ENABLE_INTS 0x0f000000
  53. #define PCIE_CTRL_OFF 0x1a00
  54. #define PCIE_CTRL_X1_MODE 0x0001
  55. #define PCIE_STAT_OFF 0x1a04
  56. #define PCIE_STAT_BUS 0xff00
  57. #define PCIE_STAT_DEV 0x1f0000
  58. #define PCIE_STAT_LINK_DOWN BIT(0)
  59. #define PCIE_RC_RTSTA 0x1a14
  60. #define PCIE_DEBUG_CTRL 0x1a60
  61. #define PCIE_DEBUG_SOFT_RESET BIT(20)
  62. struct mvebu_pcie_port;
  63. /* Structure representing all PCIe interfaces */
  64. struct mvebu_pcie {
  65. struct platform_device *pdev;
  66. struct mvebu_pcie_port *ports;
  67. struct resource io;
  68. struct resource realio;
  69. struct resource mem;
  70. struct resource busn;
  71. int nports;
  72. };
  73. struct mvebu_pcie_window {
  74. phys_addr_t base;
  75. phys_addr_t remap;
  76. size_t size;
  77. };
  78. /* Structure representing one PCIe interface */
  79. struct mvebu_pcie_port {
  80. char *name;
  81. void __iomem *base;
  82. u32 port;
  83. u32 lane;
  84. int devfn;
  85. unsigned int mem_target;
  86. unsigned int mem_attr;
  87. unsigned int io_target;
  88. unsigned int io_attr;
  89. struct clk *clk;
  90. struct gpio_desc *reset_gpio;
  91. char *reset_name;
  92. struct pci_bridge_emul bridge;
  93. struct device_node *dn;
  94. struct mvebu_pcie *pcie;
  95. struct mvebu_pcie_window memwin;
  96. struct mvebu_pcie_window iowin;
  97. u32 saved_pcie_stat;
  98. struct resource regs;
  99. };
  100. static inline void mvebu_writel(struct mvebu_pcie_port *port, u32 val, u32 reg)
  101. {
  102. writel(val, port->base + reg);
  103. }
  104. static inline u32 mvebu_readl(struct mvebu_pcie_port *port, u32 reg)
  105. {
  106. return readl(port->base + reg);
  107. }
  108. static inline bool mvebu_has_ioport(struct mvebu_pcie_port *port)
  109. {
  110. return port->io_target != -1 && port->io_attr != -1;
  111. }
  112. static bool mvebu_pcie_link_up(struct mvebu_pcie_port *port)
  113. {
  114. return !(mvebu_readl(port, PCIE_STAT_OFF) & PCIE_STAT_LINK_DOWN);
  115. }
  116. static void mvebu_pcie_set_local_bus_nr(struct mvebu_pcie_port *port, int nr)
  117. {
  118. u32 stat;
  119. stat = mvebu_readl(port, PCIE_STAT_OFF);
  120. stat &= ~PCIE_STAT_BUS;
  121. stat |= nr << 8;
  122. mvebu_writel(port, stat, PCIE_STAT_OFF);
  123. }
  124. static void mvebu_pcie_set_local_dev_nr(struct mvebu_pcie_port *port, int nr)
  125. {
  126. u32 stat;
  127. stat = mvebu_readl(port, PCIE_STAT_OFF);
  128. stat &= ~PCIE_STAT_DEV;
  129. stat |= nr << 16;
  130. mvebu_writel(port, stat, PCIE_STAT_OFF);
  131. }
  132. /*
  133. * Setup PCIE BARs and Address Decode Wins:
  134. * BAR[0] -> internal registers (needed for MSI)
  135. * BAR[1] -> covers all DRAM banks
  136. * BAR[2] -> Disabled
  137. * WIN[0-3] -> DRAM bank[0-3]
  138. */
  139. static void mvebu_pcie_setup_wins(struct mvebu_pcie_port *port)
  140. {
  141. const struct mbus_dram_target_info *dram;
  142. u32 size;
  143. int i;
  144. dram = mv_mbus_dram_info();
  145. /* First, disable and clear BARs and windows. */
  146. for (i = 1; i < 3; i++) {
  147. mvebu_writel(port, 0, PCIE_BAR_CTRL_OFF(i));
  148. mvebu_writel(port, 0, PCIE_BAR_LO_OFF(i));
  149. mvebu_writel(port, 0, PCIE_BAR_HI_OFF(i));
  150. }
  151. for (i = 0; i < 5; i++) {
  152. mvebu_writel(port, 0, PCIE_WIN04_CTRL_OFF(i));
  153. mvebu_writel(port, 0, PCIE_WIN04_BASE_OFF(i));
  154. mvebu_writel(port, 0, PCIE_WIN04_REMAP_OFF(i));
  155. }
  156. mvebu_writel(port, 0, PCIE_WIN5_CTRL_OFF);
  157. mvebu_writel(port, 0, PCIE_WIN5_BASE_OFF);
  158. mvebu_writel(port, 0, PCIE_WIN5_REMAP_OFF);
  159. /* Setup windows for DDR banks. Count total DDR size on the fly. */
  160. size = 0;
  161. for (i = 0; i < dram->num_cs; i++) {
  162. const struct mbus_dram_window *cs = dram->cs + i;
  163. mvebu_writel(port, cs->base & 0xffff0000,
  164. PCIE_WIN04_BASE_OFF(i));
  165. mvebu_writel(port, 0, PCIE_WIN04_REMAP_OFF(i));
  166. mvebu_writel(port,
  167. ((cs->size - 1) & 0xffff0000) |
  168. (cs->mbus_attr << 8) |
  169. (dram->mbus_dram_target_id << 4) | 1,
  170. PCIE_WIN04_CTRL_OFF(i));
  171. size += cs->size;
  172. }
  173. /* Round up 'size' to the nearest power of two. */
  174. if ((size & (size - 1)) != 0)
  175. size = 1 << fls(size);
  176. /* Setup BAR[1] to all DRAM banks. */
  177. mvebu_writel(port, dram->cs[0].base, PCIE_BAR_LO_OFF(1));
  178. mvebu_writel(port, 0, PCIE_BAR_HI_OFF(1));
  179. mvebu_writel(port, ((size - 1) & 0xffff0000) | 1,
  180. PCIE_BAR_CTRL_OFF(1));
  181. /*
  182. * Point BAR[0] to the device's internal registers.
  183. */
  184. mvebu_writel(port, round_down(port->regs.start, SZ_1M), PCIE_BAR_LO_OFF(0));
  185. mvebu_writel(port, 0, PCIE_BAR_HI_OFF(0));
  186. }
  187. static void mvebu_pcie_setup_hw(struct mvebu_pcie_port *port)
  188. {
  189. u32 cmd, mask;
  190. /* Point PCIe unit MBUS decode windows to DRAM space. */
  191. mvebu_pcie_setup_wins(port);
  192. /* Master + slave enable. */
  193. cmd = mvebu_readl(port, PCIE_CMD_OFF);
  194. cmd |= PCI_COMMAND_IO;
  195. cmd |= PCI_COMMAND_MEMORY;
  196. cmd |= PCI_COMMAND_MASTER;
  197. mvebu_writel(port, cmd, PCIE_CMD_OFF);
  198. /* Enable interrupt lines A-D. */
  199. mask = mvebu_readl(port, PCIE_MASK_OFF);
  200. mask |= PCIE_MASK_ENABLE_INTS;
  201. mvebu_writel(port, mask, PCIE_MASK_OFF);
  202. }
  203. static int mvebu_pcie_hw_rd_conf(struct mvebu_pcie_port *port,
  204. struct pci_bus *bus,
  205. u32 devfn, int where, int size, u32 *val)
  206. {
  207. void __iomem *conf_data = port->base + PCIE_CONF_DATA_OFF;
  208. mvebu_writel(port, PCIE_CONF_ADDR(bus->number, devfn, where),
  209. PCIE_CONF_ADDR_OFF);
  210. switch (size) {
  211. case 1:
  212. *val = readb_relaxed(conf_data + (where & 3));
  213. break;
  214. case 2:
  215. *val = readw_relaxed(conf_data + (where & 2));
  216. break;
  217. case 4:
  218. *val = readl_relaxed(conf_data);
  219. break;
  220. }
  221. return PCIBIOS_SUCCESSFUL;
  222. }
  223. static int mvebu_pcie_hw_wr_conf(struct mvebu_pcie_port *port,
  224. struct pci_bus *bus,
  225. u32 devfn, int where, int size, u32 val)
  226. {
  227. void __iomem *conf_data = port->base + PCIE_CONF_DATA_OFF;
  228. mvebu_writel(port, PCIE_CONF_ADDR(bus->number, devfn, where),
  229. PCIE_CONF_ADDR_OFF);
  230. switch (size) {
  231. case 1:
  232. writeb(val, conf_data + (where & 3));
  233. break;
  234. case 2:
  235. writew(val, conf_data + (where & 2));
  236. break;
  237. case 4:
  238. writel(val, conf_data);
  239. break;
  240. default:
  241. return PCIBIOS_BAD_REGISTER_NUMBER;
  242. }
  243. return PCIBIOS_SUCCESSFUL;
  244. }
  245. /*
  246. * Remove windows, starting from the largest ones to the smallest
  247. * ones.
  248. */
  249. static void mvebu_pcie_del_windows(struct mvebu_pcie_port *port,
  250. phys_addr_t base, size_t size)
  251. {
  252. while (size) {
  253. size_t sz = 1 << (fls(size) - 1);
  254. mvebu_mbus_del_window(base, sz);
  255. base += sz;
  256. size -= sz;
  257. }
  258. }
  259. /*
  260. * MBus windows can only have a power of two size, but PCI BARs do not
  261. * have this constraint. Therefore, we have to split the PCI BAR into
  262. * areas each having a power of two size. We start from the largest
  263. * one (i.e highest order bit set in the size).
  264. */
  265. static void mvebu_pcie_add_windows(struct mvebu_pcie_port *port,
  266. unsigned int target, unsigned int attribute,
  267. phys_addr_t base, size_t size,
  268. phys_addr_t remap)
  269. {
  270. size_t size_mapped = 0;
  271. while (size) {
  272. size_t sz = 1 << (fls(size) - 1);
  273. int ret;
  274. ret = mvebu_mbus_add_window_remap_by_id(target, attribute, base,
  275. sz, remap);
  276. if (ret) {
  277. phys_addr_t end = base + sz - 1;
  278. dev_err(&port->pcie->pdev->dev,
  279. "Could not create MBus window at [mem %pa-%pa]: %d\n",
  280. &base, &end, ret);
  281. mvebu_pcie_del_windows(port, base - size_mapped,
  282. size_mapped);
  283. return;
  284. }
  285. size -= sz;
  286. size_mapped += sz;
  287. base += sz;
  288. if (remap != MVEBU_MBUS_NO_REMAP)
  289. remap += sz;
  290. }
  291. }
  292. static void mvebu_pcie_set_window(struct mvebu_pcie_port *port,
  293. unsigned int target, unsigned int attribute,
  294. const struct mvebu_pcie_window *desired,
  295. struct mvebu_pcie_window *cur)
  296. {
  297. if (desired->base == cur->base && desired->remap == cur->remap &&
  298. desired->size == cur->size)
  299. return;
  300. if (cur->size != 0) {
  301. mvebu_pcie_del_windows(port, cur->base, cur->size);
  302. cur->size = 0;
  303. cur->base = 0;
  304. /*
  305. * If something tries to change the window while it is enabled
  306. * the change will not be done atomically. That would be
  307. * difficult to do in the general case.
  308. */
  309. }
  310. if (desired->size == 0)
  311. return;
  312. mvebu_pcie_add_windows(port, target, attribute, desired->base,
  313. desired->size, desired->remap);
  314. *cur = *desired;
  315. }
  316. static void mvebu_pcie_handle_iobase_change(struct mvebu_pcie_port *port)
  317. {
  318. struct mvebu_pcie_window desired = {};
  319. struct pci_bridge_emul_conf *conf = &port->bridge.conf;
  320. /* Are the new iobase/iolimit values invalid? */
  321. if (conf->iolimit < conf->iobase ||
  322. conf->iolimitupper < conf->iobaseupper ||
  323. !(conf->command & PCI_COMMAND_IO)) {
  324. mvebu_pcie_set_window(port, port->io_target, port->io_attr,
  325. &desired, &port->iowin);
  326. return;
  327. }
  328. if (!mvebu_has_ioport(port)) {
  329. dev_WARN(&port->pcie->pdev->dev,
  330. "Attempt to set IO when IO is disabled\n");
  331. return;
  332. }
  333. /*
  334. * We read the PCI-to-PCI bridge emulated registers, and
  335. * calculate the base address and size of the address decoding
  336. * window to setup, according to the PCI-to-PCI bridge
  337. * specifications. iobase is the bus address, port->iowin_base
  338. * is the CPU address.
  339. */
  340. desired.remap = ((conf->iobase & 0xF0) << 8) |
  341. (conf->iobaseupper << 16);
  342. desired.base = port->pcie->io.start + desired.remap;
  343. desired.size = ((0xFFF | ((conf->iolimit & 0xF0) << 8) |
  344. (conf->iolimitupper << 16)) -
  345. desired.remap) +
  346. 1;
  347. mvebu_pcie_set_window(port, port->io_target, port->io_attr, &desired,
  348. &port->iowin);
  349. }
  350. static void mvebu_pcie_handle_membase_change(struct mvebu_pcie_port *port)
  351. {
  352. struct mvebu_pcie_window desired = {.remap = MVEBU_MBUS_NO_REMAP};
  353. struct pci_bridge_emul_conf *conf = &port->bridge.conf;
  354. /* Are the new membase/memlimit values invalid? */
  355. if (conf->memlimit < conf->membase ||
  356. !(conf->command & PCI_COMMAND_MEMORY)) {
  357. mvebu_pcie_set_window(port, port->mem_target, port->mem_attr,
  358. &desired, &port->memwin);
  359. return;
  360. }
  361. /*
  362. * We read the PCI-to-PCI bridge emulated registers, and
  363. * calculate the base address and size of the address decoding
  364. * window to setup, according to the PCI-to-PCI bridge
  365. * specifications.
  366. */
  367. desired.base = ((conf->membase & 0xFFF0) << 16);
  368. desired.size = (((conf->memlimit & 0xFFF0) << 16) | 0xFFFFF) -
  369. desired.base + 1;
  370. mvebu_pcie_set_window(port, port->mem_target, port->mem_attr, &desired,
  371. &port->memwin);
  372. }
  373. static pci_bridge_emul_read_status_t
  374. mvebu_pci_bridge_emul_pcie_conf_read(struct pci_bridge_emul *bridge,
  375. int reg, u32 *value)
  376. {
  377. struct mvebu_pcie_port *port = bridge->data;
  378. switch (reg) {
  379. case PCI_EXP_DEVCAP:
  380. *value = mvebu_readl(port, PCIE_CAP_PCIEXP + PCI_EXP_DEVCAP);
  381. break;
  382. case PCI_EXP_DEVCTL:
  383. *value = mvebu_readl(port, PCIE_CAP_PCIEXP + PCI_EXP_DEVCTL) &
  384. ~(PCI_EXP_DEVCTL_URRE | PCI_EXP_DEVCTL_FERE |
  385. PCI_EXP_DEVCTL_NFERE | PCI_EXP_DEVCTL_CERE);
  386. break;
  387. case PCI_EXP_LNKCAP:
  388. /*
  389. * PCIe requires the clock power management capability to be
  390. * hard-wired to zero for downstream ports
  391. */
  392. *value = mvebu_readl(port, PCIE_CAP_PCIEXP + PCI_EXP_LNKCAP) &
  393. ~PCI_EXP_LNKCAP_CLKPM;
  394. break;
  395. case PCI_EXP_LNKCTL:
  396. *value = mvebu_readl(port, PCIE_CAP_PCIEXP + PCI_EXP_LNKCTL);
  397. break;
  398. case PCI_EXP_SLTCTL:
  399. *value = PCI_EXP_SLTSTA_PDS << 16;
  400. break;
  401. case PCI_EXP_RTSTA:
  402. *value = mvebu_readl(port, PCIE_RC_RTSTA);
  403. break;
  404. default:
  405. return PCI_BRIDGE_EMUL_NOT_HANDLED;
  406. }
  407. return PCI_BRIDGE_EMUL_HANDLED;
  408. }
  409. static void
  410. mvebu_pci_bridge_emul_base_conf_write(struct pci_bridge_emul *bridge,
  411. int reg, u32 old, u32 new, u32 mask)
  412. {
  413. struct mvebu_pcie_port *port = bridge->data;
  414. struct pci_bridge_emul_conf *conf = &bridge->conf;
  415. switch (reg) {
  416. case PCI_COMMAND:
  417. {
  418. if (!mvebu_has_ioport(port))
  419. conf->command &= ~PCI_COMMAND_IO;
  420. if ((old ^ new) & PCI_COMMAND_IO)
  421. mvebu_pcie_handle_iobase_change(port);
  422. if ((old ^ new) & PCI_COMMAND_MEMORY)
  423. mvebu_pcie_handle_membase_change(port);
  424. break;
  425. }
  426. case PCI_IO_BASE:
  427. /*
  428. * We keep bit 1 set, it is a read-only bit that
  429. * indicates we support 32 bits addressing for the
  430. * I/O
  431. */
  432. conf->iobase |= PCI_IO_RANGE_TYPE_32;
  433. conf->iolimit |= PCI_IO_RANGE_TYPE_32;
  434. mvebu_pcie_handle_iobase_change(port);
  435. break;
  436. case PCI_MEMORY_BASE:
  437. mvebu_pcie_handle_membase_change(port);
  438. break;
  439. case PCI_IO_BASE_UPPER16:
  440. mvebu_pcie_handle_iobase_change(port);
  441. break;
  442. case PCI_PRIMARY_BUS:
  443. mvebu_pcie_set_local_bus_nr(port, conf->secondary_bus);
  444. break;
  445. default:
  446. break;
  447. }
  448. }
  449. static void
  450. mvebu_pci_bridge_emul_pcie_conf_write(struct pci_bridge_emul *bridge,
  451. int reg, u32 old, u32 new, u32 mask)
  452. {
  453. struct mvebu_pcie_port *port = bridge->data;
  454. switch (reg) {
  455. case PCI_EXP_DEVCTL:
  456. /*
  457. * Armada370 data says these bits must always
  458. * be zero when in root complex mode.
  459. */
  460. new &= ~(PCI_EXP_DEVCTL_URRE | PCI_EXP_DEVCTL_FERE |
  461. PCI_EXP_DEVCTL_NFERE | PCI_EXP_DEVCTL_CERE);
  462. mvebu_writel(port, new, PCIE_CAP_PCIEXP + PCI_EXP_DEVCTL);
  463. break;
  464. case PCI_EXP_LNKCTL:
  465. /*
  466. * If we don't support CLKREQ, we must ensure that the
  467. * CLKREQ enable bit always reads zero. Since we haven't
  468. * had this capability, and it's dependent on board wiring,
  469. * disable it for the time being.
  470. */
  471. new &= ~PCI_EXP_LNKCTL_CLKREQ_EN;
  472. mvebu_writel(port, new, PCIE_CAP_PCIEXP + PCI_EXP_LNKCTL);
  473. break;
  474. case PCI_EXP_RTSTA:
  475. mvebu_writel(port, new, PCIE_RC_RTSTA);
  476. break;
  477. }
  478. }
  479. static struct pci_bridge_emul_ops mvebu_pci_bridge_emul_ops = {
  480. .write_base = mvebu_pci_bridge_emul_base_conf_write,
  481. .read_pcie = mvebu_pci_bridge_emul_pcie_conf_read,
  482. .write_pcie = mvebu_pci_bridge_emul_pcie_conf_write,
  483. };
  484. /*
  485. * Initialize the configuration space of the PCI-to-PCI bridge
  486. * associated with the given PCIe interface.
  487. */
  488. static void mvebu_pci_bridge_emul_init(struct mvebu_pcie_port *port)
  489. {
  490. struct pci_bridge_emul *bridge = &port->bridge;
  491. u32 pcie_cap = mvebu_readl(port, PCIE_CAP_PCIEXP);
  492. u8 pcie_cap_ver = ((pcie_cap >> 16) & PCI_EXP_FLAGS_VERS);
  493. bridge->conf.vendor = PCI_VENDOR_ID_MARVELL;
  494. bridge->conf.device = mvebu_readl(port, PCIE_DEV_ID_OFF) >> 16;
  495. bridge->conf.class_revision =
  496. mvebu_readl(port, PCIE_DEV_REV_OFF) & 0xff;
  497. if (mvebu_has_ioport(port)) {
  498. /* We support 32 bits I/O addressing */
  499. bridge->conf.iobase = PCI_IO_RANGE_TYPE_32;
  500. bridge->conf.iolimit = PCI_IO_RANGE_TYPE_32;
  501. }
  502. /*
  503. * Older mvebu hardware provides PCIe Capability structure only in
  504. * version 1. New hardware provides it in version 2.
  505. */
  506. bridge->pcie_conf.cap = cpu_to_le16(pcie_cap_ver);
  507. bridge->has_pcie = true;
  508. bridge->data = port;
  509. bridge->ops = &mvebu_pci_bridge_emul_ops;
  510. pci_bridge_emul_init(bridge, PCI_BRIDGE_EMUL_NO_PREFETCHABLE_BAR);
  511. }
  512. static inline struct mvebu_pcie *sys_to_pcie(struct pci_sys_data *sys)
  513. {
  514. return sys->private_data;
  515. }
  516. static struct mvebu_pcie_port *mvebu_pcie_find_port(struct mvebu_pcie *pcie,
  517. struct pci_bus *bus,
  518. int devfn)
  519. {
  520. int i;
  521. for (i = 0; i < pcie->nports; i++) {
  522. struct mvebu_pcie_port *port = &pcie->ports[i];
  523. if (bus->number == 0 && port->devfn == devfn)
  524. return port;
  525. if (bus->number != 0 &&
  526. bus->number >= port->bridge.conf.secondary_bus &&
  527. bus->number <= port->bridge.conf.subordinate_bus)
  528. return port;
  529. }
  530. return NULL;
  531. }
  532. /* PCI configuration space write function */
  533. static int mvebu_pcie_wr_conf(struct pci_bus *bus, u32 devfn,
  534. int where, int size, u32 val)
  535. {
  536. struct mvebu_pcie *pcie = bus->sysdata;
  537. struct mvebu_pcie_port *port;
  538. int ret;
  539. port = mvebu_pcie_find_port(pcie, bus, devfn);
  540. if (!port)
  541. return PCIBIOS_DEVICE_NOT_FOUND;
  542. /* Access the emulated PCI-to-PCI bridge */
  543. if (bus->number == 0)
  544. return pci_bridge_emul_conf_write(&port->bridge, where,
  545. size, val);
  546. if (!mvebu_pcie_link_up(port))
  547. return PCIBIOS_DEVICE_NOT_FOUND;
  548. /* Access the real PCIe interface */
  549. ret = mvebu_pcie_hw_wr_conf(port, bus, devfn,
  550. where, size, val);
  551. return ret;
  552. }
  553. /* PCI configuration space read function */
  554. static int mvebu_pcie_rd_conf(struct pci_bus *bus, u32 devfn, int where,
  555. int size, u32 *val)
  556. {
  557. struct mvebu_pcie *pcie = bus->sysdata;
  558. struct mvebu_pcie_port *port;
  559. int ret;
  560. port = mvebu_pcie_find_port(pcie, bus, devfn);
  561. if (!port) {
  562. *val = 0xffffffff;
  563. return PCIBIOS_DEVICE_NOT_FOUND;
  564. }
  565. /* Access the emulated PCI-to-PCI bridge */
  566. if (bus->number == 0)
  567. return pci_bridge_emul_conf_read(&port->bridge, where,
  568. size, val);
  569. if (!mvebu_pcie_link_up(port)) {
  570. *val = 0xffffffff;
  571. return PCIBIOS_DEVICE_NOT_FOUND;
  572. }
  573. /* Access the real PCIe interface */
  574. ret = mvebu_pcie_hw_rd_conf(port, bus, devfn,
  575. where, size, val);
  576. return ret;
  577. }
  578. static struct pci_ops mvebu_pcie_ops = {
  579. .read = mvebu_pcie_rd_conf,
  580. .write = mvebu_pcie_wr_conf,
  581. };
  582. static resource_size_t mvebu_pcie_align_resource(struct pci_dev *dev,
  583. const struct resource *res,
  584. resource_size_t start,
  585. resource_size_t size,
  586. resource_size_t align)
  587. {
  588. if (dev->bus->number != 0)
  589. return start;
  590. /*
  591. * On the PCI-to-PCI bridge side, the I/O windows must have at
  592. * least a 64 KB size and the memory windows must have at
  593. * least a 1 MB size. Moreover, MBus windows need to have a
  594. * base address aligned on their size, and their size must be
  595. * a power of two. This means that if the BAR doesn't have a
  596. * power of two size, several MBus windows will actually be
  597. * created. We need to ensure that the biggest MBus window
  598. * (which will be the first one) is aligned on its size, which
  599. * explains the rounddown_pow_of_two() being done here.
  600. */
  601. if (res->flags & IORESOURCE_IO)
  602. return round_up(start, max_t(resource_size_t, SZ_64K,
  603. rounddown_pow_of_two(size)));
  604. else if (res->flags & IORESOURCE_MEM)
  605. return round_up(start, max_t(resource_size_t, SZ_1M,
  606. rounddown_pow_of_two(size)));
  607. else
  608. return start;
  609. }
  610. static void __iomem *mvebu_pcie_map_registers(struct platform_device *pdev,
  611. struct device_node *np,
  612. struct mvebu_pcie_port *port)
  613. {
  614. int ret = 0;
  615. ret = of_address_to_resource(np, 0, &port->regs);
  616. if (ret)
  617. return (void __iomem *)ERR_PTR(ret);
  618. return devm_ioremap_resource(&pdev->dev, &port->regs);
  619. }
  620. #define DT_FLAGS_TO_TYPE(flags) (((flags) >> 24) & 0x03)
  621. #define DT_TYPE_IO 0x1
  622. #define DT_TYPE_MEM32 0x2
  623. #define DT_CPUADDR_TO_TARGET(cpuaddr) (((cpuaddr) >> 56) & 0xFF)
  624. #define DT_CPUADDR_TO_ATTR(cpuaddr) (((cpuaddr) >> 48) & 0xFF)
  625. static int mvebu_get_tgt_attr(struct device_node *np, int devfn,
  626. unsigned long type,
  627. unsigned int *tgt,
  628. unsigned int *attr)
  629. {
  630. const int na = 3, ns = 2;
  631. const __be32 *range;
  632. int rlen, nranges, rangesz, pna, i;
  633. *tgt = -1;
  634. *attr = -1;
  635. range = of_get_property(np, "ranges", &rlen);
  636. if (!range)
  637. return -EINVAL;
  638. pna = of_n_addr_cells(np);
  639. rangesz = pna + na + ns;
  640. nranges = rlen / sizeof(__be32) / rangesz;
  641. for (i = 0; i < nranges; i++, range += rangesz) {
  642. u32 flags = of_read_number(range, 1);
  643. u32 slot = of_read_number(range + 1, 1);
  644. u64 cpuaddr = of_read_number(range + na, pna);
  645. unsigned long rtype;
  646. if (DT_FLAGS_TO_TYPE(flags) == DT_TYPE_IO)
  647. rtype = IORESOURCE_IO;
  648. else if (DT_FLAGS_TO_TYPE(flags) == DT_TYPE_MEM32)
  649. rtype = IORESOURCE_MEM;
  650. else
  651. continue;
  652. if (slot == PCI_SLOT(devfn) && type == rtype) {
  653. *tgt = DT_CPUADDR_TO_TARGET(cpuaddr);
  654. *attr = DT_CPUADDR_TO_ATTR(cpuaddr);
  655. return 0;
  656. }
  657. }
  658. return -ENOENT;
  659. }
  660. #ifdef CONFIG_PM_SLEEP
  661. static int mvebu_pcie_suspend(struct device *dev)
  662. {
  663. struct mvebu_pcie *pcie;
  664. int i;
  665. pcie = dev_get_drvdata(dev);
  666. for (i = 0; i < pcie->nports; i++) {
  667. struct mvebu_pcie_port *port = pcie->ports + i;
  668. port->saved_pcie_stat = mvebu_readl(port, PCIE_STAT_OFF);
  669. }
  670. return 0;
  671. }
  672. static int mvebu_pcie_resume(struct device *dev)
  673. {
  674. struct mvebu_pcie *pcie;
  675. int i;
  676. pcie = dev_get_drvdata(dev);
  677. for (i = 0; i < pcie->nports; i++) {
  678. struct mvebu_pcie_port *port = pcie->ports + i;
  679. mvebu_writel(port, port->saved_pcie_stat, PCIE_STAT_OFF);
  680. mvebu_pcie_setup_hw(port);
  681. }
  682. return 0;
  683. }
  684. #endif
  685. static void mvebu_pcie_port_clk_put(void *data)
  686. {
  687. struct mvebu_pcie_port *port = data;
  688. clk_put(port->clk);
  689. }
  690. static int mvebu_pcie_parse_port(struct mvebu_pcie *pcie,
  691. struct mvebu_pcie_port *port, struct device_node *child)
  692. {
  693. struct device *dev = &pcie->pdev->dev;
  694. enum of_gpio_flags flags;
  695. int reset_gpio, ret;
  696. port->pcie = pcie;
  697. if (of_property_read_u32(child, "marvell,pcie-port", &port->port)) {
  698. dev_warn(dev, "ignoring %pOF, missing pcie-port property\n",
  699. child);
  700. goto skip;
  701. }
  702. if (of_property_read_u32(child, "marvell,pcie-lane", &port->lane))
  703. port->lane = 0;
  704. port->name = devm_kasprintf(dev, GFP_KERNEL, "pcie%d.%d", port->port,
  705. port->lane);
  706. if (!port->name) {
  707. ret = -ENOMEM;
  708. goto err;
  709. }
  710. port->devfn = of_pci_get_devfn(child);
  711. if (port->devfn < 0)
  712. goto skip;
  713. ret = mvebu_get_tgt_attr(dev->of_node, port->devfn, IORESOURCE_MEM,
  714. &port->mem_target, &port->mem_attr);
  715. if (ret < 0) {
  716. dev_err(dev, "%s: cannot get tgt/attr for mem window\n",
  717. port->name);
  718. goto skip;
  719. }
  720. if (resource_size(&pcie->io) != 0) {
  721. mvebu_get_tgt_attr(dev->of_node, port->devfn, IORESOURCE_IO,
  722. &port->io_target, &port->io_attr);
  723. } else {
  724. port->io_target = -1;
  725. port->io_attr = -1;
  726. }
  727. reset_gpio = of_get_named_gpio_flags(child, "reset-gpios", 0, &flags);
  728. if (reset_gpio == -EPROBE_DEFER) {
  729. ret = reset_gpio;
  730. goto err;
  731. }
  732. if (gpio_is_valid(reset_gpio)) {
  733. unsigned long gpio_flags;
  734. port->reset_name = devm_kasprintf(dev, GFP_KERNEL, "%s-reset",
  735. port->name);
  736. if (!port->reset_name) {
  737. ret = -ENOMEM;
  738. goto err;
  739. }
  740. if (flags & OF_GPIO_ACTIVE_LOW) {
  741. dev_info(dev, "%pOF: reset gpio is active low\n",
  742. child);
  743. gpio_flags = GPIOF_ACTIVE_LOW |
  744. GPIOF_OUT_INIT_LOW;
  745. } else {
  746. gpio_flags = GPIOF_OUT_INIT_HIGH;
  747. }
  748. ret = devm_gpio_request_one(dev, reset_gpio, gpio_flags,
  749. port->reset_name);
  750. if (ret) {
  751. if (ret == -EPROBE_DEFER)
  752. goto err;
  753. goto skip;
  754. }
  755. port->reset_gpio = gpio_to_desc(reset_gpio);
  756. }
  757. port->clk = of_clk_get_by_name(child, NULL);
  758. if (IS_ERR(port->clk)) {
  759. dev_err(dev, "%s: cannot get clock\n", port->name);
  760. goto skip;
  761. }
  762. ret = devm_add_action(dev, mvebu_pcie_port_clk_put, port);
  763. if (ret < 0) {
  764. clk_put(port->clk);
  765. goto err;
  766. }
  767. return 1;
  768. skip:
  769. ret = 0;
  770. /* In the case of skipping, we need to free these */
  771. devm_kfree(dev, port->reset_name);
  772. port->reset_name = NULL;
  773. devm_kfree(dev, port->name);
  774. port->name = NULL;
  775. err:
  776. return ret;
  777. }
  778. /*
  779. * Power up a PCIe port. PCIe requires the refclk to be stable for 100µs
  780. * prior to releasing PERST. See table 2-4 in section 2.6.2 AC Specifications
  781. * of the PCI Express Card Electromechanical Specification, 1.1.
  782. */
  783. static int mvebu_pcie_powerup(struct mvebu_pcie_port *port)
  784. {
  785. int ret;
  786. ret = clk_prepare_enable(port->clk);
  787. if (ret < 0)
  788. return ret;
  789. if (port->reset_gpio) {
  790. u32 reset_udelay = PCI_PM_D3COLD_WAIT * 1000;
  791. of_property_read_u32(port->dn, "reset-delay-us",
  792. &reset_udelay);
  793. udelay(100);
  794. gpiod_set_value_cansleep(port->reset_gpio, 0);
  795. msleep(reset_udelay / 1000);
  796. }
  797. return 0;
  798. }
  799. /*
  800. * Power down a PCIe port. Strictly, PCIe requires us to place the card
  801. * in D3hot state before asserting PERST#.
  802. */
  803. static void mvebu_pcie_powerdown(struct mvebu_pcie_port *port)
  804. {
  805. gpiod_set_value_cansleep(port->reset_gpio, 1);
  806. clk_disable_unprepare(port->clk);
  807. }
  808. /*
  809. * devm_of_pci_get_host_bridge_resources() only sets up translateable resources,
  810. * so we need extra resource setup parsing our special DT properties encoding
  811. * the MEM and IO apertures.
  812. */
  813. static int mvebu_pcie_parse_request_resources(struct mvebu_pcie *pcie)
  814. {
  815. struct device *dev = &pcie->pdev->dev;
  816. struct pci_host_bridge *bridge = pci_host_bridge_from_priv(pcie);
  817. int ret;
  818. /* Get the PCIe memory aperture */
  819. mvebu_mbus_get_pcie_mem_aperture(&pcie->mem);
  820. if (resource_size(&pcie->mem) == 0) {
  821. dev_err(dev, "invalid memory aperture size\n");
  822. return -EINVAL;
  823. }
  824. pcie->mem.name = "PCI MEM";
  825. pci_add_resource(&bridge->windows, &pcie->mem);
  826. ret = devm_request_resource(dev, &iomem_resource, &pcie->mem);
  827. if (ret)
  828. return ret;
  829. /* Get the PCIe IO aperture */
  830. mvebu_mbus_get_pcie_io_aperture(&pcie->io);
  831. if (resource_size(&pcie->io) != 0) {
  832. pcie->realio.flags = pcie->io.flags;
  833. pcie->realio.start = PCIBIOS_MIN_IO;
  834. pcie->realio.end = min_t(resource_size_t,
  835. IO_SPACE_LIMIT - SZ_64K,
  836. resource_size(&pcie->io) - 1);
  837. pcie->realio.name = "PCI I/O";
  838. pci_add_resource(&bridge->windows, &pcie->realio);
  839. ret = devm_request_resource(dev, &ioport_resource, &pcie->realio);
  840. if (ret)
  841. return ret;
  842. }
  843. return 0;
  844. }
  845. /*
  846. * This is a copy of pci_host_probe(), except that it does the I/O
  847. * remap as the last step, once we are sure we won't fail.
  848. *
  849. * It should be removed once the I/O remap error handling issue has
  850. * been sorted out.
  851. */
  852. static int mvebu_pci_host_probe(struct pci_host_bridge *bridge)
  853. {
  854. struct mvebu_pcie *pcie;
  855. struct pci_bus *bus, *child;
  856. int ret;
  857. ret = pci_scan_root_bus_bridge(bridge);
  858. if (ret < 0) {
  859. dev_err(bridge->dev.parent, "Scanning root bridge failed");
  860. return ret;
  861. }
  862. pcie = pci_host_bridge_priv(bridge);
  863. if (resource_size(&pcie->io) != 0) {
  864. unsigned int i;
  865. for (i = 0; i < resource_size(&pcie->realio); i += SZ_64K)
  866. pci_ioremap_io(i, pcie->io.start + i);
  867. }
  868. bus = bridge->bus;
  869. /*
  870. * We insert PCI resources into the iomem_resource and
  871. * ioport_resource trees in either pci_bus_claim_resources()
  872. * or pci_bus_assign_resources().
  873. */
  874. if (pci_has_flag(PCI_PROBE_ONLY)) {
  875. pci_bus_claim_resources(bus);
  876. } else {
  877. pci_bus_size_bridges(bus);
  878. pci_bus_assign_resources(bus);
  879. list_for_each_entry(child, &bus->children, node)
  880. pcie_bus_configure_settings(child);
  881. }
  882. pci_bus_add_devices(bus);
  883. return 0;
  884. }
  885. static int mvebu_pcie_probe(struct platform_device *pdev)
  886. {
  887. struct device *dev = &pdev->dev;
  888. struct mvebu_pcie *pcie;
  889. struct pci_host_bridge *bridge;
  890. struct device_node *np = dev->of_node;
  891. struct device_node *child;
  892. int num, i, ret;
  893. bridge = devm_pci_alloc_host_bridge(dev, sizeof(struct mvebu_pcie));
  894. if (!bridge)
  895. return -ENOMEM;
  896. pcie = pci_host_bridge_priv(bridge);
  897. pcie->pdev = pdev;
  898. platform_set_drvdata(pdev, pcie);
  899. ret = mvebu_pcie_parse_request_resources(pcie);
  900. if (ret)
  901. return ret;
  902. num = of_get_available_child_count(np);
  903. pcie->ports = devm_kcalloc(dev, num, sizeof(*pcie->ports), GFP_KERNEL);
  904. if (!pcie->ports)
  905. return -ENOMEM;
  906. i = 0;
  907. for_each_available_child_of_node(np, child) {
  908. struct mvebu_pcie_port *port = &pcie->ports[i];
  909. ret = mvebu_pcie_parse_port(pcie, port, child);
  910. if (ret < 0) {
  911. of_node_put(child);
  912. return ret;
  913. } else if (ret == 0) {
  914. continue;
  915. }
  916. port->dn = child;
  917. i++;
  918. }
  919. pcie->nports = i;
  920. for (i = 0; i < pcie->nports; i++) {
  921. struct mvebu_pcie_port *port = &pcie->ports[i];
  922. child = port->dn;
  923. if (!child)
  924. continue;
  925. ret = mvebu_pcie_powerup(port);
  926. if (ret < 0)
  927. continue;
  928. port->base = mvebu_pcie_map_registers(pdev, child, port);
  929. if (IS_ERR(port->base)) {
  930. dev_err(dev, "%s: cannot map registers\n", port->name);
  931. port->base = NULL;
  932. mvebu_pcie_powerdown(port);
  933. continue;
  934. }
  935. mvebu_pcie_setup_hw(port);
  936. mvebu_pcie_set_local_dev_nr(port, 1);
  937. mvebu_pci_bridge_emul_init(port);
  938. }
  939. pcie->nports = i;
  940. bridge->sysdata = pcie;
  941. bridge->ops = &mvebu_pcie_ops;
  942. bridge->align_resource = mvebu_pcie_align_resource;
  943. return mvebu_pci_host_probe(bridge);
  944. }
  945. static const struct of_device_id mvebu_pcie_of_match_table[] = {
  946. { .compatible = "marvell,armada-xp-pcie", },
  947. { .compatible = "marvell,armada-370-pcie", },
  948. { .compatible = "marvell,dove-pcie", },
  949. { .compatible = "marvell,kirkwood-pcie", },
  950. {},
  951. };
  952. static const struct dev_pm_ops mvebu_pcie_pm_ops = {
  953. SET_NOIRQ_SYSTEM_SLEEP_PM_OPS(mvebu_pcie_suspend, mvebu_pcie_resume)
  954. };
  955. static struct platform_driver mvebu_pcie_driver = {
  956. .driver = {
  957. .name = "mvebu-pcie",
  958. .of_match_table = mvebu_pcie_of_match_table,
  959. /* driver unloading/unbinding currently not supported */
  960. .suppress_bind_attrs = true,
  961. .pm = &mvebu_pcie_pm_ops,
  962. },
  963. .probe = mvebu_pcie_probe,
  964. };
  965. builtin_platform_driver(mvebu_pcie_driver);