parport_ip32.c 66 KB

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  1. // SPDX-License-Identifier: GPL-2.0-or-later
  2. /* Low-level parallel port routines for built-in port on SGI IP32
  3. *
  4. * Author: Arnaud Giersch <arnaud.giersch@free.fr>
  5. *
  6. * Based on parport_pc.c by
  7. * Phil Blundell, Tim Waugh, Jose Renau, David Campbell,
  8. * Andrea Arcangeli, et al.
  9. *
  10. * Thanks to Ilya A. Volynets-Evenbakh for his help.
  11. *
  12. * Copyright (C) 2005, 2006 Arnaud Giersch.
  13. */
  14. /* Current status:
  15. *
  16. * Basic SPP and PS2 modes are supported.
  17. * Support for parallel port IRQ is present.
  18. * Hardware SPP (a.k.a. compatibility), EPP, and ECP modes are
  19. * supported.
  20. * SPP/ECP FIFO can be driven in PIO or DMA mode. PIO mode can work with
  21. * or without interrupt support.
  22. *
  23. * Hardware ECP mode is not fully implemented (ecp_read_data and
  24. * ecp_write_addr are actually missing).
  25. *
  26. * To do:
  27. *
  28. * Fully implement ECP mode.
  29. * EPP and ECP mode need to be tested. I currently do not own any
  30. * peripheral supporting these extended mode, and cannot test them.
  31. * If DMA mode works well, decide if support for PIO FIFO modes should be
  32. * dropped.
  33. * Use the io{read,write} family functions when they become available in
  34. * the linux-mips.org tree. Note: the MIPS specific functions readsb()
  35. * and writesb() are to be translated by ioread8_rep() and iowrite8_rep()
  36. * respectively.
  37. */
  38. /* The built-in parallel port on the SGI 02 workstation (a.k.a. IP32) is an
  39. * IEEE 1284 parallel port driven by a Texas Instrument TL16PIR552PH chip[1].
  40. * This chip supports SPP, bidirectional, EPP and ECP modes. It has a 16 byte
  41. * FIFO buffer and supports DMA transfers.
  42. *
  43. * [1] http://focus.ti.com/docs/prod/folders/print/tl16pir552.html
  44. *
  45. * Theoretically, we could simply use the parport_pc module. It is however
  46. * not so simple. The parport_pc code assumes that the parallel port
  47. * registers are port-mapped. On the O2, they are memory-mapped.
  48. * Furthermore, each register is replicated on 256 consecutive addresses (as
  49. * it is for the built-in serial ports on the same chip).
  50. */
  51. /*--- Some configuration defines ---------------------------------------*/
  52. /* DEBUG_PARPORT_IP32
  53. * 0 disable debug
  54. * 1 standard level: pr_debug1 is enabled
  55. * 2 parport_ip32_dump_state is enabled
  56. * >=3 verbose level: pr_debug is enabled
  57. */
  58. #if !defined(DEBUG_PARPORT_IP32)
  59. # define DEBUG_PARPORT_IP32 0 /* 0 (disabled) for production */
  60. #endif
  61. /*----------------------------------------------------------------------*/
  62. /* Setup DEBUG macros. This is done before any includes, just in case we
  63. * activate pr_debug() with DEBUG_PARPORT_IP32 >= 3.
  64. */
  65. #if DEBUG_PARPORT_IP32 == 1
  66. # warning DEBUG_PARPORT_IP32 == 1
  67. #elif DEBUG_PARPORT_IP32 == 2
  68. # warning DEBUG_PARPORT_IP32 == 2
  69. #elif DEBUG_PARPORT_IP32 >= 3
  70. # warning DEBUG_PARPORT_IP32 >= 3
  71. # if !defined(DEBUG)
  72. # define DEBUG /* enable pr_debug() in kernel.h */
  73. # endif
  74. #endif
  75. #include <linux/completion.h>
  76. #include <linux/delay.h>
  77. #include <linux/dma-mapping.h>
  78. #include <linux/err.h>
  79. #include <linux/init.h>
  80. #include <linux/interrupt.h>
  81. #include <linux/jiffies.h>
  82. #include <linux/kernel.h>
  83. #include <linux/module.h>
  84. #include <linux/parport.h>
  85. #include <linux/sched/signal.h>
  86. #include <linux/slab.h>
  87. #include <linux/spinlock.h>
  88. #include <linux/stddef.h>
  89. #include <linux/types.h>
  90. #include <asm/io.h>
  91. #include <asm/ip32/ip32_ints.h>
  92. #include <asm/ip32/mace.h>
  93. /*--- Global variables -------------------------------------------------*/
  94. /* Verbose probing on by default for debugging. */
  95. #if DEBUG_PARPORT_IP32 >= 1
  96. # define DEFAULT_VERBOSE_PROBING 1
  97. #else
  98. # define DEFAULT_VERBOSE_PROBING 0
  99. #endif
  100. /* Default prefix for printk */
  101. #define PPIP32 "parport_ip32: "
  102. /*
  103. * These are the module parameters:
  104. * @features: bit mask of features to enable/disable
  105. * (all enabled by default)
  106. * @verbose_probing: log chit-chat during initialization
  107. */
  108. #define PARPORT_IP32_ENABLE_IRQ (1U << 0)
  109. #define PARPORT_IP32_ENABLE_DMA (1U << 1)
  110. #define PARPORT_IP32_ENABLE_SPP (1U << 2)
  111. #define PARPORT_IP32_ENABLE_EPP (1U << 3)
  112. #define PARPORT_IP32_ENABLE_ECP (1U << 4)
  113. static unsigned int features = ~0U;
  114. static bool verbose_probing = DEFAULT_VERBOSE_PROBING;
  115. /* We do not support more than one port. */
  116. static struct parport *this_port;
  117. /* Timing constants for FIFO modes. */
  118. #define FIFO_NFAULT_TIMEOUT 100 /* milliseconds */
  119. #define FIFO_POLLING_INTERVAL 50 /* microseconds */
  120. /*--- I/O register definitions -----------------------------------------*/
  121. /**
  122. * struct parport_ip32_regs - virtual addresses of parallel port registers
  123. * @data: Data Register
  124. * @dsr: Device Status Register
  125. * @dcr: Device Control Register
  126. * @eppAddr: EPP Address Register
  127. * @eppData0: EPP Data Register 0
  128. * @eppData1: EPP Data Register 1
  129. * @eppData2: EPP Data Register 2
  130. * @eppData3: EPP Data Register 3
  131. * @ecpAFifo: ECP Address FIFO
  132. * @fifo: General FIFO register. The same address is used for:
  133. * - cFifo, the Parallel Port DATA FIFO
  134. * - ecpDFifo, the ECP Data FIFO
  135. * - tFifo, the ECP Test FIFO
  136. * @cnfgA: Configuration Register A
  137. * @cnfgB: Configuration Register B
  138. * @ecr: Extended Control Register
  139. */
  140. struct parport_ip32_regs {
  141. void __iomem *data;
  142. void __iomem *dsr;
  143. void __iomem *dcr;
  144. void __iomem *eppAddr;
  145. void __iomem *eppData0;
  146. void __iomem *eppData1;
  147. void __iomem *eppData2;
  148. void __iomem *eppData3;
  149. void __iomem *ecpAFifo;
  150. void __iomem *fifo;
  151. void __iomem *cnfgA;
  152. void __iomem *cnfgB;
  153. void __iomem *ecr;
  154. };
  155. /* Device Status Register */
  156. #define DSR_nBUSY (1U << 7) /* PARPORT_STATUS_BUSY */
  157. #define DSR_nACK (1U << 6) /* PARPORT_STATUS_ACK */
  158. #define DSR_PERROR (1U << 5) /* PARPORT_STATUS_PAPEROUT */
  159. #define DSR_SELECT (1U << 4) /* PARPORT_STATUS_SELECT */
  160. #define DSR_nFAULT (1U << 3) /* PARPORT_STATUS_ERROR */
  161. #define DSR_nPRINT (1U << 2) /* specific to TL16PIR552 */
  162. /* #define DSR_reserved (1U << 1) */
  163. #define DSR_TIMEOUT (1U << 0) /* EPP timeout */
  164. /* Device Control Register */
  165. /* #define DCR_reserved (1U << 7) | (1U << 6) */
  166. #define DCR_DIR (1U << 5) /* direction */
  167. #define DCR_IRQ (1U << 4) /* interrupt on nAck */
  168. #define DCR_SELECT (1U << 3) /* PARPORT_CONTROL_SELECT */
  169. #define DCR_nINIT (1U << 2) /* PARPORT_CONTROL_INIT */
  170. #define DCR_AUTOFD (1U << 1) /* PARPORT_CONTROL_AUTOFD */
  171. #define DCR_STROBE (1U << 0) /* PARPORT_CONTROL_STROBE */
  172. /* ECP Configuration Register A */
  173. #define CNFGA_IRQ (1U << 7)
  174. #define CNFGA_ID_MASK ((1U << 6) | (1U << 5) | (1U << 4))
  175. #define CNFGA_ID_SHIFT 4
  176. #define CNFGA_ID_16 (00U << CNFGA_ID_SHIFT)
  177. #define CNFGA_ID_8 (01U << CNFGA_ID_SHIFT)
  178. #define CNFGA_ID_32 (02U << CNFGA_ID_SHIFT)
  179. /* #define CNFGA_reserved (1U << 3) */
  180. #define CNFGA_nBYTEINTRANS (1U << 2)
  181. #define CNFGA_PWORDLEFT ((1U << 1) | (1U << 0))
  182. /* ECP Configuration Register B */
  183. #define CNFGB_COMPRESS (1U << 7)
  184. #define CNFGB_INTRVAL (1U << 6)
  185. #define CNFGB_IRQ_MASK ((1U << 5) | (1U << 4) | (1U << 3))
  186. #define CNFGB_IRQ_SHIFT 3
  187. #define CNFGB_DMA_MASK ((1U << 2) | (1U << 1) | (1U << 0))
  188. #define CNFGB_DMA_SHIFT 0
  189. /* Extended Control Register */
  190. #define ECR_MODE_MASK ((1U << 7) | (1U << 6) | (1U << 5))
  191. #define ECR_MODE_SHIFT 5
  192. #define ECR_MODE_SPP (00U << ECR_MODE_SHIFT)
  193. #define ECR_MODE_PS2 (01U << ECR_MODE_SHIFT)
  194. #define ECR_MODE_PPF (02U << ECR_MODE_SHIFT)
  195. #define ECR_MODE_ECP (03U << ECR_MODE_SHIFT)
  196. #define ECR_MODE_EPP (04U << ECR_MODE_SHIFT)
  197. /* #define ECR_MODE_reserved (05U << ECR_MODE_SHIFT) */
  198. #define ECR_MODE_TST (06U << ECR_MODE_SHIFT)
  199. #define ECR_MODE_CFG (07U << ECR_MODE_SHIFT)
  200. #define ECR_nERRINTR (1U << 4)
  201. #define ECR_DMAEN (1U << 3)
  202. #define ECR_SERVINTR (1U << 2)
  203. #define ECR_F_FULL (1U << 1)
  204. #define ECR_F_EMPTY (1U << 0)
  205. /*--- Private data -----------------------------------------------------*/
  206. /**
  207. * enum parport_ip32_irq_mode - operation mode of interrupt handler
  208. * @PARPORT_IP32_IRQ_FWD: forward interrupt to the upper parport layer
  209. * @PARPORT_IP32_IRQ_HERE: interrupt is handled locally
  210. */
  211. enum parport_ip32_irq_mode { PARPORT_IP32_IRQ_FWD, PARPORT_IP32_IRQ_HERE };
  212. /**
  213. * struct parport_ip32_private - private stuff for &struct parport
  214. * @regs: register addresses
  215. * @dcr_cache: cached contents of DCR
  216. * @dcr_writable: bit mask of writable DCR bits
  217. * @pword: number of bytes per PWord
  218. * @fifo_depth: number of PWords that FIFO will hold
  219. * @readIntrThreshold: minimum number of PWords we can read
  220. * if we get an interrupt
  221. * @writeIntrThreshold: minimum number of PWords we can write
  222. * if we get an interrupt
  223. * @irq_mode: operation mode of interrupt handler for this port
  224. * @irq_complete: mutex used to wait for an interrupt to occur
  225. */
  226. struct parport_ip32_private {
  227. struct parport_ip32_regs regs;
  228. unsigned int dcr_cache;
  229. unsigned int dcr_writable;
  230. unsigned int pword;
  231. unsigned int fifo_depth;
  232. unsigned int readIntrThreshold;
  233. unsigned int writeIntrThreshold;
  234. enum parport_ip32_irq_mode irq_mode;
  235. struct completion irq_complete;
  236. };
  237. /*--- Debug code -------------------------------------------------------*/
  238. /*
  239. * pr_debug1 - print debug messages
  240. *
  241. * This is like pr_debug(), but is defined for %DEBUG_PARPORT_IP32 >= 1
  242. */
  243. #if DEBUG_PARPORT_IP32 >= 1
  244. # define pr_debug1(...) printk(KERN_DEBUG __VA_ARGS__)
  245. #else /* DEBUG_PARPORT_IP32 < 1 */
  246. # define pr_debug1(...) do { } while (0)
  247. #endif
  248. /*
  249. * pr_trace, pr_trace1 - trace function calls
  250. * @p: pointer to &struct parport
  251. * @fmt: printk format string
  252. * @...: parameters for format string
  253. *
  254. * Macros used to trace function calls. The given string is formatted after
  255. * function name. pr_trace() uses pr_debug(), and pr_trace1() uses
  256. * pr_debug1(). __pr_trace() is the low-level macro and is not to be used
  257. * directly.
  258. */
  259. #define __pr_trace(pr, p, fmt, ...) \
  260. pr("%s: %s" fmt "\n", \
  261. ({ const struct parport *__p = (p); \
  262. __p ? __p->name : "parport_ip32"; }), \
  263. __func__ , ##__VA_ARGS__)
  264. #define pr_trace(p, fmt, ...) __pr_trace(pr_debug, p, fmt , ##__VA_ARGS__)
  265. #define pr_trace1(p, fmt, ...) __pr_trace(pr_debug1, p, fmt , ##__VA_ARGS__)
  266. /*
  267. * __pr_probe, pr_probe - print message if @verbose_probing is true
  268. * @p: pointer to &struct parport
  269. * @fmt: printk format string
  270. * @...: parameters for format string
  271. *
  272. * For new lines, use pr_probe(). Use __pr_probe() for continued lines.
  273. */
  274. #define __pr_probe(...) \
  275. do { if (verbose_probing) printk(__VA_ARGS__); } while (0)
  276. #define pr_probe(p, fmt, ...) \
  277. __pr_probe(KERN_INFO PPIP32 "0x%lx: " fmt, (p)->base , ##__VA_ARGS__)
  278. /*
  279. * parport_ip32_dump_state - print register status of parport
  280. * @p: pointer to &struct parport
  281. * @str: string to add in message
  282. * @show_ecp_config: shall we dump ECP configuration registers too?
  283. *
  284. * This function is only here for debugging purpose, and should be used with
  285. * care. Reading the parallel port registers may have undesired side effects.
  286. * Especially if @show_ecp_config is true, the parallel port is resetted.
  287. * This function is only defined if %DEBUG_PARPORT_IP32 >= 2.
  288. */
  289. #if DEBUG_PARPORT_IP32 >= 2
  290. static void parport_ip32_dump_state(struct parport *p, char *str,
  291. unsigned int show_ecp_config)
  292. {
  293. struct parport_ip32_private * const priv = p->physport->private_data;
  294. unsigned int i;
  295. printk(KERN_DEBUG PPIP32 "%s: state (%s):\n", p->name, str);
  296. {
  297. static const char ecr_modes[8][4] = {"SPP", "PS2", "PPF",
  298. "ECP", "EPP", "???",
  299. "TST", "CFG"};
  300. unsigned int ecr = readb(priv->regs.ecr);
  301. printk(KERN_DEBUG PPIP32 " ecr=0x%02x", ecr);
  302. pr_cont(" %s",
  303. ecr_modes[(ecr & ECR_MODE_MASK) >> ECR_MODE_SHIFT]);
  304. if (ecr & ECR_nERRINTR)
  305. pr_cont(",nErrIntrEn");
  306. if (ecr & ECR_DMAEN)
  307. pr_cont(",dmaEn");
  308. if (ecr & ECR_SERVINTR)
  309. pr_cont(",serviceIntr");
  310. if (ecr & ECR_F_FULL)
  311. pr_cont(",f_full");
  312. if (ecr & ECR_F_EMPTY)
  313. pr_cont(",f_empty");
  314. pr_cont("\n");
  315. }
  316. if (show_ecp_config) {
  317. unsigned int oecr, cnfgA, cnfgB;
  318. oecr = readb(priv->regs.ecr);
  319. writeb(ECR_MODE_PS2, priv->regs.ecr);
  320. writeb(ECR_MODE_CFG, priv->regs.ecr);
  321. cnfgA = readb(priv->regs.cnfgA);
  322. cnfgB = readb(priv->regs.cnfgB);
  323. writeb(ECR_MODE_PS2, priv->regs.ecr);
  324. writeb(oecr, priv->regs.ecr);
  325. printk(KERN_DEBUG PPIP32 " cnfgA=0x%02x", cnfgA);
  326. pr_cont(" ISA-%s", (cnfgA & CNFGA_IRQ) ? "Level" : "Pulses");
  327. switch (cnfgA & CNFGA_ID_MASK) {
  328. case CNFGA_ID_8:
  329. pr_cont(",8 bits");
  330. break;
  331. case CNFGA_ID_16:
  332. pr_cont(",16 bits");
  333. break;
  334. case CNFGA_ID_32:
  335. pr_cont(",32 bits");
  336. break;
  337. default:
  338. pr_cont(",unknown ID");
  339. break;
  340. }
  341. if (!(cnfgA & CNFGA_nBYTEINTRANS))
  342. pr_cont(",ByteInTrans");
  343. if ((cnfgA & CNFGA_ID_MASK) != CNFGA_ID_8)
  344. pr_cont(",%d byte%s left",
  345. cnfgA & CNFGA_PWORDLEFT,
  346. ((cnfgA & CNFGA_PWORDLEFT) > 1) ? "s" : "");
  347. pr_cont("\n");
  348. printk(KERN_DEBUG PPIP32 " cnfgB=0x%02x", cnfgB);
  349. pr_cont(" irq=%u,dma=%u",
  350. (cnfgB & CNFGB_IRQ_MASK) >> CNFGB_IRQ_SHIFT,
  351. (cnfgB & CNFGB_DMA_MASK) >> CNFGB_DMA_SHIFT);
  352. pr_cont(",intrValue=%d", !!(cnfgB & CNFGB_INTRVAL));
  353. if (cnfgB & CNFGB_COMPRESS)
  354. pr_cont(",compress");
  355. pr_cont("\n");
  356. }
  357. for (i = 0; i < 2; i++) {
  358. unsigned int dcr = i ? priv->dcr_cache : readb(priv->regs.dcr);
  359. printk(KERN_DEBUG PPIP32 " dcr(%s)=0x%02x",
  360. i ? "soft" : "hard", dcr);
  361. pr_cont(" %s", (dcr & DCR_DIR) ? "rev" : "fwd");
  362. if (dcr & DCR_IRQ)
  363. pr_cont(",ackIntEn");
  364. if (!(dcr & DCR_SELECT))
  365. pr_cont(",nSelectIn");
  366. if (dcr & DCR_nINIT)
  367. pr_cont(",nInit");
  368. if (!(dcr & DCR_AUTOFD))
  369. pr_cont(",nAutoFD");
  370. if (!(dcr & DCR_STROBE))
  371. pr_cont(",nStrobe");
  372. pr_cont("\n");
  373. }
  374. #define sep (f++ ? ',' : ' ')
  375. {
  376. unsigned int f = 0;
  377. unsigned int dsr = readb(priv->regs.dsr);
  378. printk(KERN_DEBUG PPIP32 " dsr=0x%02x", dsr);
  379. if (!(dsr & DSR_nBUSY))
  380. pr_cont("%cBusy", sep);
  381. if (dsr & DSR_nACK)
  382. pr_cont("%cnAck", sep);
  383. if (dsr & DSR_PERROR)
  384. pr_cont("%cPError", sep);
  385. if (dsr & DSR_SELECT)
  386. pr_cont("%cSelect", sep);
  387. if (dsr & DSR_nFAULT)
  388. pr_cont("%cnFault", sep);
  389. if (!(dsr & DSR_nPRINT))
  390. pr_cont("%c(Print)", sep);
  391. if (dsr & DSR_TIMEOUT)
  392. pr_cont("%cTimeout", sep);
  393. pr_cont("\n");
  394. }
  395. #undef sep
  396. }
  397. #else /* DEBUG_PARPORT_IP32 < 2 */
  398. #define parport_ip32_dump_state(...) do { } while (0)
  399. #endif
  400. /*
  401. * CHECK_EXTRA_BITS - track and log extra bits
  402. * @p: pointer to &struct parport
  403. * @b: byte to inspect
  404. * @m: bit mask of authorized bits
  405. *
  406. * This is used to track and log extra bits that should not be there in
  407. * parport_ip32_write_control() and parport_ip32_frob_control(). It is only
  408. * defined if %DEBUG_PARPORT_IP32 >= 1.
  409. */
  410. #if DEBUG_PARPORT_IP32 >= 1
  411. #define CHECK_EXTRA_BITS(p, b, m) \
  412. do { \
  413. unsigned int __b = (b), __m = (m); \
  414. if (__b & ~__m) \
  415. pr_debug1(PPIP32 "%s: extra bits in %s(%s): " \
  416. "0x%02x/0x%02x\n", \
  417. (p)->name, __func__, #b, __b, __m); \
  418. } while (0)
  419. #else /* DEBUG_PARPORT_IP32 < 1 */
  420. #define CHECK_EXTRA_BITS(...) do { } while (0)
  421. #endif
  422. /*--- IP32 parallel port DMA operations --------------------------------*/
  423. /**
  424. * struct parport_ip32_dma_data - private data needed for DMA operation
  425. * @dir: DMA direction (from or to device)
  426. * @buf: buffer physical address
  427. * @len: buffer length
  428. * @next: address of next bytes to DMA transfer
  429. * @left: number of bytes remaining
  430. * @ctx: next context to write (0: context_a; 1: context_b)
  431. * @irq_on: are the DMA IRQs currently enabled?
  432. * @lock: spinlock to protect access to the structure
  433. */
  434. struct parport_ip32_dma_data {
  435. enum dma_data_direction dir;
  436. dma_addr_t buf;
  437. dma_addr_t next;
  438. size_t len;
  439. size_t left;
  440. unsigned int ctx;
  441. unsigned int irq_on;
  442. spinlock_t lock;
  443. };
  444. static struct parport_ip32_dma_data parport_ip32_dma;
  445. /**
  446. * parport_ip32_dma_setup_context - setup next DMA context
  447. * @limit: maximum data size for the context
  448. *
  449. * The alignment constraints must be verified in caller function, and the
  450. * parameter @limit must be set accordingly.
  451. */
  452. static void parport_ip32_dma_setup_context(unsigned int limit)
  453. {
  454. unsigned long flags;
  455. spin_lock_irqsave(&parport_ip32_dma.lock, flags);
  456. if (parport_ip32_dma.left > 0) {
  457. /* Note: ctxreg is "volatile" here only because
  458. * mace->perif.ctrl.parport.context_a and context_b are
  459. * "volatile". */
  460. volatile u64 __iomem *ctxreg = (parport_ip32_dma.ctx == 0) ?
  461. &mace->perif.ctrl.parport.context_a :
  462. &mace->perif.ctrl.parport.context_b;
  463. u64 count;
  464. u64 ctxval;
  465. if (parport_ip32_dma.left <= limit) {
  466. count = parport_ip32_dma.left;
  467. ctxval = MACEPAR_CONTEXT_LASTFLAG;
  468. } else {
  469. count = limit;
  470. ctxval = 0;
  471. }
  472. pr_trace(NULL,
  473. "(%u): 0x%04x:0x%04x, %u -> %u%s",
  474. limit,
  475. (unsigned int)parport_ip32_dma.buf,
  476. (unsigned int)parport_ip32_dma.next,
  477. (unsigned int)count,
  478. parport_ip32_dma.ctx, ctxval ? "*" : "");
  479. ctxval |= parport_ip32_dma.next &
  480. MACEPAR_CONTEXT_BASEADDR_MASK;
  481. ctxval |= ((count - 1) << MACEPAR_CONTEXT_DATALEN_SHIFT) &
  482. MACEPAR_CONTEXT_DATALEN_MASK;
  483. writeq(ctxval, ctxreg);
  484. parport_ip32_dma.next += count;
  485. parport_ip32_dma.left -= count;
  486. parport_ip32_dma.ctx ^= 1U;
  487. }
  488. /* If there is nothing more to send, disable IRQs to avoid to
  489. * face an IRQ storm which can lock the machine. Disable them
  490. * only once. */
  491. if (parport_ip32_dma.left == 0 && parport_ip32_dma.irq_on) {
  492. pr_debug(PPIP32 "IRQ off (ctx)\n");
  493. disable_irq_nosync(MACEISA_PAR_CTXA_IRQ);
  494. disable_irq_nosync(MACEISA_PAR_CTXB_IRQ);
  495. parport_ip32_dma.irq_on = 0;
  496. }
  497. spin_unlock_irqrestore(&parport_ip32_dma.lock, flags);
  498. }
  499. /**
  500. * parport_ip32_dma_interrupt - DMA interrupt handler
  501. * @irq: interrupt number
  502. * @dev_id: unused
  503. */
  504. static irqreturn_t parport_ip32_dma_interrupt(int irq, void *dev_id)
  505. {
  506. if (parport_ip32_dma.left)
  507. pr_trace(NULL, "(%d): ctx=%d", irq, parport_ip32_dma.ctx);
  508. parport_ip32_dma_setup_context(MACEPAR_CONTEXT_DATA_BOUND);
  509. return IRQ_HANDLED;
  510. }
  511. #if DEBUG_PARPORT_IP32
  512. static irqreturn_t parport_ip32_merr_interrupt(int irq, void *dev_id)
  513. {
  514. pr_trace1(NULL, "(%d)", irq);
  515. return IRQ_HANDLED;
  516. }
  517. #endif
  518. /**
  519. * parport_ip32_dma_start - begins a DMA transfer
  520. * @p: partport to work on
  521. * @dir: DMA direction: DMA_TO_DEVICE or DMA_FROM_DEVICE
  522. * @addr: pointer to data buffer
  523. * @count: buffer size
  524. *
  525. * Calls to parport_ip32_dma_start() and parport_ip32_dma_stop() must be
  526. * correctly balanced.
  527. */
  528. static int parport_ip32_dma_start(struct parport *p,
  529. enum dma_data_direction dir, void *addr, size_t count)
  530. {
  531. unsigned int limit;
  532. u64 ctrl;
  533. pr_trace(NULL, "(%d, %lu)", dir, (unsigned long)count);
  534. /* FIXME - add support for DMA_FROM_DEVICE. In this case, buffer must
  535. * be 64 bytes aligned. */
  536. BUG_ON(dir != DMA_TO_DEVICE);
  537. /* Reset DMA controller */
  538. ctrl = MACEPAR_CTLSTAT_RESET;
  539. writeq(ctrl, &mace->perif.ctrl.parport.cntlstat);
  540. /* DMA IRQs should normally be enabled */
  541. if (!parport_ip32_dma.irq_on) {
  542. WARN_ON(1);
  543. enable_irq(MACEISA_PAR_CTXA_IRQ);
  544. enable_irq(MACEISA_PAR_CTXB_IRQ);
  545. parport_ip32_dma.irq_on = 1;
  546. }
  547. /* Prepare DMA pointers */
  548. parport_ip32_dma.dir = dir;
  549. parport_ip32_dma.buf = dma_map_single(&p->bus_dev, addr, count, dir);
  550. parport_ip32_dma.len = count;
  551. parport_ip32_dma.next = parport_ip32_dma.buf;
  552. parport_ip32_dma.left = parport_ip32_dma.len;
  553. parport_ip32_dma.ctx = 0;
  554. /* Setup DMA direction and first two contexts */
  555. ctrl = (dir == DMA_TO_DEVICE) ? 0 : MACEPAR_CTLSTAT_DIRECTION;
  556. writeq(ctrl, &mace->perif.ctrl.parport.cntlstat);
  557. /* Single transfer should not cross a 4K page boundary */
  558. limit = MACEPAR_CONTEXT_DATA_BOUND -
  559. (parport_ip32_dma.next & (MACEPAR_CONTEXT_DATA_BOUND - 1));
  560. parport_ip32_dma_setup_context(limit);
  561. parport_ip32_dma_setup_context(MACEPAR_CONTEXT_DATA_BOUND);
  562. /* Real start of DMA transfer */
  563. ctrl |= MACEPAR_CTLSTAT_ENABLE;
  564. writeq(ctrl, &mace->perif.ctrl.parport.cntlstat);
  565. return 0;
  566. }
  567. /**
  568. * parport_ip32_dma_stop - ends a running DMA transfer
  569. * @p: partport to work on
  570. *
  571. * Calls to parport_ip32_dma_start() and parport_ip32_dma_stop() must be
  572. * correctly balanced.
  573. */
  574. static void parport_ip32_dma_stop(struct parport *p)
  575. {
  576. u64 ctx_a;
  577. u64 ctx_b;
  578. u64 ctrl;
  579. u64 diag;
  580. size_t res[2]; /* {[0] = res_a, [1] = res_b} */
  581. pr_trace(NULL, "()");
  582. /* Disable IRQs */
  583. spin_lock_irq(&parport_ip32_dma.lock);
  584. if (parport_ip32_dma.irq_on) {
  585. pr_debug(PPIP32 "IRQ off (stop)\n");
  586. disable_irq_nosync(MACEISA_PAR_CTXA_IRQ);
  587. disable_irq_nosync(MACEISA_PAR_CTXB_IRQ);
  588. parport_ip32_dma.irq_on = 0;
  589. }
  590. spin_unlock_irq(&parport_ip32_dma.lock);
  591. /* Force IRQ synchronization, even if the IRQs were disabled
  592. * elsewhere. */
  593. synchronize_irq(MACEISA_PAR_CTXA_IRQ);
  594. synchronize_irq(MACEISA_PAR_CTXB_IRQ);
  595. /* Stop DMA transfer */
  596. ctrl = readq(&mace->perif.ctrl.parport.cntlstat);
  597. ctrl &= ~MACEPAR_CTLSTAT_ENABLE;
  598. writeq(ctrl, &mace->perif.ctrl.parport.cntlstat);
  599. /* Adjust residue (parport_ip32_dma.left) */
  600. ctx_a = readq(&mace->perif.ctrl.parport.context_a);
  601. ctx_b = readq(&mace->perif.ctrl.parport.context_b);
  602. ctrl = readq(&mace->perif.ctrl.parport.cntlstat);
  603. diag = readq(&mace->perif.ctrl.parport.diagnostic);
  604. res[0] = (ctrl & MACEPAR_CTLSTAT_CTXA_VALID) ?
  605. 1 + ((ctx_a & MACEPAR_CONTEXT_DATALEN_MASK) >>
  606. MACEPAR_CONTEXT_DATALEN_SHIFT) :
  607. 0;
  608. res[1] = (ctrl & MACEPAR_CTLSTAT_CTXB_VALID) ?
  609. 1 + ((ctx_b & MACEPAR_CONTEXT_DATALEN_MASK) >>
  610. MACEPAR_CONTEXT_DATALEN_SHIFT) :
  611. 0;
  612. if (diag & MACEPAR_DIAG_DMACTIVE)
  613. res[(diag & MACEPAR_DIAG_CTXINUSE) != 0] =
  614. 1 + ((diag & MACEPAR_DIAG_CTRMASK) >>
  615. MACEPAR_DIAG_CTRSHIFT);
  616. parport_ip32_dma.left += res[0] + res[1];
  617. /* Reset DMA controller, and re-enable IRQs */
  618. ctrl = MACEPAR_CTLSTAT_RESET;
  619. writeq(ctrl, &mace->perif.ctrl.parport.cntlstat);
  620. pr_debug(PPIP32 "IRQ on (stop)\n");
  621. enable_irq(MACEISA_PAR_CTXA_IRQ);
  622. enable_irq(MACEISA_PAR_CTXB_IRQ);
  623. parport_ip32_dma.irq_on = 1;
  624. dma_unmap_single(&p->bus_dev, parport_ip32_dma.buf,
  625. parport_ip32_dma.len, parport_ip32_dma.dir);
  626. }
  627. /**
  628. * parport_ip32_dma_get_residue - get residue from last DMA transfer
  629. *
  630. * Returns the number of bytes remaining from last DMA transfer.
  631. */
  632. static inline size_t parport_ip32_dma_get_residue(void)
  633. {
  634. return parport_ip32_dma.left;
  635. }
  636. /**
  637. * parport_ip32_dma_register - initialize DMA engine
  638. *
  639. * Returns zero for success.
  640. */
  641. static int parport_ip32_dma_register(void)
  642. {
  643. int err;
  644. spin_lock_init(&parport_ip32_dma.lock);
  645. parport_ip32_dma.irq_on = 1;
  646. /* Reset DMA controller */
  647. writeq(MACEPAR_CTLSTAT_RESET, &mace->perif.ctrl.parport.cntlstat);
  648. /* Request IRQs */
  649. err = request_irq(MACEISA_PAR_CTXA_IRQ, parport_ip32_dma_interrupt,
  650. 0, "parport_ip32", NULL);
  651. if (err)
  652. goto fail_a;
  653. err = request_irq(MACEISA_PAR_CTXB_IRQ, parport_ip32_dma_interrupt,
  654. 0, "parport_ip32", NULL);
  655. if (err)
  656. goto fail_b;
  657. #if DEBUG_PARPORT_IP32
  658. /* FIXME - what is this IRQ for? */
  659. err = request_irq(MACEISA_PAR_MERR_IRQ, parport_ip32_merr_interrupt,
  660. 0, "parport_ip32", NULL);
  661. if (err)
  662. goto fail_merr;
  663. #endif
  664. return 0;
  665. #if DEBUG_PARPORT_IP32
  666. fail_merr:
  667. free_irq(MACEISA_PAR_CTXB_IRQ, NULL);
  668. #endif
  669. fail_b:
  670. free_irq(MACEISA_PAR_CTXA_IRQ, NULL);
  671. fail_a:
  672. return err;
  673. }
  674. /**
  675. * parport_ip32_dma_unregister - release and free resources for DMA engine
  676. */
  677. static void parport_ip32_dma_unregister(void)
  678. {
  679. #if DEBUG_PARPORT_IP32
  680. free_irq(MACEISA_PAR_MERR_IRQ, NULL);
  681. #endif
  682. free_irq(MACEISA_PAR_CTXB_IRQ, NULL);
  683. free_irq(MACEISA_PAR_CTXA_IRQ, NULL);
  684. }
  685. /*--- Interrupt handlers and associates --------------------------------*/
  686. /**
  687. * parport_ip32_wakeup - wakes up code waiting for an interrupt
  688. * @p: pointer to &struct parport
  689. */
  690. static inline void parport_ip32_wakeup(struct parport *p)
  691. {
  692. struct parport_ip32_private * const priv = p->physport->private_data;
  693. complete(&priv->irq_complete);
  694. }
  695. /**
  696. * parport_ip32_interrupt - interrupt handler
  697. * @irq: interrupt number
  698. * @dev_id: pointer to &struct parport
  699. *
  700. * Caught interrupts are forwarded to the upper parport layer if IRQ_mode is
  701. * %PARPORT_IP32_IRQ_FWD.
  702. */
  703. static irqreturn_t parport_ip32_interrupt(int irq, void *dev_id)
  704. {
  705. struct parport * const p = dev_id;
  706. struct parport_ip32_private * const priv = p->physport->private_data;
  707. enum parport_ip32_irq_mode irq_mode = priv->irq_mode;
  708. switch (irq_mode) {
  709. case PARPORT_IP32_IRQ_FWD:
  710. return parport_irq_handler(irq, dev_id);
  711. case PARPORT_IP32_IRQ_HERE:
  712. parport_ip32_wakeup(p);
  713. break;
  714. }
  715. return IRQ_HANDLED;
  716. }
  717. /*--- Some utility function to manipulate ECR register -----------------*/
  718. /**
  719. * parport_ip32_read_econtrol - read contents of the ECR register
  720. * @p: pointer to &struct parport
  721. */
  722. static inline unsigned int parport_ip32_read_econtrol(struct parport *p)
  723. {
  724. struct parport_ip32_private * const priv = p->physport->private_data;
  725. return readb(priv->regs.ecr);
  726. }
  727. /**
  728. * parport_ip32_write_econtrol - write new contents to the ECR register
  729. * @p: pointer to &struct parport
  730. * @c: new value to write
  731. */
  732. static inline void parport_ip32_write_econtrol(struct parport *p,
  733. unsigned int c)
  734. {
  735. struct parport_ip32_private * const priv = p->physport->private_data;
  736. writeb(c, priv->regs.ecr);
  737. }
  738. /**
  739. * parport_ip32_frob_econtrol - change bits from the ECR register
  740. * @p: pointer to &struct parport
  741. * @mask: bit mask of bits to change
  742. * @val: new value for changed bits
  743. *
  744. * Read from the ECR, mask out the bits in @mask, exclusive-or with the bits
  745. * in @val, and write the result to the ECR.
  746. */
  747. static inline void parport_ip32_frob_econtrol(struct parport *p,
  748. unsigned int mask,
  749. unsigned int val)
  750. {
  751. unsigned int c;
  752. c = (parport_ip32_read_econtrol(p) & ~mask) ^ val;
  753. parport_ip32_write_econtrol(p, c);
  754. }
  755. /**
  756. * parport_ip32_set_mode - change mode of ECP port
  757. * @p: pointer to &struct parport
  758. * @mode: new mode to write in ECR
  759. *
  760. * ECR is reset in a sane state (interrupts and DMA disabled), and placed in
  761. * mode @mode. Go through PS2 mode if needed.
  762. */
  763. static void parport_ip32_set_mode(struct parport *p, unsigned int mode)
  764. {
  765. unsigned int omode;
  766. mode &= ECR_MODE_MASK;
  767. omode = parport_ip32_read_econtrol(p) & ECR_MODE_MASK;
  768. if (!(mode == ECR_MODE_SPP || mode == ECR_MODE_PS2
  769. || omode == ECR_MODE_SPP || omode == ECR_MODE_PS2)) {
  770. /* We have to go through PS2 mode */
  771. unsigned int ecr = ECR_MODE_PS2 | ECR_nERRINTR | ECR_SERVINTR;
  772. parport_ip32_write_econtrol(p, ecr);
  773. }
  774. parport_ip32_write_econtrol(p, mode | ECR_nERRINTR | ECR_SERVINTR);
  775. }
  776. /*--- Basic functions needed for parport -------------------------------*/
  777. /**
  778. * parport_ip32_read_data - return current contents of the DATA register
  779. * @p: pointer to &struct parport
  780. */
  781. static inline unsigned char parport_ip32_read_data(struct parport *p)
  782. {
  783. struct parport_ip32_private * const priv = p->physport->private_data;
  784. return readb(priv->regs.data);
  785. }
  786. /**
  787. * parport_ip32_write_data - set new contents for the DATA register
  788. * @p: pointer to &struct parport
  789. * @d: new value to write
  790. */
  791. static inline void parport_ip32_write_data(struct parport *p, unsigned char d)
  792. {
  793. struct parport_ip32_private * const priv = p->physport->private_data;
  794. writeb(d, priv->regs.data);
  795. }
  796. /**
  797. * parport_ip32_read_status - return current contents of the DSR register
  798. * @p: pointer to &struct parport
  799. */
  800. static inline unsigned char parport_ip32_read_status(struct parport *p)
  801. {
  802. struct parport_ip32_private * const priv = p->physport->private_data;
  803. return readb(priv->regs.dsr);
  804. }
  805. /**
  806. * __parport_ip32_read_control - return cached contents of the DCR register
  807. * @p: pointer to &struct parport
  808. */
  809. static inline unsigned int __parport_ip32_read_control(struct parport *p)
  810. {
  811. struct parport_ip32_private * const priv = p->physport->private_data;
  812. return priv->dcr_cache; /* use soft copy */
  813. }
  814. /**
  815. * __parport_ip32_write_control - set new contents for the DCR register
  816. * @p: pointer to &struct parport
  817. * @c: new value to write
  818. */
  819. static inline void __parport_ip32_write_control(struct parport *p,
  820. unsigned int c)
  821. {
  822. struct parport_ip32_private * const priv = p->physport->private_data;
  823. CHECK_EXTRA_BITS(p, c, priv->dcr_writable);
  824. c &= priv->dcr_writable; /* only writable bits */
  825. writeb(c, priv->regs.dcr);
  826. priv->dcr_cache = c; /* update soft copy */
  827. }
  828. /**
  829. * __parport_ip32_frob_control - change bits from the DCR register
  830. * @p: pointer to &struct parport
  831. * @mask: bit mask of bits to change
  832. * @val: new value for changed bits
  833. *
  834. * This is equivalent to read from the DCR, mask out the bits in @mask,
  835. * exclusive-or with the bits in @val, and write the result to the DCR.
  836. * Actually, the cached contents of the DCR is used.
  837. */
  838. static inline void __parport_ip32_frob_control(struct parport *p,
  839. unsigned int mask,
  840. unsigned int val)
  841. {
  842. unsigned int c;
  843. c = (__parport_ip32_read_control(p) & ~mask) ^ val;
  844. __parport_ip32_write_control(p, c);
  845. }
  846. /**
  847. * parport_ip32_read_control - return cached contents of the DCR register
  848. * @p: pointer to &struct parport
  849. *
  850. * The return value is masked so as to only return the value of %DCR_STROBE,
  851. * %DCR_AUTOFD, %DCR_nINIT, and %DCR_SELECT.
  852. */
  853. static inline unsigned char parport_ip32_read_control(struct parport *p)
  854. {
  855. const unsigned int rm =
  856. DCR_STROBE | DCR_AUTOFD | DCR_nINIT | DCR_SELECT;
  857. return __parport_ip32_read_control(p) & rm;
  858. }
  859. /**
  860. * parport_ip32_write_control - set new contents for the DCR register
  861. * @p: pointer to &struct parport
  862. * @c: new value to write
  863. *
  864. * The value is masked so as to only change the value of %DCR_STROBE,
  865. * %DCR_AUTOFD, %DCR_nINIT, and %DCR_SELECT.
  866. */
  867. static inline void parport_ip32_write_control(struct parport *p,
  868. unsigned char c)
  869. {
  870. const unsigned int wm =
  871. DCR_STROBE | DCR_AUTOFD | DCR_nINIT | DCR_SELECT;
  872. CHECK_EXTRA_BITS(p, c, wm);
  873. __parport_ip32_frob_control(p, wm, c & wm);
  874. }
  875. /**
  876. * parport_ip32_frob_control - change bits from the DCR register
  877. * @p: pointer to &struct parport
  878. * @mask: bit mask of bits to change
  879. * @val: new value for changed bits
  880. *
  881. * This differs from __parport_ip32_frob_control() in that it only allows to
  882. * change the value of %DCR_STROBE, %DCR_AUTOFD, %DCR_nINIT, and %DCR_SELECT.
  883. */
  884. static inline unsigned char parport_ip32_frob_control(struct parport *p,
  885. unsigned char mask,
  886. unsigned char val)
  887. {
  888. const unsigned int wm =
  889. DCR_STROBE | DCR_AUTOFD | DCR_nINIT | DCR_SELECT;
  890. CHECK_EXTRA_BITS(p, mask, wm);
  891. CHECK_EXTRA_BITS(p, val, wm);
  892. __parport_ip32_frob_control(p, mask & wm, val & wm);
  893. return parport_ip32_read_control(p);
  894. }
  895. /**
  896. * parport_ip32_disable_irq - disable interrupts on the rising edge of nACK
  897. * @p: pointer to &struct parport
  898. */
  899. static inline void parport_ip32_disable_irq(struct parport *p)
  900. {
  901. __parport_ip32_frob_control(p, DCR_IRQ, 0);
  902. }
  903. /**
  904. * parport_ip32_enable_irq - enable interrupts on the rising edge of nACK
  905. * @p: pointer to &struct parport
  906. */
  907. static inline void parport_ip32_enable_irq(struct parport *p)
  908. {
  909. __parport_ip32_frob_control(p, DCR_IRQ, DCR_IRQ);
  910. }
  911. /**
  912. * parport_ip32_data_forward - enable host-to-peripheral communications
  913. * @p: pointer to &struct parport
  914. *
  915. * Enable the data line drivers, for 8-bit host-to-peripheral communications.
  916. */
  917. static inline void parport_ip32_data_forward(struct parport *p)
  918. {
  919. __parport_ip32_frob_control(p, DCR_DIR, 0);
  920. }
  921. /**
  922. * parport_ip32_data_reverse - enable peripheral-to-host communications
  923. * @p: pointer to &struct parport
  924. *
  925. * Place the data bus in a high impedance state, if @p->modes has the
  926. * PARPORT_MODE_TRISTATE bit set.
  927. */
  928. static inline void parport_ip32_data_reverse(struct parport *p)
  929. {
  930. __parport_ip32_frob_control(p, DCR_DIR, DCR_DIR);
  931. }
  932. /**
  933. * parport_ip32_init_state - for core parport code
  934. * @dev: pointer to &struct pardevice
  935. * @s: pointer to &struct parport_state to initialize
  936. */
  937. static void parport_ip32_init_state(struct pardevice *dev,
  938. struct parport_state *s)
  939. {
  940. s->u.ip32.dcr = DCR_SELECT | DCR_nINIT;
  941. s->u.ip32.ecr = ECR_MODE_PS2 | ECR_nERRINTR | ECR_SERVINTR;
  942. }
  943. /**
  944. * parport_ip32_save_state - for core parport code
  945. * @p: pointer to &struct parport
  946. * @s: pointer to &struct parport_state to save state to
  947. */
  948. static void parport_ip32_save_state(struct parport *p,
  949. struct parport_state *s)
  950. {
  951. s->u.ip32.dcr = __parport_ip32_read_control(p);
  952. s->u.ip32.ecr = parport_ip32_read_econtrol(p);
  953. }
  954. /**
  955. * parport_ip32_restore_state - for core parport code
  956. * @p: pointer to &struct parport
  957. * @s: pointer to &struct parport_state to restore state from
  958. */
  959. static void parport_ip32_restore_state(struct parport *p,
  960. struct parport_state *s)
  961. {
  962. parport_ip32_set_mode(p, s->u.ip32.ecr & ECR_MODE_MASK);
  963. parport_ip32_write_econtrol(p, s->u.ip32.ecr);
  964. __parport_ip32_write_control(p, s->u.ip32.dcr);
  965. }
  966. /*--- EPP mode functions -----------------------------------------------*/
  967. /**
  968. * parport_ip32_clear_epp_timeout - clear Timeout bit in EPP mode
  969. * @p: pointer to &struct parport
  970. *
  971. * Returns 1 if the Timeout bit is clear, and 0 otherwise.
  972. */
  973. static unsigned int parport_ip32_clear_epp_timeout(struct parport *p)
  974. {
  975. struct parport_ip32_private * const priv = p->physport->private_data;
  976. unsigned int cleared;
  977. if (!(parport_ip32_read_status(p) & DSR_TIMEOUT))
  978. cleared = 1;
  979. else {
  980. unsigned int r;
  981. /* To clear timeout some chips require double read */
  982. parport_ip32_read_status(p);
  983. r = parport_ip32_read_status(p);
  984. /* Some reset by writing 1 */
  985. writeb(r | DSR_TIMEOUT, priv->regs.dsr);
  986. /* Others by writing 0 */
  987. writeb(r & ~DSR_TIMEOUT, priv->regs.dsr);
  988. r = parport_ip32_read_status(p);
  989. cleared = !(r & DSR_TIMEOUT);
  990. }
  991. pr_trace(p, "(): %s", cleared ? "cleared" : "failed");
  992. return cleared;
  993. }
  994. /**
  995. * parport_ip32_epp_read - generic EPP read function
  996. * @eppreg: I/O register to read from
  997. * @p: pointer to &struct parport
  998. * @buf: buffer to store read data
  999. * @len: length of buffer @buf
  1000. * @flags: may be PARPORT_EPP_FAST
  1001. */
  1002. static size_t parport_ip32_epp_read(void __iomem *eppreg,
  1003. struct parport *p, void *buf,
  1004. size_t len, int flags)
  1005. {
  1006. struct parport_ip32_private * const priv = p->physport->private_data;
  1007. size_t got;
  1008. parport_ip32_set_mode(p, ECR_MODE_EPP);
  1009. parport_ip32_data_reverse(p);
  1010. parport_ip32_write_control(p, DCR_nINIT);
  1011. if ((flags & PARPORT_EPP_FAST) && (len > 1)) {
  1012. readsb(eppreg, buf, len);
  1013. if (readb(priv->regs.dsr) & DSR_TIMEOUT) {
  1014. parport_ip32_clear_epp_timeout(p);
  1015. return -EIO;
  1016. }
  1017. got = len;
  1018. } else {
  1019. u8 *bufp = buf;
  1020. for (got = 0; got < len; got++) {
  1021. *bufp++ = readb(eppreg);
  1022. if (readb(priv->regs.dsr) & DSR_TIMEOUT) {
  1023. parport_ip32_clear_epp_timeout(p);
  1024. break;
  1025. }
  1026. }
  1027. }
  1028. parport_ip32_data_forward(p);
  1029. parport_ip32_set_mode(p, ECR_MODE_PS2);
  1030. return got;
  1031. }
  1032. /**
  1033. * parport_ip32_epp_write - generic EPP write function
  1034. * @eppreg: I/O register to write to
  1035. * @p: pointer to &struct parport
  1036. * @buf: buffer of data to write
  1037. * @len: length of buffer @buf
  1038. * @flags: may be PARPORT_EPP_FAST
  1039. */
  1040. static size_t parport_ip32_epp_write(void __iomem *eppreg,
  1041. struct parport *p, const void *buf,
  1042. size_t len, int flags)
  1043. {
  1044. struct parport_ip32_private * const priv = p->physport->private_data;
  1045. size_t written;
  1046. parport_ip32_set_mode(p, ECR_MODE_EPP);
  1047. parport_ip32_data_forward(p);
  1048. parport_ip32_write_control(p, DCR_nINIT);
  1049. if ((flags & PARPORT_EPP_FAST) && (len > 1)) {
  1050. writesb(eppreg, buf, len);
  1051. if (readb(priv->regs.dsr) & DSR_TIMEOUT) {
  1052. parport_ip32_clear_epp_timeout(p);
  1053. return -EIO;
  1054. }
  1055. written = len;
  1056. } else {
  1057. const u8 *bufp = buf;
  1058. for (written = 0; written < len; written++) {
  1059. writeb(*bufp++, eppreg);
  1060. if (readb(priv->regs.dsr) & DSR_TIMEOUT) {
  1061. parport_ip32_clear_epp_timeout(p);
  1062. break;
  1063. }
  1064. }
  1065. }
  1066. parport_ip32_set_mode(p, ECR_MODE_PS2);
  1067. return written;
  1068. }
  1069. /**
  1070. * parport_ip32_epp_read_data - read a block of data in EPP mode
  1071. * @p: pointer to &struct parport
  1072. * @buf: buffer to store read data
  1073. * @len: length of buffer @buf
  1074. * @flags: may be PARPORT_EPP_FAST
  1075. */
  1076. static size_t parport_ip32_epp_read_data(struct parport *p, void *buf,
  1077. size_t len, int flags)
  1078. {
  1079. struct parport_ip32_private * const priv = p->physport->private_data;
  1080. return parport_ip32_epp_read(priv->regs.eppData0, p, buf, len, flags);
  1081. }
  1082. /**
  1083. * parport_ip32_epp_write_data - write a block of data in EPP mode
  1084. * @p: pointer to &struct parport
  1085. * @buf: buffer of data to write
  1086. * @len: length of buffer @buf
  1087. * @flags: may be PARPORT_EPP_FAST
  1088. */
  1089. static size_t parport_ip32_epp_write_data(struct parport *p, const void *buf,
  1090. size_t len, int flags)
  1091. {
  1092. struct parport_ip32_private * const priv = p->physport->private_data;
  1093. return parport_ip32_epp_write(priv->regs.eppData0, p, buf, len, flags);
  1094. }
  1095. /**
  1096. * parport_ip32_epp_read_addr - read a block of addresses in EPP mode
  1097. * @p: pointer to &struct parport
  1098. * @buf: buffer to store read data
  1099. * @len: length of buffer @buf
  1100. * @flags: may be PARPORT_EPP_FAST
  1101. */
  1102. static size_t parport_ip32_epp_read_addr(struct parport *p, void *buf,
  1103. size_t len, int flags)
  1104. {
  1105. struct parport_ip32_private * const priv = p->physport->private_data;
  1106. return parport_ip32_epp_read(priv->regs.eppAddr, p, buf, len, flags);
  1107. }
  1108. /**
  1109. * parport_ip32_epp_write_addr - write a block of addresses in EPP mode
  1110. * @p: pointer to &struct parport
  1111. * @buf: buffer of data to write
  1112. * @len: length of buffer @buf
  1113. * @flags: may be PARPORT_EPP_FAST
  1114. */
  1115. static size_t parport_ip32_epp_write_addr(struct parport *p, const void *buf,
  1116. size_t len, int flags)
  1117. {
  1118. struct parport_ip32_private * const priv = p->physport->private_data;
  1119. return parport_ip32_epp_write(priv->regs.eppAddr, p, buf, len, flags);
  1120. }
  1121. /*--- ECP mode functions (FIFO) ----------------------------------------*/
  1122. /**
  1123. * parport_ip32_fifo_wait_break - check if the waiting function should return
  1124. * @p: pointer to &struct parport
  1125. * @expire: timeout expiring date, in jiffies
  1126. *
  1127. * parport_ip32_fifo_wait_break() checks if the waiting function should return
  1128. * immediately or not. The break conditions are:
  1129. * - expired timeout;
  1130. * - a pending signal;
  1131. * - nFault asserted low.
  1132. * This function also calls cond_resched().
  1133. */
  1134. static unsigned int parport_ip32_fifo_wait_break(struct parport *p,
  1135. unsigned long expire)
  1136. {
  1137. cond_resched();
  1138. if (time_after(jiffies, expire)) {
  1139. pr_debug1(PPIP32 "%s: FIFO write timed out\n", p->name);
  1140. return 1;
  1141. }
  1142. if (signal_pending(current)) {
  1143. pr_debug1(PPIP32 "%s: Signal pending\n", p->name);
  1144. return 1;
  1145. }
  1146. if (!(parport_ip32_read_status(p) & DSR_nFAULT)) {
  1147. pr_debug1(PPIP32 "%s: nFault asserted low\n", p->name);
  1148. return 1;
  1149. }
  1150. return 0;
  1151. }
  1152. /**
  1153. * parport_ip32_fwp_wait_polling - wait for FIFO to empty (polling)
  1154. * @p: pointer to &struct parport
  1155. *
  1156. * Returns the number of bytes that can safely be written in the FIFO. A
  1157. * return value of zero means that the calling function should terminate as
  1158. * fast as possible.
  1159. */
  1160. static unsigned int parport_ip32_fwp_wait_polling(struct parport *p)
  1161. {
  1162. struct parport_ip32_private * const priv = p->physport->private_data;
  1163. struct parport * const physport = p->physport;
  1164. unsigned long expire;
  1165. unsigned int count;
  1166. unsigned int ecr;
  1167. expire = jiffies + physport->cad->timeout;
  1168. count = 0;
  1169. while (1) {
  1170. if (parport_ip32_fifo_wait_break(p, expire))
  1171. break;
  1172. /* Check FIFO state. We do nothing when the FIFO is nor full,
  1173. * nor empty. It appears that the FIFO full bit is not always
  1174. * reliable, the FIFO state is sometimes wrongly reported, and
  1175. * the chip gets confused if we give it another byte. */
  1176. ecr = parport_ip32_read_econtrol(p);
  1177. if (ecr & ECR_F_EMPTY) {
  1178. /* FIFO is empty, fill it up */
  1179. count = priv->fifo_depth;
  1180. break;
  1181. }
  1182. /* Wait a moment... */
  1183. udelay(FIFO_POLLING_INTERVAL);
  1184. } /* while (1) */
  1185. return count;
  1186. }
  1187. /**
  1188. * parport_ip32_fwp_wait_interrupt - wait for FIFO to empty (interrupt-driven)
  1189. * @p: pointer to &struct parport
  1190. *
  1191. * Returns the number of bytes that can safely be written in the FIFO. A
  1192. * return value of zero means that the calling function should terminate as
  1193. * fast as possible.
  1194. */
  1195. static unsigned int parport_ip32_fwp_wait_interrupt(struct parport *p)
  1196. {
  1197. static unsigned int lost_interrupt = 0;
  1198. struct parport_ip32_private * const priv = p->physport->private_data;
  1199. struct parport * const physport = p->physport;
  1200. unsigned long nfault_timeout;
  1201. unsigned long expire;
  1202. unsigned int count;
  1203. unsigned int ecr;
  1204. nfault_timeout = min((unsigned long)physport->cad->timeout,
  1205. msecs_to_jiffies(FIFO_NFAULT_TIMEOUT));
  1206. expire = jiffies + physport->cad->timeout;
  1207. count = 0;
  1208. while (1) {
  1209. if (parport_ip32_fifo_wait_break(p, expire))
  1210. break;
  1211. /* Initialize mutex used to take interrupts into account */
  1212. reinit_completion(&priv->irq_complete);
  1213. /* Enable serviceIntr */
  1214. parport_ip32_frob_econtrol(p, ECR_SERVINTR, 0);
  1215. /* Enabling serviceIntr while the FIFO is empty does not
  1216. * always generate an interrupt, so check for emptiness
  1217. * now. */
  1218. ecr = parport_ip32_read_econtrol(p);
  1219. if (!(ecr & ECR_F_EMPTY)) {
  1220. /* FIFO is not empty: wait for an interrupt or a
  1221. * timeout to occur */
  1222. wait_for_completion_interruptible_timeout(
  1223. &priv->irq_complete, nfault_timeout);
  1224. ecr = parport_ip32_read_econtrol(p);
  1225. if ((ecr & ECR_F_EMPTY) && !(ecr & ECR_SERVINTR)
  1226. && !lost_interrupt) {
  1227. pr_warn(PPIP32 "%s: lost interrupt in %s\n",
  1228. p->name, __func__);
  1229. lost_interrupt = 1;
  1230. }
  1231. }
  1232. /* Disable serviceIntr */
  1233. parport_ip32_frob_econtrol(p, ECR_SERVINTR, ECR_SERVINTR);
  1234. /* Check FIFO state */
  1235. if (ecr & ECR_F_EMPTY) {
  1236. /* FIFO is empty, fill it up */
  1237. count = priv->fifo_depth;
  1238. break;
  1239. } else if (ecr & ECR_SERVINTR) {
  1240. /* FIFO is not empty, but we know that can safely push
  1241. * writeIntrThreshold bytes into it */
  1242. count = priv->writeIntrThreshold;
  1243. break;
  1244. }
  1245. /* FIFO is not empty, and we did not get any interrupt.
  1246. * Either it's time to check for nFault, or a signal is
  1247. * pending. This is verified in
  1248. * parport_ip32_fifo_wait_break(), so we continue the loop. */
  1249. } /* while (1) */
  1250. return count;
  1251. }
  1252. /**
  1253. * parport_ip32_fifo_write_block_pio - write a block of data (PIO mode)
  1254. * @p: pointer to &struct parport
  1255. * @buf: buffer of data to write
  1256. * @len: length of buffer @buf
  1257. *
  1258. * Uses PIO to write the contents of the buffer @buf into the parallel port
  1259. * FIFO. Returns the number of bytes that were actually written. It can work
  1260. * with or without the help of interrupts. The parallel port must be
  1261. * correctly initialized before calling parport_ip32_fifo_write_block_pio().
  1262. */
  1263. static size_t parport_ip32_fifo_write_block_pio(struct parport *p,
  1264. const void *buf, size_t len)
  1265. {
  1266. struct parport_ip32_private * const priv = p->physport->private_data;
  1267. const u8 *bufp = buf;
  1268. size_t left = len;
  1269. priv->irq_mode = PARPORT_IP32_IRQ_HERE;
  1270. while (left > 0) {
  1271. unsigned int count;
  1272. count = (p->irq == PARPORT_IRQ_NONE) ?
  1273. parport_ip32_fwp_wait_polling(p) :
  1274. parport_ip32_fwp_wait_interrupt(p);
  1275. if (count == 0)
  1276. break; /* Transmission should be stopped */
  1277. if (count > left)
  1278. count = left;
  1279. if (count == 1) {
  1280. writeb(*bufp, priv->regs.fifo);
  1281. bufp++, left--;
  1282. } else {
  1283. writesb(priv->regs.fifo, bufp, count);
  1284. bufp += count, left -= count;
  1285. }
  1286. }
  1287. priv->irq_mode = PARPORT_IP32_IRQ_FWD;
  1288. return len - left;
  1289. }
  1290. /**
  1291. * parport_ip32_fifo_write_block_dma - write a block of data (DMA mode)
  1292. * @p: pointer to &struct parport
  1293. * @buf: buffer of data to write
  1294. * @len: length of buffer @buf
  1295. *
  1296. * Uses DMA to write the contents of the buffer @buf into the parallel port
  1297. * FIFO. Returns the number of bytes that were actually written. The
  1298. * parallel port must be correctly initialized before calling
  1299. * parport_ip32_fifo_write_block_dma().
  1300. */
  1301. static size_t parport_ip32_fifo_write_block_dma(struct parport *p,
  1302. const void *buf, size_t len)
  1303. {
  1304. struct parport_ip32_private * const priv = p->physport->private_data;
  1305. struct parport * const physport = p->physport;
  1306. unsigned long nfault_timeout;
  1307. unsigned long expire;
  1308. size_t written;
  1309. unsigned int ecr;
  1310. priv->irq_mode = PARPORT_IP32_IRQ_HERE;
  1311. parport_ip32_dma_start(p, DMA_TO_DEVICE, (void *)buf, len);
  1312. reinit_completion(&priv->irq_complete);
  1313. parport_ip32_frob_econtrol(p, ECR_DMAEN | ECR_SERVINTR, ECR_DMAEN);
  1314. nfault_timeout = min((unsigned long)physport->cad->timeout,
  1315. msecs_to_jiffies(FIFO_NFAULT_TIMEOUT));
  1316. expire = jiffies + physport->cad->timeout;
  1317. while (1) {
  1318. if (parport_ip32_fifo_wait_break(p, expire))
  1319. break;
  1320. wait_for_completion_interruptible_timeout(&priv->irq_complete,
  1321. nfault_timeout);
  1322. ecr = parport_ip32_read_econtrol(p);
  1323. if (ecr & ECR_SERVINTR)
  1324. break; /* DMA transfer just finished */
  1325. }
  1326. parport_ip32_dma_stop(p);
  1327. written = len - parport_ip32_dma_get_residue();
  1328. priv->irq_mode = PARPORT_IP32_IRQ_FWD;
  1329. return written;
  1330. }
  1331. /**
  1332. * parport_ip32_fifo_write_block - write a block of data
  1333. * @p: pointer to &struct parport
  1334. * @buf: buffer of data to write
  1335. * @len: length of buffer @buf
  1336. *
  1337. * Uses PIO or DMA to write the contents of the buffer @buf into the parallel
  1338. * p FIFO. Returns the number of bytes that were actually written.
  1339. */
  1340. static size_t parport_ip32_fifo_write_block(struct parport *p,
  1341. const void *buf, size_t len)
  1342. {
  1343. size_t written = 0;
  1344. if (len)
  1345. /* FIXME - Maybe some threshold value should be set for @len
  1346. * under which we revert to PIO mode? */
  1347. written = (p->modes & PARPORT_MODE_DMA) ?
  1348. parport_ip32_fifo_write_block_dma(p, buf, len) :
  1349. parport_ip32_fifo_write_block_pio(p, buf, len);
  1350. return written;
  1351. }
  1352. /**
  1353. * parport_ip32_drain_fifo - wait for FIFO to empty
  1354. * @p: pointer to &struct parport
  1355. * @timeout: timeout, in jiffies
  1356. *
  1357. * This function waits for FIFO to empty. It returns 1 when FIFO is empty, or
  1358. * 0 if the timeout @timeout is reached before, or if a signal is pending.
  1359. */
  1360. static unsigned int parport_ip32_drain_fifo(struct parport *p,
  1361. unsigned long timeout)
  1362. {
  1363. unsigned long expire = jiffies + timeout;
  1364. unsigned int polling_interval;
  1365. unsigned int counter;
  1366. /* Busy wait for approx. 200us */
  1367. for (counter = 0; counter < 40; counter++) {
  1368. if (parport_ip32_read_econtrol(p) & ECR_F_EMPTY)
  1369. break;
  1370. if (time_after(jiffies, expire))
  1371. break;
  1372. if (signal_pending(current))
  1373. break;
  1374. udelay(5);
  1375. }
  1376. /* Poll slowly. Polling interval starts with 1 millisecond, and is
  1377. * increased exponentially until 128. */
  1378. polling_interval = 1; /* msecs */
  1379. while (!(parport_ip32_read_econtrol(p) & ECR_F_EMPTY)) {
  1380. if (time_after_eq(jiffies, expire))
  1381. break;
  1382. msleep_interruptible(polling_interval);
  1383. if (signal_pending(current))
  1384. break;
  1385. if (polling_interval < 128)
  1386. polling_interval *= 2;
  1387. }
  1388. return !!(parport_ip32_read_econtrol(p) & ECR_F_EMPTY);
  1389. }
  1390. /**
  1391. * parport_ip32_get_fifo_residue - reset FIFO
  1392. * @p: pointer to &struct parport
  1393. * @mode: current operation mode (ECR_MODE_PPF or ECR_MODE_ECP)
  1394. *
  1395. * This function resets FIFO, and returns the number of bytes remaining in it.
  1396. */
  1397. static unsigned int parport_ip32_get_fifo_residue(struct parport *p,
  1398. unsigned int mode)
  1399. {
  1400. struct parport_ip32_private * const priv = p->physport->private_data;
  1401. unsigned int residue;
  1402. unsigned int cnfga;
  1403. /* FIXME - We are missing one byte if the printer is off-line. I
  1404. * don't know how to detect this. It looks that the full bit is not
  1405. * always reliable. For the moment, the problem is avoided in most
  1406. * cases by testing for BUSY in parport_ip32_compat_write_data().
  1407. */
  1408. if (parport_ip32_read_econtrol(p) & ECR_F_EMPTY)
  1409. residue = 0;
  1410. else {
  1411. pr_debug1(PPIP32 "%s: FIFO is stuck\n", p->name);
  1412. /* Stop all transfers.
  1413. *
  1414. * Microsoft's document instructs to drive DCR_STROBE to 0,
  1415. * but it doesn't work (at least in Compatibility mode, not
  1416. * tested in ECP mode). Switching directly to Test mode (as
  1417. * in parport_pc) is not an option: it does confuse the port,
  1418. * ECP service interrupts are no more working after that. A
  1419. * hard reset is then needed to revert to a sane state.
  1420. *
  1421. * Let's hope that the FIFO is really stuck and that the
  1422. * peripheral doesn't wake up now.
  1423. */
  1424. parport_ip32_frob_control(p, DCR_STROBE, 0);
  1425. /* Fill up FIFO */
  1426. for (residue = priv->fifo_depth; residue > 0; residue--) {
  1427. if (parport_ip32_read_econtrol(p) & ECR_F_FULL)
  1428. break;
  1429. writeb(0x00, priv->regs.fifo);
  1430. }
  1431. }
  1432. if (residue)
  1433. pr_debug1(PPIP32 "%s: %d PWord%s left in FIFO\n",
  1434. p->name, residue,
  1435. (residue == 1) ? " was" : "s were");
  1436. /* Now reset the FIFO */
  1437. parport_ip32_set_mode(p, ECR_MODE_PS2);
  1438. /* Host recovery for ECP mode */
  1439. if (mode == ECR_MODE_ECP) {
  1440. parport_ip32_data_reverse(p);
  1441. parport_ip32_frob_control(p, DCR_nINIT, 0);
  1442. if (parport_wait_peripheral(p, DSR_PERROR, 0))
  1443. pr_debug1(PPIP32 "%s: PEerror timeout 1 in %s\n",
  1444. p->name, __func__);
  1445. parport_ip32_frob_control(p, DCR_STROBE, DCR_STROBE);
  1446. parport_ip32_frob_control(p, DCR_nINIT, DCR_nINIT);
  1447. if (parport_wait_peripheral(p, DSR_PERROR, DSR_PERROR))
  1448. pr_debug1(PPIP32 "%s: PEerror timeout 2 in %s\n",
  1449. p->name, __func__);
  1450. }
  1451. /* Adjust residue if needed */
  1452. parport_ip32_set_mode(p, ECR_MODE_CFG);
  1453. cnfga = readb(priv->regs.cnfgA);
  1454. if (!(cnfga & CNFGA_nBYTEINTRANS)) {
  1455. pr_debug1(PPIP32 "%s: cnfgA contains 0x%02x\n",
  1456. p->name, cnfga);
  1457. pr_debug1(PPIP32 "%s: Accounting for extra byte\n",
  1458. p->name);
  1459. residue++;
  1460. }
  1461. /* Don't care about partial PWords since we do not support
  1462. * PWord != 1 byte. */
  1463. /* Back to forward PS2 mode. */
  1464. parport_ip32_set_mode(p, ECR_MODE_PS2);
  1465. parport_ip32_data_forward(p);
  1466. return residue;
  1467. }
  1468. /**
  1469. * parport_ip32_compat_write_data - write a block of data in SPP mode
  1470. * @p: pointer to &struct parport
  1471. * @buf: buffer of data to write
  1472. * @len: length of buffer @buf
  1473. * @flags: ignored
  1474. */
  1475. static size_t parport_ip32_compat_write_data(struct parport *p,
  1476. const void *buf, size_t len,
  1477. int flags)
  1478. {
  1479. static unsigned int ready_before = 1;
  1480. struct parport_ip32_private * const priv = p->physport->private_data;
  1481. struct parport * const physport = p->physport;
  1482. size_t written = 0;
  1483. /* Special case: a timeout of zero means we cannot call schedule().
  1484. * Also if O_NONBLOCK is set then use the default implementation. */
  1485. if (physport->cad->timeout <= PARPORT_INACTIVITY_O_NONBLOCK)
  1486. return parport_ieee1284_write_compat(p, buf, len, flags);
  1487. /* Reset FIFO, go in forward mode, and disable ackIntEn */
  1488. parport_ip32_set_mode(p, ECR_MODE_PS2);
  1489. parport_ip32_write_control(p, DCR_SELECT | DCR_nINIT);
  1490. parport_ip32_data_forward(p);
  1491. parport_ip32_disable_irq(p);
  1492. parport_ip32_set_mode(p, ECR_MODE_PPF);
  1493. physport->ieee1284.phase = IEEE1284_PH_FWD_DATA;
  1494. /* Wait for peripheral to become ready */
  1495. if (parport_wait_peripheral(p, DSR_nBUSY | DSR_nFAULT,
  1496. DSR_nBUSY | DSR_nFAULT)) {
  1497. /* Avoid to flood the logs */
  1498. if (ready_before)
  1499. pr_info(PPIP32 "%s: not ready in %s\n",
  1500. p->name, __func__);
  1501. ready_before = 0;
  1502. goto stop;
  1503. }
  1504. ready_before = 1;
  1505. written = parport_ip32_fifo_write_block(p, buf, len);
  1506. /* Wait FIFO to empty. Timeout is proportional to FIFO_depth. */
  1507. parport_ip32_drain_fifo(p, physport->cad->timeout * priv->fifo_depth);
  1508. /* Check for a potential residue */
  1509. written -= parport_ip32_get_fifo_residue(p, ECR_MODE_PPF);
  1510. /* Then, wait for BUSY to get low. */
  1511. if (parport_wait_peripheral(p, DSR_nBUSY, DSR_nBUSY))
  1512. printk(KERN_DEBUG PPIP32 "%s: BUSY timeout in %s\n",
  1513. p->name, __func__);
  1514. stop:
  1515. /* Reset FIFO */
  1516. parport_ip32_set_mode(p, ECR_MODE_PS2);
  1517. physport->ieee1284.phase = IEEE1284_PH_FWD_IDLE;
  1518. return written;
  1519. }
  1520. /*
  1521. * FIXME - Insert here parport_ip32_ecp_read_data().
  1522. */
  1523. /**
  1524. * parport_ip32_ecp_write_data - write a block of data in ECP mode
  1525. * @p: pointer to &struct parport
  1526. * @buf: buffer of data to write
  1527. * @len: length of buffer @buf
  1528. * @flags: ignored
  1529. */
  1530. static size_t parport_ip32_ecp_write_data(struct parport *p,
  1531. const void *buf, size_t len,
  1532. int flags)
  1533. {
  1534. static unsigned int ready_before = 1;
  1535. struct parport_ip32_private * const priv = p->physport->private_data;
  1536. struct parport * const physport = p->physport;
  1537. size_t written = 0;
  1538. /* Special case: a timeout of zero means we cannot call schedule().
  1539. * Also if O_NONBLOCK is set then use the default implementation. */
  1540. if (physport->cad->timeout <= PARPORT_INACTIVITY_O_NONBLOCK)
  1541. return parport_ieee1284_ecp_write_data(p, buf, len, flags);
  1542. /* Negotiate to forward mode if necessary. */
  1543. if (physport->ieee1284.phase != IEEE1284_PH_FWD_IDLE) {
  1544. /* Event 47: Set nInit high. */
  1545. parport_ip32_frob_control(p, DCR_nINIT | DCR_AUTOFD,
  1546. DCR_nINIT | DCR_AUTOFD);
  1547. /* Event 49: PError goes high. */
  1548. if (parport_wait_peripheral(p, DSR_PERROR, DSR_PERROR)) {
  1549. printk(KERN_DEBUG PPIP32 "%s: PError timeout in %s\n",
  1550. p->name, __func__);
  1551. physport->ieee1284.phase = IEEE1284_PH_ECP_DIR_UNKNOWN;
  1552. return 0;
  1553. }
  1554. }
  1555. /* Reset FIFO, go in forward mode, and disable ackIntEn */
  1556. parport_ip32_set_mode(p, ECR_MODE_PS2);
  1557. parport_ip32_write_control(p, DCR_SELECT | DCR_nINIT);
  1558. parport_ip32_data_forward(p);
  1559. parport_ip32_disable_irq(p);
  1560. parport_ip32_set_mode(p, ECR_MODE_ECP);
  1561. physport->ieee1284.phase = IEEE1284_PH_FWD_DATA;
  1562. /* Wait for peripheral to become ready */
  1563. if (parport_wait_peripheral(p, DSR_nBUSY | DSR_nFAULT,
  1564. DSR_nBUSY | DSR_nFAULT)) {
  1565. /* Avoid to flood the logs */
  1566. if (ready_before)
  1567. pr_info(PPIP32 "%s: not ready in %s\n",
  1568. p->name, __func__);
  1569. ready_before = 0;
  1570. goto stop;
  1571. }
  1572. ready_before = 1;
  1573. written = parport_ip32_fifo_write_block(p, buf, len);
  1574. /* Wait FIFO to empty. Timeout is proportional to FIFO_depth. */
  1575. parport_ip32_drain_fifo(p, physport->cad->timeout * priv->fifo_depth);
  1576. /* Check for a potential residue */
  1577. written -= parport_ip32_get_fifo_residue(p, ECR_MODE_ECP);
  1578. /* Then, wait for BUSY to get low. */
  1579. if (parport_wait_peripheral(p, DSR_nBUSY, DSR_nBUSY))
  1580. printk(KERN_DEBUG PPIP32 "%s: BUSY timeout in %s\n",
  1581. p->name, __func__);
  1582. stop:
  1583. /* Reset FIFO */
  1584. parport_ip32_set_mode(p, ECR_MODE_PS2);
  1585. physport->ieee1284.phase = IEEE1284_PH_FWD_IDLE;
  1586. return written;
  1587. }
  1588. /*
  1589. * FIXME - Insert here parport_ip32_ecp_write_addr().
  1590. */
  1591. /*--- Default parport operations ---------------------------------------*/
  1592. static const struct parport_operations parport_ip32_ops __initconst = {
  1593. .write_data = parport_ip32_write_data,
  1594. .read_data = parport_ip32_read_data,
  1595. .write_control = parport_ip32_write_control,
  1596. .read_control = parport_ip32_read_control,
  1597. .frob_control = parport_ip32_frob_control,
  1598. .read_status = parport_ip32_read_status,
  1599. .enable_irq = parport_ip32_enable_irq,
  1600. .disable_irq = parport_ip32_disable_irq,
  1601. .data_forward = parport_ip32_data_forward,
  1602. .data_reverse = parport_ip32_data_reverse,
  1603. .init_state = parport_ip32_init_state,
  1604. .save_state = parport_ip32_save_state,
  1605. .restore_state = parport_ip32_restore_state,
  1606. .epp_write_data = parport_ieee1284_epp_write_data,
  1607. .epp_read_data = parport_ieee1284_epp_read_data,
  1608. .epp_write_addr = parport_ieee1284_epp_write_addr,
  1609. .epp_read_addr = parport_ieee1284_epp_read_addr,
  1610. .ecp_write_data = parport_ieee1284_ecp_write_data,
  1611. .ecp_read_data = parport_ieee1284_ecp_read_data,
  1612. .ecp_write_addr = parport_ieee1284_ecp_write_addr,
  1613. .compat_write_data = parport_ieee1284_write_compat,
  1614. .nibble_read_data = parport_ieee1284_read_nibble,
  1615. .byte_read_data = parport_ieee1284_read_byte,
  1616. .owner = THIS_MODULE,
  1617. };
  1618. /*--- Device detection -------------------------------------------------*/
  1619. /**
  1620. * parport_ip32_ecp_supported - check for an ECP port
  1621. * @p: pointer to the &parport structure
  1622. *
  1623. * Returns 1 if an ECP port is found, and 0 otherwise. This function actually
  1624. * checks if an Extended Control Register seems to be present. On successful
  1625. * return, the port is placed in SPP mode.
  1626. */
  1627. static __init unsigned int parport_ip32_ecp_supported(struct parport *p)
  1628. {
  1629. struct parport_ip32_private * const priv = p->physport->private_data;
  1630. unsigned int ecr;
  1631. ecr = ECR_MODE_PS2 | ECR_nERRINTR | ECR_SERVINTR;
  1632. writeb(ecr, priv->regs.ecr);
  1633. if (readb(priv->regs.ecr) != (ecr | ECR_F_EMPTY))
  1634. goto fail;
  1635. pr_probe(p, "Found working ECR register\n");
  1636. parport_ip32_set_mode(p, ECR_MODE_SPP);
  1637. parport_ip32_write_control(p, DCR_SELECT | DCR_nINIT);
  1638. return 1;
  1639. fail:
  1640. pr_probe(p, "ECR register not found\n");
  1641. return 0;
  1642. }
  1643. /**
  1644. * parport_ip32_fifo_supported - check for FIFO parameters
  1645. * @p: pointer to the &parport structure
  1646. *
  1647. * Check for FIFO parameters of an Extended Capabilities Port. Returns 1 on
  1648. * success, and 0 otherwise. Adjust FIFO parameters in the parport structure.
  1649. * On return, the port is placed in SPP mode.
  1650. */
  1651. static __init unsigned int parport_ip32_fifo_supported(struct parport *p)
  1652. {
  1653. struct parport_ip32_private * const priv = p->physport->private_data;
  1654. unsigned int configa, configb;
  1655. unsigned int pword;
  1656. unsigned int i;
  1657. /* Configuration mode */
  1658. parport_ip32_set_mode(p, ECR_MODE_CFG);
  1659. configa = readb(priv->regs.cnfgA);
  1660. configb = readb(priv->regs.cnfgB);
  1661. /* Find out PWord size */
  1662. switch (configa & CNFGA_ID_MASK) {
  1663. case CNFGA_ID_8:
  1664. pword = 1;
  1665. break;
  1666. case CNFGA_ID_16:
  1667. pword = 2;
  1668. break;
  1669. case CNFGA_ID_32:
  1670. pword = 4;
  1671. break;
  1672. default:
  1673. pr_probe(p, "Unknown implementation ID: 0x%0x\n",
  1674. (configa & CNFGA_ID_MASK) >> CNFGA_ID_SHIFT);
  1675. goto fail;
  1676. break;
  1677. }
  1678. if (pword != 1) {
  1679. pr_probe(p, "Unsupported PWord size: %u\n", pword);
  1680. goto fail;
  1681. }
  1682. priv->pword = pword;
  1683. pr_probe(p, "PWord is %u bits\n", 8 * priv->pword);
  1684. /* Check for compression support */
  1685. writeb(configb | CNFGB_COMPRESS, priv->regs.cnfgB);
  1686. if (readb(priv->regs.cnfgB) & CNFGB_COMPRESS)
  1687. pr_probe(p, "Hardware compression detected (unsupported)\n");
  1688. writeb(configb & ~CNFGB_COMPRESS, priv->regs.cnfgB);
  1689. /* Reset FIFO and go in test mode (no interrupt, no DMA) */
  1690. parport_ip32_set_mode(p, ECR_MODE_TST);
  1691. /* FIFO must be empty now */
  1692. if (!(readb(priv->regs.ecr) & ECR_F_EMPTY)) {
  1693. pr_probe(p, "FIFO not reset\n");
  1694. goto fail;
  1695. }
  1696. /* Find out FIFO depth. */
  1697. priv->fifo_depth = 0;
  1698. for (i = 0; i < 1024; i++) {
  1699. if (readb(priv->regs.ecr) & ECR_F_FULL) {
  1700. /* FIFO full */
  1701. priv->fifo_depth = i;
  1702. break;
  1703. }
  1704. writeb((u8)i, priv->regs.fifo);
  1705. }
  1706. if (i >= 1024) {
  1707. pr_probe(p, "Can't fill FIFO\n");
  1708. goto fail;
  1709. }
  1710. if (!priv->fifo_depth) {
  1711. pr_probe(p, "Can't get FIFO depth\n");
  1712. goto fail;
  1713. }
  1714. pr_probe(p, "FIFO is %u PWords deep\n", priv->fifo_depth);
  1715. /* Enable interrupts */
  1716. parport_ip32_frob_econtrol(p, ECR_SERVINTR, 0);
  1717. /* Find out writeIntrThreshold: number of PWords we know we can write
  1718. * if we get an interrupt. */
  1719. priv->writeIntrThreshold = 0;
  1720. for (i = 0; i < priv->fifo_depth; i++) {
  1721. if (readb(priv->regs.fifo) != (u8)i) {
  1722. pr_probe(p, "Invalid data in FIFO\n");
  1723. goto fail;
  1724. }
  1725. if (!priv->writeIntrThreshold
  1726. && readb(priv->regs.ecr) & ECR_SERVINTR)
  1727. /* writeIntrThreshold reached */
  1728. priv->writeIntrThreshold = i + 1;
  1729. if (i + 1 < priv->fifo_depth
  1730. && readb(priv->regs.ecr) & ECR_F_EMPTY) {
  1731. /* FIFO empty before the last byte? */
  1732. pr_probe(p, "Data lost in FIFO\n");
  1733. goto fail;
  1734. }
  1735. }
  1736. if (!priv->writeIntrThreshold) {
  1737. pr_probe(p, "Can't get writeIntrThreshold\n");
  1738. goto fail;
  1739. }
  1740. pr_probe(p, "writeIntrThreshold is %u\n", priv->writeIntrThreshold);
  1741. /* FIFO must be empty now */
  1742. if (!(readb(priv->regs.ecr) & ECR_F_EMPTY)) {
  1743. pr_probe(p, "Can't empty FIFO\n");
  1744. goto fail;
  1745. }
  1746. /* Reset FIFO */
  1747. parport_ip32_set_mode(p, ECR_MODE_PS2);
  1748. /* Set reverse direction (must be in PS2 mode) */
  1749. parport_ip32_data_reverse(p);
  1750. /* Test FIFO, no interrupt, no DMA */
  1751. parport_ip32_set_mode(p, ECR_MODE_TST);
  1752. /* Enable interrupts */
  1753. parport_ip32_frob_econtrol(p, ECR_SERVINTR, 0);
  1754. /* Find out readIntrThreshold: number of PWords we can read if we get
  1755. * an interrupt. */
  1756. priv->readIntrThreshold = 0;
  1757. for (i = 0; i < priv->fifo_depth; i++) {
  1758. writeb(0xaa, priv->regs.fifo);
  1759. if (readb(priv->regs.ecr) & ECR_SERVINTR) {
  1760. /* readIntrThreshold reached */
  1761. priv->readIntrThreshold = i + 1;
  1762. break;
  1763. }
  1764. }
  1765. if (!priv->readIntrThreshold) {
  1766. pr_probe(p, "Can't get readIntrThreshold\n");
  1767. goto fail;
  1768. }
  1769. pr_probe(p, "readIntrThreshold is %u\n", priv->readIntrThreshold);
  1770. /* Reset ECR */
  1771. parport_ip32_set_mode(p, ECR_MODE_PS2);
  1772. parport_ip32_data_forward(p);
  1773. parport_ip32_set_mode(p, ECR_MODE_SPP);
  1774. return 1;
  1775. fail:
  1776. priv->fifo_depth = 0;
  1777. parport_ip32_set_mode(p, ECR_MODE_SPP);
  1778. return 0;
  1779. }
  1780. /*--- Initialization code ----------------------------------------------*/
  1781. /**
  1782. * parport_ip32_make_isa_registers - compute (ISA) register addresses
  1783. * @regs: pointer to &struct parport_ip32_regs to fill
  1784. * @base: base address of standard and EPP registers
  1785. * @base_hi: base address of ECP registers
  1786. * @regshift: how much to shift register offset by
  1787. *
  1788. * Compute register addresses, according to the ISA standard. The addresses
  1789. * of the standard and EPP registers are computed from address @base. The
  1790. * addresses of the ECP registers are computed from address @base_hi.
  1791. */
  1792. static void __init
  1793. parport_ip32_make_isa_registers(struct parport_ip32_regs *regs,
  1794. void __iomem *base, void __iomem *base_hi,
  1795. unsigned int regshift)
  1796. {
  1797. #define r_base(offset) ((u8 __iomem *)base + ((offset) << regshift))
  1798. #define r_base_hi(offset) ((u8 __iomem *)base_hi + ((offset) << regshift))
  1799. *regs = (struct parport_ip32_regs){
  1800. .data = r_base(0),
  1801. .dsr = r_base(1),
  1802. .dcr = r_base(2),
  1803. .eppAddr = r_base(3),
  1804. .eppData0 = r_base(4),
  1805. .eppData1 = r_base(5),
  1806. .eppData2 = r_base(6),
  1807. .eppData3 = r_base(7),
  1808. .ecpAFifo = r_base(0),
  1809. .fifo = r_base_hi(0),
  1810. .cnfgA = r_base_hi(0),
  1811. .cnfgB = r_base_hi(1),
  1812. .ecr = r_base_hi(2)
  1813. };
  1814. #undef r_base_hi
  1815. #undef r_base
  1816. }
  1817. /**
  1818. * parport_ip32_probe_port - probe and register IP32 built-in parallel port
  1819. *
  1820. * Returns the new allocated &parport structure. On error, an error code is
  1821. * encoded in return value with the ERR_PTR function.
  1822. */
  1823. static __init struct parport *parport_ip32_probe_port(void)
  1824. {
  1825. struct parport_ip32_regs regs;
  1826. struct parport_ip32_private *priv = NULL;
  1827. struct parport_operations *ops = NULL;
  1828. struct parport *p = NULL;
  1829. int err;
  1830. parport_ip32_make_isa_registers(&regs, &mace->isa.parallel,
  1831. &mace->isa.ecp1284, 8 /* regshift */);
  1832. ops = kmalloc(sizeof(struct parport_operations), GFP_KERNEL);
  1833. priv = kmalloc(sizeof(struct parport_ip32_private), GFP_KERNEL);
  1834. p = parport_register_port(0, PARPORT_IRQ_NONE, PARPORT_DMA_NONE, ops);
  1835. if (ops == NULL || priv == NULL || p == NULL) {
  1836. err = -ENOMEM;
  1837. goto fail;
  1838. }
  1839. p->base = MACE_BASE + offsetof(struct sgi_mace, isa.parallel);
  1840. p->base_hi = MACE_BASE + offsetof(struct sgi_mace, isa.ecp1284);
  1841. p->private_data = priv;
  1842. *ops = parport_ip32_ops;
  1843. *priv = (struct parport_ip32_private){
  1844. .regs = regs,
  1845. .dcr_writable = DCR_DIR | DCR_SELECT | DCR_nINIT |
  1846. DCR_AUTOFD | DCR_STROBE,
  1847. .irq_mode = PARPORT_IP32_IRQ_FWD,
  1848. };
  1849. init_completion(&priv->irq_complete);
  1850. /* Probe port. */
  1851. if (!parport_ip32_ecp_supported(p)) {
  1852. err = -ENODEV;
  1853. goto fail;
  1854. }
  1855. parport_ip32_dump_state(p, "begin init", 0);
  1856. /* We found what looks like a working ECR register. Simply assume
  1857. * that all modes are correctly supported. Enable basic modes. */
  1858. p->modes = PARPORT_MODE_PCSPP | PARPORT_MODE_SAFEININT;
  1859. p->modes |= PARPORT_MODE_TRISTATE;
  1860. if (!parport_ip32_fifo_supported(p)) {
  1861. pr_warn(PPIP32 "%s: error: FIFO disabled\n", p->name);
  1862. /* Disable hardware modes depending on a working FIFO. */
  1863. features &= ~PARPORT_IP32_ENABLE_SPP;
  1864. features &= ~PARPORT_IP32_ENABLE_ECP;
  1865. /* DMA is not needed if FIFO is not supported. */
  1866. features &= ~PARPORT_IP32_ENABLE_DMA;
  1867. }
  1868. /* Request IRQ */
  1869. if (features & PARPORT_IP32_ENABLE_IRQ) {
  1870. int irq = MACEISA_PARALLEL_IRQ;
  1871. if (request_irq(irq, parport_ip32_interrupt, 0, p->name, p)) {
  1872. pr_warn(PPIP32 "%s: error: IRQ disabled\n", p->name);
  1873. /* DMA cannot work without interrupts. */
  1874. features &= ~PARPORT_IP32_ENABLE_DMA;
  1875. } else {
  1876. pr_probe(p, "Interrupt support enabled\n");
  1877. p->irq = irq;
  1878. priv->dcr_writable |= DCR_IRQ;
  1879. }
  1880. }
  1881. /* Allocate DMA resources */
  1882. if (features & PARPORT_IP32_ENABLE_DMA) {
  1883. if (parport_ip32_dma_register())
  1884. pr_warn(PPIP32 "%s: error: DMA disabled\n", p->name);
  1885. else {
  1886. pr_probe(p, "DMA support enabled\n");
  1887. p->dma = 0; /* arbitrary value != PARPORT_DMA_NONE */
  1888. p->modes |= PARPORT_MODE_DMA;
  1889. }
  1890. }
  1891. if (features & PARPORT_IP32_ENABLE_SPP) {
  1892. /* Enable compatibility FIFO mode */
  1893. p->ops->compat_write_data = parport_ip32_compat_write_data;
  1894. p->modes |= PARPORT_MODE_COMPAT;
  1895. pr_probe(p, "Hardware support for SPP mode enabled\n");
  1896. }
  1897. if (features & PARPORT_IP32_ENABLE_EPP) {
  1898. /* Set up access functions to use EPP hardware. */
  1899. p->ops->epp_read_data = parport_ip32_epp_read_data;
  1900. p->ops->epp_write_data = parport_ip32_epp_write_data;
  1901. p->ops->epp_read_addr = parport_ip32_epp_read_addr;
  1902. p->ops->epp_write_addr = parport_ip32_epp_write_addr;
  1903. p->modes |= PARPORT_MODE_EPP;
  1904. pr_probe(p, "Hardware support for EPP mode enabled\n");
  1905. }
  1906. if (features & PARPORT_IP32_ENABLE_ECP) {
  1907. /* Enable ECP FIFO mode */
  1908. p->ops->ecp_write_data = parport_ip32_ecp_write_data;
  1909. /* FIXME - not implemented */
  1910. /* p->ops->ecp_read_data = parport_ip32_ecp_read_data; */
  1911. /* p->ops->ecp_write_addr = parport_ip32_ecp_write_addr; */
  1912. p->modes |= PARPORT_MODE_ECP;
  1913. pr_probe(p, "Hardware support for ECP mode enabled\n");
  1914. }
  1915. /* Initialize the port with sensible values */
  1916. parport_ip32_set_mode(p, ECR_MODE_PS2);
  1917. parport_ip32_write_control(p, DCR_SELECT | DCR_nINIT);
  1918. parport_ip32_data_forward(p);
  1919. parport_ip32_disable_irq(p);
  1920. parport_ip32_write_data(p, 0x00);
  1921. parport_ip32_dump_state(p, "end init", 0);
  1922. /* Print out what we found */
  1923. pr_info("%s: SGI IP32 at 0x%lx (0x%lx)", p->name, p->base, p->base_hi);
  1924. if (p->irq != PARPORT_IRQ_NONE)
  1925. pr_cont(", irq %d", p->irq);
  1926. pr_cont(" [");
  1927. #define printmode(x) \
  1928. do { \
  1929. if (p->modes & PARPORT_MODE_##x) \
  1930. pr_cont("%s%s", f++ ? "," : "", #x); \
  1931. } while (0)
  1932. {
  1933. unsigned int f = 0;
  1934. printmode(PCSPP);
  1935. printmode(TRISTATE);
  1936. printmode(COMPAT);
  1937. printmode(EPP);
  1938. printmode(ECP);
  1939. printmode(DMA);
  1940. }
  1941. #undef printmode
  1942. pr_cont("]\n");
  1943. parport_announce_port(p);
  1944. return p;
  1945. fail:
  1946. if (p)
  1947. parport_put_port(p);
  1948. kfree(priv);
  1949. kfree(ops);
  1950. return ERR_PTR(err);
  1951. }
  1952. /**
  1953. * parport_ip32_unregister_port - unregister a parallel port
  1954. * @p: pointer to the &struct parport
  1955. *
  1956. * Unregisters a parallel port and free previously allocated resources
  1957. * (memory, IRQ, ...).
  1958. */
  1959. static __exit void parport_ip32_unregister_port(struct parport *p)
  1960. {
  1961. struct parport_ip32_private * const priv = p->physport->private_data;
  1962. struct parport_operations *ops = p->ops;
  1963. parport_remove_port(p);
  1964. if (p->modes & PARPORT_MODE_DMA)
  1965. parport_ip32_dma_unregister();
  1966. if (p->irq != PARPORT_IRQ_NONE)
  1967. free_irq(p->irq, p);
  1968. parport_put_port(p);
  1969. kfree(priv);
  1970. kfree(ops);
  1971. }
  1972. /**
  1973. * parport_ip32_init - module initialization function
  1974. */
  1975. static int __init parport_ip32_init(void)
  1976. {
  1977. pr_info(PPIP32 "SGI IP32 built-in parallel port driver v0.6\n");
  1978. this_port = parport_ip32_probe_port();
  1979. return PTR_ERR_OR_ZERO(this_port);
  1980. }
  1981. /**
  1982. * parport_ip32_exit - module termination function
  1983. */
  1984. static void __exit parport_ip32_exit(void)
  1985. {
  1986. parport_ip32_unregister_port(this_port);
  1987. }
  1988. /*--- Module stuff -----------------------------------------------------*/
  1989. MODULE_AUTHOR("Arnaud Giersch <arnaud.giersch@free.fr>");
  1990. MODULE_DESCRIPTION("SGI IP32 built-in parallel port driver");
  1991. MODULE_LICENSE("GPL");
  1992. MODULE_VERSION("0.6"); /* update in parport_ip32_init() too */
  1993. module_init(parport_ip32_init);
  1994. module_exit(parport_ip32_exit);
  1995. module_param(verbose_probing, bool, S_IRUGO);
  1996. MODULE_PARM_DESC(verbose_probing, "Log chit-chat during initialization");
  1997. module_param(features, uint, S_IRUGO);
  1998. MODULE_PARM_DESC(features,
  1999. "Bit mask of features to enable"
  2000. ", bit 0: IRQ support"
  2001. ", bit 1: DMA support"
  2002. ", bit 2: hardware SPP mode"
  2003. ", bit 3: hardware EPP mode"
  2004. ", bit 4: hardware ECP mode");
  2005. /*--- Inform (X)Emacs about preferred coding style ---------------------*/
  2006. /*
  2007. * Local Variables:
  2008. * mode: c
  2009. * c-file-style: "linux"
  2010. * indent-tabs-mode: t
  2011. * tab-width: 8
  2012. * fill-column: 78
  2013. * ispell-local-dictionary: "american"
  2014. * End:
  2015. */