sba_iommu.c 57 KB

123456789101112131415161718192021222324252627282930313233343536373839404142434445464748495051525354555657585960616263646566676869707172737475767778798081828384858687888990919293949596979899100101102103104105106107108109110111112113114115116117118119120121122123124125126127128129130131132133134135136137138139140141142143144145146147148149150151152153154155156157158159160161162163164165166167168169170171172173174175176177178179180181182183184185186187188189190191192193194195196197198199200201202203204205206207208209210211212213214215216217218219220221222223224225226227228229230231232233234235236237238239240241242243244245246247248249250251252253254255256257258259260261262263264265266267268269270271272273274275276277278279280281282283284285286287288289290291292293294295296297298299300301302303304305306307308309310311312313314315316317318319320321322323324325326327328329330331332333334335336337338339340341342343344345346347348349350351352353354355356357358359360361362363364365366367368369370371372373374375376377378379380381382383384385386387388389390391392393394395396397398399400401402403404405406407408409410411412413414415416417418419420421422423424425426427428429430431432433434435436437438439440441442443444445446447448449450451452453454455456457458459460461462463464465466467468469470471472473474475476477478479480481482483484485486487488489490491492493494495496497498499500501502503504505506507508509510511512513514515516517518519520521522523524525526527528529530531532533534535536537538539540541542543544545546547548549550551552553554555556557558559560561562563564565566567568569570571572573574575576577578579580581582583584585586587588589590591592593594595596597598599600601602603604605606607608609610611612613614615616617618619620621622623624625626627628629630631632633634635636637638639640641642643644645646647648649650651652653654655656657658659660661662663664665666667668669670671672673674675676677678679680681682683684685686687688689690691692693694695696697698699700701702703704705706707708709710711712713714715716717718719720721722723724725726727728729730731732733734735736737738739740741742743744745746747748749750751752753754755756757758759760761762763764765766767768769770771772773774775776777778779780781782783784785786787788789790791792793794795796797798799800801802803804805806807808809810811812813814815816817818819820821822823824825826827828829830831832833834835836837838839840841842843844845846847848849850851852853854855856857858859860861862863864865866867868869870871872873874875876877878879880881882883884885886887888889890891892893894895896897898899900901902903904905906907908909910911912913914915916917918919920921922923924925926927928929930931932933934935936937938939940941942943944945946947948949950951952953954955956957958959960961962963964965966967968969970971972973974975976977978979980981982983984985986987988989990991992993994995996997998999100010011002100310041005100610071008100910101011101210131014101510161017101810191020102110221023102410251026102710281029103010311032103310341035103610371038103910401041104210431044104510461047104810491050105110521053105410551056105710581059106010611062106310641065106610671068106910701071107210731074107510761077107810791080108110821083108410851086108710881089109010911092109310941095109610971098109911001101110211031104110511061107110811091110111111121113111411151116111711181119112011211122112311241125112611271128112911301131113211331134113511361137113811391140114111421143114411451146114711481149115011511152115311541155115611571158115911601161116211631164116511661167116811691170117111721173117411751176117711781179118011811182118311841185118611871188118911901191119211931194119511961197119811991200120112021203120412051206120712081209121012111212121312141215121612171218121912201221122212231224122512261227122812291230123112321233123412351236123712381239124012411242124312441245124612471248124912501251125212531254125512561257125812591260126112621263126412651266126712681269127012711272127312741275127612771278127912801281128212831284128512861287128812891290129112921293129412951296129712981299130013011302130313041305130613071308130913101311131213131314131513161317131813191320132113221323132413251326132713281329133013311332133313341335133613371338133913401341134213431344134513461347134813491350135113521353135413551356135713581359136013611362136313641365136613671368136913701371137213731374137513761377137813791380138113821383138413851386138713881389139013911392139313941395139613971398139914001401140214031404140514061407140814091410141114121413141414151416141714181419142014211422142314241425142614271428142914301431143214331434143514361437143814391440144114421443144414451446144714481449145014511452145314541455145614571458145914601461146214631464146514661467146814691470147114721473147414751476147714781479148014811482148314841485148614871488148914901491149214931494149514961497149814991500150115021503150415051506150715081509151015111512151315141515151615171518151915201521152215231524152515261527152815291530153115321533153415351536153715381539154015411542154315441545154615471548154915501551155215531554155515561557155815591560156115621563156415651566156715681569157015711572157315741575157615771578157915801581158215831584158515861587158815891590159115921593159415951596159715981599160016011602160316041605160616071608160916101611161216131614161516161617161816191620162116221623162416251626162716281629163016311632163316341635163616371638163916401641164216431644164516461647164816491650165116521653165416551656165716581659166016611662166316641665166616671668166916701671167216731674167516761677167816791680168116821683168416851686168716881689169016911692169316941695169616971698169917001701170217031704170517061707170817091710171117121713171417151716171717181719172017211722172317241725172617271728172917301731173217331734173517361737173817391740174117421743174417451746174717481749175017511752175317541755175617571758175917601761176217631764176517661767176817691770177117721773177417751776177717781779178017811782178317841785178617871788178917901791179217931794179517961797179817991800180118021803180418051806180718081809181018111812181318141815181618171818181918201821182218231824182518261827182818291830183118321833183418351836183718381839184018411842184318441845184618471848184918501851185218531854185518561857185818591860186118621863186418651866186718681869187018711872187318741875187618771878187918801881188218831884188518861887188818891890189118921893189418951896189718981899190019011902190319041905190619071908190919101911191219131914191519161917191819191920192119221923192419251926192719281929193019311932193319341935193619371938193919401941194219431944194519461947194819491950195119521953195419551956195719581959196019611962196319641965196619671968196919701971197219731974197519761977197819791980198119821983198419851986198719881989199019911992199319941995199619971998199920002001200220032004200520062007200820092010201120122013201420152016201720182019202020212022202320242025202620272028202920302031203220332034203520362037203820392040204120422043204420452046204720482049205020512052205320542055205620572058205920602061206220632064206520662067206820692070207120722073207420752076207720782079208020812082
  1. // SPDX-License-Identifier: GPL-2.0-or-later
  2. /*
  3. ** System Bus Adapter (SBA) I/O MMU manager
  4. **
  5. ** (c) Copyright 2000-2004 Grant Grundler <grundler @ parisc-linux x org>
  6. ** (c) Copyright 2004 Naresh Kumar Inna <knaresh at india x hp x com>
  7. ** (c) Copyright 2000-2004 Hewlett-Packard Company
  8. **
  9. ** Portions (c) 1999 Dave S. Miller (from sparc64 I/O MMU code)
  10. **
  11. **
  12. **
  13. ** This module initializes the IOC (I/O Controller) found on B1000/C3000/
  14. ** J5000/J7000/N-class/L-class machines and their successors.
  15. **
  16. ** FIXME: add DMA hint support programming in both sba and lba modules.
  17. */
  18. #include <linux/types.h>
  19. #include <linux/kernel.h>
  20. #include <linux/spinlock.h>
  21. #include <linux/slab.h>
  22. #include <linux/init.h>
  23. #include <linux/mm.h>
  24. #include <linux/string.h>
  25. #include <linux/pci.h>
  26. #include <linux/dma-map-ops.h>
  27. #include <linux/scatterlist.h>
  28. #include <linux/iommu-helper.h>
  29. #include <asm/byteorder.h>
  30. #include <asm/io.h>
  31. #include <asm/dma.h> /* for DMA_CHUNK_SIZE */
  32. #include <asm/hardware.h> /* for register_parisc_driver() stuff */
  33. #include <linux/proc_fs.h>
  34. #include <linux/seq_file.h>
  35. #include <linux/module.h>
  36. #include <asm/ropes.h>
  37. #include <asm/mckinley.h> /* for proc_mckinley_root */
  38. #include <asm/runway.h> /* for proc_runway_root */
  39. #include <asm/page.h> /* for PAGE0 */
  40. #include <asm/pdc.h> /* for PDC_MODEL_* */
  41. #include <asm/pdcpat.h> /* for is_pdc_pat() */
  42. #include <asm/parisc-device.h>
  43. #include "iommu.h"
  44. #define MODULE_NAME "SBA"
  45. /*
  46. ** The number of debug flags is a clue - this code is fragile.
  47. ** Don't even think about messing with it unless you have
  48. ** plenty of 710's to sacrifice to the computer gods. :^)
  49. */
  50. #undef DEBUG_SBA_INIT
  51. #undef DEBUG_SBA_RUN
  52. #undef DEBUG_SBA_RUN_SG
  53. #undef DEBUG_SBA_RESOURCE
  54. #undef ASSERT_PDIR_SANITY
  55. #undef DEBUG_LARGE_SG_ENTRIES
  56. #undef DEBUG_DMB_TRAP
  57. #ifdef DEBUG_SBA_INIT
  58. #define DBG_INIT(x...) printk(x)
  59. #else
  60. #define DBG_INIT(x...)
  61. #endif
  62. #ifdef DEBUG_SBA_RUN
  63. #define DBG_RUN(x...) printk(x)
  64. #else
  65. #define DBG_RUN(x...)
  66. #endif
  67. #ifdef DEBUG_SBA_RUN_SG
  68. #define DBG_RUN_SG(x...) printk(x)
  69. #else
  70. #define DBG_RUN_SG(x...)
  71. #endif
  72. #ifdef DEBUG_SBA_RESOURCE
  73. #define DBG_RES(x...) printk(x)
  74. #else
  75. #define DBG_RES(x...)
  76. #endif
  77. #define SBA_INLINE __inline__
  78. #define DEFAULT_DMA_HINT_REG 0
  79. struct sba_device *sba_list;
  80. EXPORT_SYMBOL_GPL(sba_list);
  81. static unsigned long ioc_needs_fdc = 0;
  82. /* global count of IOMMUs in the system */
  83. static unsigned int global_ioc_cnt = 0;
  84. /* PA8700 (Piranha 2.2) bug workaround */
  85. static unsigned long piranha_bad_128k = 0;
  86. /* Looks nice and keeps the compiler happy */
  87. #define SBA_DEV(d) ((struct sba_device *) (d))
  88. #ifdef CONFIG_AGP_PARISC
  89. #define SBA_AGP_SUPPORT
  90. #endif /*CONFIG_AGP_PARISC*/
  91. #ifdef SBA_AGP_SUPPORT
  92. static int sba_reserve_agpgart = 1;
  93. module_param(sba_reserve_agpgart, int, 0444);
  94. MODULE_PARM_DESC(sba_reserve_agpgart, "Reserve half of IO pdir as AGPGART");
  95. #endif
  96. /************************************
  97. ** SBA register read and write support
  98. **
  99. ** BE WARNED: register writes are posted.
  100. ** (ie follow writes which must reach HW with a read)
  101. **
  102. ** Superdome (in particular, REO) allows only 64-bit CSR accesses.
  103. */
  104. #define READ_REG32(addr) readl(addr)
  105. #define READ_REG64(addr) readq(addr)
  106. #define WRITE_REG32(val, addr) writel((val), (addr))
  107. #define WRITE_REG64(val, addr) writeq((val), (addr))
  108. #ifdef CONFIG_64BIT
  109. #define READ_REG(addr) READ_REG64(addr)
  110. #define WRITE_REG(value, addr) WRITE_REG64(value, addr)
  111. #else
  112. #define READ_REG(addr) READ_REG32(addr)
  113. #define WRITE_REG(value, addr) WRITE_REG32(value, addr)
  114. #endif
  115. #ifdef DEBUG_SBA_INIT
  116. /* NOTE: When CONFIG_64BIT isn't defined, READ_REG64() is two 32-bit reads */
  117. /**
  118. * sba_dump_ranges - debugging only - print ranges assigned to this IOA
  119. * @hpa: base address of the sba
  120. *
  121. * Print the MMIO and IO Port address ranges forwarded by an Astro/Ike/RIO
  122. * IO Adapter (aka Bus Converter).
  123. */
  124. static void
  125. sba_dump_ranges(void __iomem *hpa)
  126. {
  127. DBG_INIT("SBA at 0x%p\n", hpa);
  128. DBG_INIT("IOS_DIST_BASE : %Lx\n", READ_REG64(hpa+IOS_DIST_BASE));
  129. DBG_INIT("IOS_DIST_MASK : %Lx\n", READ_REG64(hpa+IOS_DIST_MASK));
  130. DBG_INIT("IOS_DIST_ROUTE : %Lx\n", READ_REG64(hpa+IOS_DIST_ROUTE));
  131. DBG_INIT("\n");
  132. DBG_INIT("IOS_DIRECT_BASE : %Lx\n", READ_REG64(hpa+IOS_DIRECT_BASE));
  133. DBG_INIT("IOS_DIRECT_MASK : %Lx\n", READ_REG64(hpa+IOS_DIRECT_MASK));
  134. DBG_INIT("IOS_DIRECT_ROUTE: %Lx\n", READ_REG64(hpa+IOS_DIRECT_ROUTE));
  135. }
  136. /**
  137. * sba_dump_tlb - debugging only - print IOMMU operating parameters
  138. * @hpa: base address of the IOMMU
  139. *
  140. * Print the size/location of the IO MMU PDIR.
  141. */
  142. static void sba_dump_tlb(void __iomem *hpa)
  143. {
  144. DBG_INIT("IO TLB at 0x%p\n", hpa);
  145. DBG_INIT("IOC_IBASE : 0x%Lx\n", READ_REG64(hpa+IOC_IBASE));
  146. DBG_INIT("IOC_IMASK : 0x%Lx\n", READ_REG64(hpa+IOC_IMASK));
  147. DBG_INIT("IOC_TCNFG : 0x%Lx\n", READ_REG64(hpa+IOC_TCNFG));
  148. DBG_INIT("IOC_PDIR_BASE: 0x%Lx\n", READ_REG64(hpa+IOC_PDIR_BASE));
  149. DBG_INIT("\n");
  150. }
  151. #else
  152. #define sba_dump_ranges(x)
  153. #define sba_dump_tlb(x)
  154. #endif /* DEBUG_SBA_INIT */
  155. #ifdef ASSERT_PDIR_SANITY
  156. /**
  157. * sba_dump_pdir_entry - debugging only - print one IOMMU PDIR entry
  158. * @ioc: IO MMU structure which owns the pdir we are interested in.
  159. * @msg: text to print ont the output line.
  160. * @pide: pdir index.
  161. *
  162. * Print one entry of the IO MMU PDIR in human readable form.
  163. */
  164. static void
  165. sba_dump_pdir_entry(struct ioc *ioc, char *msg, uint pide)
  166. {
  167. /* start printing from lowest pde in rval */
  168. u64 *ptr = &(ioc->pdir_base[pide & (~0U * BITS_PER_LONG)]);
  169. unsigned long *rptr = (unsigned long *) &(ioc->res_map[(pide >>3) & ~(sizeof(unsigned long) - 1)]);
  170. uint rcnt;
  171. printk(KERN_DEBUG "SBA: %s rp %p bit %d rval 0x%lx\n",
  172. msg,
  173. rptr, pide & (BITS_PER_LONG - 1), *rptr);
  174. rcnt = 0;
  175. while (rcnt < BITS_PER_LONG) {
  176. printk(KERN_DEBUG "%s %2d %p %016Lx\n",
  177. (rcnt == (pide & (BITS_PER_LONG - 1)))
  178. ? " -->" : " ",
  179. rcnt, ptr, *ptr );
  180. rcnt++;
  181. ptr++;
  182. }
  183. printk(KERN_DEBUG "%s", msg);
  184. }
  185. /**
  186. * sba_check_pdir - debugging only - consistency checker
  187. * @ioc: IO MMU structure which owns the pdir we are interested in.
  188. * @msg: text to print ont the output line.
  189. *
  190. * Verify the resource map and pdir state is consistent
  191. */
  192. static int
  193. sba_check_pdir(struct ioc *ioc, char *msg)
  194. {
  195. u32 *rptr_end = (u32 *) &(ioc->res_map[ioc->res_size]);
  196. u32 *rptr = (u32 *) ioc->res_map; /* resource map ptr */
  197. u64 *pptr = ioc->pdir_base; /* pdir ptr */
  198. uint pide = 0;
  199. while (rptr < rptr_end) {
  200. u32 rval = *rptr;
  201. int rcnt = 32; /* number of bits we might check */
  202. while (rcnt) {
  203. /* Get last byte and highest bit from that */
  204. u32 pde = ((u32) (((char *)pptr)[7])) << 24;
  205. if ((rval ^ pde) & 0x80000000)
  206. {
  207. /*
  208. ** BUMMER! -- res_map != pdir --
  209. ** Dump rval and matching pdir entries
  210. */
  211. sba_dump_pdir_entry(ioc, msg, pide);
  212. return(1);
  213. }
  214. rcnt--;
  215. rval <<= 1; /* try the next bit */
  216. pptr++;
  217. pide++;
  218. }
  219. rptr++; /* look at next word of res_map */
  220. }
  221. /* It'd be nice if we always got here :^) */
  222. return 0;
  223. }
  224. /**
  225. * sba_dump_sg - debugging only - print Scatter-Gather list
  226. * @ioc: IO MMU structure which owns the pdir we are interested in.
  227. * @startsg: head of the SG list
  228. * @nents: number of entries in SG list
  229. *
  230. * print the SG list so we can verify it's correct by hand.
  231. */
  232. static void
  233. sba_dump_sg( struct ioc *ioc, struct scatterlist *startsg, int nents)
  234. {
  235. while (nents-- > 0) {
  236. printk(KERN_DEBUG " %d : %08lx/%05x %p/%05x\n",
  237. nents,
  238. (unsigned long) sg_dma_address(startsg),
  239. sg_dma_len(startsg),
  240. sg_virt(startsg), startsg->length);
  241. startsg++;
  242. }
  243. }
  244. #endif /* ASSERT_PDIR_SANITY */
  245. /**************************************************************
  246. *
  247. * I/O Pdir Resource Management
  248. *
  249. * Bits set in the resource map are in use.
  250. * Each bit can represent a number of pages.
  251. * LSbs represent lower addresses (IOVA's).
  252. *
  253. ***************************************************************/
  254. #define PAGES_PER_RANGE 1 /* could increase this to 4 or 8 if needed */
  255. /* Convert from IOVP to IOVA and vice versa. */
  256. #ifdef ZX1_SUPPORT
  257. /* Pluto (aka ZX1) boxes need to set or clear the ibase bits appropriately */
  258. #define SBA_IOVA(ioc,iovp,offset,hint_reg) ((ioc->ibase) | (iovp) | (offset))
  259. #define SBA_IOVP(ioc,iova) ((iova) & (ioc)->iovp_mask)
  260. #else
  261. /* only support Astro and ancestors. Saves a few cycles in key places */
  262. #define SBA_IOVA(ioc,iovp,offset,hint_reg) ((iovp) | (offset))
  263. #define SBA_IOVP(ioc,iova) (iova)
  264. #endif
  265. #define PDIR_INDEX(iovp) ((iovp)>>IOVP_SHIFT)
  266. #define RESMAP_MASK(n) (~0UL << (BITS_PER_LONG - (n)))
  267. #define RESMAP_IDX_MASK (sizeof(unsigned long) - 1)
  268. static unsigned long ptr_to_pide(struct ioc *ioc, unsigned long *res_ptr,
  269. unsigned int bitshiftcnt)
  270. {
  271. return (((unsigned long)res_ptr - (unsigned long)ioc->res_map) << 3)
  272. + bitshiftcnt;
  273. }
  274. /**
  275. * sba_search_bitmap - find free space in IO PDIR resource bitmap
  276. * @ioc: IO MMU structure which owns the pdir we are interested in.
  277. * @bits_wanted: number of entries we need.
  278. *
  279. * Find consecutive free bits in resource bitmap.
  280. * Each bit represents one entry in the IO Pdir.
  281. * Cool perf optimization: search for log2(size) bits at a time.
  282. */
  283. static SBA_INLINE unsigned long
  284. sba_search_bitmap(struct ioc *ioc, struct device *dev,
  285. unsigned long bits_wanted)
  286. {
  287. unsigned long *res_ptr = ioc->res_hint;
  288. unsigned long *res_end = (unsigned long *) &(ioc->res_map[ioc->res_size]);
  289. unsigned long pide = ~0UL, tpide;
  290. unsigned long boundary_size;
  291. unsigned long shift;
  292. int ret;
  293. boundary_size = dma_get_seg_boundary_nr_pages(dev, IOVP_SHIFT);
  294. #if defined(ZX1_SUPPORT)
  295. BUG_ON(ioc->ibase & ~IOVP_MASK);
  296. shift = ioc->ibase >> IOVP_SHIFT;
  297. #else
  298. shift = 0;
  299. #endif
  300. if (bits_wanted > (BITS_PER_LONG/2)) {
  301. /* Search word at a time - no mask needed */
  302. for(; res_ptr < res_end; ++res_ptr) {
  303. tpide = ptr_to_pide(ioc, res_ptr, 0);
  304. ret = iommu_is_span_boundary(tpide, bits_wanted,
  305. shift,
  306. boundary_size);
  307. if ((*res_ptr == 0) && !ret) {
  308. *res_ptr = RESMAP_MASK(bits_wanted);
  309. pide = tpide;
  310. break;
  311. }
  312. }
  313. /* point to the next word on next pass */
  314. res_ptr++;
  315. ioc->res_bitshift = 0;
  316. } else {
  317. /*
  318. ** Search the resource bit map on well-aligned values.
  319. ** "o" is the alignment.
  320. ** We need the alignment to invalidate I/O TLB using
  321. ** SBA HW features in the unmap path.
  322. */
  323. unsigned long o = 1 << get_order(bits_wanted << PAGE_SHIFT);
  324. uint bitshiftcnt = ALIGN(ioc->res_bitshift, o);
  325. unsigned long mask;
  326. if (bitshiftcnt >= BITS_PER_LONG) {
  327. bitshiftcnt = 0;
  328. res_ptr++;
  329. }
  330. mask = RESMAP_MASK(bits_wanted) >> bitshiftcnt;
  331. DBG_RES("%s() o %ld %p", __func__, o, res_ptr);
  332. while(res_ptr < res_end)
  333. {
  334. DBG_RES(" %p %lx %lx\n", res_ptr, mask, *res_ptr);
  335. WARN_ON(mask == 0);
  336. tpide = ptr_to_pide(ioc, res_ptr, bitshiftcnt);
  337. ret = iommu_is_span_boundary(tpide, bits_wanted,
  338. shift,
  339. boundary_size);
  340. if ((((*res_ptr) & mask) == 0) && !ret) {
  341. *res_ptr |= mask; /* mark resources busy! */
  342. pide = tpide;
  343. break;
  344. }
  345. mask >>= o;
  346. bitshiftcnt += o;
  347. if (mask == 0) {
  348. mask = RESMAP_MASK(bits_wanted);
  349. bitshiftcnt=0;
  350. res_ptr++;
  351. }
  352. }
  353. /* look in the same word on the next pass */
  354. ioc->res_bitshift = bitshiftcnt + bits_wanted;
  355. }
  356. /* wrapped ? */
  357. if (res_end <= res_ptr) {
  358. ioc->res_hint = (unsigned long *) ioc->res_map;
  359. ioc->res_bitshift = 0;
  360. } else {
  361. ioc->res_hint = res_ptr;
  362. }
  363. return (pide);
  364. }
  365. /**
  366. * sba_alloc_range - find free bits and mark them in IO PDIR resource bitmap
  367. * @ioc: IO MMU structure which owns the pdir we are interested in.
  368. * @size: number of bytes to create a mapping for
  369. *
  370. * Given a size, find consecutive unmarked and then mark those bits in the
  371. * resource bit map.
  372. */
  373. static int
  374. sba_alloc_range(struct ioc *ioc, struct device *dev, size_t size)
  375. {
  376. unsigned int pages_needed = size >> IOVP_SHIFT;
  377. #ifdef SBA_COLLECT_STATS
  378. unsigned long cr_start = mfctl(16);
  379. #endif
  380. unsigned long pide;
  381. pide = sba_search_bitmap(ioc, dev, pages_needed);
  382. if (pide >= (ioc->res_size << 3)) {
  383. pide = sba_search_bitmap(ioc, dev, pages_needed);
  384. if (pide >= (ioc->res_size << 3))
  385. panic("%s: I/O MMU @ %p is out of mapping resources\n",
  386. __FILE__, ioc->ioc_hpa);
  387. }
  388. #ifdef ASSERT_PDIR_SANITY
  389. /* verify the first enable bit is clear */
  390. if(0x00 != ((u8 *) ioc->pdir_base)[pide*sizeof(u64) + 7]) {
  391. sba_dump_pdir_entry(ioc, "sba_search_bitmap() botched it?", pide);
  392. }
  393. #endif
  394. DBG_RES("%s(%x) %d -> %lx hint %x/%x\n",
  395. __func__, size, pages_needed, pide,
  396. (uint) ((unsigned long) ioc->res_hint - (unsigned long) ioc->res_map),
  397. ioc->res_bitshift );
  398. #ifdef SBA_COLLECT_STATS
  399. {
  400. unsigned long cr_end = mfctl(16);
  401. unsigned long tmp = cr_end - cr_start;
  402. /* check for roll over */
  403. cr_start = (cr_end < cr_start) ? -(tmp) : (tmp);
  404. }
  405. ioc->avg_search[ioc->avg_idx++] = cr_start;
  406. ioc->avg_idx &= SBA_SEARCH_SAMPLE - 1;
  407. ioc->used_pages += pages_needed;
  408. #endif
  409. return (pide);
  410. }
  411. /**
  412. * sba_free_range - unmark bits in IO PDIR resource bitmap
  413. * @ioc: IO MMU structure which owns the pdir we are interested in.
  414. * @iova: IO virtual address which was previously allocated.
  415. * @size: number of bytes to create a mapping for
  416. *
  417. * clear bits in the ioc's resource map
  418. */
  419. static SBA_INLINE void
  420. sba_free_range(struct ioc *ioc, dma_addr_t iova, size_t size)
  421. {
  422. unsigned long iovp = SBA_IOVP(ioc, iova);
  423. unsigned int pide = PDIR_INDEX(iovp);
  424. unsigned int ridx = pide >> 3; /* convert bit to byte address */
  425. unsigned long *res_ptr = (unsigned long *) &((ioc)->res_map[ridx & ~RESMAP_IDX_MASK]);
  426. int bits_not_wanted = size >> IOVP_SHIFT;
  427. /* 3-bits "bit" address plus 2 (or 3) bits for "byte" == bit in word */
  428. unsigned long m = RESMAP_MASK(bits_not_wanted) >> (pide & (BITS_PER_LONG - 1));
  429. DBG_RES("%s( ,%x,%x) %x/%lx %x %p %lx\n",
  430. __func__, (uint) iova, size,
  431. bits_not_wanted, m, pide, res_ptr, *res_ptr);
  432. #ifdef SBA_COLLECT_STATS
  433. ioc->used_pages -= bits_not_wanted;
  434. #endif
  435. *res_ptr &= ~m;
  436. }
  437. /**************************************************************
  438. *
  439. * "Dynamic DMA Mapping" support (aka "Coherent I/O")
  440. *
  441. ***************************************************************/
  442. #ifdef SBA_HINT_SUPPORT
  443. #define SBA_DMA_HINT(ioc, val) ((val) << (ioc)->hint_shift_pdir)
  444. #endif
  445. typedef unsigned long space_t;
  446. #define KERNEL_SPACE 0
  447. /**
  448. * sba_io_pdir_entry - fill in one IO PDIR entry
  449. * @pdir_ptr: pointer to IO PDIR entry
  450. * @sid: process Space ID - currently only support KERNEL_SPACE
  451. * @vba: Virtual CPU address of buffer to map
  452. * @hint: DMA hint set to use for this mapping
  453. *
  454. * SBA Mapping Routine
  455. *
  456. * Given a virtual address (vba, arg2) and space id, (sid, arg1)
  457. * sba_io_pdir_entry() loads the I/O PDIR entry pointed to by
  458. * pdir_ptr (arg0).
  459. * Using the bass-ackwards HP bit numbering, Each IO Pdir entry
  460. * for Astro/Ike looks like:
  461. *
  462. *
  463. * 0 19 51 55 63
  464. * +-+---------------------+----------------------------------+----+--------+
  465. * |V| U | PPN[43:12] | U | VI |
  466. * +-+---------------------+----------------------------------+----+--------+
  467. *
  468. * Pluto is basically identical, supports fewer physical address bits:
  469. *
  470. * 0 23 51 55 63
  471. * +-+------------------------+-------------------------------+----+--------+
  472. * |V| U | PPN[39:12] | U | VI |
  473. * +-+------------------------+-------------------------------+----+--------+
  474. *
  475. * V == Valid Bit (Most Significant Bit is bit 0)
  476. * U == Unused
  477. * PPN == Physical Page Number
  478. * VI == Virtual Index (aka Coherent Index)
  479. *
  480. * LPA instruction output is put into PPN field.
  481. * LCI (Load Coherence Index) instruction provides the "VI" bits.
  482. *
  483. * We pre-swap the bytes since PCX-W is Big Endian and the
  484. * IOMMU uses little endian for the pdir.
  485. */
  486. static void SBA_INLINE
  487. sba_io_pdir_entry(u64 *pdir_ptr, space_t sid, unsigned long vba,
  488. unsigned long hint)
  489. {
  490. u64 pa; /* physical address */
  491. register unsigned ci; /* coherent index */
  492. pa = lpa(vba);
  493. pa &= IOVP_MASK;
  494. asm("lci 0(%1), %0" : "=r" (ci) : "r" (vba));
  495. pa |= (ci >> PAGE_SHIFT) & 0xff; /* move CI (8 bits) into lowest byte */
  496. pa |= SBA_PDIR_VALID_BIT; /* set "valid" bit */
  497. *pdir_ptr = cpu_to_le64(pa); /* swap and store into I/O Pdir */
  498. /*
  499. * If the PDC_MODEL capabilities has Non-coherent IO-PDIR bit set
  500. * (bit #61, big endian), we have to flush and sync every time
  501. * IO-PDIR is changed in Ike/Astro.
  502. */
  503. asm_io_fdc(pdir_ptr);
  504. }
  505. /**
  506. * sba_mark_invalid - invalidate one or more IO PDIR entries
  507. * @ioc: IO MMU structure which owns the pdir we are interested in.
  508. * @iova: IO Virtual Address mapped earlier
  509. * @byte_cnt: number of bytes this mapping covers.
  510. *
  511. * Marking the IO PDIR entry(ies) as Invalid and invalidate
  512. * corresponding IO TLB entry. The Ike PCOM (Purge Command Register)
  513. * is to purge stale entries in the IO TLB when unmapping entries.
  514. *
  515. * The PCOM register supports purging of multiple pages, with a minium
  516. * of 1 page and a maximum of 2GB. Hardware requires the address be
  517. * aligned to the size of the range being purged. The size of the range
  518. * must be a power of 2. The "Cool perf optimization" in the
  519. * allocation routine helps keep that true.
  520. */
  521. static SBA_INLINE void
  522. sba_mark_invalid(struct ioc *ioc, dma_addr_t iova, size_t byte_cnt)
  523. {
  524. u32 iovp = (u32) SBA_IOVP(ioc,iova);
  525. u64 *pdir_ptr = &ioc->pdir_base[PDIR_INDEX(iovp)];
  526. #ifdef ASSERT_PDIR_SANITY
  527. /* Assert first pdir entry is set.
  528. **
  529. ** Even though this is a big-endian machine, the entries
  530. ** in the iopdir are little endian. That's why we look at
  531. ** the byte at +7 instead of at +0.
  532. */
  533. if (0x80 != (((u8 *) pdir_ptr)[7])) {
  534. sba_dump_pdir_entry(ioc,"sba_mark_invalid()", PDIR_INDEX(iovp));
  535. }
  536. #endif
  537. if (byte_cnt > IOVP_SIZE)
  538. {
  539. #if 0
  540. unsigned long entries_per_cacheline = ioc_needs_fdc ?
  541. L1_CACHE_ALIGN(((unsigned long) pdir_ptr))
  542. - (unsigned long) pdir_ptr;
  543. : 262144;
  544. #endif
  545. /* set "size" field for PCOM */
  546. iovp |= get_order(byte_cnt) + PAGE_SHIFT;
  547. do {
  548. /* clear I/O Pdir entry "valid" bit first */
  549. ((u8 *) pdir_ptr)[7] = 0;
  550. asm_io_fdc(pdir_ptr);
  551. if (ioc_needs_fdc) {
  552. #if 0
  553. entries_per_cacheline = L1_CACHE_SHIFT - 3;
  554. #endif
  555. }
  556. pdir_ptr++;
  557. byte_cnt -= IOVP_SIZE;
  558. } while (byte_cnt > IOVP_SIZE);
  559. } else
  560. iovp |= IOVP_SHIFT; /* set "size" field for PCOM */
  561. /*
  562. ** clear I/O PDIR entry "valid" bit.
  563. ** We have to R/M/W the cacheline regardless how much of the
  564. ** pdir entry that we clobber.
  565. ** The rest of the entry would be useful for debugging if we
  566. ** could dump core on HPMC.
  567. */
  568. ((u8 *) pdir_ptr)[7] = 0;
  569. asm_io_fdc(pdir_ptr);
  570. WRITE_REG( SBA_IOVA(ioc, iovp, 0, 0), ioc->ioc_hpa+IOC_PCOM);
  571. }
  572. /**
  573. * sba_dma_supported - PCI driver can query DMA support
  574. * @dev: instance of PCI owned by the driver that's asking
  575. * @mask: number of address bits this PCI device can handle
  576. *
  577. * See Documentation/core-api/dma-api-howto.rst
  578. */
  579. static int sba_dma_supported( struct device *dev, u64 mask)
  580. {
  581. struct ioc *ioc;
  582. if (dev == NULL) {
  583. printk(KERN_ERR MODULE_NAME ": EISA/ISA/et al not supported\n");
  584. BUG();
  585. return(0);
  586. }
  587. ioc = GET_IOC(dev);
  588. if (!ioc)
  589. return 0;
  590. /*
  591. * check if mask is >= than the current max IO Virt Address
  592. * The max IO Virt address will *always* < 30 bits.
  593. */
  594. return((int)(mask >= (ioc->ibase - 1 +
  595. (ioc->pdir_size / sizeof(u64) * IOVP_SIZE) )));
  596. }
  597. /**
  598. * sba_map_single - map one buffer and return IOVA for DMA
  599. * @dev: instance of PCI owned by the driver that's asking.
  600. * @addr: driver buffer to map.
  601. * @size: number of bytes to map in driver buffer.
  602. * @direction: R/W or both.
  603. *
  604. * See Documentation/core-api/dma-api-howto.rst
  605. */
  606. static dma_addr_t
  607. sba_map_single(struct device *dev, void *addr, size_t size,
  608. enum dma_data_direction direction)
  609. {
  610. struct ioc *ioc;
  611. unsigned long flags;
  612. dma_addr_t iovp;
  613. dma_addr_t offset;
  614. u64 *pdir_start;
  615. int pide;
  616. ioc = GET_IOC(dev);
  617. if (!ioc)
  618. return DMA_MAPPING_ERROR;
  619. /* save offset bits */
  620. offset = ((dma_addr_t) (long) addr) & ~IOVP_MASK;
  621. /* round up to nearest IOVP_SIZE */
  622. size = (size + offset + ~IOVP_MASK) & IOVP_MASK;
  623. spin_lock_irqsave(&ioc->res_lock, flags);
  624. #ifdef ASSERT_PDIR_SANITY
  625. sba_check_pdir(ioc,"Check before sba_map_single()");
  626. #endif
  627. #ifdef SBA_COLLECT_STATS
  628. ioc->msingle_calls++;
  629. ioc->msingle_pages += size >> IOVP_SHIFT;
  630. #endif
  631. pide = sba_alloc_range(ioc, dev, size);
  632. iovp = (dma_addr_t) pide << IOVP_SHIFT;
  633. DBG_RUN("%s() 0x%p -> 0x%lx\n",
  634. __func__, addr, (long) iovp | offset);
  635. pdir_start = &(ioc->pdir_base[pide]);
  636. while (size > 0) {
  637. sba_io_pdir_entry(pdir_start, KERNEL_SPACE, (unsigned long) addr, 0);
  638. DBG_RUN(" pdir 0x%p %02x%02x%02x%02x%02x%02x%02x%02x\n",
  639. pdir_start,
  640. (u8) (((u8 *) pdir_start)[7]),
  641. (u8) (((u8 *) pdir_start)[6]),
  642. (u8) (((u8 *) pdir_start)[5]),
  643. (u8) (((u8 *) pdir_start)[4]),
  644. (u8) (((u8 *) pdir_start)[3]),
  645. (u8) (((u8 *) pdir_start)[2]),
  646. (u8) (((u8 *) pdir_start)[1]),
  647. (u8) (((u8 *) pdir_start)[0])
  648. );
  649. addr += IOVP_SIZE;
  650. size -= IOVP_SIZE;
  651. pdir_start++;
  652. }
  653. /* force FDC ops in io_pdir_entry() to be visible to IOMMU */
  654. asm_io_sync();
  655. #ifdef ASSERT_PDIR_SANITY
  656. sba_check_pdir(ioc,"Check after sba_map_single()");
  657. #endif
  658. spin_unlock_irqrestore(&ioc->res_lock, flags);
  659. /* form complete address */
  660. return SBA_IOVA(ioc, iovp, offset, DEFAULT_DMA_HINT_REG);
  661. }
  662. static dma_addr_t
  663. sba_map_page(struct device *dev, struct page *page, unsigned long offset,
  664. size_t size, enum dma_data_direction direction,
  665. unsigned long attrs)
  666. {
  667. return sba_map_single(dev, page_address(page) + offset, size,
  668. direction);
  669. }
  670. /**
  671. * sba_unmap_page - unmap one IOVA and free resources
  672. * @dev: instance of PCI owned by the driver that's asking.
  673. * @iova: IOVA of driver buffer previously mapped.
  674. * @size: number of bytes mapped in driver buffer.
  675. * @direction: R/W or both.
  676. *
  677. * See Documentation/core-api/dma-api-howto.rst
  678. */
  679. static void
  680. sba_unmap_page(struct device *dev, dma_addr_t iova, size_t size,
  681. enum dma_data_direction direction, unsigned long attrs)
  682. {
  683. struct ioc *ioc;
  684. #if DELAYED_RESOURCE_CNT > 0
  685. struct sba_dma_pair *d;
  686. #endif
  687. unsigned long flags;
  688. dma_addr_t offset;
  689. DBG_RUN("%s() iovp 0x%lx/%x\n", __func__, (long) iova, size);
  690. ioc = GET_IOC(dev);
  691. if (!ioc) {
  692. WARN_ON(!ioc);
  693. return;
  694. }
  695. offset = iova & ~IOVP_MASK;
  696. iova ^= offset; /* clear offset bits */
  697. size += offset;
  698. size = ALIGN(size, IOVP_SIZE);
  699. spin_lock_irqsave(&ioc->res_lock, flags);
  700. #ifdef SBA_COLLECT_STATS
  701. ioc->usingle_calls++;
  702. ioc->usingle_pages += size >> IOVP_SHIFT;
  703. #endif
  704. sba_mark_invalid(ioc, iova, size);
  705. #if DELAYED_RESOURCE_CNT > 0
  706. /* Delaying when we re-use a IO Pdir entry reduces the number
  707. * of MMIO reads needed to flush writes to the PCOM register.
  708. */
  709. d = &(ioc->saved[ioc->saved_cnt]);
  710. d->iova = iova;
  711. d->size = size;
  712. if (++(ioc->saved_cnt) >= DELAYED_RESOURCE_CNT) {
  713. int cnt = ioc->saved_cnt;
  714. while (cnt--) {
  715. sba_free_range(ioc, d->iova, d->size);
  716. d--;
  717. }
  718. ioc->saved_cnt = 0;
  719. READ_REG(ioc->ioc_hpa+IOC_PCOM); /* flush purges */
  720. }
  721. #else /* DELAYED_RESOURCE_CNT == 0 */
  722. sba_free_range(ioc, iova, size);
  723. /* If fdc's were issued, force fdc's to be visible now */
  724. asm_io_sync();
  725. READ_REG(ioc->ioc_hpa+IOC_PCOM); /* flush purges */
  726. #endif /* DELAYED_RESOURCE_CNT == 0 */
  727. spin_unlock_irqrestore(&ioc->res_lock, flags);
  728. /* XXX REVISIT for 2.5 Linux - need syncdma for zero-copy support.
  729. ** For Astro based systems this isn't a big deal WRT performance.
  730. ** As long as 2.4 kernels copyin/copyout data from/to userspace,
  731. ** we don't need the syncdma. The issue here is I/O MMU cachelines
  732. ** are *not* coherent in all cases. May be hwrev dependent.
  733. ** Need to investigate more.
  734. asm volatile("syncdma");
  735. */
  736. }
  737. /**
  738. * sba_alloc - allocate/map shared mem for DMA
  739. * @hwdev: instance of PCI owned by the driver that's asking.
  740. * @size: number of bytes mapped in driver buffer.
  741. * @dma_handle: IOVA of new buffer.
  742. *
  743. * See Documentation/core-api/dma-api-howto.rst
  744. */
  745. static void *sba_alloc(struct device *hwdev, size_t size, dma_addr_t *dma_handle,
  746. gfp_t gfp, unsigned long attrs)
  747. {
  748. void *ret;
  749. if (!hwdev) {
  750. /* only support PCI */
  751. *dma_handle = 0;
  752. return NULL;
  753. }
  754. ret = (void *) __get_free_pages(gfp, get_order(size));
  755. if (ret) {
  756. memset(ret, 0, size);
  757. *dma_handle = sba_map_single(hwdev, ret, size, 0);
  758. }
  759. return ret;
  760. }
  761. /**
  762. * sba_free - free/unmap shared mem for DMA
  763. * @hwdev: instance of PCI owned by the driver that's asking.
  764. * @size: number of bytes mapped in driver buffer.
  765. * @vaddr: virtual address IOVA of "consistent" buffer.
  766. * @dma_handler: IO virtual address of "consistent" buffer.
  767. *
  768. * See Documentation/core-api/dma-api-howto.rst
  769. */
  770. static void
  771. sba_free(struct device *hwdev, size_t size, void *vaddr,
  772. dma_addr_t dma_handle, unsigned long attrs)
  773. {
  774. sba_unmap_page(hwdev, dma_handle, size, 0, 0);
  775. free_pages((unsigned long) vaddr, get_order(size));
  776. }
  777. /*
  778. ** Since 0 is a valid pdir_base index value, can't use that
  779. ** to determine if a value is valid or not. Use a flag to indicate
  780. ** the SG list entry contains a valid pdir index.
  781. */
  782. #define PIDE_FLAG 0x80000000UL
  783. #ifdef SBA_COLLECT_STATS
  784. #define IOMMU_MAP_STATS
  785. #endif
  786. #include "iommu-helpers.h"
  787. #ifdef DEBUG_LARGE_SG_ENTRIES
  788. int dump_run_sg = 0;
  789. #endif
  790. /**
  791. * sba_map_sg - map Scatter/Gather list
  792. * @dev: instance of PCI owned by the driver that's asking.
  793. * @sglist: array of buffer/length pairs
  794. * @nents: number of entries in list
  795. * @direction: R/W or both.
  796. *
  797. * See Documentation/core-api/dma-api-howto.rst
  798. */
  799. static int
  800. sba_map_sg(struct device *dev, struct scatterlist *sglist, int nents,
  801. enum dma_data_direction direction, unsigned long attrs)
  802. {
  803. struct ioc *ioc;
  804. int coalesced, filled = 0;
  805. unsigned long flags;
  806. DBG_RUN_SG("%s() START %d entries\n", __func__, nents);
  807. ioc = GET_IOC(dev);
  808. if (!ioc)
  809. return 0;
  810. /* Fast path single entry scatterlists. */
  811. if (nents == 1) {
  812. sg_dma_address(sglist) = sba_map_single(dev, sg_virt(sglist),
  813. sglist->length, direction);
  814. sg_dma_len(sglist) = sglist->length;
  815. return 1;
  816. }
  817. spin_lock_irqsave(&ioc->res_lock, flags);
  818. #ifdef ASSERT_PDIR_SANITY
  819. if (sba_check_pdir(ioc,"Check before sba_map_sg()"))
  820. {
  821. sba_dump_sg(ioc, sglist, nents);
  822. panic("Check before sba_map_sg()");
  823. }
  824. #endif
  825. #ifdef SBA_COLLECT_STATS
  826. ioc->msg_calls++;
  827. #endif
  828. /*
  829. ** First coalesce the chunks and allocate I/O pdir space
  830. **
  831. ** If this is one DMA stream, we can properly map using the
  832. ** correct virtual address associated with each DMA page.
  833. ** w/o this association, we wouldn't have coherent DMA!
  834. ** Access to the virtual address is what forces a two pass algorithm.
  835. */
  836. coalesced = iommu_coalesce_chunks(ioc, dev, sglist, nents, sba_alloc_range);
  837. /*
  838. ** Program the I/O Pdir
  839. **
  840. ** map the virtual addresses to the I/O Pdir
  841. ** o dma_address will contain the pdir index
  842. ** o dma_len will contain the number of bytes to map
  843. ** o address contains the virtual address.
  844. */
  845. filled = iommu_fill_pdir(ioc, sglist, nents, 0, sba_io_pdir_entry);
  846. /* force FDC ops in io_pdir_entry() to be visible to IOMMU */
  847. asm_io_sync();
  848. #ifdef ASSERT_PDIR_SANITY
  849. if (sba_check_pdir(ioc,"Check after sba_map_sg()"))
  850. {
  851. sba_dump_sg(ioc, sglist, nents);
  852. panic("Check after sba_map_sg()\n");
  853. }
  854. #endif
  855. spin_unlock_irqrestore(&ioc->res_lock, flags);
  856. DBG_RUN_SG("%s() DONE %d mappings\n", __func__, filled);
  857. return filled;
  858. }
  859. /**
  860. * sba_unmap_sg - unmap Scatter/Gather list
  861. * @dev: instance of PCI owned by the driver that's asking.
  862. * @sglist: array of buffer/length pairs
  863. * @nents: number of entries in list
  864. * @direction: R/W or both.
  865. *
  866. * See Documentation/core-api/dma-api-howto.rst
  867. */
  868. static void
  869. sba_unmap_sg(struct device *dev, struct scatterlist *sglist, int nents,
  870. enum dma_data_direction direction, unsigned long attrs)
  871. {
  872. struct ioc *ioc;
  873. #ifdef ASSERT_PDIR_SANITY
  874. unsigned long flags;
  875. #endif
  876. DBG_RUN_SG("%s() START %d entries, %p,%x\n",
  877. __func__, nents, sg_virt(sglist), sglist->length);
  878. ioc = GET_IOC(dev);
  879. if (!ioc) {
  880. WARN_ON(!ioc);
  881. return;
  882. }
  883. #ifdef SBA_COLLECT_STATS
  884. ioc->usg_calls++;
  885. #endif
  886. #ifdef ASSERT_PDIR_SANITY
  887. spin_lock_irqsave(&ioc->res_lock, flags);
  888. sba_check_pdir(ioc,"Check before sba_unmap_sg()");
  889. spin_unlock_irqrestore(&ioc->res_lock, flags);
  890. #endif
  891. while (nents && sg_dma_len(sglist)) {
  892. sba_unmap_page(dev, sg_dma_address(sglist), sg_dma_len(sglist),
  893. direction, 0);
  894. #ifdef SBA_COLLECT_STATS
  895. ioc->usg_pages += ((sg_dma_address(sglist) & ~IOVP_MASK) + sg_dma_len(sglist) + IOVP_SIZE - 1) >> PAGE_SHIFT;
  896. ioc->usingle_calls--; /* kluge since call is unmap_sg() */
  897. #endif
  898. ++sglist;
  899. nents--;
  900. }
  901. DBG_RUN_SG("%s() DONE (nents %d)\n", __func__, nents);
  902. #ifdef ASSERT_PDIR_SANITY
  903. spin_lock_irqsave(&ioc->res_lock, flags);
  904. sba_check_pdir(ioc,"Check after sba_unmap_sg()");
  905. spin_unlock_irqrestore(&ioc->res_lock, flags);
  906. #endif
  907. }
  908. static const struct dma_map_ops sba_ops = {
  909. .dma_supported = sba_dma_supported,
  910. .alloc = sba_alloc,
  911. .free = sba_free,
  912. .map_page = sba_map_page,
  913. .unmap_page = sba_unmap_page,
  914. .map_sg = sba_map_sg,
  915. .unmap_sg = sba_unmap_sg,
  916. .get_sgtable = dma_common_get_sgtable,
  917. .alloc_pages = dma_common_alloc_pages,
  918. .free_pages = dma_common_free_pages,
  919. };
  920. /**************************************************************************
  921. **
  922. ** SBA PAT PDC support
  923. **
  924. ** o call pdc_pat_cell_module()
  925. ** o store ranges in PCI "resource" structures
  926. **
  927. **************************************************************************/
  928. static void
  929. sba_get_pat_resources(struct sba_device *sba_dev)
  930. {
  931. #if 0
  932. /*
  933. ** TODO/REVISIT/FIXME: support for directed ranges requires calls to
  934. ** PAT PDC to program the SBA/LBA directed range registers...this
  935. ** burden may fall on the LBA code since it directly supports the
  936. ** PCI subsystem. It's not clear yet. - ggg
  937. */
  938. PAT_MOD(mod)->mod_info.mod_pages = PAT_GET_MOD_PAGES(temp);
  939. FIXME : ???
  940. PAT_MOD(mod)->mod_info.dvi = PAT_GET_DVI(temp);
  941. Tells where the dvi bits are located in the address.
  942. PAT_MOD(mod)->mod_info.ioc = PAT_GET_IOC(temp);
  943. FIXME : ???
  944. #endif
  945. }
  946. /**************************************************************
  947. *
  948. * Initialization and claim
  949. *
  950. ***************************************************************/
  951. #define PIRANHA_ADDR_MASK 0x00160000UL /* bit 17,18,20 */
  952. #define PIRANHA_ADDR_VAL 0x00060000UL /* bit 17,18 on */
  953. static void *
  954. sba_alloc_pdir(unsigned int pdir_size)
  955. {
  956. unsigned long pdir_base;
  957. unsigned long pdir_order = get_order(pdir_size);
  958. pdir_base = __get_free_pages(GFP_KERNEL, pdir_order);
  959. if (NULL == (void *) pdir_base) {
  960. panic("%s() could not allocate I/O Page Table\n",
  961. __func__);
  962. }
  963. /* If this is not PA8700 (PCX-W2)
  964. ** OR newer than ver 2.2
  965. ** OR in a system that doesn't need VINDEX bits from SBA,
  966. **
  967. ** then we aren't exposed to the HW bug.
  968. */
  969. if ( ((boot_cpu_data.pdc.cpuid >> 5) & 0x7f) != 0x13
  970. || (boot_cpu_data.pdc.versions > 0x202)
  971. || (boot_cpu_data.pdc.capabilities & 0x08L) )
  972. return (void *) pdir_base;
  973. /*
  974. * PA8700 (PCX-W2, aka piranha) silent data corruption fix
  975. *
  976. * An interaction between PA8700 CPU (Ver 2.2 or older) and
  977. * Ike/Astro can cause silent data corruption. This is only
  978. * a problem if the I/O PDIR is located in memory such that
  979. * (little-endian) bits 17 and 18 are on and bit 20 is off.
  980. *
  981. * Since the max IO Pdir size is 2MB, by cleverly allocating the
  982. * right physical address, we can either avoid (IOPDIR <= 1MB)
  983. * or minimize (2MB IO Pdir) the problem if we restrict the
  984. * IO Pdir to a maximum size of 2MB-128K (1902K).
  985. *
  986. * Because we always allocate 2^N sized IO pdirs, either of the
  987. * "bad" regions will be the last 128K if at all. That's easy
  988. * to test for.
  989. *
  990. */
  991. if (pdir_order <= (19-12)) {
  992. if (((virt_to_phys(pdir_base)+pdir_size-1) & PIRANHA_ADDR_MASK) == PIRANHA_ADDR_VAL) {
  993. /* allocate a new one on 512k alignment */
  994. unsigned long new_pdir = __get_free_pages(GFP_KERNEL, (19-12));
  995. /* release original */
  996. free_pages(pdir_base, pdir_order);
  997. pdir_base = new_pdir;
  998. /* release excess */
  999. while (pdir_order < (19-12)) {
  1000. new_pdir += pdir_size;
  1001. free_pages(new_pdir, pdir_order);
  1002. pdir_order +=1;
  1003. pdir_size <<=1;
  1004. }
  1005. }
  1006. } else {
  1007. /*
  1008. ** 1MB or 2MB Pdir
  1009. ** Needs to be aligned on an "odd" 1MB boundary.
  1010. */
  1011. unsigned long new_pdir = __get_free_pages(GFP_KERNEL, pdir_order+1); /* 2 or 4MB */
  1012. /* release original */
  1013. free_pages( pdir_base, pdir_order);
  1014. /* release first 1MB */
  1015. free_pages(new_pdir, 20-12);
  1016. pdir_base = new_pdir + 1024*1024;
  1017. if (pdir_order > (20-12)) {
  1018. /*
  1019. ** 2MB Pdir.
  1020. **
  1021. ** Flag tells init_bitmap() to mark bad 128k as used
  1022. ** and to reduce the size by 128k.
  1023. */
  1024. piranha_bad_128k = 1;
  1025. new_pdir += 3*1024*1024;
  1026. /* release last 1MB */
  1027. free_pages(new_pdir, 20-12);
  1028. /* release unusable 128KB */
  1029. free_pages(new_pdir - 128*1024 , 17-12);
  1030. pdir_size -= 128*1024;
  1031. }
  1032. }
  1033. memset((void *) pdir_base, 0, pdir_size);
  1034. return (void *) pdir_base;
  1035. }
  1036. struct ibase_data_struct {
  1037. struct ioc *ioc;
  1038. int ioc_num;
  1039. };
  1040. static int setup_ibase_imask_callback(struct device *dev, void *data)
  1041. {
  1042. /* lba_set_iregs() is in drivers/parisc/lba_pci.c */
  1043. extern void lba_set_iregs(struct parisc_device *, u32, u32);
  1044. struct parisc_device *lba = to_parisc_device(dev);
  1045. struct ibase_data_struct *ibd = data;
  1046. int rope_num = (lba->hpa.start >> 13) & 0xf;
  1047. if (rope_num >> 3 == ibd->ioc_num)
  1048. lba_set_iregs(lba, ibd->ioc->ibase, ibd->ioc->imask);
  1049. return 0;
  1050. }
  1051. /* setup Mercury or Elroy IBASE/IMASK registers. */
  1052. static void
  1053. setup_ibase_imask(struct parisc_device *sba, struct ioc *ioc, int ioc_num)
  1054. {
  1055. struct ibase_data_struct ibase_data = {
  1056. .ioc = ioc,
  1057. .ioc_num = ioc_num,
  1058. };
  1059. device_for_each_child(&sba->dev, &ibase_data,
  1060. setup_ibase_imask_callback);
  1061. }
  1062. #ifdef SBA_AGP_SUPPORT
  1063. static int
  1064. sba_ioc_find_quicksilver(struct device *dev, void *data)
  1065. {
  1066. int *agp_found = data;
  1067. struct parisc_device *lba = to_parisc_device(dev);
  1068. if (IS_QUICKSILVER(lba))
  1069. *agp_found = 1;
  1070. return 0;
  1071. }
  1072. #endif
  1073. static void
  1074. sba_ioc_init_pluto(struct parisc_device *sba, struct ioc *ioc, int ioc_num)
  1075. {
  1076. u32 iova_space_mask;
  1077. u32 iova_space_size;
  1078. int iov_order, tcnfg;
  1079. #ifdef SBA_AGP_SUPPORT
  1080. int agp_found = 0;
  1081. #endif
  1082. /*
  1083. ** Firmware programs the base and size of a "safe IOVA space"
  1084. ** (one that doesn't overlap memory or LMMIO space) in the
  1085. ** IBASE and IMASK registers.
  1086. */
  1087. ioc->ibase = READ_REG(ioc->ioc_hpa + IOC_IBASE) & ~0x1fffffULL;
  1088. iova_space_size = ~(READ_REG(ioc->ioc_hpa + IOC_IMASK) & 0xFFFFFFFFUL) + 1;
  1089. if ((ioc->ibase < 0xfed00000UL) && ((ioc->ibase + iova_space_size) > 0xfee00000UL)) {
  1090. printk("WARNING: IOV space overlaps local config and interrupt message, truncating\n");
  1091. iova_space_size /= 2;
  1092. }
  1093. /*
  1094. ** iov_order is always based on a 1GB IOVA space since we want to
  1095. ** turn on the other half for AGP GART.
  1096. */
  1097. iov_order = get_order(iova_space_size >> (IOVP_SHIFT - PAGE_SHIFT));
  1098. ioc->pdir_size = (iova_space_size / IOVP_SIZE) * sizeof(u64);
  1099. DBG_INIT("%s() hpa 0x%p IOV %dMB (%d bits)\n",
  1100. __func__, ioc->ioc_hpa, iova_space_size >> 20,
  1101. iov_order + PAGE_SHIFT);
  1102. ioc->pdir_base = (void *) __get_free_pages(GFP_KERNEL,
  1103. get_order(ioc->pdir_size));
  1104. if (!ioc->pdir_base)
  1105. panic("Couldn't allocate I/O Page Table\n");
  1106. memset(ioc->pdir_base, 0, ioc->pdir_size);
  1107. DBG_INIT("%s() pdir %p size %x\n",
  1108. __func__, ioc->pdir_base, ioc->pdir_size);
  1109. #ifdef SBA_HINT_SUPPORT
  1110. ioc->hint_shift_pdir = iov_order + PAGE_SHIFT;
  1111. ioc->hint_mask_pdir = ~(0x3 << (iov_order + PAGE_SHIFT));
  1112. DBG_INIT(" hint_shift_pdir %x hint_mask_pdir %lx\n",
  1113. ioc->hint_shift_pdir, ioc->hint_mask_pdir);
  1114. #endif
  1115. WARN_ON((((unsigned long) ioc->pdir_base) & PAGE_MASK) != (unsigned long) ioc->pdir_base);
  1116. WRITE_REG(virt_to_phys(ioc->pdir_base), ioc->ioc_hpa + IOC_PDIR_BASE);
  1117. /* build IMASK for IOC and Elroy */
  1118. iova_space_mask = 0xffffffff;
  1119. iova_space_mask <<= (iov_order + PAGE_SHIFT);
  1120. ioc->imask = iova_space_mask;
  1121. #ifdef ZX1_SUPPORT
  1122. ioc->iovp_mask = ~(iova_space_mask + PAGE_SIZE - 1);
  1123. #endif
  1124. sba_dump_tlb(ioc->ioc_hpa);
  1125. setup_ibase_imask(sba, ioc, ioc_num);
  1126. WRITE_REG(ioc->imask, ioc->ioc_hpa + IOC_IMASK);
  1127. #ifdef CONFIG_64BIT
  1128. /*
  1129. ** Setting the upper bits makes checking for bypass addresses
  1130. ** a little faster later on.
  1131. */
  1132. ioc->imask |= 0xFFFFFFFF00000000UL;
  1133. #endif
  1134. /* Set I/O PDIR Page size to system page size */
  1135. switch (PAGE_SHIFT) {
  1136. case 12: tcnfg = 0; break; /* 4K */
  1137. case 13: tcnfg = 1; break; /* 8K */
  1138. case 14: tcnfg = 2; break; /* 16K */
  1139. case 16: tcnfg = 3; break; /* 64K */
  1140. default:
  1141. panic(__FILE__ "Unsupported system page size %d",
  1142. 1 << PAGE_SHIFT);
  1143. break;
  1144. }
  1145. WRITE_REG(tcnfg, ioc->ioc_hpa + IOC_TCNFG);
  1146. /*
  1147. ** Program the IOC's ibase and enable IOVA translation
  1148. ** Bit zero == enable bit.
  1149. */
  1150. WRITE_REG(ioc->ibase | 1, ioc->ioc_hpa + IOC_IBASE);
  1151. /*
  1152. ** Clear I/O TLB of any possible entries.
  1153. ** (Yes. This is a bit paranoid...but so what)
  1154. */
  1155. WRITE_REG(ioc->ibase | 31, ioc->ioc_hpa + IOC_PCOM);
  1156. #ifdef SBA_AGP_SUPPORT
  1157. /*
  1158. ** If an AGP device is present, only use half of the IOV space
  1159. ** for PCI DMA. Unfortunately we can't know ahead of time
  1160. ** whether GART support will actually be used, for now we
  1161. ** can just key on any AGP device found in the system.
  1162. ** We program the next pdir index after we stop w/ a key for
  1163. ** the GART code to handshake on.
  1164. */
  1165. device_for_each_child(&sba->dev, &agp_found, sba_ioc_find_quicksilver);
  1166. if (agp_found && sba_reserve_agpgart) {
  1167. printk(KERN_INFO "%s: reserving %dMb of IOVA space for agpgart\n",
  1168. __func__, (iova_space_size/2) >> 20);
  1169. ioc->pdir_size /= 2;
  1170. ioc->pdir_base[PDIR_INDEX(iova_space_size/2)] = SBA_AGPGART_COOKIE;
  1171. }
  1172. #endif /*SBA_AGP_SUPPORT*/
  1173. }
  1174. static void
  1175. sba_ioc_init(struct parisc_device *sba, struct ioc *ioc, int ioc_num)
  1176. {
  1177. u32 iova_space_size, iova_space_mask;
  1178. unsigned int pdir_size, iov_order, tcnfg;
  1179. /*
  1180. ** Determine IOVA Space size from memory size.
  1181. **
  1182. ** Ideally, PCI drivers would register the maximum number
  1183. ** of DMA they can have outstanding for each device they
  1184. ** own. Next best thing would be to guess how much DMA
  1185. ** can be outstanding based on PCI Class/sub-class. Both
  1186. ** methods still require some "extra" to support PCI
  1187. ** Hot-Plug/Removal of PCI cards. (aka PCI OLARD).
  1188. **
  1189. ** While we have 32-bits "IOVA" space, top two 2 bits are used
  1190. ** for DMA hints - ergo only 30 bits max.
  1191. */
  1192. iova_space_size = (u32) (totalram_pages()/global_ioc_cnt);
  1193. /* limit IOVA space size to 1MB-1GB */
  1194. if (iova_space_size < (1 << (20 - PAGE_SHIFT))) {
  1195. iova_space_size = 1 << (20 - PAGE_SHIFT);
  1196. }
  1197. else if (iova_space_size > (1 << (30 - PAGE_SHIFT))) {
  1198. iova_space_size = 1 << (30 - PAGE_SHIFT);
  1199. }
  1200. /*
  1201. ** iova space must be log2() in size.
  1202. ** thus, pdir/res_map will also be log2().
  1203. ** PIRANHA BUG: Exception is when IO Pdir is 2MB (gets reduced)
  1204. */
  1205. iov_order = get_order(iova_space_size << PAGE_SHIFT);
  1206. /* iova_space_size is now bytes, not pages */
  1207. iova_space_size = 1 << (iov_order + PAGE_SHIFT);
  1208. ioc->pdir_size = pdir_size = (iova_space_size/IOVP_SIZE) * sizeof(u64);
  1209. DBG_INIT("%s() hpa 0x%lx mem %ldMB IOV %dMB (%d bits)\n",
  1210. __func__,
  1211. ioc->ioc_hpa,
  1212. (unsigned long) totalram_pages() >> (20 - PAGE_SHIFT),
  1213. iova_space_size>>20,
  1214. iov_order + PAGE_SHIFT);
  1215. ioc->pdir_base = sba_alloc_pdir(pdir_size);
  1216. DBG_INIT("%s() pdir %p size %x\n",
  1217. __func__, ioc->pdir_base, pdir_size);
  1218. #ifdef SBA_HINT_SUPPORT
  1219. /* FIXME : DMA HINTs not used */
  1220. ioc->hint_shift_pdir = iov_order + PAGE_SHIFT;
  1221. ioc->hint_mask_pdir = ~(0x3 << (iov_order + PAGE_SHIFT));
  1222. DBG_INIT(" hint_shift_pdir %x hint_mask_pdir %lx\n",
  1223. ioc->hint_shift_pdir, ioc->hint_mask_pdir);
  1224. #endif
  1225. WRITE_REG64(virt_to_phys(ioc->pdir_base), ioc->ioc_hpa + IOC_PDIR_BASE);
  1226. /* build IMASK for IOC and Elroy */
  1227. iova_space_mask = 0xffffffff;
  1228. iova_space_mask <<= (iov_order + PAGE_SHIFT);
  1229. /*
  1230. ** On C3000 w/512MB mem, HP-UX 10.20 reports:
  1231. ** ibase=0, imask=0xFE000000, size=0x2000000.
  1232. */
  1233. ioc->ibase = 0;
  1234. ioc->imask = iova_space_mask; /* save it */
  1235. #ifdef ZX1_SUPPORT
  1236. ioc->iovp_mask = ~(iova_space_mask + PAGE_SIZE - 1);
  1237. #endif
  1238. DBG_INIT("%s() IOV base 0x%lx mask 0x%0lx\n",
  1239. __func__, ioc->ibase, ioc->imask);
  1240. /*
  1241. ** FIXME: Hint registers are programmed with default hint
  1242. ** values during boot, so hints should be sane even if we
  1243. ** can't reprogram them the way drivers want.
  1244. */
  1245. setup_ibase_imask(sba, ioc, ioc_num);
  1246. /*
  1247. ** Program the IOC's ibase and enable IOVA translation
  1248. */
  1249. WRITE_REG(ioc->ibase | 1, ioc->ioc_hpa+IOC_IBASE);
  1250. WRITE_REG(ioc->imask, ioc->ioc_hpa+IOC_IMASK);
  1251. /* Set I/O PDIR Page size to system page size */
  1252. switch (PAGE_SHIFT) {
  1253. case 12: tcnfg = 0; break; /* 4K */
  1254. case 13: tcnfg = 1; break; /* 8K */
  1255. case 14: tcnfg = 2; break; /* 16K */
  1256. case 16: tcnfg = 3; break; /* 64K */
  1257. default:
  1258. panic(__FILE__ "Unsupported system page size %d",
  1259. 1 << PAGE_SHIFT);
  1260. break;
  1261. }
  1262. /* Set I/O PDIR Page size to PAGE_SIZE (4k/16k/...) */
  1263. WRITE_REG(tcnfg, ioc->ioc_hpa+IOC_TCNFG);
  1264. /*
  1265. ** Clear I/O TLB of any possible entries.
  1266. ** (Yes. This is a bit paranoid...but so what)
  1267. */
  1268. WRITE_REG(0 | 31, ioc->ioc_hpa+IOC_PCOM);
  1269. ioc->ibase = 0; /* used by SBA_IOVA and related macros */
  1270. DBG_INIT("%s() DONE\n", __func__);
  1271. }
  1272. /**************************************************************************
  1273. **
  1274. ** SBA initialization code (HW and SW)
  1275. **
  1276. ** o identify SBA chip itself
  1277. ** o initialize SBA chip modes (HardFail)
  1278. ** o initialize SBA chip modes (HardFail)
  1279. ** o FIXME: initialize DMA hints for reasonable defaults
  1280. **
  1281. **************************************************************************/
  1282. static void __iomem *ioc_remap(struct sba_device *sba_dev, unsigned int offset)
  1283. {
  1284. return ioremap(sba_dev->dev->hpa.start + offset, SBA_FUNC_SIZE);
  1285. }
  1286. static void sba_hw_init(struct sba_device *sba_dev)
  1287. {
  1288. int i;
  1289. int num_ioc;
  1290. u64 ioc_ctl;
  1291. if (!is_pdc_pat()) {
  1292. /* Shutdown the USB controller on Astro-based workstations.
  1293. ** Once we reprogram the IOMMU, the next DMA performed by
  1294. ** USB will HPMC the box. USB is only enabled if a
  1295. ** keyboard is present and found.
  1296. **
  1297. ** With serial console, j6k v5.0 firmware says:
  1298. ** mem_kbd hpa 0xfee003f8 sba 0x0 pad 0x0 cl_class 0x7
  1299. **
  1300. ** FIXME: Using GFX+USB console at power up but direct
  1301. ** linux to serial console is still broken.
  1302. ** USB could generate DMA so we must reset USB.
  1303. ** The proper sequence would be:
  1304. ** o block console output
  1305. ** o reset USB device
  1306. ** o reprogram serial port
  1307. ** o unblock console output
  1308. */
  1309. if (PAGE0->mem_kbd.cl_class == CL_KEYBD) {
  1310. pdc_io_reset_devices();
  1311. }
  1312. }
  1313. #if 0
  1314. printk("sba_hw_init(): mem_boot 0x%x 0x%x 0x%x 0x%x\n", PAGE0->mem_boot.hpa,
  1315. PAGE0->mem_boot.spa, PAGE0->mem_boot.pad, PAGE0->mem_boot.cl_class);
  1316. /*
  1317. ** Need to deal with DMA from LAN.
  1318. ** Maybe use page zero boot device as a handle to talk
  1319. ** to PDC about which device to shutdown.
  1320. **
  1321. ** Netbooting, j6k v5.0 firmware says:
  1322. ** mem_boot hpa 0xf4008000 sba 0x0 pad 0x0 cl_class 0x1002
  1323. ** ARGH! invalid class.
  1324. */
  1325. if ((PAGE0->mem_boot.cl_class != CL_RANDOM)
  1326. && (PAGE0->mem_boot.cl_class != CL_SEQU)) {
  1327. pdc_io_reset();
  1328. }
  1329. #endif
  1330. if (!IS_PLUTO(sba_dev->dev)) {
  1331. ioc_ctl = READ_REG(sba_dev->sba_hpa+IOC_CTRL);
  1332. DBG_INIT("%s() hpa 0x%lx ioc_ctl 0x%Lx ->",
  1333. __func__, sba_dev->sba_hpa, ioc_ctl);
  1334. ioc_ctl &= ~(IOC_CTRL_RM | IOC_CTRL_NC | IOC_CTRL_CE);
  1335. ioc_ctl |= IOC_CTRL_DD | IOC_CTRL_D4 | IOC_CTRL_TC;
  1336. /* j6700 v1.6 firmware sets 0x294f */
  1337. /* A500 firmware sets 0x4d */
  1338. WRITE_REG(ioc_ctl, sba_dev->sba_hpa+IOC_CTRL);
  1339. #ifdef DEBUG_SBA_INIT
  1340. ioc_ctl = READ_REG64(sba_dev->sba_hpa+IOC_CTRL);
  1341. DBG_INIT(" 0x%Lx\n", ioc_ctl);
  1342. #endif
  1343. } /* if !PLUTO */
  1344. if (IS_ASTRO(sba_dev->dev)) {
  1345. int err;
  1346. sba_dev->ioc[0].ioc_hpa = ioc_remap(sba_dev, ASTRO_IOC_OFFSET);
  1347. num_ioc = 1;
  1348. sba_dev->chip_resv.name = "Astro Intr Ack";
  1349. sba_dev->chip_resv.start = PCI_F_EXTEND | 0xfef00000UL;
  1350. sba_dev->chip_resv.end = PCI_F_EXTEND | (0xff000000UL - 1) ;
  1351. err = request_resource(&iomem_resource, &(sba_dev->chip_resv));
  1352. BUG_ON(err < 0);
  1353. } else if (IS_PLUTO(sba_dev->dev)) {
  1354. int err;
  1355. sba_dev->ioc[0].ioc_hpa = ioc_remap(sba_dev, PLUTO_IOC_OFFSET);
  1356. num_ioc = 1;
  1357. sba_dev->chip_resv.name = "Pluto Intr/PIOP/VGA";
  1358. sba_dev->chip_resv.start = PCI_F_EXTEND | 0xfee00000UL;
  1359. sba_dev->chip_resv.end = PCI_F_EXTEND | (0xff200000UL - 1);
  1360. err = request_resource(&iomem_resource, &(sba_dev->chip_resv));
  1361. WARN_ON(err < 0);
  1362. sba_dev->iommu_resv.name = "IOVA Space";
  1363. sba_dev->iommu_resv.start = 0x40000000UL;
  1364. sba_dev->iommu_resv.end = 0x50000000UL - 1;
  1365. err = request_resource(&iomem_resource, &(sba_dev->iommu_resv));
  1366. WARN_ON(err < 0);
  1367. } else {
  1368. /* IKE, REO */
  1369. sba_dev->ioc[0].ioc_hpa = ioc_remap(sba_dev, IKE_IOC_OFFSET(0));
  1370. sba_dev->ioc[1].ioc_hpa = ioc_remap(sba_dev, IKE_IOC_OFFSET(1));
  1371. num_ioc = 2;
  1372. /* TODO - LOOKUP Ike/Stretch chipset mem map */
  1373. }
  1374. /* XXX: What about Reo Grande? */
  1375. sba_dev->num_ioc = num_ioc;
  1376. for (i = 0; i < num_ioc; i++) {
  1377. void __iomem *ioc_hpa = sba_dev->ioc[i].ioc_hpa;
  1378. unsigned int j;
  1379. for (j=0; j < sizeof(u64) * ROPES_PER_IOC; j+=sizeof(u64)) {
  1380. /*
  1381. * Clear ROPE(N)_CONFIG AO bit.
  1382. * Disables "NT Ordering" (~= !"Relaxed Ordering")
  1383. * Overrides bit 1 in DMA Hint Sets.
  1384. * Improves netperf UDP_STREAM by ~10% for bcm5701.
  1385. */
  1386. if (IS_PLUTO(sba_dev->dev)) {
  1387. void __iomem *rope_cfg;
  1388. unsigned long cfg_val;
  1389. rope_cfg = ioc_hpa + IOC_ROPE0_CFG + j;
  1390. cfg_val = READ_REG(rope_cfg);
  1391. cfg_val &= ~IOC_ROPE_AO;
  1392. WRITE_REG(cfg_val, rope_cfg);
  1393. }
  1394. /*
  1395. ** Make sure the box crashes on rope errors.
  1396. */
  1397. WRITE_REG(HF_ENABLE, ioc_hpa + ROPE0_CTL + j);
  1398. }
  1399. /* flush out the last writes */
  1400. READ_REG(sba_dev->ioc[i].ioc_hpa + ROPE7_CTL);
  1401. DBG_INIT(" ioc[%d] ROPE_CFG 0x%Lx ROPE_DBG 0x%Lx\n",
  1402. i,
  1403. READ_REG(sba_dev->ioc[i].ioc_hpa + 0x40),
  1404. READ_REG(sba_dev->ioc[i].ioc_hpa + 0x50)
  1405. );
  1406. DBG_INIT(" STATUS_CONTROL 0x%Lx FLUSH_CTRL 0x%Lx\n",
  1407. READ_REG(sba_dev->ioc[i].ioc_hpa + 0x108),
  1408. READ_REG(sba_dev->ioc[i].ioc_hpa + 0x400)
  1409. );
  1410. if (IS_PLUTO(sba_dev->dev)) {
  1411. sba_ioc_init_pluto(sba_dev->dev, &(sba_dev->ioc[i]), i);
  1412. } else {
  1413. sba_ioc_init(sba_dev->dev, &(sba_dev->ioc[i]), i);
  1414. }
  1415. }
  1416. }
  1417. static void
  1418. sba_common_init(struct sba_device *sba_dev)
  1419. {
  1420. int i;
  1421. /* add this one to the head of the list (order doesn't matter)
  1422. ** This will be useful for debugging - especially if we get coredumps
  1423. */
  1424. sba_dev->next = sba_list;
  1425. sba_list = sba_dev;
  1426. for(i=0; i< sba_dev->num_ioc; i++) {
  1427. int res_size;
  1428. #ifdef DEBUG_DMB_TRAP
  1429. extern void iterate_pages(unsigned long , unsigned long ,
  1430. void (*)(pte_t * , unsigned long),
  1431. unsigned long );
  1432. void set_data_memory_break(pte_t * , unsigned long);
  1433. #endif
  1434. /* resource map size dictated by pdir_size */
  1435. res_size = sba_dev->ioc[i].pdir_size/sizeof(u64); /* entries */
  1436. /* Second part of PIRANHA BUG */
  1437. if (piranha_bad_128k) {
  1438. res_size -= (128*1024)/sizeof(u64);
  1439. }
  1440. res_size >>= 3; /* convert bit count to byte count */
  1441. DBG_INIT("%s() res_size 0x%x\n",
  1442. __func__, res_size);
  1443. sba_dev->ioc[i].res_size = res_size;
  1444. sba_dev->ioc[i].res_map = (char *) __get_free_pages(GFP_KERNEL, get_order(res_size));
  1445. #ifdef DEBUG_DMB_TRAP
  1446. iterate_pages( sba_dev->ioc[i].res_map, res_size,
  1447. set_data_memory_break, 0);
  1448. #endif
  1449. if (NULL == sba_dev->ioc[i].res_map)
  1450. {
  1451. panic("%s:%s() could not allocate resource map\n",
  1452. __FILE__, __func__ );
  1453. }
  1454. memset(sba_dev->ioc[i].res_map, 0, res_size);
  1455. /* next available IOVP - circular search */
  1456. sba_dev->ioc[i].res_hint = (unsigned long *)
  1457. &(sba_dev->ioc[i].res_map[L1_CACHE_BYTES]);
  1458. #ifdef ASSERT_PDIR_SANITY
  1459. /* Mark first bit busy - ie no IOVA 0 */
  1460. sba_dev->ioc[i].res_map[0] = 0x80;
  1461. sba_dev->ioc[i].pdir_base[0] = 0xeeffc0addbba0080ULL;
  1462. #endif
  1463. /* Third (and last) part of PIRANHA BUG */
  1464. if (piranha_bad_128k) {
  1465. /* region from +1408K to +1536 is un-usable. */
  1466. int idx_start = (1408*1024/sizeof(u64)) >> 3;
  1467. int idx_end = (1536*1024/sizeof(u64)) >> 3;
  1468. long *p_start = (long *) &(sba_dev->ioc[i].res_map[idx_start]);
  1469. long *p_end = (long *) &(sba_dev->ioc[i].res_map[idx_end]);
  1470. /* mark that part of the io pdir busy */
  1471. while (p_start < p_end)
  1472. *p_start++ = -1;
  1473. }
  1474. #ifdef DEBUG_DMB_TRAP
  1475. iterate_pages( sba_dev->ioc[i].res_map, res_size,
  1476. set_data_memory_break, 0);
  1477. iterate_pages( sba_dev->ioc[i].pdir_base, sba_dev->ioc[i].pdir_size,
  1478. set_data_memory_break, 0);
  1479. #endif
  1480. DBG_INIT("%s() %d res_map %x %p\n",
  1481. __func__, i, res_size, sba_dev->ioc[i].res_map);
  1482. }
  1483. spin_lock_init(&sba_dev->sba_lock);
  1484. ioc_needs_fdc = boot_cpu_data.pdc.capabilities & PDC_MODEL_IOPDIR_FDC;
  1485. #ifdef DEBUG_SBA_INIT
  1486. /*
  1487. * If the PDC_MODEL capabilities has Non-coherent IO-PDIR bit set
  1488. * (bit #61, big endian), we have to flush and sync every time
  1489. * IO-PDIR is changed in Ike/Astro.
  1490. */
  1491. if (ioc_needs_fdc) {
  1492. printk(KERN_INFO MODULE_NAME " FDC/SYNC required.\n");
  1493. } else {
  1494. printk(KERN_INFO MODULE_NAME " IOC has cache coherent PDIR.\n");
  1495. }
  1496. #endif
  1497. }
  1498. #ifdef CONFIG_PROC_FS
  1499. static int sba_proc_info(struct seq_file *m, void *p)
  1500. {
  1501. struct sba_device *sba_dev = sba_list;
  1502. struct ioc *ioc = &sba_dev->ioc[0]; /* FIXME: Multi-IOC support! */
  1503. int total_pages = (int) (ioc->res_size << 3); /* 8 bits per byte */
  1504. #ifdef SBA_COLLECT_STATS
  1505. unsigned long avg = 0, min, max;
  1506. #endif
  1507. int i;
  1508. seq_printf(m, "%s rev %d.%d\n",
  1509. sba_dev->name,
  1510. (sba_dev->hw_rev & 0x7) + 1,
  1511. (sba_dev->hw_rev & 0x18) >> 3);
  1512. seq_printf(m, "IO PDIR size : %d bytes (%d entries)\n",
  1513. (int)((ioc->res_size << 3) * sizeof(u64)), /* 8 bits/byte */
  1514. total_pages);
  1515. seq_printf(m, "Resource bitmap : %d bytes (%d pages)\n",
  1516. ioc->res_size, ioc->res_size << 3); /* 8 bits per byte */
  1517. seq_printf(m, "LMMIO_BASE/MASK/ROUTE %08x %08x %08x\n",
  1518. READ_REG32(sba_dev->sba_hpa + LMMIO_DIST_BASE),
  1519. READ_REG32(sba_dev->sba_hpa + LMMIO_DIST_MASK),
  1520. READ_REG32(sba_dev->sba_hpa + LMMIO_DIST_ROUTE));
  1521. for (i=0; i<4; i++)
  1522. seq_printf(m, "DIR%d_BASE/MASK/ROUTE %08x %08x %08x\n",
  1523. i,
  1524. READ_REG32(sba_dev->sba_hpa + LMMIO_DIRECT0_BASE + i*0x18),
  1525. READ_REG32(sba_dev->sba_hpa + LMMIO_DIRECT0_MASK + i*0x18),
  1526. READ_REG32(sba_dev->sba_hpa + LMMIO_DIRECT0_ROUTE + i*0x18));
  1527. #ifdef SBA_COLLECT_STATS
  1528. seq_printf(m, "IO PDIR entries : %ld free %ld used (%d%%)\n",
  1529. total_pages - ioc->used_pages, ioc->used_pages,
  1530. (int)(ioc->used_pages * 100 / total_pages));
  1531. min = max = ioc->avg_search[0];
  1532. for (i = 0; i < SBA_SEARCH_SAMPLE; i++) {
  1533. avg += ioc->avg_search[i];
  1534. if (ioc->avg_search[i] > max) max = ioc->avg_search[i];
  1535. if (ioc->avg_search[i] < min) min = ioc->avg_search[i];
  1536. }
  1537. avg /= SBA_SEARCH_SAMPLE;
  1538. seq_printf(m, " Bitmap search : %ld/%ld/%ld (min/avg/max CPU Cycles)\n",
  1539. min, avg, max);
  1540. seq_printf(m, "pci_map_single(): %12ld calls %12ld pages (avg %d/1000)\n",
  1541. ioc->msingle_calls, ioc->msingle_pages,
  1542. (int)((ioc->msingle_pages * 1000)/ioc->msingle_calls));
  1543. /* KLUGE - unmap_sg calls unmap_single for each mapped page */
  1544. min = ioc->usingle_calls;
  1545. max = ioc->usingle_pages - ioc->usg_pages;
  1546. seq_printf(m, "pci_unmap_single: %12ld calls %12ld pages (avg %d/1000)\n",
  1547. min, max, (int)((max * 1000)/min));
  1548. seq_printf(m, "pci_map_sg() : %12ld calls %12ld pages (avg %d/1000)\n",
  1549. ioc->msg_calls, ioc->msg_pages,
  1550. (int)((ioc->msg_pages * 1000)/ioc->msg_calls));
  1551. seq_printf(m, "pci_unmap_sg() : %12ld calls %12ld pages (avg %d/1000)\n",
  1552. ioc->usg_calls, ioc->usg_pages,
  1553. (int)((ioc->usg_pages * 1000)/ioc->usg_calls));
  1554. #endif
  1555. return 0;
  1556. }
  1557. static int
  1558. sba_proc_bitmap_info(struct seq_file *m, void *p)
  1559. {
  1560. struct sba_device *sba_dev = sba_list;
  1561. struct ioc *ioc = &sba_dev->ioc[0]; /* FIXME: Multi-IOC support! */
  1562. seq_hex_dump(m, " ", DUMP_PREFIX_NONE, 32, 4, ioc->res_map,
  1563. ioc->res_size, false);
  1564. seq_putc(m, '\n');
  1565. return 0;
  1566. }
  1567. #endif /* CONFIG_PROC_FS */
  1568. static const struct parisc_device_id sba_tbl[] __initconst = {
  1569. { HPHW_IOA, HVERSION_REV_ANY_ID, ASTRO_RUNWAY_PORT, 0xb },
  1570. { HPHW_BCPORT, HVERSION_REV_ANY_ID, IKE_MERCED_PORT, 0xc },
  1571. { HPHW_BCPORT, HVERSION_REV_ANY_ID, REO_MERCED_PORT, 0xc },
  1572. { HPHW_BCPORT, HVERSION_REV_ANY_ID, REOG_MERCED_PORT, 0xc },
  1573. { HPHW_IOA, HVERSION_REV_ANY_ID, PLUTO_MCKINLEY_PORT, 0xc },
  1574. { 0, }
  1575. };
  1576. static int sba_driver_callback(struct parisc_device *);
  1577. static struct parisc_driver sba_driver __refdata = {
  1578. .name = MODULE_NAME,
  1579. .id_table = sba_tbl,
  1580. .probe = sba_driver_callback,
  1581. };
  1582. /*
  1583. ** Determine if sba should claim this chip (return 0) or not (return 1).
  1584. ** If so, initialize the chip and tell other partners in crime they
  1585. ** have work to do.
  1586. */
  1587. static int __init sba_driver_callback(struct parisc_device *dev)
  1588. {
  1589. struct sba_device *sba_dev;
  1590. u32 func_class;
  1591. int i;
  1592. char *version;
  1593. void __iomem *sba_addr = ioremap(dev->hpa.start, SBA_FUNC_SIZE);
  1594. #ifdef CONFIG_PROC_FS
  1595. struct proc_dir_entry *root;
  1596. #endif
  1597. sba_dump_ranges(sba_addr);
  1598. /* Read HW Rev First */
  1599. func_class = READ_REG(sba_addr + SBA_FCLASS);
  1600. if (IS_ASTRO(dev)) {
  1601. unsigned long fclass;
  1602. static char astro_rev[]="Astro ?.?";
  1603. /* Astro is broken...Read HW Rev First */
  1604. fclass = READ_REG(sba_addr);
  1605. astro_rev[6] = '1' + (char) (fclass & 0x7);
  1606. astro_rev[8] = '0' + (char) ((fclass & 0x18) >> 3);
  1607. version = astro_rev;
  1608. } else if (IS_IKE(dev)) {
  1609. static char ike_rev[] = "Ike rev ?";
  1610. ike_rev[8] = '0' + (char) (func_class & 0xff);
  1611. version = ike_rev;
  1612. } else if (IS_PLUTO(dev)) {
  1613. static char pluto_rev[]="Pluto ?.?";
  1614. pluto_rev[6] = '0' + (char) ((func_class & 0xf0) >> 4);
  1615. pluto_rev[8] = '0' + (char) (func_class & 0x0f);
  1616. version = pluto_rev;
  1617. } else {
  1618. static char reo_rev[] = "REO rev ?";
  1619. reo_rev[8] = '0' + (char) (func_class & 0xff);
  1620. version = reo_rev;
  1621. }
  1622. if (!global_ioc_cnt) {
  1623. global_ioc_cnt = count_parisc_driver(&sba_driver);
  1624. /* Astro and Pluto have one IOC per SBA */
  1625. if ((!IS_ASTRO(dev)) || (!IS_PLUTO(dev)))
  1626. global_ioc_cnt *= 2;
  1627. }
  1628. printk(KERN_INFO "%s found %s at 0x%llx\n",
  1629. MODULE_NAME, version, (unsigned long long)dev->hpa.start);
  1630. sba_dev = kzalloc(sizeof(struct sba_device), GFP_KERNEL);
  1631. if (!sba_dev) {
  1632. printk(KERN_ERR MODULE_NAME " - couldn't alloc sba_device\n");
  1633. return -ENOMEM;
  1634. }
  1635. parisc_set_drvdata(dev, sba_dev);
  1636. for(i=0; i<MAX_IOC; i++)
  1637. spin_lock_init(&(sba_dev->ioc[i].res_lock));
  1638. sba_dev->dev = dev;
  1639. sba_dev->hw_rev = func_class;
  1640. sba_dev->name = dev->name;
  1641. sba_dev->sba_hpa = sba_addr;
  1642. sba_get_pat_resources(sba_dev);
  1643. sba_hw_init(sba_dev);
  1644. sba_common_init(sba_dev);
  1645. hppa_dma_ops = &sba_ops;
  1646. #ifdef CONFIG_PROC_FS
  1647. switch (dev->id.hversion) {
  1648. case PLUTO_MCKINLEY_PORT:
  1649. root = proc_mckinley_root;
  1650. break;
  1651. case ASTRO_RUNWAY_PORT:
  1652. case IKE_MERCED_PORT:
  1653. default:
  1654. root = proc_runway_root;
  1655. break;
  1656. }
  1657. proc_create_single("sba_iommu", 0, root, sba_proc_info);
  1658. proc_create_single("sba_iommu-bitmap", 0, root, sba_proc_bitmap_info);
  1659. #endif
  1660. return 0;
  1661. }
  1662. /*
  1663. ** One time initialization to let the world know the SBA was found.
  1664. ** This is the only routine which is NOT static.
  1665. ** Must be called exactly once before pci_init().
  1666. */
  1667. void __init sba_init(void)
  1668. {
  1669. register_parisc_driver(&sba_driver);
  1670. }
  1671. /**
  1672. * sba_get_iommu - Assign the iommu pointer for the pci bus controller.
  1673. * @dev: The parisc device.
  1674. *
  1675. * Returns the appropriate IOMMU data for the given parisc PCI controller.
  1676. * This is cached and used later for PCI DMA Mapping.
  1677. */
  1678. void * sba_get_iommu(struct parisc_device *pci_hba)
  1679. {
  1680. struct parisc_device *sba_dev = parisc_parent(pci_hba);
  1681. struct sba_device *sba = dev_get_drvdata(&sba_dev->dev);
  1682. char t = sba_dev->id.hw_type;
  1683. int iocnum = (pci_hba->hw_path >> 3); /* rope # */
  1684. WARN_ON((t != HPHW_IOA) && (t != HPHW_BCPORT));
  1685. return &(sba->ioc[iocnum]);
  1686. }
  1687. /**
  1688. * sba_directed_lmmio - return first directed LMMIO range routed to rope
  1689. * @pa_dev: The parisc device.
  1690. * @r: resource PCI host controller wants start/end fields assigned.
  1691. *
  1692. * For the given parisc PCI controller, determine if any direct ranges
  1693. * are routed down the corresponding rope.
  1694. */
  1695. void sba_directed_lmmio(struct parisc_device *pci_hba, struct resource *r)
  1696. {
  1697. struct parisc_device *sba_dev = parisc_parent(pci_hba);
  1698. struct sba_device *sba = dev_get_drvdata(&sba_dev->dev);
  1699. char t = sba_dev->id.hw_type;
  1700. int i;
  1701. int rope = (pci_hba->hw_path & (ROPES_PER_IOC-1)); /* rope # */
  1702. BUG_ON((t!=HPHW_IOA) && (t!=HPHW_BCPORT));
  1703. r->start = r->end = 0;
  1704. /* Astro has 4 directed ranges. Not sure about Ike/Pluto/et al */
  1705. for (i=0; i<4; i++) {
  1706. int base, size;
  1707. void __iomem *reg = sba->sba_hpa + i*0x18;
  1708. base = READ_REG32(reg + LMMIO_DIRECT0_BASE);
  1709. if ((base & 1) == 0)
  1710. continue; /* not enabled */
  1711. size = READ_REG32(reg + LMMIO_DIRECT0_ROUTE);
  1712. if ((size & (ROPES_PER_IOC-1)) != rope)
  1713. continue; /* directed down different rope */
  1714. r->start = (base & ~1UL) | PCI_F_EXTEND;
  1715. size = ~ READ_REG32(reg + LMMIO_DIRECT0_MASK);
  1716. r->end = r->start + size;
  1717. r->flags = IORESOURCE_MEM;
  1718. }
  1719. }
  1720. /**
  1721. * sba_distributed_lmmio - return portion of distributed LMMIO range
  1722. * @pa_dev: The parisc device.
  1723. * @r: resource PCI host controller wants start/end fields assigned.
  1724. *
  1725. * For the given parisc PCI controller, return portion of distributed LMMIO
  1726. * range. The distributed LMMIO is always present and it's just a question
  1727. * of the base address and size of the range.
  1728. */
  1729. void sba_distributed_lmmio(struct parisc_device *pci_hba, struct resource *r )
  1730. {
  1731. struct parisc_device *sba_dev = parisc_parent(pci_hba);
  1732. struct sba_device *sba = dev_get_drvdata(&sba_dev->dev);
  1733. char t = sba_dev->id.hw_type;
  1734. int base, size;
  1735. int rope = (pci_hba->hw_path & (ROPES_PER_IOC-1)); /* rope # */
  1736. BUG_ON((t!=HPHW_IOA) && (t!=HPHW_BCPORT));
  1737. r->start = r->end = 0;
  1738. base = READ_REG32(sba->sba_hpa + LMMIO_DIST_BASE);
  1739. if ((base & 1) == 0) {
  1740. BUG(); /* Gah! Distr Range wasn't enabled! */
  1741. return;
  1742. }
  1743. r->start = (base & ~1UL) | PCI_F_EXTEND;
  1744. size = (~READ_REG32(sba->sba_hpa + LMMIO_DIST_MASK)) / ROPES_PER_IOC;
  1745. r->start += rope * (size + 1); /* adjust base for this rope */
  1746. r->end = r->start + size;
  1747. r->flags = IORESOURCE_MEM;
  1748. }