lba_pci.c 51 KB

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  1. // SPDX-License-Identifier: GPL-2.0-or-later
  2. /*
  3. **
  4. ** PCI Lower Bus Adapter (LBA) manager
  5. **
  6. ** (c) Copyright 1999,2000 Grant Grundler
  7. ** (c) Copyright 1999,2000 Hewlett-Packard Company
  8. **
  9. **
  10. **
  11. ** This module primarily provides access to PCI bus (config/IOport
  12. ** spaces) on platforms with an SBA/LBA chipset. A/B/C/J/L/N-class
  13. ** with 4 digit model numbers - eg C3000 (and A400...sigh).
  14. **
  15. ** LBA driver isn't as simple as the Dino driver because:
  16. ** (a) this chip has substantial bug fixes between revisions
  17. ** (Only one Dino bug has a software workaround :^( )
  18. ** (b) has more options which we don't (yet) support (DMA hints, OLARD)
  19. ** (c) IRQ support lives in the I/O SAPIC driver (not with PCI driver)
  20. ** (d) play nicely with both PAT and "Legacy" PA-RISC firmware (PDC).
  21. ** (dino only deals with "Legacy" PDC)
  22. **
  23. ** LBA driver passes the I/O SAPIC HPA to the I/O SAPIC driver.
  24. ** (I/O SAPIC is integratd in the LBA chip).
  25. **
  26. ** FIXME: Add support to SBA and LBA drivers for DMA hint sets
  27. ** FIXME: Add support for PCI card hot-plug (OLARD).
  28. */
  29. #include <linux/delay.h>
  30. #include <linux/types.h>
  31. #include <linux/kernel.h>
  32. #include <linux/spinlock.h>
  33. #include <linux/init.h> /* for __init */
  34. #include <linux/pci.h>
  35. #include <linux/ioport.h>
  36. #include <linux/slab.h>
  37. #include <asm/byteorder.h>
  38. #include <asm/pdc.h>
  39. #include <asm/pdcpat.h>
  40. #include <asm/page.h>
  41. #include <asm/ropes.h>
  42. #include <asm/hardware.h> /* for register_parisc_driver() stuff */
  43. #include <asm/parisc-device.h>
  44. #include <asm/io.h> /* read/write stuff */
  45. #include "iommu.h"
  46. #undef DEBUG_LBA /* general stuff */
  47. #undef DEBUG_LBA_PORT /* debug I/O Port access */
  48. #undef DEBUG_LBA_CFG /* debug Config Space Access (ie PCI Bus walk) */
  49. #undef DEBUG_LBA_PAT /* debug PCI Resource Mgt code - PDC PAT only */
  50. #undef FBB_SUPPORT /* Fast Back-Back xfers - NOT READY YET */
  51. #ifdef DEBUG_LBA
  52. #define DBG(x...) printk(x)
  53. #else
  54. #define DBG(x...)
  55. #endif
  56. #ifdef DEBUG_LBA_PORT
  57. #define DBG_PORT(x...) printk(x)
  58. #else
  59. #define DBG_PORT(x...)
  60. #endif
  61. #ifdef DEBUG_LBA_CFG
  62. #define DBG_CFG(x...) printk(x)
  63. #else
  64. #define DBG_CFG(x...)
  65. #endif
  66. #ifdef DEBUG_LBA_PAT
  67. #define DBG_PAT(x...) printk(x)
  68. #else
  69. #define DBG_PAT(x...)
  70. #endif
  71. /*
  72. ** Config accessor functions only pass in the 8-bit bus number and not
  73. ** the 8-bit "PCI Segment" number. Each LBA will be assigned a PCI bus
  74. ** number based on what firmware wrote into the scratch register.
  75. **
  76. ** The "secondary" bus number is set to this before calling
  77. ** pci_register_ops(). If any PPB's are present, the scan will
  78. ** discover them and update the "secondary" and "subordinate"
  79. ** fields in the pci_bus structure.
  80. **
  81. ** Changes in the configuration *may* result in a different
  82. ** bus number for each LBA depending on what firmware does.
  83. */
  84. #define MODULE_NAME "LBA"
  85. /* non-postable I/O port space, densely packed */
  86. #define LBA_PORT_BASE (PCI_F_EXTEND | 0xfee00000UL)
  87. static void __iomem *astro_iop_base __read_mostly;
  88. static u32 lba_t32;
  89. /* lba flags */
  90. #define LBA_FLAG_SKIP_PROBE 0x10
  91. #define LBA_SKIP_PROBE(d) ((d)->flags & LBA_FLAG_SKIP_PROBE)
  92. static inline struct lba_device *LBA_DEV(struct pci_hba_data *hba)
  93. {
  94. return container_of(hba, struct lba_device, hba);
  95. }
  96. /*
  97. ** Only allow 8 subsidiary busses per LBA
  98. ** Problem is the PCI bus numbering is globally shared.
  99. */
  100. #define LBA_MAX_NUM_BUSES 8
  101. /************************************
  102. * LBA register read and write support
  103. *
  104. * BE WARNED: register writes are posted.
  105. * (ie follow writes which must reach HW with a read)
  106. */
  107. #define READ_U8(addr) __raw_readb(addr)
  108. #define READ_U16(addr) __raw_readw(addr)
  109. #define READ_U32(addr) __raw_readl(addr)
  110. #define WRITE_U8(value, addr) __raw_writeb(value, addr)
  111. #define WRITE_U16(value, addr) __raw_writew(value, addr)
  112. #define WRITE_U32(value, addr) __raw_writel(value, addr)
  113. #define READ_REG8(addr) readb(addr)
  114. #define READ_REG16(addr) readw(addr)
  115. #define READ_REG32(addr) readl(addr)
  116. #define READ_REG64(addr) readq(addr)
  117. #define WRITE_REG8(value, addr) writeb(value, addr)
  118. #define WRITE_REG16(value, addr) writew(value, addr)
  119. #define WRITE_REG32(value, addr) writel(value, addr)
  120. #define LBA_CFG_TOK(bus,dfn) ((u32) ((bus)<<16 | (dfn)<<8))
  121. #define LBA_CFG_BUS(tok) ((u8) ((tok)>>16))
  122. #define LBA_CFG_DEV(tok) ((u8) ((tok)>>11) & 0x1f)
  123. #define LBA_CFG_FUNC(tok) ((u8) ((tok)>>8 ) & 0x7)
  124. /*
  125. ** Extract LBA (Rope) number from HPA
  126. ** REVISIT: 16 ropes for Stretch/Ike?
  127. */
  128. #define ROPES_PER_IOC 8
  129. #define LBA_NUM(x) ((((unsigned long) x) >> 13) & (ROPES_PER_IOC-1))
  130. static void
  131. lba_dump_res(struct resource *r, int d)
  132. {
  133. int i;
  134. if (NULL == r)
  135. return;
  136. printk(KERN_DEBUG "(%p)", r->parent);
  137. for (i = d; i ; --i) printk(" ");
  138. printk(KERN_DEBUG "%p [%lx,%lx]/%lx\n", r,
  139. (long)r->start, (long)r->end, r->flags);
  140. lba_dump_res(r->child, d+2);
  141. lba_dump_res(r->sibling, d);
  142. }
  143. /*
  144. ** LBA rev 2.0, 2.1, 2.2, and 3.0 bus walks require a complex
  145. ** workaround for cfg cycles:
  146. ** -- preserve LBA state
  147. ** -- prevent any DMA from occurring
  148. ** -- turn on smart mode
  149. ** -- probe with config writes before doing config reads
  150. ** -- check ERROR_STATUS
  151. ** -- clear ERROR_STATUS
  152. ** -- restore LBA state
  153. **
  154. ** The workaround is only used for device discovery.
  155. */
  156. static int lba_device_present(u8 bus, u8 dfn, struct lba_device *d)
  157. {
  158. u8 first_bus = d->hba.hba_bus->busn_res.start;
  159. u8 last_sub_bus = d->hba.hba_bus->busn_res.end;
  160. if ((bus < first_bus) ||
  161. (bus > last_sub_bus) ||
  162. ((bus - first_bus) >= LBA_MAX_NUM_BUSES)) {
  163. return 0;
  164. }
  165. return 1;
  166. }
  167. #define LBA_CFG_SETUP(d, tok) { \
  168. /* Save contents of error config register. */ \
  169. error_config = READ_REG32(d->hba.base_addr + LBA_ERROR_CONFIG); \
  170. \
  171. /* Save contents of status control register. */ \
  172. status_control = READ_REG32(d->hba.base_addr + LBA_STAT_CTL); \
  173. \
  174. /* For LBA rev 2.0, 2.1, 2.2, and 3.0, we must disable DMA \
  175. ** arbitration for full bus walks. \
  176. */ \
  177. /* Save contents of arb mask register. */ \
  178. arb_mask = READ_REG32(d->hba.base_addr + LBA_ARB_MASK); \
  179. \
  180. /* \
  181. * Turn off all device arbitration bits (i.e. everything \
  182. * except arbitration enable bit). \
  183. */ \
  184. WRITE_REG32(0x1, d->hba.base_addr + LBA_ARB_MASK); \
  185. \
  186. /* \
  187. * Set the smart mode bit so that master aborts don't cause \
  188. * LBA to go into PCI fatal mode (required). \
  189. */ \
  190. WRITE_REG32(error_config | LBA_SMART_MODE, d->hba.base_addr + LBA_ERROR_CONFIG); \
  191. }
  192. #define LBA_CFG_PROBE(d, tok) { \
  193. /* \
  194. * Setup Vendor ID write and read back the address register \
  195. * to make sure that LBA is the bus master. \
  196. */ \
  197. WRITE_REG32(tok | PCI_VENDOR_ID, (d)->hba.base_addr + LBA_PCI_CFG_ADDR);\
  198. /* \
  199. * Read address register to ensure that LBA is the bus master, \
  200. * which implies that DMA traffic has stopped when DMA arb is off. \
  201. */ \
  202. lba_t32 = READ_REG32((d)->hba.base_addr + LBA_PCI_CFG_ADDR); \
  203. /* \
  204. * Generate a cfg write cycle (will have no affect on \
  205. * Vendor ID register since read-only). \
  206. */ \
  207. WRITE_REG32(~0, (d)->hba.base_addr + LBA_PCI_CFG_DATA); \
  208. /* \
  209. * Make sure write has completed before proceeding further, \
  210. * i.e. before setting clear enable. \
  211. */ \
  212. lba_t32 = READ_REG32((d)->hba.base_addr + LBA_PCI_CFG_ADDR); \
  213. }
  214. /*
  215. * HPREVISIT:
  216. * -- Can't tell if config cycle got the error.
  217. *
  218. * OV bit is broken until rev 4.0, so can't use OV bit and
  219. * LBA_ERROR_LOG_ADDR to tell if error belongs to config cycle.
  220. *
  221. * As of rev 4.0, no longer need the error check.
  222. *
  223. * -- Even if we could tell, we still want to return -1
  224. * for **ANY** error (not just master abort).
  225. *
  226. * -- Only clear non-fatal errors (we don't want to bring
  227. * LBA out of pci-fatal mode).
  228. *
  229. * Actually, there is still a race in which
  230. * we could be clearing a fatal error. We will
  231. * live with this during our initial bus walk
  232. * until rev 4.0 (no driver activity during
  233. * initial bus walk). The initial bus walk
  234. * has race conditions concerning the use of
  235. * smart mode as well.
  236. */
  237. #define LBA_MASTER_ABORT_ERROR 0xc
  238. #define LBA_FATAL_ERROR 0x10
  239. #define LBA_CFG_MASTER_ABORT_CHECK(d, base, tok, error) { \
  240. u32 error_status = 0; \
  241. /* \
  242. * Set clear enable (CE) bit. Unset by HW when new \
  243. * errors are logged -- LBA HW ERS section 14.3.3). \
  244. */ \
  245. WRITE_REG32(status_control | CLEAR_ERRLOG_ENABLE, base + LBA_STAT_CTL); \
  246. error_status = READ_REG32(base + LBA_ERROR_STATUS); \
  247. if ((error_status & 0x1f) != 0) { \
  248. /* \
  249. * Fail the config read request. \
  250. */ \
  251. error = 1; \
  252. if ((error_status & LBA_FATAL_ERROR) == 0) { \
  253. /* \
  254. * Clear error status (if fatal bit not set) by setting \
  255. * clear error log bit (CL). \
  256. */ \
  257. WRITE_REG32(status_control | CLEAR_ERRLOG, base + LBA_STAT_CTL); \
  258. } \
  259. } \
  260. }
  261. #define LBA_CFG_TR4_ADDR_SETUP(d, addr) \
  262. WRITE_REG32(((addr) & ~3), (d)->hba.base_addr + LBA_PCI_CFG_ADDR);
  263. #define LBA_CFG_ADDR_SETUP(d, addr) { \
  264. WRITE_REG32(((addr) & ~3), (d)->hba.base_addr + LBA_PCI_CFG_ADDR); \
  265. /* \
  266. * Read address register to ensure that LBA is the bus master, \
  267. * which implies that DMA traffic has stopped when DMA arb is off. \
  268. */ \
  269. lba_t32 = READ_REG32((d)->hba.base_addr + LBA_PCI_CFG_ADDR); \
  270. }
  271. #define LBA_CFG_RESTORE(d, base) { \
  272. /* \
  273. * Restore status control register (turn off clear enable). \
  274. */ \
  275. WRITE_REG32(status_control, base + LBA_STAT_CTL); \
  276. /* \
  277. * Restore error config register (turn off smart mode). \
  278. */ \
  279. WRITE_REG32(error_config, base + LBA_ERROR_CONFIG); \
  280. /* \
  281. * Restore arb mask register (reenables DMA arbitration). \
  282. */ \
  283. WRITE_REG32(arb_mask, base + LBA_ARB_MASK); \
  284. }
  285. static unsigned int
  286. lba_rd_cfg(struct lba_device *d, u32 tok, u8 reg, u32 size)
  287. {
  288. u32 data = ~0U;
  289. int error = 0;
  290. u32 arb_mask = 0; /* used by LBA_CFG_SETUP/RESTORE */
  291. u32 error_config = 0; /* used by LBA_CFG_SETUP/RESTORE */
  292. u32 status_control = 0; /* used by LBA_CFG_SETUP/RESTORE */
  293. LBA_CFG_SETUP(d, tok);
  294. LBA_CFG_PROBE(d, tok);
  295. LBA_CFG_MASTER_ABORT_CHECK(d, d->hba.base_addr, tok, error);
  296. if (!error) {
  297. void __iomem *data_reg = d->hba.base_addr + LBA_PCI_CFG_DATA;
  298. LBA_CFG_ADDR_SETUP(d, tok | reg);
  299. switch (size) {
  300. case 1: data = (u32) READ_REG8(data_reg + (reg & 3)); break;
  301. case 2: data = (u32) READ_REG16(data_reg+ (reg & 2)); break;
  302. case 4: data = READ_REG32(data_reg); break;
  303. }
  304. }
  305. LBA_CFG_RESTORE(d, d->hba.base_addr);
  306. return(data);
  307. }
  308. static int elroy_cfg_read(struct pci_bus *bus, unsigned int devfn, int pos, int size, u32 *data)
  309. {
  310. struct lba_device *d = LBA_DEV(parisc_walk_tree(bus->bridge));
  311. u32 local_bus = (bus->parent == NULL) ? 0 : bus->busn_res.start;
  312. u32 tok = LBA_CFG_TOK(local_bus, devfn);
  313. void __iomem *data_reg = d->hba.base_addr + LBA_PCI_CFG_DATA;
  314. if ((pos > 255) || (devfn > 255))
  315. return -EINVAL;
  316. /* FIXME: B2K/C3600 workaround is always use old method... */
  317. /* if (!LBA_SKIP_PROBE(d)) */ {
  318. /* original - Generate config cycle on broken elroy
  319. with risk we will miss PCI bus errors. */
  320. *data = lba_rd_cfg(d, tok, pos, size);
  321. DBG_CFG("%s(%x+%2x) -> 0x%x (a)\n", __func__, tok, pos, *data);
  322. return 0;
  323. }
  324. if (LBA_SKIP_PROBE(d) && !lba_device_present(bus->busn_res.start, devfn, d)) {
  325. DBG_CFG("%s(%x+%2x) -> -1 (b)\n", __func__, tok, pos);
  326. /* either don't want to look or know device isn't present. */
  327. *data = ~0U;
  328. return(0);
  329. }
  330. /* Basic Algorithm
  331. ** Should only get here on fully working LBA rev.
  332. ** This is how simple the code should have been.
  333. */
  334. LBA_CFG_ADDR_SETUP(d, tok | pos);
  335. switch(size) {
  336. case 1: *data = READ_REG8 (data_reg + (pos & 3)); break;
  337. case 2: *data = READ_REG16(data_reg + (pos & 2)); break;
  338. case 4: *data = READ_REG32(data_reg); break;
  339. }
  340. DBG_CFG("%s(%x+%2x) -> 0x%x (c)\n", __func__, tok, pos, *data);
  341. return 0;
  342. }
  343. static void
  344. lba_wr_cfg(struct lba_device *d, u32 tok, u8 reg, u32 data, u32 size)
  345. {
  346. int error = 0;
  347. u32 arb_mask = 0;
  348. u32 error_config = 0;
  349. u32 status_control = 0;
  350. void __iomem *data_reg = d->hba.base_addr + LBA_PCI_CFG_DATA;
  351. LBA_CFG_SETUP(d, tok);
  352. LBA_CFG_ADDR_SETUP(d, tok | reg);
  353. switch (size) {
  354. case 1: WRITE_REG8 (data, data_reg + (reg & 3)); break;
  355. case 2: WRITE_REG16(data, data_reg + (reg & 2)); break;
  356. case 4: WRITE_REG32(data, data_reg); break;
  357. }
  358. LBA_CFG_MASTER_ABORT_CHECK(d, d->hba.base_addr, tok, error);
  359. LBA_CFG_RESTORE(d, d->hba.base_addr);
  360. }
  361. /*
  362. * LBA 4.0 config write code implements non-postable semantics
  363. * by doing a read of CONFIG ADDR after the write.
  364. */
  365. static int elroy_cfg_write(struct pci_bus *bus, unsigned int devfn, int pos, int size, u32 data)
  366. {
  367. struct lba_device *d = LBA_DEV(parisc_walk_tree(bus->bridge));
  368. u32 local_bus = (bus->parent == NULL) ? 0 : bus->busn_res.start;
  369. u32 tok = LBA_CFG_TOK(local_bus,devfn);
  370. if ((pos > 255) || (devfn > 255))
  371. return -EINVAL;
  372. if (!LBA_SKIP_PROBE(d)) {
  373. /* Original Workaround */
  374. lba_wr_cfg(d, tok, pos, (u32) data, size);
  375. DBG_CFG("%s(%x+%2x) = 0x%x (a)\n", __func__, tok, pos,data);
  376. return 0;
  377. }
  378. if (LBA_SKIP_PROBE(d) && (!lba_device_present(bus->busn_res.start, devfn, d))) {
  379. DBG_CFG("%s(%x+%2x) = 0x%x (b)\n", __func__, tok, pos,data);
  380. return 1; /* New Workaround */
  381. }
  382. DBG_CFG("%s(%x+%2x) = 0x%x (c)\n", __func__, tok, pos, data);
  383. /* Basic Algorithm */
  384. LBA_CFG_ADDR_SETUP(d, tok | pos);
  385. switch(size) {
  386. case 1: WRITE_REG8 (data, d->hba.base_addr + LBA_PCI_CFG_DATA + (pos & 3));
  387. break;
  388. case 2: WRITE_REG16(data, d->hba.base_addr + LBA_PCI_CFG_DATA + (pos & 2));
  389. break;
  390. case 4: WRITE_REG32(data, d->hba.base_addr + LBA_PCI_CFG_DATA);
  391. break;
  392. }
  393. /* flush posted write */
  394. lba_t32 = READ_REG32(d->hba.base_addr + LBA_PCI_CFG_ADDR);
  395. return 0;
  396. }
  397. static struct pci_ops elroy_cfg_ops = {
  398. .read = elroy_cfg_read,
  399. .write = elroy_cfg_write,
  400. };
  401. /*
  402. * The mercury_cfg_ops are slightly misnamed; they're also used for Elroy
  403. * TR4.0 as no additional bugs were found in this areea between Elroy and
  404. * Mercury
  405. */
  406. static int mercury_cfg_read(struct pci_bus *bus, unsigned int devfn, int pos, int size, u32 *data)
  407. {
  408. struct lba_device *d = LBA_DEV(parisc_walk_tree(bus->bridge));
  409. u32 local_bus = (bus->parent == NULL) ? 0 : bus->busn_res.start;
  410. u32 tok = LBA_CFG_TOK(local_bus, devfn);
  411. void __iomem *data_reg = d->hba.base_addr + LBA_PCI_CFG_DATA;
  412. if ((pos > 255) || (devfn > 255))
  413. return -EINVAL;
  414. LBA_CFG_TR4_ADDR_SETUP(d, tok | pos);
  415. switch(size) {
  416. case 1:
  417. *data = READ_REG8(data_reg + (pos & 3));
  418. break;
  419. case 2:
  420. *data = READ_REG16(data_reg + (pos & 2));
  421. break;
  422. case 4:
  423. *data = READ_REG32(data_reg); break;
  424. break;
  425. }
  426. DBG_CFG("mercury_cfg_read(%x+%2x) -> 0x%x\n", tok, pos, *data);
  427. return 0;
  428. }
  429. /*
  430. * LBA 4.0 config write code implements non-postable semantics
  431. * by doing a read of CONFIG ADDR after the write.
  432. */
  433. static int mercury_cfg_write(struct pci_bus *bus, unsigned int devfn, int pos, int size, u32 data)
  434. {
  435. struct lba_device *d = LBA_DEV(parisc_walk_tree(bus->bridge));
  436. void __iomem *data_reg = d->hba.base_addr + LBA_PCI_CFG_DATA;
  437. u32 local_bus = (bus->parent == NULL) ? 0 : bus->busn_res.start;
  438. u32 tok = LBA_CFG_TOK(local_bus,devfn);
  439. if ((pos > 255) || (devfn > 255))
  440. return -EINVAL;
  441. DBG_CFG("%s(%x+%2x) <- 0x%x (c)\n", __func__, tok, pos, data);
  442. LBA_CFG_TR4_ADDR_SETUP(d, tok | pos);
  443. switch(size) {
  444. case 1:
  445. WRITE_REG8 (data, data_reg + (pos & 3));
  446. break;
  447. case 2:
  448. WRITE_REG16(data, data_reg + (pos & 2));
  449. break;
  450. case 4:
  451. WRITE_REG32(data, data_reg);
  452. break;
  453. }
  454. /* flush posted write */
  455. lba_t32 = READ_U32(d->hba.base_addr + LBA_PCI_CFG_ADDR);
  456. return 0;
  457. }
  458. static struct pci_ops mercury_cfg_ops = {
  459. .read = mercury_cfg_read,
  460. .write = mercury_cfg_write,
  461. };
  462. static void
  463. lba_bios_init(void)
  464. {
  465. DBG(MODULE_NAME ": lba_bios_init\n");
  466. }
  467. #ifdef CONFIG_64BIT
  468. /*
  469. * truncate_pat_collision: Deal with overlaps or outright collisions
  470. * between PAT PDC reported ranges.
  471. *
  472. * Broken PA8800 firmware will report lmmio range that
  473. * overlaps with CPU HPA. Just truncate the lmmio range.
  474. *
  475. * BEWARE: conflicts with this lmmio range may be an
  476. * elmmio range which is pointing down another rope.
  477. *
  478. * FIXME: only deals with one collision per range...theoretically we
  479. * could have several. Supporting more than one collision will get messy.
  480. */
  481. static unsigned long
  482. truncate_pat_collision(struct resource *root, struct resource *new)
  483. {
  484. unsigned long start = new->start;
  485. unsigned long end = new->end;
  486. struct resource *tmp = root->child;
  487. if (end <= start || start < root->start || !tmp)
  488. return 0;
  489. /* find first overlap */
  490. while (tmp && tmp->end < start)
  491. tmp = tmp->sibling;
  492. /* no entries overlap */
  493. if (!tmp) return 0;
  494. /* found one that starts behind the new one
  495. ** Don't need to do anything.
  496. */
  497. if (tmp->start >= end) return 0;
  498. if (tmp->start <= start) {
  499. /* "front" of new one overlaps */
  500. new->start = tmp->end + 1;
  501. if (tmp->end >= end) {
  502. /* AACCKK! totally overlaps! drop this range. */
  503. return 1;
  504. }
  505. }
  506. if (tmp->end < end ) {
  507. /* "end" of new one overlaps */
  508. new->end = tmp->start - 1;
  509. }
  510. printk(KERN_WARNING "LBA: Truncating lmmio_space [%lx/%lx] "
  511. "to [%lx,%lx]\n",
  512. start, end,
  513. (long)new->start, (long)new->end );
  514. return 0; /* truncation successful */
  515. }
  516. /*
  517. * extend_lmmio_len: extend lmmio range to maximum length
  518. *
  519. * This is needed at least on C8000 systems to get the ATI FireGL card
  520. * working. On other systems we will currently not extend the lmmio space.
  521. */
  522. static unsigned long
  523. extend_lmmio_len(unsigned long start, unsigned long end, unsigned long lba_len)
  524. {
  525. struct resource *tmp;
  526. /* exit if not a C8000 */
  527. if (boot_cpu_data.cpu_type < mako)
  528. return end;
  529. pr_debug("LMMIO mismatch: PAT length = 0x%lx, MASK register = 0x%lx\n",
  530. end - start, lba_len);
  531. lba_len = min(lba_len+1, 256UL*1024*1024); /* limit to 256 MB */
  532. pr_debug("LBA: lmmio_space [0x%lx-0x%lx] - original\n", start, end);
  533. end += lba_len;
  534. if (end < start) /* fix overflow */
  535. end = -1ULL;
  536. pr_debug("LBA: lmmio_space [0x%lx-0x%lx] - current\n", start, end);
  537. /* first overlap */
  538. for (tmp = iomem_resource.child; tmp; tmp = tmp->sibling) {
  539. pr_debug("LBA: testing %pR\n", tmp);
  540. if (tmp->start == start)
  541. continue; /* ignore ourself */
  542. if (tmp->end < start)
  543. continue;
  544. if (tmp->start > end)
  545. continue;
  546. if (end >= tmp->start)
  547. end = tmp->start - 1;
  548. }
  549. pr_info("LBA: lmmio_space [0x%lx-0x%lx] - new\n", start, end);
  550. /* return new end */
  551. return end;
  552. }
  553. #else
  554. #define truncate_pat_collision(r,n) (0)
  555. #endif
  556. static void pcibios_allocate_bridge_resources(struct pci_dev *dev)
  557. {
  558. int idx;
  559. struct resource *r;
  560. for (idx = PCI_BRIDGE_RESOURCES; idx < PCI_NUM_RESOURCES; idx++) {
  561. r = &dev->resource[idx];
  562. if (!r->flags)
  563. continue;
  564. if (r->parent) /* Already allocated */
  565. continue;
  566. if (!r->start || pci_claim_bridge_resource(dev, idx) < 0) {
  567. /*
  568. * Something is wrong with the region.
  569. * Invalidate the resource to prevent
  570. * child resource allocations in this
  571. * range.
  572. */
  573. r->start = r->end = 0;
  574. r->flags = 0;
  575. }
  576. }
  577. }
  578. static void pcibios_allocate_bus_resources(struct pci_bus *bus)
  579. {
  580. struct pci_bus *child;
  581. /* Depth-First Search on bus tree */
  582. if (bus->self)
  583. pcibios_allocate_bridge_resources(bus->self);
  584. list_for_each_entry(child, &bus->children, node)
  585. pcibios_allocate_bus_resources(child);
  586. }
  587. /*
  588. ** The algorithm is generic code.
  589. ** But it needs to access local data structures to get the IRQ base.
  590. ** Could make this a "pci_fixup_irq(bus, region)" but not sure
  591. ** it's worth it.
  592. **
  593. ** Called by do_pci_scan_bus() immediately after each PCI bus is walked.
  594. ** Resources aren't allocated until recursive buswalk below HBA is completed.
  595. */
  596. static void
  597. lba_fixup_bus(struct pci_bus *bus)
  598. {
  599. struct pci_dev *dev;
  600. #ifdef FBB_SUPPORT
  601. u16 status;
  602. #endif
  603. struct lba_device *ldev = LBA_DEV(parisc_walk_tree(bus->bridge));
  604. DBG("lba_fixup_bus(0x%p) bus %d platform_data 0x%p\n",
  605. bus, (int)bus->busn_res.start, bus->bridge->platform_data);
  606. /*
  607. ** Properly Setup MMIO resources for this bus.
  608. ** pci_alloc_primary_bus() mangles this.
  609. */
  610. if (bus->parent) {
  611. /* PCI-PCI Bridge */
  612. pci_read_bridge_bases(bus);
  613. /* check and allocate bridge resources */
  614. pcibios_allocate_bus_resources(bus);
  615. } else {
  616. /* Host-PCI Bridge */
  617. int err;
  618. DBG("lba_fixup_bus() %s [%lx/%lx]/%lx\n",
  619. ldev->hba.io_space.name,
  620. ldev->hba.io_space.start, ldev->hba.io_space.end,
  621. ldev->hba.io_space.flags);
  622. DBG("lba_fixup_bus() %s [%lx/%lx]/%lx\n",
  623. ldev->hba.lmmio_space.name,
  624. ldev->hba.lmmio_space.start, ldev->hba.lmmio_space.end,
  625. ldev->hba.lmmio_space.flags);
  626. err = request_resource(&ioport_resource, &(ldev->hba.io_space));
  627. if (err < 0) {
  628. lba_dump_res(&ioport_resource, 2);
  629. BUG();
  630. }
  631. if (ldev->hba.elmmio_space.flags) {
  632. err = request_resource(&iomem_resource,
  633. &(ldev->hba.elmmio_space));
  634. if (err < 0) {
  635. printk("FAILED: lba_fixup_bus() request for "
  636. "elmmio_space [%lx/%lx]\n",
  637. (long)ldev->hba.elmmio_space.start,
  638. (long)ldev->hba.elmmio_space.end);
  639. /* lba_dump_res(&iomem_resource, 2); */
  640. /* BUG(); */
  641. }
  642. }
  643. if (ldev->hba.lmmio_space.flags) {
  644. err = request_resource(&iomem_resource, &(ldev->hba.lmmio_space));
  645. if (err < 0) {
  646. printk(KERN_ERR "FAILED: lba_fixup_bus() request for "
  647. "lmmio_space [%lx/%lx]\n",
  648. (long)ldev->hba.lmmio_space.start,
  649. (long)ldev->hba.lmmio_space.end);
  650. }
  651. }
  652. #ifdef CONFIG_64BIT
  653. /* GMMIO is distributed range. Every LBA/Rope gets part it. */
  654. if (ldev->hba.gmmio_space.flags) {
  655. err = request_resource(&iomem_resource, &(ldev->hba.gmmio_space));
  656. if (err < 0) {
  657. printk("FAILED: lba_fixup_bus() request for "
  658. "gmmio_space [%lx/%lx]\n",
  659. (long)ldev->hba.gmmio_space.start,
  660. (long)ldev->hba.gmmio_space.end);
  661. lba_dump_res(&iomem_resource, 2);
  662. BUG();
  663. }
  664. }
  665. #endif
  666. }
  667. list_for_each_entry(dev, &bus->devices, bus_list) {
  668. int i;
  669. DBG("lba_fixup_bus() %s\n", pci_name(dev));
  670. /* Virtualize Device/Bridge Resources. */
  671. for (i = 0; i < PCI_BRIDGE_RESOURCES; i++) {
  672. struct resource *res = &dev->resource[i];
  673. /* If resource not allocated - skip it */
  674. if (!res->start)
  675. continue;
  676. /*
  677. ** FIXME: this will result in whinging for devices
  678. ** that share expansion ROMs (think quad tulip), but
  679. ** isn't harmful.
  680. */
  681. pci_claim_resource(dev, i);
  682. }
  683. #ifdef FBB_SUPPORT
  684. /*
  685. ** If one device does not support FBB transfers,
  686. ** No one on the bus can be allowed to use them.
  687. */
  688. (void) pci_read_config_word(dev, PCI_STATUS, &status);
  689. bus->bridge_ctl &= ~(status & PCI_STATUS_FAST_BACK);
  690. #endif
  691. /*
  692. ** P2PB's have no IRQs. ignore them.
  693. */
  694. if ((dev->class >> 8) == PCI_CLASS_BRIDGE_PCI) {
  695. pcibios_init_bridge(dev);
  696. continue;
  697. }
  698. /* Adjust INTERRUPT_LINE for this dev */
  699. iosapic_fixup_irq(ldev->iosapic_obj, dev);
  700. }
  701. #ifdef FBB_SUPPORT
  702. /* FIXME/REVISIT - finish figuring out to set FBB on both
  703. ** pci_setup_bridge() clobbers PCI_BRIDGE_CONTROL.
  704. ** Can't fixup here anyway....garr...
  705. */
  706. if (fbb_enable) {
  707. if (bus->parent) {
  708. u8 control;
  709. /* enable on PPB */
  710. (void) pci_read_config_byte(bus->self, PCI_BRIDGE_CONTROL, &control);
  711. (void) pci_write_config_byte(bus->self, PCI_BRIDGE_CONTROL, control | PCI_STATUS_FAST_BACK);
  712. } else {
  713. /* enable on LBA */
  714. }
  715. fbb_enable = PCI_COMMAND_FAST_BACK;
  716. }
  717. /* Lastly enable FBB/PERR/SERR on all devices too */
  718. list_for_each_entry(dev, &bus->devices, bus_list) {
  719. (void) pci_read_config_word(dev, PCI_COMMAND, &status);
  720. status |= PCI_COMMAND_PARITY | PCI_COMMAND_SERR | fbb_enable;
  721. (void) pci_write_config_word(dev, PCI_COMMAND, status);
  722. }
  723. #endif
  724. }
  725. static struct pci_bios_ops lba_bios_ops = {
  726. .init = lba_bios_init,
  727. .fixup_bus = lba_fixup_bus,
  728. };
  729. /*******************************************************
  730. **
  731. ** LBA Sprockets "I/O Port" Space Accessor Functions
  732. **
  733. ** This set of accessor functions is intended for use with
  734. ** "legacy firmware" (ie Sprockets on Allegro/Forte boxes).
  735. **
  736. ** Many PCI devices don't require use of I/O port space (eg Tulip,
  737. ** NCR720) since they export the same registers to both MMIO and
  738. ** I/O port space. In general I/O port space is slower than
  739. ** MMIO since drivers are designed so PIO writes can be posted.
  740. **
  741. ********************************************************/
  742. #define LBA_PORT_IN(size, mask) \
  743. static u##size lba_astro_in##size (struct pci_hba_data *d, u16 addr) \
  744. { \
  745. u##size t; \
  746. t = READ_REG##size(astro_iop_base + addr); \
  747. DBG_PORT(" 0x%x\n", t); \
  748. return (t); \
  749. }
  750. LBA_PORT_IN( 8, 3)
  751. LBA_PORT_IN(16, 2)
  752. LBA_PORT_IN(32, 0)
  753. /*
  754. ** BUG X4107: Ordering broken - DMA RD return can bypass PIO WR
  755. **
  756. ** Fixed in Elroy 2.2. The READ_U32(..., LBA_FUNC_ID) below is
  757. ** guarantee non-postable completion semantics - not avoid X4107.
  758. ** The READ_U32 only guarantees the write data gets to elroy but
  759. ** out to the PCI bus. We can't read stuff from I/O port space
  760. ** since we don't know what has side-effects. Attempting to read
  761. ** from configuration space would be suicidal given the number of
  762. ** bugs in that elroy functionality.
  763. **
  764. ** Description:
  765. ** DMA read results can improperly pass PIO writes (X4107). The
  766. ** result of this bug is that if a processor modifies a location in
  767. ** memory after having issued PIO writes, the PIO writes are not
  768. ** guaranteed to be completed before a PCI device is allowed to see
  769. ** the modified data in a DMA read.
  770. **
  771. ** Note that IKE bug X3719 in TR1 IKEs will result in the same
  772. ** symptom.
  773. **
  774. ** Workaround:
  775. ** The workaround for this bug is to always follow a PIO write with
  776. ** a PIO read to the same bus before starting DMA on that PCI bus.
  777. **
  778. */
  779. #define LBA_PORT_OUT(size, mask) \
  780. static void lba_astro_out##size (struct pci_hba_data *d, u16 addr, u##size val) \
  781. { \
  782. DBG_PORT("%s(0x%p, 0x%x, 0x%x)\n", __func__, d, addr, val); \
  783. WRITE_REG##size(val, astro_iop_base + addr); \
  784. if (LBA_DEV(d)->hw_rev < 3) \
  785. lba_t32 = READ_U32(d->base_addr + LBA_FUNC_ID); \
  786. }
  787. LBA_PORT_OUT( 8, 3)
  788. LBA_PORT_OUT(16, 2)
  789. LBA_PORT_OUT(32, 0)
  790. static struct pci_port_ops lba_astro_port_ops = {
  791. .inb = lba_astro_in8,
  792. .inw = lba_astro_in16,
  793. .inl = lba_astro_in32,
  794. .outb = lba_astro_out8,
  795. .outw = lba_astro_out16,
  796. .outl = lba_astro_out32
  797. };
  798. #ifdef CONFIG_64BIT
  799. #define PIOP_TO_GMMIO(lba, addr) \
  800. ((lba)->iop_base + (((addr)&0xFFFC)<<10) + ((addr)&3))
  801. /*******************************************************
  802. **
  803. ** LBA PAT "I/O Port" Space Accessor Functions
  804. **
  805. ** This set of accessor functions is intended for use with
  806. ** "PAT PDC" firmware (ie Prelude/Rhapsody/Piranha boxes).
  807. **
  808. ** This uses the PIOP space located in the first 64MB of GMMIO.
  809. ** Each rope gets a full 64*KB* (ie 4 bytes per page) this way.
  810. ** bits 1:0 stay the same. bits 15:2 become 25:12.
  811. ** Then add the base and we can generate an I/O Port cycle.
  812. ********************************************************/
  813. #undef LBA_PORT_IN
  814. #define LBA_PORT_IN(size, mask) \
  815. static u##size lba_pat_in##size (struct pci_hba_data *l, u16 addr) \
  816. { \
  817. u##size t; \
  818. DBG_PORT("%s(0x%p, 0x%x) ->", __func__, l, addr); \
  819. t = READ_REG##size(PIOP_TO_GMMIO(LBA_DEV(l), addr)); \
  820. DBG_PORT(" 0x%x\n", t); \
  821. return (t); \
  822. }
  823. LBA_PORT_IN( 8, 3)
  824. LBA_PORT_IN(16, 2)
  825. LBA_PORT_IN(32, 0)
  826. #undef LBA_PORT_OUT
  827. #define LBA_PORT_OUT(size, mask) \
  828. static void lba_pat_out##size (struct pci_hba_data *l, u16 addr, u##size val) \
  829. { \
  830. void __iomem *where = PIOP_TO_GMMIO(LBA_DEV(l), addr); \
  831. DBG_PORT("%s(0x%p, 0x%x, 0x%x)\n", __func__, l, addr, val); \
  832. WRITE_REG##size(val, where); \
  833. /* flush the I/O down to the elroy at least */ \
  834. lba_t32 = READ_U32(l->base_addr + LBA_FUNC_ID); \
  835. }
  836. LBA_PORT_OUT( 8, 3)
  837. LBA_PORT_OUT(16, 2)
  838. LBA_PORT_OUT(32, 0)
  839. static struct pci_port_ops lba_pat_port_ops = {
  840. .inb = lba_pat_in8,
  841. .inw = lba_pat_in16,
  842. .inl = lba_pat_in32,
  843. .outb = lba_pat_out8,
  844. .outw = lba_pat_out16,
  845. .outl = lba_pat_out32
  846. };
  847. /*
  848. ** make range information from PDC available to PCI subsystem.
  849. ** We make the PDC call here in order to get the PCI bus range
  850. ** numbers. The rest will get forwarded in pcibios_fixup_bus().
  851. ** We don't have a struct pci_bus assigned to us yet.
  852. */
  853. static void
  854. lba_pat_resources(struct parisc_device *pa_dev, struct lba_device *lba_dev)
  855. {
  856. unsigned long bytecnt;
  857. long io_count;
  858. long status; /* PDC return status */
  859. long pa_count;
  860. pdc_pat_cell_mod_maddr_block_t *pa_pdc_cell; /* PA_VIEW */
  861. pdc_pat_cell_mod_maddr_block_t *io_pdc_cell; /* IO_VIEW */
  862. int i;
  863. pa_pdc_cell = kzalloc(sizeof(pdc_pat_cell_mod_maddr_block_t), GFP_KERNEL);
  864. if (!pa_pdc_cell)
  865. return;
  866. io_pdc_cell = kzalloc(sizeof(pdc_pat_cell_mod_maddr_block_t), GFP_KERNEL);
  867. if (!io_pdc_cell) {
  868. kfree(pa_pdc_cell);
  869. return;
  870. }
  871. /* return cell module (IO view) */
  872. status = pdc_pat_cell_module(&bytecnt, pa_dev->pcell_loc, pa_dev->mod_index,
  873. PA_VIEW, pa_pdc_cell);
  874. pa_count = pa_pdc_cell->mod[1];
  875. status |= pdc_pat_cell_module(&bytecnt, pa_dev->pcell_loc, pa_dev->mod_index,
  876. IO_VIEW, io_pdc_cell);
  877. io_count = io_pdc_cell->mod[1];
  878. /* We've already done this once for device discovery...*/
  879. if (status != PDC_OK) {
  880. panic("pdc_pat_cell_module() call failed for LBA!\n");
  881. }
  882. if (PAT_GET_ENTITY(pa_pdc_cell->mod_info) != PAT_ENTITY_LBA) {
  883. panic("pdc_pat_cell_module() entity returned != PAT_ENTITY_LBA!\n");
  884. }
  885. /*
  886. ** Inspect the resources PAT tells us about
  887. */
  888. for (i = 0; i < pa_count; i++) {
  889. struct {
  890. unsigned long type;
  891. unsigned long start;
  892. unsigned long end; /* aka finish */
  893. } *p, *io;
  894. struct resource *r;
  895. p = (void *) &(pa_pdc_cell->mod[2+i*3]);
  896. io = (void *) &(io_pdc_cell->mod[2+i*3]);
  897. /* Convert the PAT range data to PCI "struct resource" */
  898. switch(p->type & 0xff) {
  899. case PAT_PBNUM:
  900. lba_dev->hba.bus_num.start = p->start;
  901. lba_dev->hba.bus_num.end = p->end;
  902. lba_dev->hba.bus_num.flags = IORESOURCE_BUS;
  903. break;
  904. case PAT_LMMIO:
  905. /* used to fix up pre-initialized MEM BARs */
  906. if (!lba_dev->hba.lmmio_space.flags) {
  907. unsigned long lba_len;
  908. lba_len = ~READ_REG32(lba_dev->hba.base_addr
  909. + LBA_LMMIO_MASK);
  910. if ((p->end - p->start) != lba_len)
  911. p->end = extend_lmmio_len(p->start,
  912. p->end, lba_len);
  913. sprintf(lba_dev->hba.lmmio_name,
  914. "PCI%02x LMMIO",
  915. (int)lba_dev->hba.bus_num.start);
  916. lba_dev->hba.lmmio_space_offset = p->start -
  917. io->start;
  918. r = &lba_dev->hba.lmmio_space;
  919. r->name = lba_dev->hba.lmmio_name;
  920. } else if (!lba_dev->hba.elmmio_space.flags) {
  921. sprintf(lba_dev->hba.elmmio_name,
  922. "PCI%02x ELMMIO",
  923. (int)lba_dev->hba.bus_num.start);
  924. r = &lba_dev->hba.elmmio_space;
  925. r->name = lba_dev->hba.elmmio_name;
  926. } else {
  927. printk(KERN_WARNING MODULE_NAME
  928. " only supports 2 LMMIO resources!\n");
  929. break;
  930. }
  931. r->start = p->start;
  932. r->end = p->end;
  933. r->flags = IORESOURCE_MEM;
  934. r->parent = r->sibling = r->child = NULL;
  935. break;
  936. case PAT_GMMIO:
  937. /* MMIO space > 4GB phys addr; for 64-bit BAR */
  938. sprintf(lba_dev->hba.gmmio_name, "PCI%02x GMMIO",
  939. (int)lba_dev->hba.bus_num.start);
  940. r = &lba_dev->hba.gmmio_space;
  941. r->name = lba_dev->hba.gmmio_name;
  942. r->start = p->start;
  943. r->end = p->end;
  944. r->flags = IORESOURCE_MEM;
  945. r->parent = r->sibling = r->child = NULL;
  946. break;
  947. case PAT_NPIOP:
  948. printk(KERN_WARNING MODULE_NAME
  949. " range[%d] : ignoring NPIOP (0x%lx)\n",
  950. i, p->start);
  951. break;
  952. case PAT_PIOP:
  953. /*
  954. ** Postable I/O port space is per PCI host adapter.
  955. ** base of 64MB PIOP region
  956. */
  957. lba_dev->iop_base = ioremap(p->start, 64 * 1024 * 1024);
  958. sprintf(lba_dev->hba.io_name, "PCI%02x Ports",
  959. (int)lba_dev->hba.bus_num.start);
  960. r = &lba_dev->hba.io_space;
  961. r->name = lba_dev->hba.io_name;
  962. r->start = HBA_PORT_BASE(lba_dev->hba.hba_num);
  963. r->end = r->start + HBA_PORT_SPACE_SIZE - 1;
  964. r->flags = IORESOURCE_IO;
  965. r->parent = r->sibling = r->child = NULL;
  966. break;
  967. default:
  968. printk(KERN_WARNING MODULE_NAME
  969. " range[%d] : unknown pat range type (0x%lx)\n",
  970. i, p->type & 0xff);
  971. break;
  972. }
  973. }
  974. kfree(pa_pdc_cell);
  975. kfree(io_pdc_cell);
  976. }
  977. #else
  978. /* keep compiler from complaining about missing declarations */
  979. #define lba_pat_port_ops lba_astro_port_ops
  980. #define lba_pat_resources(pa_dev, lba_dev)
  981. #endif /* CONFIG_64BIT */
  982. extern void sba_distributed_lmmio(struct parisc_device *, struct resource *);
  983. extern void sba_directed_lmmio(struct parisc_device *, struct resource *);
  984. static void
  985. lba_legacy_resources(struct parisc_device *pa_dev, struct lba_device *lba_dev)
  986. {
  987. struct resource *r;
  988. int lba_num;
  989. lba_dev->hba.lmmio_space_offset = PCI_F_EXTEND;
  990. /*
  991. ** With "legacy" firmware, the lowest byte of FW_SCRATCH
  992. ** represents bus->secondary and the second byte represents
  993. ** bus->subsidiary (i.e. highest PPB programmed by firmware).
  994. ** PCI bus walk *should* end up with the same result.
  995. ** FIXME: But we don't have sanity checks in PCI or LBA.
  996. */
  997. lba_num = READ_REG32(lba_dev->hba.base_addr + LBA_FW_SCRATCH);
  998. r = &(lba_dev->hba.bus_num);
  999. r->name = "LBA PCI Busses";
  1000. r->start = lba_num & 0xff;
  1001. r->end = (lba_num>>8) & 0xff;
  1002. r->flags = IORESOURCE_BUS;
  1003. /* Set up local PCI Bus resources - we don't need them for
  1004. ** Legacy boxes but it's nice to see in /proc/iomem.
  1005. */
  1006. r = &(lba_dev->hba.lmmio_space);
  1007. sprintf(lba_dev->hba.lmmio_name, "PCI%02x LMMIO",
  1008. (int)lba_dev->hba.bus_num.start);
  1009. r->name = lba_dev->hba.lmmio_name;
  1010. #if 1
  1011. /* We want the CPU -> IO routing of addresses.
  1012. * The SBA BASE/MASK registers control CPU -> IO routing.
  1013. * Ask SBA what is routed to this rope/LBA.
  1014. */
  1015. sba_distributed_lmmio(pa_dev, r);
  1016. #else
  1017. /*
  1018. * The LBA BASE/MASK registers control IO -> System routing.
  1019. *
  1020. * The following code works but doesn't get us what we want.
  1021. * Well, only because firmware (v5.0) on C3000 doesn't program
  1022. * the LBA BASE/MASE registers to be the exact inverse of
  1023. * the corresponding SBA registers. Other Astro/Pluto
  1024. * based platform firmware may do it right.
  1025. *
  1026. * Should someone want to mess with MSI, they may need to
  1027. * reprogram LBA BASE/MASK registers. Thus preserve the code
  1028. * below until MSI is known to work on C3000/A500/N4000/RP3440.
  1029. *
  1030. * Using the code below, /proc/iomem shows:
  1031. * ...
  1032. * f0000000-f0ffffff : PCI00 LMMIO
  1033. * f05d0000-f05d0000 : lcd_data
  1034. * f05d0008-f05d0008 : lcd_cmd
  1035. * f1000000-f1ffffff : PCI01 LMMIO
  1036. * f4000000-f4ffffff : PCI02 LMMIO
  1037. * f4000000-f4001fff : sym53c8xx
  1038. * f4002000-f4003fff : sym53c8xx
  1039. * f4004000-f40043ff : sym53c8xx
  1040. * f4005000-f40053ff : sym53c8xx
  1041. * f4007000-f4007fff : ohci_hcd
  1042. * f4008000-f40083ff : tulip
  1043. * f6000000-f6ffffff : PCI03 LMMIO
  1044. * f8000000-fbffffff : PCI00 ELMMIO
  1045. * fa100000-fa4fffff : stifb mmio
  1046. * fb000000-fb1fffff : stifb fb
  1047. *
  1048. * But everything listed under PCI02 actually lives under PCI00.
  1049. * This is clearly wrong.
  1050. *
  1051. * Asking SBA how things are routed tells the correct story:
  1052. * LMMIO_BASE/MASK/ROUTE f4000001 fc000000 00000000
  1053. * DIR0_BASE/MASK/ROUTE fa000001 fe000000 00000006
  1054. * DIR1_BASE/MASK/ROUTE f9000001 ff000000 00000004
  1055. * DIR2_BASE/MASK/ROUTE f0000000 fc000000 00000000
  1056. * DIR3_BASE/MASK/ROUTE f0000000 fc000000 00000000
  1057. *
  1058. * Which looks like this in /proc/iomem:
  1059. * f4000000-f47fffff : PCI00 LMMIO
  1060. * f4000000-f4001fff : sym53c8xx
  1061. * ...[deteled core devices - same as above]...
  1062. * f4008000-f40083ff : tulip
  1063. * f4800000-f4ffffff : PCI01 LMMIO
  1064. * f6000000-f67fffff : PCI02 LMMIO
  1065. * f7000000-f77fffff : PCI03 LMMIO
  1066. * f9000000-f9ffffff : PCI02 ELMMIO
  1067. * fa000000-fbffffff : PCI03 ELMMIO
  1068. * fa100000-fa4fffff : stifb mmio
  1069. * fb000000-fb1fffff : stifb fb
  1070. *
  1071. * ie all Built-in core are under now correctly under PCI00.
  1072. * The "PCI02 ELMMIO" directed range is for:
  1073. * +-[02]---03.0 3Dfx Interactive, Inc. Voodoo 2
  1074. *
  1075. * All is well now.
  1076. */
  1077. r->start = READ_REG32(lba_dev->hba.base_addr + LBA_LMMIO_BASE);
  1078. if (r->start & 1) {
  1079. unsigned long rsize;
  1080. r->flags = IORESOURCE_MEM;
  1081. /* mmio_mask also clears Enable bit */
  1082. r->start &= mmio_mask;
  1083. r->start = PCI_HOST_ADDR(&lba_dev->hba, r->start);
  1084. rsize = ~ READ_REG32(lba_dev->hba.base_addr + LBA_LMMIO_MASK);
  1085. /*
  1086. ** Each rope only gets part of the distributed range.
  1087. ** Adjust "window" for this rope.
  1088. */
  1089. rsize /= ROPES_PER_IOC;
  1090. r->start += (rsize + 1) * LBA_NUM(pa_dev->hpa.start);
  1091. r->end = r->start + rsize;
  1092. } else {
  1093. r->end = r->start = 0; /* Not enabled. */
  1094. }
  1095. #endif
  1096. /*
  1097. ** "Directed" ranges are used when the "distributed range" isn't
  1098. ** sufficient for all devices below a given LBA. Typically devices
  1099. ** like graphics cards or X25 may need a directed range when the
  1100. ** bus has multiple slots (ie multiple devices) or the device
  1101. ** needs more than the typical 4 or 8MB a distributed range offers.
  1102. **
  1103. ** The main reason for ignoring it now frigging complications.
  1104. ** Directed ranges may overlap (and have precedence) over
  1105. ** distributed ranges. Or a distributed range assigned to a unused
  1106. ** rope may be used by a directed range on a different rope.
  1107. ** Support for graphics devices may require fixing this
  1108. ** since they may be assigned a directed range which overlaps
  1109. ** an existing (but unused portion of) distributed range.
  1110. */
  1111. r = &(lba_dev->hba.elmmio_space);
  1112. sprintf(lba_dev->hba.elmmio_name, "PCI%02x ELMMIO",
  1113. (int)lba_dev->hba.bus_num.start);
  1114. r->name = lba_dev->hba.elmmio_name;
  1115. #if 1
  1116. /* See comment which precedes call to sba_directed_lmmio() */
  1117. sba_directed_lmmio(pa_dev, r);
  1118. #else
  1119. r->start = READ_REG32(lba_dev->hba.base_addr + LBA_ELMMIO_BASE);
  1120. if (r->start & 1) {
  1121. unsigned long rsize;
  1122. r->flags = IORESOURCE_MEM;
  1123. /* mmio_mask also clears Enable bit */
  1124. r->start &= mmio_mask;
  1125. r->start = PCI_HOST_ADDR(&lba_dev->hba, r->start);
  1126. rsize = READ_REG32(lba_dev->hba.base_addr + LBA_ELMMIO_MASK);
  1127. r->end = r->start + ~rsize;
  1128. }
  1129. #endif
  1130. r = &(lba_dev->hba.io_space);
  1131. sprintf(lba_dev->hba.io_name, "PCI%02x Ports",
  1132. (int)lba_dev->hba.bus_num.start);
  1133. r->name = lba_dev->hba.io_name;
  1134. r->flags = IORESOURCE_IO;
  1135. r->start = READ_REG32(lba_dev->hba.base_addr + LBA_IOS_BASE) & ~1L;
  1136. r->end = r->start + (READ_REG32(lba_dev->hba.base_addr + LBA_IOS_MASK) ^ (HBA_PORT_SPACE_SIZE - 1));
  1137. /* Virtualize the I/O Port space ranges */
  1138. lba_num = HBA_PORT_BASE(lba_dev->hba.hba_num);
  1139. r->start |= lba_num;
  1140. r->end |= lba_num;
  1141. }
  1142. /**************************************************************************
  1143. **
  1144. ** LBA initialization code (HW and SW)
  1145. **
  1146. ** o identify LBA chip itself
  1147. ** o initialize LBA chip modes (HardFail)
  1148. ** o FIXME: initialize DMA hints for reasonable defaults
  1149. ** o enable configuration functions
  1150. ** o call pci_register_ops() to discover devs (fixup/fixup_bus get invoked)
  1151. **
  1152. **************************************************************************/
  1153. static int __init
  1154. lba_hw_init(struct lba_device *d)
  1155. {
  1156. u32 stat;
  1157. u32 bus_reset; /* PDC_PAT_BUG */
  1158. #if 0
  1159. printk(KERN_DEBUG "LBA %lx STAT_CTL %Lx ERROR_CFG %Lx STATUS %Lx DMA_CTL %Lx\n",
  1160. d->hba.base_addr,
  1161. READ_REG64(d->hba.base_addr + LBA_STAT_CTL),
  1162. READ_REG64(d->hba.base_addr + LBA_ERROR_CONFIG),
  1163. READ_REG64(d->hba.base_addr + LBA_ERROR_STATUS),
  1164. READ_REG64(d->hba.base_addr + LBA_DMA_CTL) );
  1165. printk(KERN_DEBUG " ARB mask %Lx pri %Lx mode %Lx mtlt %Lx\n",
  1166. READ_REG64(d->hba.base_addr + LBA_ARB_MASK),
  1167. READ_REG64(d->hba.base_addr + LBA_ARB_PRI),
  1168. READ_REG64(d->hba.base_addr + LBA_ARB_MODE),
  1169. READ_REG64(d->hba.base_addr + LBA_ARB_MTLT) );
  1170. printk(KERN_DEBUG " HINT cfg 0x%Lx\n",
  1171. READ_REG64(d->hba.base_addr + LBA_HINT_CFG));
  1172. printk(KERN_DEBUG " HINT reg ");
  1173. { int i;
  1174. for (i=LBA_HINT_BASE; i< (14*8 + LBA_HINT_BASE); i+=8)
  1175. printk(" %Lx", READ_REG64(d->hba.base_addr + i));
  1176. }
  1177. printk("\n");
  1178. #endif /* DEBUG_LBA_PAT */
  1179. #ifdef CONFIG_64BIT
  1180. /*
  1181. * FIXME add support for PDC_PAT_IO "Get slot status" - OLAR support
  1182. * Only N-Class and up can really make use of Get slot status.
  1183. * maybe L-class too but I've never played with it there.
  1184. */
  1185. #endif
  1186. /* PDC_PAT_BUG: exhibited in rev 40.48 on L2000 */
  1187. bus_reset = READ_REG32(d->hba.base_addr + LBA_STAT_CTL + 4) & 1;
  1188. if (bus_reset) {
  1189. printk(KERN_DEBUG "NOTICE: PCI bus reset still asserted! (clearing)\n");
  1190. }
  1191. stat = READ_REG32(d->hba.base_addr + LBA_ERROR_CONFIG);
  1192. if (stat & LBA_SMART_MODE) {
  1193. printk(KERN_DEBUG "NOTICE: LBA in SMART mode! (cleared)\n");
  1194. stat &= ~LBA_SMART_MODE;
  1195. WRITE_REG32(stat, d->hba.base_addr + LBA_ERROR_CONFIG);
  1196. }
  1197. /*
  1198. * Hard Fail vs. Soft Fail on PCI "Master Abort".
  1199. *
  1200. * "Master Abort" means the MMIO transaction timed out - usually due to
  1201. * the device not responding to an MMIO read. We would like HF to be
  1202. * enabled to find driver problems, though it means the system will
  1203. * crash with a HPMC.
  1204. *
  1205. * In SoftFail mode "~0L" is returned as a result of a timeout on the
  1206. * pci bus. This is like how PCI busses on x86 and most other
  1207. * architectures behave. In order to increase compatibility with
  1208. * existing (x86) PCI hardware and existing Linux drivers we enable
  1209. * Soft Faul mode on PA-RISC now too.
  1210. */
  1211. stat = READ_REG32(d->hba.base_addr + LBA_STAT_CTL);
  1212. #if defined(ENABLE_HARDFAIL)
  1213. WRITE_REG32(stat | HF_ENABLE, d->hba.base_addr + LBA_STAT_CTL);
  1214. #else
  1215. WRITE_REG32(stat & ~HF_ENABLE, d->hba.base_addr + LBA_STAT_CTL);
  1216. #endif
  1217. /*
  1218. ** Writing a zero to STAT_CTL.rf (bit 0) will clear reset signal
  1219. ** if it's not already set. If we just cleared the PCI Bus Reset
  1220. ** signal, wait a bit for the PCI devices to recover and setup.
  1221. */
  1222. if (bus_reset)
  1223. mdelay(pci_post_reset_delay);
  1224. if (0 == READ_REG32(d->hba.base_addr + LBA_ARB_MASK)) {
  1225. /*
  1226. ** PDC_PAT_BUG: PDC rev 40.48 on L2000.
  1227. ** B2000/C3600/J6000 also have this problem?
  1228. **
  1229. ** Elroys with hot pluggable slots don't get configured
  1230. ** correctly if the slot is empty. ARB_MASK is set to 0
  1231. ** and we can't master transactions on the bus if it's
  1232. ** not at least one. 0x3 enables elroy and first slot.
  1233. */
  1234. printk(KERN_DEBUG "NOTICE: Enabling PCI Arbitration\n");
  1235. WRITE_REG32(0x3, d->hba.base_addr + LBA_ARB_MASK);
  1236. }
  1237. /*
  1238. ** FIXME: Hint registers are programmed with default hint
  1239. ** values by firmware. Hints should be sane even if we
  1240. ** can't reprogram them the way drivers want.
  1241. */
  1242. return 0;
  1243. }
  1244. /*
  1245. * Unfortunately, when firmware numbers busses, it doesn't take into account
  1246. * Cardbus bridges. So we have to renumber the busses to suit ourselves.
  1247. * Elroy/Mercury don't actually know what bus number they're attached to;
  1248. * we use bus 0 to indicate the directly attached bus and any other bus
  1249. * number will be taken care of by the PCI-PCI bridge.
  1250. */
  1251. static unsigned int lba_next_bus = 0;
  1252. /*
  1253. * Determine if lba should claim this chip (return 0) or not (return 1).
  1254. * If so, initialize the chip and tell other partners in crime they
  1255. * have work to do.
  1256. */
  1257. static int __init
  1258. lba_driver_probe(struct parisc_device *dev)
  1259. {
  1260. struct lba_device *lba_dev;
  1261. LIST_HEAD(resources);
  1262. struct pci_bus *lba_bus;
  1263. struct pci_ops *cfg_ops;
  1264. u32 func_class;
  1265. void *tmp_obj;
  1266. char *version;
  1267. void __iomem *addr = ioremap(dev->hpa.start, 4096);
  1268. int max;
  1269. /* Read HW Rev First */
  1270. func_class = READ_REG32(addr + LBA_FCLASS);
  1271. if (IS_ELROY(dev)) {
  1272. func_class &= 0xf;
  1273. switch (func_class) {
  1274. case 0: version = "TR1.0"; break;
  1275. case 1: version = "TR2.0"; break;
  1276. case 2: version = "TR2.1"; break;
  1277. case 3: version = "TR2.2"; break;
  1278. case 4: version = "TR3.0"; break;
  1279. case 5: version = "TR4.0"; break;
  1280. default: version = "TR4+";
  1281. }
  1282. printk(KERN_INFO "Elroy version %s (0x%x) found at 0x%lx\n",
  1283. version, func_class & 0xf, (long)dev->hpa.start);
  1284. if (func_class < 2) {
  1285. printk(KERN_WARNING "Can't support LBA older than "
  1286. "TR2.1 - continuing under adversity.\n");
  1287. }
  1288. #if 0
  1289. /* Elroy TR4.0 should work with simple algorithm.
  1290. But it doesn't. Still missing something. *sigh*
  1291. */
  1292. if (func_class > 4) {
  1293. cfg_ops = &mercury_cfg_ops;
  1294. } else
  1295. #endif
  1296. {
  1297. cfg_ops = &elroy_cfg_ops;
  1298. }
  1299. } else if (IS_MERCURY(dev) || IS_QUICKSILVER(dev)) {
  1300. int major, minor;
  1301. func_class &= 0xff;
  1302. major = func_class >> 4, minor = func_class & 0xf;
  1303. /* We could use one printk for both Elroy and Mercury,
  1304. * but for the mask for func_class.
  1305. */
  1306. printk(KERN_INFO "%s version TR%d.%d (0x%x) found at 0x%lx\n",
  1307. IS_MERCURY(dev) ? "Mercury" : "Quicksilver", major,
  1308. minor, func_class, (long)dev->hpa.start);
  1309. cfg_ops = &mercury_cfg_ops;
  1310. } else {
  1311. printk(KERN_ERR "Unknown LBA found at 0x%lx\n",
  1312. (long)dev->hpa.start);
  1313. return -ENODEV;
  1314. }
  1315. /* Tell I/O SAPIC driver we have a IRQ handler/region. */
  1316. tmp_obj = iosapic_register(dev->hpa.start + LBA_IOSAPIC_BASE);
  1317. /* NOTE: PCI devices (e.g. 103c:1005 graphics card) which don't
  1318. ** have an IRT entry will get NULL back from iosapic code.
  1319. */
  1320. lba_dev = kzalloc(sizeof(struct lba_device), GFP_KERNEL);
  1321. if (!lba_dev) {
  1322. printk(KERN_ERR "lba_init_chip - couldn't alloc lba_device\n");
  1323. return(1);
  1324. }
  1325. /* ---------- First : initialize data we already have --------- */
  1326. lba_dev->hw_rev = func_class;
  1327. lba_dev->hba.base_addr = addr;
  1328. lba_dev->hba.dev = dev;
  1329. lba_dev->iosapic_obj = tmp_obj; /* save interrupt handle */
  1330. lba_dev->hba.iommu = sba_get_iommu(dev); /* get iommu data */
  1331. parisc_set_drvdata(dev, lba_dev);
  1332. /* ------------ Second : initialize common stuff ---------- */
  1333. pci_bios = &lba_bios_ops;
  1334. pcibios_register_hba(&lba_dev->hba);
  1335. spin_lock_init(&lba_dev->lba_lock);
  1336. if (lba_hw_init(lba_dev))
  1337. return(1);
  1338. /* ---------- Third : setup I/O Port and MMIO resources --------- */
  1339. if (is_pdc_pat()) {
  1340. /* PDC PAT firmware uses PIOP region of GMMIO space. */
  1341. pci_port = &lba_pat_port_ops;
  1342. /* Go ask PDC PAT what resources this LBA has */
  1343. lba_pat_resources(dev, lba_dev);
  1344. } else {
  1345. if (!astro_iop_base) {
  1346. /* Sprockets PDC uses NPIOP region */
  1347. astro_iop_base = ioremap(LBA_PORT_BASE, 64 * 1024);
  1348. pci_port = &lba_astro_port_ops;
  1349. }
  1350. /* Poke the chip a bit for /proc output */
  1351. lba_legacy_resources(dev, lba_dev);
  1352. }
  1353. if (lba_dev->hba.bus_num.start < lba_next_bus)
  1354. lba_dev->hba.bus_num.start = lba_next_bus;
  1355. /* Overlaps with elmmio can (and should) fail here.
  1356. * We will prune (or ignore) the distributed range.
  1357. *
  1358. * FIXME: SBA code should register all elmmio ranges first.
  1359. * that would take care of elmmio ranges routed
  1360. * to a different rope (already discovered) from
  1361. * getting registered *after* LBA code has already
  1362. * registered it's distributed lmmio range.
  1363. */
  1364. if (truncate_pat_collision(&iomem_resource,
  1365. &(lba_dev->hba.lmmio_space))) {
  1366. printk(KERN_WARNING "LBA: lmmio_space [%lx/%lx] duplicate!\n",
  1367. (long)lba_dev->hba.lmmio_space.start,
  1368. (long)lba_dev->hba.lmmio_space.end);
  1369. lba_dev->hba.lmmio_space.flags = 0;
  1370. }
  1371. pci_add_resource_offset(&resources, &lba_dev->hba.io_space,
  1372. HBA_PORT_BASE(lba_dev->hba.hba_num));
  1373. if (lba_dev->hba.elmmio_space.flags)
  1374. pci_add_resource_offset(&resources, &lba_dev->hba.elmmio_space,
  1375. lba_dev->hba.lmmio_space_offset);
  1376. if (lba_dev->hba.lmmio_space.flags)
  1377. pci_add_resource_offset(&resources, &lba_dev->hba.lmmio_space,
  1378. lba_dev->hba.lmmio_space_offset);
  1379. if (lba_dev->hba.gmmio_space.flags) {
  1380. /* Not registering GMMIO space - according to docs it's not
  1381. * even used on HP-UX. */
  1382. /* pci_add_resource(&resources, &lba_dev->hba.gmmio_space); */
  1383. }
  1384. pci_add_resource(&resources, &lba_dev->hba.bus_num);
  1385. dev->dev.platform_data = lba_dev;
  1386. lba_bus = lba_dev->hba.hba_bus =
  1387. pci_create_root_bus(&dev->dev, lba_dev->hba.bus_num.start,
  1388. cfg_ops, NULL, &resources);
  1389. if (!lba_bus) {
  1390. pci_free_resource_list(&resources);
  1391. return 0;
  1392. }
  1393. max = pci_scan_child_bus(lba_bus);
  1394. /* This is in lieu of calling pci_assign_unassigned_resources() */
  1395. if (is_pdc_pat()) {
  1396. /* assign resources to un-initialized devices */
  1397. DBG_PAT("LBA pci_bus_size_bridges()\n");
  1398. pci_bus_size_bridges(lba_bus);
  1399. DBG_PAT("LBA pci_bus_assign_resources()\n");
  1400. pci_bus_assign_resources(lba_bus);
  1401. #ifdef DEBUG_LBA_PAT
  1402. DBG_PAT("\nLBA PIOP resource tree\n");
  1403. lba_dump_res(&lba_dev->hba.io_space, 2);
  1404. DBG_PAT("\nLBA LMMIO resource tree\n");
  1405. lba_dump_res(&lba_dev->hba.lmmio_space, 2);
  1406. #endif
  1407. }
  1408. /*
  1409. ** Once PCI register ops has walked the bus, access to config
  1410. ** space is restricted. Avoids master aborts on config cycles.
  1411. ** Early LBA revs go fatal on *any* master abort.
  1412. */
  1413. if (cfg_ops == &elroy_cfg_ops) {
  1414. lba_dev->flags |= LBA_FLAG_SKIP_PROBE;
  1415. }
  1416. lba_next_bus = max + 1;
  1417. pci_bus_add_devices(lba_bus);
  1418. /* Whew! Finally done! Tell services we got this one covered. */
  1419. return 0;
  1420. }
  1421. static const struct parisc_device_id lba_tbl[] __initconst = {
  1422. { HPHW_BRIDGE, HVERSION_REV_ANY_ID, ELROY_HVERS, 0xa },
  1423. { HPHW_BRIDGE, HVERSION_REV_ANY_ID, MERCURY_HVERS, 0xa },
  1424. { HPHW_BRIDGE, HVERSION_REV_ANY_ID, QUICKSILVER_HVERS, 0xa },
  1425. { 0, }
  1426. };
  1427. static struct parisc_driver lba_driver __refdata = {
  1428. .name = MODULE_NAME,
  1429. .id_table = lba_tbl,
  1430. .probe = lba_driver_probe,
  1431. };
  1432. /*
  1433. ** One time initialization to let the world know the LBA was found.
  1434. ** Must be called exactly once before pci_init().
  1435. */
  1436. void __init lba_init(void)
  1437. {
  1438. register_parisc_driver(&lba_driver);
  1439. }
  1440. /*
  1441. ** Initialize the IBASE/IMASK registers for LBA (Elroy).
  1442. ** Only called from sba_iommu.c in order to route ranges (MMIO vs DMA).
  1443. ** sba_iommu is responsible for locking (none needed at init time).
  1444. */
  1445. void lba_set_iregs(struct parisc_device *lba, u32 ibase, u32 imask)
  1446. {
  1447. void __iomem * base_addr = ioremap(lba->hpa.start, 4096);
  1448. imask <<= 2; /* adjust for hints - 2 more bits */
  1449. /* Make sure we aren't trying to set bits that aren't writeable. */
  1450. WARN_ON((ibase & 0x001fffff) != 0);
  1451. WARN_ON((imask & 0x001fffff) != 0);
  1452. DBG("%s() ibase 0x%x imask 0x%x\n", __func__, ibase, imask);
  1453. WRITE_REG32( imask, base_addr + LBA_IMASK);
  1454. WRITE_REG32( ibase, base_addr + LBA_IBASE);
  1455. iounmap(base_addr);
  1456. }
  1457. /*
  1458. * The design of the Diva management card in rp34x0 machines (rp3410, rp3440)
  1459. * seems rushed, so that many built-in components simply don't work.
  1460. * The following quirks disable the serial AUX port and the built-in ATI RV100
  1461. * Radeon 7000 graphics card which both don't have any external connectors and
  1462. * thus are useless, and even worse, e.g. the AUX port occupies ttyS0 and as
  1463. * such makes those machines the only PARISC machines on which we can't use
  1464. * ttyS0 as boot console.
  1465. */
  1466. static void quirk_diva_ati_card(struct pci_dev *dev)
  1467. {
  1468. if (dev->subsystem_vendor != PCI_VENDOR_ID_HP ||
  1469. dev->subsystem_device != 0x1292)
  1470. return;
  1471. dev_info(&dev->dev, "Hiding Diva built-in ATI card");
  1472. dev->device = 0;
  1473. }
  1474. DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_RADEON_QY,
  1475. quirk_diva_ati_card);
  1476. static void quirk_diva_aux_disable(struct pci_dev *dev)
  1477. {
  1478. if (dev->subsystem_vendor != PCI_VENDOR_ID_HP ||
  1479. dev->subsystem_device != 0x1291)
  1480. return;
  1481. dev_info(&dev->dev, "Hiding Diva built-in AUX serial device");
  1482. dev->device = 0;
  1483. }
  1484. DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_DIVA_AUX,
  1485. quirk_diva_aux_disable);
  1486. static void quirk_tosca_aux_disable(struct pci_dev *dev)
  1487. {
  1488. if (dev->subsystem_vendor != PCI_VENDOR_ID_HP ||
  1489. dev->subsystem_device != 0x104a)
  1490. return;
  1491. dev_info(&dev->dev, "Hiding Tosca secondary built-in AUX serial device");
  1492. dev->device = 0;
  1493. }
  1494. DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_DIVA,
  1495. quirk_tosca_aux_disable);