iosapic_private.h 5.0 KB

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  1. /* SPDX-License-Identifier: GPL-2.0-or-later */
  2. /*
  3. * Private structs/constants for PARISC IOSAPIC support
  4. *
  5. * Copyright (C) 2000 Hewlett Packard (Grant Grundler)
  6. * Copyright (C) 2000,2003 Grant Grundler (grundler at parisc-linux.org)
  7. * Copyright (C) 2002 Matthew Wilcox (willy at parisc-linux.org)
  8. */
  9. /*
  10. ** This file is private to iosapic driver.
  11. ** If stuff needs to be used by another driver, move it to a common file.
  12. **
  13. ** WARNING: fields most data structures here are ordered to make sure
  14. ** they pack nicely for 64-bit compilation. (ie sizeof(long) == 8)
  15. */
  16. /*
  17. ** Interrupt Routing Stuff
  18. ** -----------------------
  19. ** The interrupt routing table consists of entries derived from
  20. ** MP Specification Draft 1.5. There is one interrupt routing
  21. ** table per cell. N- and L-class consist of a single cell.
  22. */
  23. struct irt_entry {
  24. /* Entry Type 139 identifies an I/O SAPIC interrupt entry */
  25. u8 entry_type;
  26. /* Entry Length 16 indicates entry is 16 bytes long */
  27. u8 entry_length;
  28. /*
  29. ** Interrupt Type of 0 indicates a vectored interrupt,
  30. ** all other values are reserved
  31. */
  32. u8 interrupt_type;
  33. /*
  34. ** PO and EL
  35. ** Polarity of SAPIC I/O input signals:
  36. ** 00 = Reserved
  37. ** 01 = Active high
  38. ** 10 = Reserved
  39. ** 11 = Active low
  40. ** Trigger mode of SAPIC I/O input signals:
  41. ** 00 = Reserved
  42. ** 01 = Edge-triggered
  43. ** 10 = Reserved
  44. ** 11 = Level-triggered
  45. */
  46. u8 polarity_trigger;
  47. /*
  48. ** IRQ and DEVNO
  49. ** irq identifies PCI interrupt signal where
  50. ** 0x0 corresponds to INT_A#,
  51. ** 0x1 corresponds to INT_B#,
  52. ** 0x2 corresponds to INT_C#
  53. ** 0x3 corresponds to INT_D#
  54. ** PCI device number where interrupt originates
  55. */
  56. u8 src_bus_irq_devno;
  57. /* Source Bus ID identifies the bus where interrupt signal comes from */
  58. u8 src_bus_id;
  59. /*
  60. ** Segment ID is unique across a protection domain and
  61. ** identifies a segment of PCI buses (reserved in
  62. ** MP Specification Draft 1.5)
  63. */
  64. u8 src_seg_id;
  65. /*
  66. ** Destination I/O SAPIC INTIN# identifies the INTIN n pin
  67. ** to which the signal is connected
  68. */
  69. u8 dest_iosapic_intin;
  70. /*
  71. ** Destination I/O SAPIC Address identifies the I/O SAPIC
  72. ** to which the signal is connected
  73. */
  74. u64 dest_iosapic_addr;
  75. };
  76. #define IRT_IOSAPIC_TYPE 139
  77. #define IRT_IOSAPIC_LENGTH 16
  78. #define IRT_VECTORED_INTR 0
  79. #define IRT_PO_MASK 0x3
  80. #define IRT_ACTIVE_HI 1
  81. #define IRT_ACTIVE_LO 3
  82. #define IRT_EL_MASK 0x3
  83. #define IRT_EL_SHIFT 2
  84. #define IRT_EDGE_TRIG 1
  85. #define IRT_LEVEL_TRIG 3
  86. #define IRT_IRQ_MASK 0x3
  87. #define IRT_DEV_MASK 0x1f
  88. #define IRT_DEV_SHIFT 2
  89. #define IRT_IRQ_DEVNO_MASK ((IRT_DEV_MASK << IRT_DEV_SHIFT) | IRT_IRQ_MASK)
  90. #ifdef SUPPORT_MULTI_CELL
  91. struct iosapic_irt {
  92. struct iosapic_irt *irt_next; /* next routing table */
  93. struct irt_entry *irt_base; /* intr routing table address */
  94. size_t irte_count; /* number of entries in the table */
  95. size_t irte_size; /* size (bytes) of each entry */
  96. };
  97. #endif
  98. struct vector_info {
  99. struct iosapic_info *iosapic; /* I/O SAPIC this vector is on */
  100. struct irt_entry *irte; /* IRT entry */
  101. u32 __iomem *eoi_addr; /* precalculate EOI reg address */
  102. u32 eoi_data; /* IA64: ? PA: swapped txn_data */
  103. int txn_irq; /* virtual IRQ number for processor */
  104. ulong txn_addr; /* IA64: id_eid PA: partial HPA */
  105. u32 txn_data; /* CPU interrupt bit */
  106. u8 status; /* status/flags */
  107. u8 irqline; /* INTINn(IRQ) */
  108. };
  109. struct iosapic_info {
  110. struct iosapic_info * isi_next; /* list of I/O SAPIC */
  111. void __iomem * addr; /* remapped address */
  112. unsigned long isi_hpa; /* physical base address */
  113. struct vector_info * isi_vector; /* IRdT (IRQ line) array */
  114. int isi_num_vectors; /* size of IRdT array */
  115. int isi_status; /* status/flags */
  116. unsigned int isi_version; /* DEBUG: data fr version reg */
  117. };
  118. #ifdef __IA64__
  119. /*
  120. ** PA risc does NOT have any local sapics. IA64 does.
  121. ** PIB (Processor Interrupt Block) is handled by Astro or Dew (Stretch CEC).
  122. **
  123. ** PA: Get id_eid from IRT and hardcode PIB to 0xfeeNNNN0
  124. ** Emulate the data on PAT platforms.
  125. */
  126. struct local_sapic_info {
  127. struct local_sapic_info *lsi_next; /* point to next CPU info */
  128. int *lsi_cpu_id; /* point to logical CPU id */
  129. unsigned long *lsi_id_eid; /* point to IA-64 CPU id */
  130. int *lsi_status; /* point to CPU status */
  131. void *lsi_private; /* point to special info */
  132. };
  133. /*
  134. ** "root" data structure which ties everything together.
  135. ** Should always be able to start with sapic_root and locate
  136. ** the desired information.
  137. */
  138. struct sapic_info {
  139. struct sapic_info *si_next; /* info is per cell */
  140. int si_cellid; /* cell id */
  141. unsigned int si_status; /* status */
  142. char *si_pib_base; /* intr blk base address */
  143. local_sapic_info_t *si_local_info;
  144. io_sapic_info_t *si_io_info;
  145. extint_info_t *si_extint_info;/* External Intr info */
  146. };
  147. #endif