eisa.c 12 KB

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  1. // SPDX-License-Identifier: GPL-2.0-or-later
  2. /*
  3. * eisa.c - provide support for EISA adapters in PA-RISC machines
  4. *
  5. * Copyright (c) 2001 Matthew Wilcox for Hewlett Packard
  6. * Copyright (c) 2001 Daniel Engstrom <5116@telia.com>
  7. *
  8. * There are two distinct EISA adapters. Mongoose is found in machines
  9. * before the 712; then the Wax ASIC is used. To complicate matters, the
  10. * Wax ASIC also includes a PS/2 and RS-232 controller, but those are
  11. * dealt with elsewhere; this file is concerned only with the EISA portions
  12. * of Wax.
  13. *
  14. * HINT:
  15. * -----
  16. * To allow an ISA card to work properly in the EISA slot you need to
  17. * set an edge trigger level. This may be done on the palo command line
  18. * by adding the kernel parameter "eisa_irq_edge=n,n2,[...]]", with
  19. * n and n2 as the irq levels you want to use.
  20. *
  21. * Example: "eisa_irq_edge=10,11" allows ISA cards to operate at
  22. * irq levels 10 and 11.
  23. */
  24. #include <linux/init.h>
  25. #include <linux/ioport.h>
  26. #include <linux/interrupt.h>
  27. #include <linux/kernel.h>
  28. #include <linux/module.h>
  29. #include <linux/pci.h>
  30. #include <linux/spinlock.h>
  31. #include <linux/eisa.h>
  32. #include <asm/byteorder.h>
  33. #include <asm/io.h>
  34. #include <asm/hardware.h>
  35. #include <asm/processor.h>
  36. #include <asm/parisc-device.h>
  37. #include <asm/delay.h>
  38. #include <asm/eisa_bus.h>
  39. #include <asm/eisa_eeprom.h>
  40. #include "iommu.h"
  41. #if 0
  42. #define EISA_DBG(msg, arg...) printk(KERN_DEBUG "eisa: " msg, ## arg)
  43. #else
  44. #define EISA_DBG(msg, arg...)
  45. #endif
  46. #define SNAKES_EEPROM_BASE_ADDR 0xF0810400
  47. #define MIRAGE_EEPROM_BASE_ADDR 0xF00C0400
  48. static DEFINE_SPINLOCK(eisa_irq_lock);
  49. void __iomem *eisa_eeprom_addr __read_mostly;
  50. /* We can only have one EISA adapter in the system because neither
  51. * implementation can be flexed.
  52. */
  53. static struct eisa_ba {
  54. struct pci_hba_data hba;
  55. unsigned long eeprom_addr;
  56. struct eisa_root_device root;
  57. } eisa_dev;
  58. /* Port ops */
  59. static inline unsigned long eisa_permute(unsigned short port)
  60. {
  61. if (port & 0x300) {
  62. return 0xfc000000 | ((port & 0xfc00) >> 6)
  63. | ((port & 0x3f8) << 9) | (port & 7);
  64. } else {
  65. return 0xfc000000 | port;
  66. }
  67. }
  68. unsigned char eisa_in8(unsigned short port)
  69. {
  70. if (EISA_bus)
  71. return gsc_readb(eisa_permute(port));
  72. return 0xff;
  73. }
  74. unsigned short eisa_in16(unsigned short port)
  75. {
  76. if (EISA_bus)
  77. return le16_to_cpu(gsc_readw(eisa_permute(port)));
  78. return 0xffff;
  79. }
  80. unsigned int eisa_in32(unsigned short port)
  81. {
  82. if (EISA_bus)
  83. return le32_to_cpu(gsc_readl(eisa_permute(port)));
  84. return 0xffffffff;
  85. }
  86. void eisa_out8(unsigned char data, unsigned short port)
  87. {
  88. if (EISA_bus)
  89. gsc_writeb(data, eisa_permute(port));
  90. }
  91. void eisa_out16(unsigned short data, unsigned short port)
  92. {
  93. if (EISA_bus)
  94. gsc_writew(cpu_to_le16(data), eisa_permute(port));
  95. }
  96. void eisa_out32(unsigned int data, unsigned short port)
  97. {
  98. if (EISA_bus)
  99. gsc_writel(cpu_to_le32(data), eisa_permute(port));
  100. }
  101. #ifndef CONFIG_PCI
  102. /* We call these directly without PCI. See asm/io.h. */
  103. EXPORT_SYMBOL(eisa_in8);
  104. EXPORT_SYMBOL(eisa_in16);
  105. EXPORT_SYMBOL(eisa_in32);
  106. EXPORT_SYMBOL(eisa_out8);
  107. EXPORT_SYMBOL(eisa_out16);
  108. EXPORT_SYMBOL(eisa_out32);
  109. #endif
  110. /* Interrupt handling */
  111. /* cached interrupt mask registers */
  112. static int master_mask;
  113. static int slave_mask;
  114. /* the trig level can be set with the
  115. * eisa_irq_edge=n,n,n commandline parameter
  116. * We should really read this from the EEPROM
  117. * in the furure.
  118. */
  119. /* irq 13,8,2,1,0 must be edge */
  120. static unsigned int eisa_irq_level __read_mostly; /* default to edge triggered */
  121. /* called by free irq */
  122. static void eisa_mask_irq(struct irq_data *d)
  123. {
  124. unsigned int irq = d->irq;
  125. unsigned long flags;
  126. EISA_DBG("disable irq %d\n", irq);
  127. /* just mask for now */
  128. spin_lock_irqsave(&eisa_irq_lock, flags);
  129. if (irq & 8) {
  130. slave_mask |= (1 << (irq&7));
  131. eisa_out8(slave_mask, 0xa1);
  132. } else {
  133. master_mask |= (1 << (irq&7));
  134. eisa_out8(master_mask, 0x21);
  135. }
  136. spin_unlock_irqrestore(&eisa_irq_lock, flags);
  137. EISA_DBG("pic0 mask %02x\n", eisa_in8(0x21));
  138. EISA_DBG("pic1 mask %02x\n", eisa_in8(0xa1));
  139. }
  140. /* called by request irq */
  141. static void eisa_unmask_irq(struct irq_data *d)
  142. {
  143. unsigned int irq = d->irq;
  144. unsigned long flags;
  145. EISA_DBG("enable irq %d\n", irq);
  146. spin_lock_irqsave(&eisa_irq_lock, flags);
  147. if (irq & 8) {
  148. slave_mask &= ~(1 << (irq&7));
  149. eisa_out8(slave_mask, 0xa1);
  150. } else {
  151. master_mask &= ~(1 << (irq&7));
  152. eisa_out8(master_mask, 0x21);
  153. }
  154. spin_unlock_irqrestore(&eisa_irq_lock, flags);
  155. EISA_DBG("pic0 mask %02x\n", eisa_in8(0x21));
  156. EISA_DBG("pic1 mask %02x\n", eisa_in8(0xa1));
  157. }
  158. static struct irq_chip eisa_interrupt_type = {
  159. .name = "EISA",
  160. .irq_unmask = eisa_unmask_irq,
  161. .irq_mask = eisa_mask_irq,
  162. };
  163. static irqreturn_t eisa_irq(int wax_irq, void *intr_dev)
  164. {
  165. int irq = gsc_readb(0xfc01f000); /* EISA supports 16 irqs */
  166. unsigned long flags;
  167. spin_lock_irqsave(&eisa_irq_lock, flags);
  168. /* read IRR command */
  169. eisa_out8(0x0a, 0x20);
  170. eisa_out8(0x0a, 0xa0);
  171. EISA_DBG("irq IAR %02x 8259-1 irr %02x 8259-2 irr %02x\n",
  172. irq, eisa_in8(0x20), eisa_in8(0xa0));
  173. /* read ISR command */
  174. eisa_out8(0x0a, 0x20);
  175. eisa_out8(0x0a, 0xa0);
  176. EISA_DBG("irq 8259-1 isr %02x imr %02x 8259-2 isr %02x imr %02x\n",
  177. eisa_in8(0x20), eisa_in8(0x21), eisa_in8(0xa0), eisa_in8(0xa1));
  178. irq &= 0xf;
  179. /* mask irq and write eoi */
  180. if (irq & 8) {
  181. slave_mask |= (1 << (irq&7));
  182. eisa_out8(slave_mask, 0xa1);
  183. eisa_out8(0x60 | (irq&7),0xa0);/* 'Specific EOI' to slave */
  184. eisa_out8(0x62, 0x20); /* 'Specific EOI' to master-IRQ2 */
  185. } else {
  186. master_mask |= (1 << (irq&7));
  187. eisa_out8(master_mask, 0x21);
  188. eisa_out8(0x60|irq, 0x20); /* 'Specific EOI' to master */
  189. }
  190. spin_unlock_irqrestore(&eisa_irq_lock, flags);
  191. generic_handle_irq(irq);
  192. spin_lock_irqsave(&eisa_irq_lock, flags);
  193. /* unmask */
  194. if (irq & 8) {
  195. slave_mask &= ~(1 << (irq&7));
  196. eisa_out8(slave_mask, 0xa1);
  197. } else {
  198. master_mask &= ~(1 << (irq&7));
  199. eisa_out8(master_mask, 0x21);
  200. }
  201. spin_unlock_irqrestore(&eisa_irq_lock, flags);
  202. return IRQ_HANDLED;
  203. }
  204. static irqreturn_t dummy_irq2_handler(int _, void *dev)
  205. {
  206. printk(KERN_ALERT "eisa: uhh, irq2?\n");
  207. return IRQ_HANDLED;
  208. }
  209. static void init_eisa_pic(void)
  210. {
  211. unsigned long flags;
  212. spin_lock_irqsave(&eisa_irq_lock, flags);
  213. eisa_out8(0xff, 0x21); /* mask during init */
  214. eisa_out8(0xff, 0xa1); /* mask during init */
  215. /* master pic */
  216. eisa_out8(0x11, 0x20); /* ICW1 */
  217. eisa_out8(0x00, 0x21); /* ICW2 */
  218. eisa_out8(0x04, 0x21); /* ICW3 */
  219. eisa_out8(0x01, 0x21); /* ICW4 */
  220. eisa_out8(0x40, 0x20); /* OCW2 */
  221. /* slave pic */
  222. eisa_out8(0x11, 0xa0); /* ICW1 */
  223. eisa_out8(0x08, 0xa1); /* ICW2 */
  224. eisa_out8(0x02, 0xa1); /* ICW3 */
  225. eisa_out8(0x01, 0xa1); /* ICW4 */
  226. eisa_out8(0x40, 0xa0); /* OCW2 */
  227. udelay(100);
  228. slave_mask = 0xff;
  229. master_mask = 0xfb;
  230. eisa_out8(slave_mask, 0xa1); /* OCW1 */
  231. eisa_out8(master_mask, 0x21); /* OCW1 */
  232. /* setup trig level */
  233. EISA_DBG("EISA edge/level %04x\n", eisa_irq_level);
  234. eisa_out8(eisa_irq_level&0xff, 0x4d0); /* Set all irq's to edge */
  235. eisa_out8((eisa_irq_level >> 8) & 0xff, 0x4d1);
  236. EISA_DBG("pic0 mask %02x\n", eisa_in8(0x21));
  237. EISA_DBG("pic1 mask %02x\n", eisa_in8(0xa1));
  238. EISA_DBG("pic0 edge/level %02x\n", eisa_in8(0x4d0));
  239. EISA_DBG("pic1 edge/level %02x\n", eisa_in8(0x4d1));
  240. spin_unlock_irqrestore(&eisa_irq_lock, flags);
  241. }
  242. /* Device initialisation */
  243. #define is_mongoose(dev) (dev->id.sversion == 0x00076)
  244. static int __init eisa_probe(struct parisc_device *dev)
  245. {
  246. int i, result;
  247. char *name = is_mongoose(dev) ? "Mongoose" : "Wax";
  248. printk(KERN_INFO "%s EISA Adapter found at 0x%08lx\n",
  249. name, (unsigned long)dev->hpa.start);
  250. eisa_dev.hba.dev = dev;
  251. eisa_dev.hba.iommu = ccio_get_iommu(dev);
  252. eisa_dev.hba.lmmio_space.name = "EISA";
  253. eisa_dev.hba.lmmio_space.start = F_EXTEND(0xfc000000);
  254. eisa_dev.hba.lmmio_space.end = F_EXTEND(0xffbfffff);
  255. eisa_dev.hba.lmmio_space.flags = IORESOURCE_MEM;
  256. result = ccio_request_resource(dev, &eisa_dev.hba.lmmio_space);
  257. if (result < 0) {
  258. printk(KERN_ERR "EISA: failed to claim EISA Bus address space!\n");
  259. return result;
  260. }
  261. eisa_dev.hba.io_space.name = "EISA";
  262. eisa_dev.hba.io_space.start = 0;
  263. eisa_dev.hba.io_space.end = 0xffff;
  264. eisa_dev.hba.lmmio_space.flags = IORESOURCE_IO;
  265. result = request_resource(&ioport_resource, &eisa_dev.hba.io_space);
  266. if (result < 0) {
  267. printk(KERN_ERR "EISA: failed to claim EISA Bus port space!\n");
  268. return result;
  269. }
  270. pcibios_register_hba(&eisa_dev.hba);
  271. result = request_irq(dev->irq, eisa_irq, IRQF_SHARED, "EISA", &eisa_dev);
  272. if (result) {
  273. printk(KERN_ERR "EISA: request_irq failed!\n");
  274. goto error_release;
  275. }
  276. /* Reserve IRQ2 */
  277. if (request_irq(2, dummy_irq2_handler, 0, "cascade", NULL))
  278. pr_err("Failed to request irq 2 (cascade)\n");
  279. for (i = 0; i < 16; i++) {
  280. irq_set_chip_and_handler(i, &eisa_interrupt_type,
  281. handle_simple_irq);
  282. }
  283. EISA_bus = 1;
  284. if (dev->num_addrs) {
  285. /* newer firmware hand out the eeprom address */
  286. eisa_dev.eeprom_addr = dev->addr[0];
  287. } else {
  288. /* old firmware, need to figure out the box */
  289. if (is_mongoose(dev)) {
  290. eisa_dev.eeprom_addr = SNAKES_EEPROM_BASE_ADDR;
  291. } else {
  292. eisa_dev.eeprom_addr = MIRAGE_EEPROM_BASE_ADDR;
  293. }
  294. }
  295. eisa_eeprom_addr = ioremap(eisa_dev.eeprom_addr, HPEE_MAX_LENGTH);
  296. if (!eisa_eeprom_addr) {
  297. result = -ENOMEM;
  298. printk(KERN_ERR "EISA: ioremap failed!\n");
  299. goto error_free_irq;
  300. }
  301. result = eisa_enumerator(eisa_dev.eeprom_addr, &eisa_dev.hba.io_space,
  302. &eisa_dev.hba.lmmio_space);
  303. init_eisa_pic();
  304. if (result >= 0) {
  305. /* FIXME : Don't enumerate the bus twice. */
  306. eisa_dev.root.dev = &dev->dev;
  307. dev_set_drvdata(&dev->dev, &eisa_dev.root);
  308. eisa_dev.root.bus_base_addr = 0;
  309. eisa_dev.root.res = &eisa_dev.hba.io_space;
  310. eisa_dev.root.slots = result;
  311. eisa_dev.root.dma_mask = 0xffffffff; /* wild guess */
  312. if (eisa_root_register (&eisa_dev.root)) {
  313. printk(KERN_ERR "EISA: Failed to register EISA root\n");
  314. result = -ENOMEM;
  315. goto error_iounmap;
  316. }
  317. }
  318. return 0;
  319. error_iounmap:
  320. iounmap(eisa_eeprom_addr);
  321. error_free_irq:
  322. free_irq(dev->irq, &eisa_dev);
  323. error_release:
  324. release_resource(&eisa_dev.hba.io_space);
  325. return result;
  326. }
  327. static const struct parisc_device_id eisa_tbl[] __initconst = {
  328. { HPHW_BA, HVERSION_REV_ANY_ID, HVERSION_ANY_ID, 0x00076 }, /* Mongoose */
  329. { HPHW_BA, HVERSION_REV_ANY_ID, HVERSION_ANY_ID, 0x00090 }, /* Wax EISA */
  330. { 0, }
  331. };
  332. MODULE_DEVICE_TABLE(parisc, eisa_tbl);
  333. static struct parisc_driver eisa_driver __refdata = {
  334. .name = "eisa_ba",
  335. .id_table = eisa_tbl,
  336. .probe = eisa_probe,
  337. };
  338. void __init eisa_init(void)
  339. {
  340. register_parisc_driver(&eisa_driver);
  341. }
  342. static unsigned int eisa_irq_configured;
  343. void eisa_make_irq_level(int num)
  344. {
  345. if (eisa_irq_configured& (1<<num)) {
  346. printk(KERN_WARNING
  347. "IRQ %d polarity configured twice (last to level)\n",
  348. num);
  349. }
  350. eisa_irq_level |= (1<<num); /* set the corresponding bit */
  351. eisa_irq_configured |= (1<<num); /* set the corresponding bit */
  352. }
  353. void eisa_make_irq_edge(int num)
  354. {
  355. if (eisa_irq_configured& (1<<num)) {
  356. printk(KERN_WARNING
  357. "IRQ %d polarity configured twice (last to edge)\n",
  358. num);
  359. }
  360. eisa_irq_level &= ~(1<<num); /* clear the corresponding bit */
  361. eisa_irq_configured |= (1<<num); /* set the corresponding bit */
  362. }
  363. static int __init eisa_irq_setup(char *str)
  364. {
  365. char *cur = str;
  366. int val;
  367. EISA_DBG("IRQ setup\n");
  368. while (cur != NULL) {
  369. char *pe;
  370. val = (int) simple_strtoul(cur, &pe, 0);
  371. if (val > 15 || val < 0) {
  372. printk(KERN_ERR "eisa: EISA irq value are 0-15\n");
  373. continue;
  374. }
  375. if (val == 2) {
  376. val = 9;
  377. }
  378. eisa_make_irq_edge(val); /* clear the corresponding bit */
  379. EISA_DBG("setting IRQ %d to edge-triggered mode\n", val);
  380. if ((cur = strchr(cur, ','))) {
  381. cur++;
  382. } else {
  383. break;
  384. }
  385. }
  386. return 1;
  387. }
  388. __setup("eisa_irq_edge=", eisa_irq_setup);