ccio-dma.c 47 KB

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  1. // SPDX-License-Identifier: GPL-2.0-or-later
  2. /*
  3. ** ccio-dma.c:
  4. ** DMA management routines for first generation cache-coherent machines.
  5. ** Program U2/Uturn in "Virtual Mode" and use the I/O MMU.
  6. **
  7. ** (c) Copyright 2000 Grant Grundler
  8. ** (c) Copyright 2000 Ryan Bradetich
  9. ** (c) Copyright 2000 Hewlett-Packard Company
  10. **
  11. **
  12. **
  13. ** "Real Mode" operation refers to U2/Uturn chip operation.
  14. ** U2/Uturn were designed to perform coherency checks w/o using
  15. ** the I/O MMU - basically what x86 does.
  16. **
  17. ** Philipp Rumpf has a "Real Mode" driver for PCX-W machines at:
  18. ** CVSROOT=:pserver:anonymous@198.186.203.37:/cvsroot/linux-parisc
  19. ** cvs -z3 co linux/arch/parisc/kernel/dma-rm.c
  20. **
  21. ** I've rewritten his code to work under TPG's tree. See ccio-rm-dma.c.
  22. **
  23. ** Drawbacks of using Real Mode are:
  24. ** o outbound DMA is slower - U2 won't prefetch data (GSC+ XQL signal).
  25. ** o Inbound DMA less efficient - U2 can't use DMA_FAST attribute.
  26. ** o Ability to do scatter/gather in HW is lost.
  27. ** o Doesn't work under PCX-U/U+ machines since they didn't follow
  28. ** the coherency design originally worked out. Only PCX-W does.
  29. */
  30. #include <linux/types.h>
  31. #include <linux/kernel.h>
  32. #include <linux/init.h>
  33. #include <linux/mm.h>
  34. #include <linux/spinlock.h>
  35. #include <linux/slab.h>
  36. #include <linux/string.h>
  37. #include <linux/pci.h>
  38. #include <linux/reboot.h>
  39. #include <linux/proc_fs.h>
  40. #include <linux/seq_file.h>
  41. #include <linux/dma-map-ops.h>
  42. #include <linux/scatterlist.h>
  43. #include <linux/iommu-helper.h>
  44. #include <linux/export.h>
  45. #include <asm/byteorder.h>
  46. #include <asm/cache.h> /* for L1_CACHE_BYTES */
  47. #include <linux/uaccess.h>
  48. #include <asm/page.h>
  49. #include <asm/dma.h>
  50. #include <asm/io.h>
  51. #include <asm/hardware.h> /* for register_module() */
  52. #include <asm/parisc-device.h>
  53. #include "iommu.h"
  54. /*
  55. ** Choose "ccio" since that's what HP-UX calls it.
  56. ** Make it easier for folks to migrate from one to the other :^)
  57. */
  58. #define MODULE_NAME "ccio"
  59. #undef DEBUG_CCIO_RES
  60. #undef DEBUG_CCIO_RUN
  61. #undef DEBUG_CCIO_INIT
  62. #undef DEBUG_CCIO_RUN_SG
  63. #ifdef CONFIG_PROC_FS
  64. /* depends on proc fs support. But costs CPU performance. */
  65. #undef CCIO_COLLECT_STATS
  66. #endif
  67. #include <asm/runway.h> /* for proc_runway_root */
  68. #ifdef DEBUG_CCIO_INIT
  69. #define DBG_INIT(x...) printk(x)
  70. #else
  71. #define DBG_INIT(x...)
  72. #endif
  73. #ifdef DEBUG_CCIO_RUN
  74. #define DBG_RUN(x...) printk(x)
  75. #else
  76. #define DBG_RUN(x...)
  77. #endif
  78. #ifdef DEBUG_CCIO_RES
  79. #define DBG_RES(x...) printk(x)
  80. #else
  81. #define DBG_RES(x...)
  82. #endif
  83. #ifdef DEBUG_CCIO_RUN_SG
  84. #define DBG_RUN_SG(x...) printk(x)
  85. #else
  86. #define DBG_RUN_SG(x...)
  87. #endif
  88. #define CCIO_INLINE inline
  89. #define WRITE_U32(value, addr) __raw_writel(value, addr)
  90. #define READ_U32(addr) __raw_readl(addr)
  91. #define U2_IOA_RUNWAY 0x580
  92. #define U2_BC_GSC 0x501
  93. #define UTURN_IOA_RUNWAY 0x581
  94. #define UTURN_BC_GSC 0x502
  95. #define IOA_NORMAL_MODE 0x00020080 /* IO_CONTROL to turn on CCIO */
  96. #define CMD_TLB_DIRECT_WRITE 35 /* IO_COMMAND for I/O TLB Writes */
  97. #define CMD_TLB_PURGE 33 /* IO_COMMAND to Purge I/O TLB entry */
  98. struct ioa_registers {
  99. /* Runway Supervisory Set */
  100. int32_t unused1[12];
  101. uint32_t io_command; /* Offset 12 */
  102. uint32_t io_status; /* Offset 13 */
  103. uint32_t io_control; /* Offset 14 */
  104. int32_t unused2[1];
  105. /* Runway Auxiliary Register Set */
  106. uint32_t io_err_resp; /* Offset 0 */
  107. uint32_t io_err_info; /* Offset 1 */
  108. uint32_t io_err_req; /* Offset 2 */
  109. uint32_t io_err_resp_hi; /* Offset 3 */
  110. uint32_t io_tlb_entry_m; /* Offset 4 */
  111. uint32_t io_tlb_entry_l; /* Offset 5 */
  112. uint32_t unused3[1];
  113. uint32_t io_pdir_base; /* Offset 7 */
  114. uint32_t io_io_low_hv; /* Offset 8 */
  115. uint32_t io_io_high_hv; /* Offset 9 */
  116. uint32_t unused4[1];
  117. uint32_t io_chain_id_mask; /* Offset 11 */
  118. uint32_t unused5[2];
  119. uint32_t io_io_low; /* Offset 14 */
  120. uint32_t io_io_high; /* Offset 15 */
  121. };
  122. /*
  123. ** IOA Registers
  124. ** -------------
  125. **
  126. ** Runway IO_CONTROL Register (+0x38)
  127. **
  128. ** The Runway IO_CONTROL register controls the forwarding of transactions.
  129. **
  130. ** | 0 ... 13 | 14 15 | 16 ... 21 | 22 | 23 24 | 25 ... 31 |
  131. ** | HV | TLB | reserved | HV | mode | reserved |
  132. **
  133. ** o mode field indicates the address translation of transactions
  134. ** forwarded from Runway to GSC+:
  135. ** Mode Name Value Definition
  136. ** Off (default) 0 Opaque to matching addresses.
  137. ** Include 1 Transparent for matching addresses.
  138. ** Peek 3 Map matching addresses.
  139. **
  140. ** + "Off" mode: Runway transactions which match the I/O range
  141. ** specified by the IO_IO_LOW/IO_IO_HIGH registers will be ignored.
  142. ** + "Include" mode: all addresses within the I/O range specified
  143. ** by the IO_IO_LOW and IO_IO_HIGH registers are transparently
  144. ** forwarded. This is the I/O Adapter's normal operating mode.
  145. ** + "Peek" mode: used during system configuration to initialize the
  146. ** GSC+ bus. Runway Write_Shorts in the address range specified by
  147. ** IO_IO_LOW and IO_IO_HIGH are forwarded through the I/O Adapter
  148. ** *AND* the GSC+ address is remapped to the Broadcast Physical
  149. ** Address space by setting the 14 high order address bits of the
  150. ** 32 bit GSC+ address to ones.
  151. **
  152. ** o TLB field affects transactions which are forwarded from GSC+ to Runway.
  153. ** "Real" mode is the poweron default.
  154. **
  155. ** TLB Mode Value Description
  156. ** Real 0 No TLB translation. Address is directly mapped and the
  157. ** virtual address is composed of selected physical bits.
  158. ** Error 1 Software fills the TLB manually.
  159. ** Normal 2 IOA fetches IO TLB misses from IO PDIR (in host memory).
  160. **
  161. **
  162. ** IO_IO_LOW_HV +0x60 (HV dependent)
  163. ** IO_IO_HIGH_HV +0x64 (HV dependent)
  164. ** IO_IO_LOW +0x78 (Architected register)
  165. ** IO_IO_HIGH +0x7c (Architected register)
  166. **
  167. ** IO_IO_LOW and IO_IO_HIGH set the lower and upper bounds of the
  168. ** I/O Adapter address space, respectively.
  169. **
  170. ** 0 ... 7 | 8 ... 15 | 16 ... 31 |
  171. ** 11111111 | 11111111 | address |
  172. **
  173. ** Each LOW/HIGH pair describes a disjoint address space region.
  174. ** (2 per GSC+ port). Each incoming Runway transaction address is compared
  175. ** with both sets of LOW/HIGH registers. If the address is in the range
  176. ** greater than or equal to IO_IO_LOW and less than IO_IO_HIGH the transaction
  177. ** for forwarded to the respective GSC+ bus.
  178. ** Specify IO_IO_LOW equal to or greater than IO_IO_HIGH to avoid specifying
  179. ** an address space region.
  180. **
  181. ** In order for a Runway address to reside within GSC+ extended address space:
  182. ** Runway Address [0:7] must identically compare to 8'b11111111
  183. ** Runway Address [8:11] must be equal to IO_IO_LOW(_HV)[16:19]
  184. ** Runway Address [12:23] must be greater than or equal to
  185. ** IO_IO_LOW(_HV)[20:31] and less than IO_IO_HIGH(_HV)[20:31].
  186. ** Runway Address [24:39] is not used in the comparison.
  187. **
  188. ** When the Runway transaction is forwarded to GSC+, the GSC+ address is
  189. ** as follows:
  190. ** GSC+ Address[0:3] 4'b1111
  191. ** GSC+ Address[4:29] Runway Address[12:37]
  192. ** GSC+ Address[30:31] 2'b00
  193. **
  194. ** All 4 Low/High registers must be initialized (by PDC) once the lower bus
  195. ** is interrogated and address space is defined. The operating system will
  196. ** modify the architectural IO_IO_LOW and IO_IO_HIGH registers following
  197. ** the PDC initialization. However, the hardware version dependent IO_IO_LOW
  198. ** and IO_IO_HIGH registers should not be subsequently altered by the OS.
  199. **
  200. ** Writes to both sets of registers will take effect immediately, bypassing
  201. ** the queues, which ensures that subsequent Runway transactions are checked
  202. ** against the updated bounds values. However reads are queued, introducing
  203. ** the possibility of a read being bypassed by a subsequent write to the same
  204. ** register. This sequence can be avoided by having software wait for read
  205. ** returns before issuing subsequent writes.
  206. */
  207. struct ioc {
  208. struct ioa_registers __iomem *ioc_regs; /* I/O MMU base address */
  209. u8 *res_map; /* resource map, bit == pdir entry */
  210. u64 *pdir_base; /* physical base address */
  211. u32 pdir_size; /* bytes, function of IOV Space size */
  212. u32 res_hint; /* next available IOVP -
  213. circular search */
  214. u32 res_size; /* size of resource map in bytes */
  215. spinlock_t res_lock;
  216. #ifdef CCIO_COLLECT_STATS
  217. #define CCIO_SEARCH_SAMPLE 0x100
  218. unsigned long avg_search[CCIO_SEARCH_SAMPLE];
  219. unsigned long avg_idx; /* current index into avg_search */
  220. unsigned long used_pages;
  221. unsigned long msingle_calls;
  222. unsigned long msingle_pages;
  223. unsigned long msg_calls;
  224. unsigned long msg_pages;
  225. unsigned long usingle_calls;
  226. unsigned long usingle_pages;
  227. unsigned long usg_calls;
  228. unsigned long usg_pages;
  229. #endif
  230. unsigned short cujo20_bug;
  231. /* STUFF We don't need in performance path */
  232. u32 chainid_shift; /* specify bit location of chain_id */
  233. struct ioc *next; /* Linked list of discovered iocs */
  234. const char *name; /* device name from firmware */
  235. unsigned int hw_path; /* the hardware path this ioc is associatd with */
  236. struct pci_dev *fake_pci_dev; /* the fake pci_dev for non-pci devs */
  237. struct resource mmio_region[2]; /* The "routed" MMIO regions */
  238. };
  239. static struct ioc *ioc_list;
  240. static int ioc_count;
  241. /**************************************************************
  242. *
  243. * I/O Pdir Resource Management
  244. *
  245. * Bits set in the resource map are in use.
  246. * Each bit can represent a number of pages.
  247. * LSbs represent lower addresses (IOVA's).
  248. *
  249. * This was was copied from sba_iommu.c. Don't try to unify
  250. * the two resource managers unless a way to have different
  251. * allocation policies is also adjusted. We'd like to avoid
  252. * I/O TLB thrashing by having resource allocation policy
  253. * match the I/O TLB replacement policy.
  254. *
  255. ***************************************************************/
  256. #define IOVP_SIZE PAGE_SIZE
  257. #define IOVP_SHIFT PAGE_SHIFT
  258. #define IOVP_MASK PAGE_MASK
  259. /* Convert from IOVP to IOVA and vice versa. */
  260. #define CCIO_IOVA(iovp,offset) ((iovp) | (offset))
  261. #define CCIO_IOVP(iova) ((iova) & IOVP_MASK)
  262. #define PDIR_INDEX(iovp) ((iovp)>>IOVP_SHIFT)
  263. #define MKIOVP(pdir_idx) ((long)(pdir_idx) << IOVP_SHIFT)
  264. #define MKIOVA(iovp,offset) (dma_addr_t)((long)iovp | (long)offset)
  265. /*
  266. ** Don't worry about the 150% average search length on a miss.
  267. ** If the search wraps around, and passes the res_hint, it will
  268. ** cause the kernel to panic anyhow.
  269. */
  270. #define CCIO_SEARCH_LOOP(ioc, res_idx, mask, size) \
  271. for(; res_ptr < res_end; ++res_ptr) { \
  272. int ret;\
  273. unsigned int idx;\
  274. idx = (unsigned int)((unsigned long)res_ptr - (unsigned long)ioc->res_map); \
  275. ret = iommu_is_span_boundary(idx << 3, pages_needed, 0, boundary_size);\
  276. if ((0 == (*res_ptr & mask)) && !ret) { \
  277. *res_ptr |= mask; \
  278. res_idx = idx;\
  279. ioc->res_hint = res_idx + (size >> 3); \
  280. goto resource_found; \
  281. } \
  282. }
  283. #define CCIO_FIND_FREE_MAPPING(ioa, res_idx, mask, size) \
  284. u##size *res_ptr = (u##size *)&((ioc)->res_map[ioa->res_hint & ~((size >> 3) - 1)]); \
  285. u##size *res_end = (u##size *)&(ioc)->res_map[ioa->res_size]; \
  286. CCIO_SEARCH_LOOP(ioc, res_idx, mask, size); \
  287. res_ptr = (u##size *)&(ioc)->res_map[0]; \
  288. CCIO_SEARCH_LOOP(ioa, res_idx, mask, size);
  289. /*
  290. ** Find available bit in this ioa's resource map.
  291. ** Use a "circular" search:
  292. ** o Most IOVA's are "temporary" - avg search time should be small.
  293. ** o keep a history of what happened for debugging
  294. ** o KISS.
  295. **
  296. ** Perf optimizations:
  297. ** o search for log2(size) bits at a time.
  298. ** o search for available resource bits using byte/word/whatever.
  299. ** o use different search for "large" (eg > 4 pages) or "very large"
  300. ** (eg > 16 pages) mappings.
  301. */
  302. /**
  303. * ccio_alloc_range - Allocate pages in the ioc's resource map.
  304. * @ioc: The I/O Controller.
  305. * @pages_needed: The requested number of pages to be mapped into the
  306. * I/O Pdir...
  307. *
  308. * This function searches the resource map of the ioc to locate a range
  309. * of available pages for the requested size.
  310. */
  311. static int
  312. ccio_alloc_range(struct ioc *ioc, struct device *dev, size_t size)
  313. {
  314. unsigned int pages_needed = size >> IOVP_SHIFT;
  315. unsigned int res_idx;
  316. unsigned long boundary_size;
  317. #ifdef CCIO_COLLECT_STATS
  318. unsigned long cr_start = mfctl(16);
  319. #endif
  320. BUG_ON(pages_needed == 0);
  321. BUG_ON((pages_needed * IOVP_SIZE) > DMA_CHUNK_SIZE);
  322. DBG_RES("%s() size: %d pages_needed %d\n",
  323. __func__, size, pages_needed);
  324. /*
  325. ** "seek and ye shall find"...praying never hurts either...
  326. ** ggg sacrifices another 710 to the computer gods.
  327. */
  328. boundary_size = dma_get_seg_boundary_nr_pages(dev, IOVP_SHIFT);
  329. if (pages_needed <= 8) {
  330. /*
  331. * LAN traffic will not thrash the TLB IFF the same NIC
  332. * uses 8 adjacent pages to map separate payload data.
  333. * ie the same byte in the resource bit map.
  334. */
  335. #if 0
  336. /* FIXME: bit search should shift it's way through
  337. * an unsigned long - not byte at a time. As it is now,
  338. * we effectively allocate this byte to this mapping.
  339. */
  340. unsigned long mask = ~(~0UL >> pages_needed);
  341. CCIO_FIND_FREE_MAPPING(ioc, res_idx, mask, 8);
  342. #else
  343. CCIO_FIND_FREE_MAPPING(ioc, res_idx, 0xff, 8);
  344. #endif
  345. } else if (pages_needed <= 16) {
  346. CCIO_FIND_FREE_MAPPING(ioc, res_idx, 0xffff, 16);
  347. } else if (pages_needed <= 32) {
  348. CCIO_FIND_FREE_MAPPING(ioc, res_idx, ~(unsigned int)0, 32);
  349. #ifdef __LP64__
  350. } else if (pages_needed <= 64) {
  351. CCIO_FIND_FREE_MAPPING(ioc, res_idx, ~0UL, 64);
  352. #endif
  353. } else {
  354. panic("%s: %s() Too many pages to map. pages_needed: %u\n",
  355. __FILE__, __func__, pages_needed);
  356. }
  357. panic("%s: %s() I/O MMU is out of mapping resources.\n", __FILE__,
  358. __func__);
  359. resource_found:
  360. DBG_RES("%s() res_idx %d res_hint: %d\n",
  361. __func__, res_idx, ioc->res_hint);
  362. #ifdef CCIO_COLLECT_STATS
  363. {
  364. unsigned long cr_end = mfctl(16);
  365. unsigned long tmp = cr_end - cr_start;
  366. /* check for roll over */
  367. cr_start = (cr_end < cr_start) ? -(tmp) : (tmp);
  368. }
  369. ioc->avg_search[ioc->avg_idx++] = cr_start;
  370. ioc->avg_idx &= CCIO_SEARCH_SAMPLE - 1;
  371. ioc->used_pages += pages_needed;
  372. #endif
  373. /*
  374. ** return the bit address.
  375. */
  376. return res_idx << 3;
  377. }
  378. #define CCIO_FREE_MAPPINGS(ioc, res_idx, mask, size) \
  379. u##size *res_ptr = (u##size *)&((ioc)->res_map[res_idx]); \
  380. BUG_ON((*res_ptr & mask) != mask); \
  381. *res_ptr &= ~(mask);
  382. /**
  383. * ccio_free_range - Free pages from the ioc's resource map.
  384. * @ioc: The I/O Controller.
  385. * @iova: The I/O Virtual Address.
  386. * @pages_mapped: The requested number of pages to be freed from the
  387. * I/O Pdir.
  388. *
  389. * This function frees the resouces allocated for the iova.
  390. */
  391. static void
  392. ccio_free_range(struct ioc *ioc, dma_addr_t iova, unsigned long pages_mapped)
  393. {
  394. unsigned long iovp = CCIO_IOVP(iova);
  395. unsigned int res_idx = PDIR_INDEX(iovp) >> 3;
  396. BUG_ON(pages_mapped == 0);
  397. BUG_ON((pages_mapped * IOVP_SIZE) > DMA_CHUNK_SIZE);
  398. BUG_ON(pages_mapped > BITS_PER_LONG);
  399. DBG_RES("%s(): res_idx: %d pages_mapped %d\n",
  400. __func__, res_idx, pages_mapped);
  401. #ifdef CCIO_COLLECT_STATS
  402. ioc->used_pages -= pages_mapped;
  403. #endif
  404. if(pages_mapped <= 8) {
  405. #if 0
  406. /* see matching comments in alloc_range */
  407. unsigned long mask = ~(~0UL >> pages_mapped);
  408. CCIO_FREE_MAPPINGS(ioc, res_idx, mask, 8);
  409. #else
  410. CCIO_FREE_MAPPINGS(ioc, res_idx, 0xffUL, 8);
  411. #endif
  412. } else if(pages_mapped <= 16) {
  413. CCIO_FREE_MAPPINGS(ioc, res_idx, 0xffffUL, 16);
  414. } else if(pages_mapped <= 32) {
  415. CCIO_FREE_MAPPINGS(ioc, res_idx, ~(unsigned int)0, 32);
  416. #ifdef __LP64__
  417. } else if(pages_mapped <= 64) {
  418. CCIO_FREE_MAPPINGS(ioc, res_idx, ~0UL, 64);
  419. #endif
  420. } else {
  421. panic("%s:%s() Too many pages to unmap.\n", __FILE__,
  422. __func__);
  423. }
  424. }
  425. /****************************************************************
  426. **
  427. ** CCIO dma_ops support routines
  428. **
  429. *****************************************************************/
  430. typedef unsigned long space_t;
  431. #define KERNEL_SPACE 0
  432. /*
  433. ** DMA "Page Type" and Hints
  434. ** o if SAFE_DMA isn't set, mapping is for FAST_DMA. SAFE_DMA should be
  435. ** set for subcacheline DMA transfers since we don't want to damage the
  436. ** other part of a cacheline.
  437. ** o SAFE_DMA must be set for "memory" allocated via pci_alloc_consistent().
  438. ** This bit tells U2 to do R/M/W for partial cachelines. "Streaming"
  439. ** data can avoid this if the mapping covers full cache lines.
  440. ** o STOP_MOST is needed for atomicity across cachelines.
  441. ** Apparently only "some EISA devices" need this.
  442. ** Using CONFIG_ISA is hack. Only the IOA with EISA under it needs
  443. ** to use this hint iff the EISA devices needs this feature.
  444. ** According to the U2 ERS, STOP_MOST enabled pages hurt performance.
  445. ** o PREFETCH should *not* be set for cases like Multiple PCI devices
  446. ** behind GSCtoPCI (dino) bus converter. Only one cacheline per GSC
  447. ** device can be fetched and multiply DMA streams will thrash the
  448. ** prefetch buffer and burn memory bandwidth. See 6.7.3 "Prefetch Rules
  449. ** and Invalidation of Prefetch Entries".
  450. **
  451. ** FIXME: the default hints need to be per GSC device - not global.
  452. **
  453. ** HP-UX dorks: linux device driver programming model is totally different
  454. ** than HP-UX's. HP-UX always sets HINT_PREFETCH since it's drivers
  455. ** do special things to work on non-coherent platforms...linux has to
  456. ** be much more careful with this.
  457. */
  458. #define IOPDIR_VALID 0x01UL
  459. #define HINT_SAFE_DMA 0x02UL /* used for pci_alloc_consistent() pages */
  460. #ifdef CONFIG_EISA
  461. #define HINT_STOP_MOST 0x04UL /* LSL support */
  462. #else
  463. #define HINT_STOP_MOST 0x00UL /* only needed for "some EISA devices" */
  464. #endif
  465. #define HINT_UDPATE_ENB 0x08UL /* not used/supported by U2 */
  466. #define HINT_PREFETCH 0x10UL /* for outbound pages which are not SAFE */
  467. /*
  468. ** Use direction (ie PCI_DMA_TODEVICE) to pick hint.
  469. ** ccio_alloc_consistent() depends on this to get SAFE_DMA
  470. ** when it passes in BIDIRECTIONAL flag.
  471. */
  472. static u32 hint_lookup[] = {
  473. [PCI_DMA_BIDIRECTIONAL] = HINT_STOP_MOST | HINT_SAFE_DMA | IOPDIR_VALID,
  474. [PCI_DMA_TODEVICE] = HINT_STOP_MOST | HINT_PREFETCH | IOPDIR_VALID,
  475. [PCI_DMA_FROMDEVICE] = HINT_STOP_MOST | IOPDIR_VALID,
  476. };
  477. /**
  478. * ccio_io_pdir_entry - Initialize an I/O Pdir.
  479. * @pdir_ptr: A pointer into I/O Pdir.
  480. * @sid: The Space Identifier.
  481. * @vba: The virtual address.
  482. * @hints: The DMA Hint.
  483. *
  484. * Given a virtual address (vba, arg2) and space id, (sid, arg1),
  485. * load the I/O PDIR entry pointed to by pdir_ptr (arg0). Each IO Pdir
  486. * entry consists of 8 bytes as shown below (MSB == bit 0):
  487. *
  488. *
  489. * WORD 0:
  490. * +------+----------------+-----------------------------------------------+
  491. * | Phys | Virtual Index | Phys |
  492. * | 0:3 | 0:11 | 4:19 |
  493. * |4 bits| 12 bits | 16 bits |
  494. * +------+----------------+-----------------------------------------------+
  495. * WORD 1:
  496. * +-----------------------+-----------------------------------------------+
  497. * | Phys | Rsvd | Prefetch |Update |Rsvd |Lock |Safe |Valid |
  498. * | 20:39 | | Enable |Enable | |Enable|DMA | |
  499. * | 20 bits | 5 bits | 1 bit |1 bit |2 bits|1 bit |1 bit |1 bit |
  500. * +-----------------------+-----------------------------------------------+
  501. *
  502. * The virtual index field is filled with the results of the LCI
  503. * (Load Coherence Index) instruction. The 8 bits used for the virtual
  504. * index are bits 12:19 of the value returned by LCI.
  505. */
  506. static void CCIO_INLINE
  507. ccio_io_pdir_entry(u64 *pdir_ptr, space_t sid, unsigned long vba,
  508. unsigned long hints)
  509. {
  510. register unsigned long pa;
  511. register unsigned long ci; /* coherent index */
  512. /* We currently only support kernel addresses */
  513. BUG_ON(sid != KERNEL_SPACE);
  514. /*
  515. ** WORD 1 - low order word
  516. ** "hints" parm includes the VALID bit!
  517. ** "dep" clobbers the physical address offset bits as well.
  518. */
  519. pa = lpa(vba);
  520. asm volatile("depw %1,31,12,%0" : "+r" (pa) : "r" (hints));
  521. ((u32 *)pdir_ptr)[1] = (u32) pa;
  522. /*
  523. ** WORD 0 - high order word
  524. */
  525. #ifdef __LP64__
  526. /*
  527. ** get bits 12:15 of physical address
  528. ** shift bits 16:31 of physical address
  529. ** and deposit them
  530. */
  531. asm volatile ("extrd,u %1,15,4,%0" : "=r" (ci) : "r" (pa));
  532. asm volatile ("extrd,u %1,31,16,%0" : "+r" (pa) : "r" (pa));
  533. asm volatile ("depd %1,35,4,%0" : "+r" (pa) : "r" (ci));
  534. #else
  535. pa = 0;
  536. #endif
  537. /*
  538. ** get CPU coherency index bits
  539. ** Grab virtual index [0:11]
  540. ** Deposit virt_idx bits into I/O PDIR word
  541. */
  542. asm volatile ("lci %%r0(%1), %0" : "=r" (ci) : "r" (vba));
  543. asm volatile ("extru %1,19,12,%0" : "+r" (ci) : "r" (ci));
  544. asm volatile ("depw %1,15,12,%0" : "+r" (pa) : "r" (ci));
  545. ((u32 *)pdir_ptr)[0] = (u32) pa;
  546. /* FIXME: PCX_W platforms don't need FDC/SYNC. (eg C360)
  547. ** PCX-U/U+ do. (eg C200/C240)
  548. ** PCX-T'? Don't know. (eg C110 or similar K-class)
  549. **
  550. ** See PDC_MODEL/option 0/SW_CAP word for "Non-coherent IO-PDIR bit".
  551. **
  552. ** "Since PCX-U employs an offset hash that is incompatible with
  553. ** the real mode coherence index generation of U2, the PDIR entry
  554. ** must be flushed to memory to retain coherence."
  555. */
  556. asm_io_fdc(pdir_ptr);
  557. asm_io_sync();
  558. }
  559. /**
  560. * ccio_clear_io_tlb - Remove stale entries from the I/O TLB.
  561. * @ioc: The I/O Controller.
  562. * @iovp: The I/O Virtual Page.
  563. * @byte_cnt: The requested number of bytes to be freed from the I/O Pdir.
  564. *
  565. * Purge invalid I/O PDIR entries from the I/O TLB.
  566. *
  567. * FIXME: Can we change the byte_cnt to pages_mapped?
  568. */
  569. static CCIO_INLINE void
  570. ccio_clear_io_tlb(struct ioc *ioc, dma_addr_t iovp, size_t byte_cnt)
  571. {
  572. u32 chain_size = 1 << ioc->chainid_shift;
  573. iovp &= IOVP_MASK; /* clear offset bits, just want pagenum */
  574. byte_cnt += chain_size;
  575. while(byte_cnt > chain_size) {
  576. WRITE_U32(CMD_TLB_PURGE | iovp, &ioc->ioc_regs->io_command);
  577. iovp += chain_size;
  578. byte_cnt -= chain_size;
  579. }
  580. }
  581. /**
  582. * ccio_mark_invalid - Mark the I/O Pdir entries invalid.
  583. * @ioc: The I/O Controller.
  584. * @iova: The I/O Virtual Address.
  585. * @byte_cnt: The requested number of bytes to be freed from the I/O Pdir.
  586. *
  587. * Mark the I/O Pdir entries invalid and blow away the corresponding I/O
  588. * TLB entries.
  589. *
  590. * FIXME: at some threshold it might be "cheaper" to just blow
  591. * away the entire I/O TLB instead of individual entries.
  592. *
  593. * FIXME: Uturn has 256 TLB entries. We don't need to purge every
  594. * PDIR entry - just once for each possible TLB entry.
  595. * (We do need to maker I/O PDIR entries invalid regardless).
  596. *
  597. * FIXME: Can we change byte_cnt to pages_mapped?
  598. */
  599. static CCIO_INLINE void
  600. ccio_mark_invalid(struct ioc *ioc, dma_addr_t iova, size_t byte_cnt)
  601. {
  602. u32 iovp = (u32)CCIO_IOVP(iova);
  603. size_t saved_byte_cnt;
  604. /* round up to nearest page size */
  605. saved_byte_cnt = byte_cnt = ALIGN(byte_cnt, IOVP_SIZE);
  606. while(byte_cnt > 0) {
  607. /* invalidate one page at a time */
  608. unsigned int idx = PDIR_INDEX(iovp);
  609. char *pdir_ptr = (char *) &(ioc->pdir_base[idx]);
  610. BUG_ON(idx >= (ioc->pdir_size / sizeof(u64)));
  611. pdir_ptr[7] = 0; /* clear only VALID bit */
  612. /*
  613. ** FIXME: PCX_W platforms don't need FDC/SYNC. (eg C360)
  614. ** PCX-U/U+ do. (eg C200/C240)
  615. ** See PDC_MODEL/option 0/SW_CAP for "Non-coherent IO-PDIR bit".
  616. */
  617. asm_io_fdc(pdir_ptr);
  618. iovp += IOVP_SIZE;
  619. byte_cnt -= IOVP_SIZE;
  620. }
  621. asm_io_sync();
  622. ccio_clear_io_tlb(ioc, CCIO_IOVP(iova), saved_byte_cnt);
  623. }
  624. /****************************************************************
  625. **
  626. ** CCIO dma_ops
  627. **
  628. *****************************************************************/
  629. /**
  630. * ccio_dma_supported - Verify the IOMMU supports the DMA address range.
  631. * @dev: The PCI device.
  632. * @mask: A bit mask describing the DMA address range of the device.
  633. */
  634. static int
  635. ccio_dma_supported(struct device *dev, u64 mask)
  636. {
  637. if(dev == NULL) {
  638. printk(KERN_ERR MODULE_NAME ": EISA/ISA/et al not supported\n");
  639. BUG();
  640. return 0;
  641. }
  642. /* only support 32-bit or better devices (ie PCI/GSC) */
  643. return (int)(mask >= 0xffffffffUL);
  644. }
  645. /**
  646. * ccio_map_single - Map an address range into the IOMMU.
  647. * @dev: The PCI device.
  648. * @addr: The start address of the DMA region.
  649. * @size: The length of the DMA region.
  650. * @direction: The direction of the DMA transaction (to/from device).
  651. *
  652. * This function implements the pci_map_single function.
  653. */
  654. static dma_addr_t
  655. ccio_map_single(struct device *dev, void *addr, size_t size,
  656. enum dma_data_direction direction)
  657. {
  658. int idx;
  659. struct ioc *ioc;
  660. unsigned long flags;
  661. dma_addr_t iovp;
  662. dma_addr_t offset;
  663. u64 *pdir_start;
  664. unsigned long hint = hint_lookup[(int)direction];
  665. BUG_ON(!dev);
  666. ioc = GET_IOC(dev);
  667. if (!ioc)
  668. return DMA_MAPPING_ERROR;
  669. BUG_ON(size <= 0);
  670. /* save offset bits */
  671. offset = ((unsigned long) addr) & ~IOVP_MASK;
  672. /* round up to nearest IOVP_SIZE */
  673. size = ALIGN(size + offset, IOVP_SIZE);
  674. spin_lock_irqsave(&ioc->res_lock, flags);
  675. #ifdef CCIO_COLLECT_STATS
  676. ioc->msingle_calls++;
  677. ioc->msingle_pages += size >> IOVP_SHIFT;
  678. #endif
  679. idx = ccio_alloc_range(ioc, dev, size);
  680. iovp = (dma_addr_t)MKIOVP(idx);
  681. pdir_start = &(ioc->pdir_base[idx]);
  682. DBG_RUN("%s() 0x%p -> 0x%lx size: %0x%x\n",
  683. __func__, addr, (long)iovp | offset, size);
  684. /* If not cacheline aligned, force SAFE_DMA on the whole mess */
  685. if((size % L1_CACHE_BYTES) || ((unsigned long)addr % L1_CACHE_BYTES))
  686. hint |= HINT_SAFE_DMA;
  687. while(size > 0) {
  688. ccio_io_pdir_entry(pdir_start, KERNEL_SPACE, (unsigned long)addr, hint);
  689. DBG_RUN(" pdir %p %08x%08x\n",
  690. pdir_start,
  691. (u32) (((u32 *) pdir_start)[0]),
  692. (u32) (((u32 *) pdir_start)[1]));
  693. ++pdir_start;
  694. addr += IOVP_SIZE;
  695. size -= IOVP_SIZE;
  696. }
  697. spin_unlock_irqrestore(&ioc->res_lock, flags);
  698. /* form complete address */
  699. return CCIO_IOVA(iovp, offset);
  700. }
  701. static dma_addr_t
  702. ccio_map_page(struct device *dev, struct page *page, unsigned long offset,
  703. size_t size, enum dma_data_direction direction,
  704. unsigned long attrs)
  705. {
  706. return ccio_map_single(dev, page_address(page) + offset, size,
  707. direction);
  708. }
  709. /**
  710. * ccio_unmap_page - Unmap an address range from the IOMMU.
  711. * @dev: The PCI device.
  712. * @addr: The start address of the DMA region.
  713. * @size: The length of the DMA region.
  714. * @direction: The direction of the DMA transaction (to/from device).
  715. */
  716. static void
  717. ccio_unmap_page(struct device *dev, dma_addr_t iova, size_t size,
  718. enum dma_data_direction direction, unsigned long attrs)
  719. {
  720. struct ioc *ioc;
  721. unsigned long flags;
  722. dma_addr_t offset = iova & ~IOVP_MASK;
  723. BUG_ON(!dev);
  724. ioc = GET_IOC(dev);
  725. if (!ioc) {
  726. WARN_ON(!ioc);
  727. return;
  728. }
  729. DBG_RUN("%s() iovp 0x%lx/%x\n",
  730. __func__, (long)iova, size);
  731. iova ^= offset; /* clear offset bits */
  732. size += offset;
  733. size = ALIGN(size, IOVP_SIZE);
  734. spin_lock_irqsave(&ioc->res_lock, flags);
  735. #ifdef CCIO_COLLECT_STATS
  736. ioc->usingle_calls++;
  737. ioc->usingle_pages += size >> IOVP_SHIFT;
  738. #endif
  739. ccio_mark_invalid(ioc, iova, size);
  740. ccio_free_range(ioc, iova, (size >> IOVP_SHIFT));
  741. spin_unlock_irqrestore(&ioc->res_lock, flags);
  742. }
  743. /**
  744. * ccio_alloc - Allocate a consistent DMA mapping.
  745. * @dev: The PCI device.
  746. * @size: The length of the DMA region.
  747. * @dma_handle: The DMA address handed back to the device (not the cpu).
  748. *
  749. * This function implements the pci_alloc_consistent function.
  750. */
  751. static void *
  752. ccio_alloc(struct device *dev, size_t size, dma_addr_t *dma_handle, gfp_t flag,
  753. unsigned long attrs)
  754. {
  755. void *ret;
  756. #if 0
  757. /* GRANT Need to establish hierarchy for non-PCI devs as well
  758. ** and then provide matching gsc_map_xxx() functions for them as well.
  759. */
  760. if(!hwdev) {
  761. /* only support PCI */
  762. *dma_handle = 0;
  763. return 0;
  764. }
  765. #endif
  766. ret = (void *) __get_free_pages(flag, get_order(size));
  767. if (ret) {
  768. memset(ret, 0, size);
  769. *dma_handle = ccio_map_single(dev, ret, size, PCI_DMA_BIDIRECTIONAL);
  770. }
  771. return ret;
  772. }
  773. /**
  774. * ccio_free - Free a consistent DMA mapping.
  775. * @dev: The PCI device.
  776. * @size: The length of the DMA region.
  777. * @cpu_addr: The cpu address returned from the ccio_alloc_consistent.
  778. * @dma_handle: The device address returned from the ccio_alloc_consistent.
  779. *
  780. * This function implements the pci_free_consistent function.
  781. */
  782. static void
  783. ccio_free(struct device *dev, size_t size, void *cpu_addr,
  784. dma_addr_t dma_handle, unsigned long attrs)
  785. {
  786. ccio_unmap_page(dev, dma_handle, size, 0, 0);
  787. free_pages((unsigned long)cpu_addr, get_order(size));
  788. }
  789. /*
  790. ** Since 0 is a valid pdir_base index value, can't use that
  791. ** to determine if a value is valid or not. Use a flag to indicate
  792. ** the SG list entry contains a valid pdir index.
  793. */
  794. #define PIDE_FLAG 0x80000000UL
  795. #ifdef CCIO_COLLECT_STATS
  796. #define IOMMU_MAP_STATS
  797. #endif
  798. #include "iommu-helpers.h"
  799. /**
  800. * ccio_map_sg - Map the scatter/gather list into the IOMMU.
  801. * @dev: The PCI device.
  802. * @sglist: The scatter/gather list to be mapped in the IOMMU.
  803. * @nents: The number of entries in the scatter/gather list.
  804. * @direction: The direction of the DMA transaction (to/from device).
  805. *
  806. * This function implements the pci_map_sg function.
  807. */
  808. static int
  809. ccio_map_sg(struct device *dev, struct scatterlist *sglist, int nents,
  810. enum dma_data_direction direction, unsigned long attrs)
  811. {
  812. struct ioc *ioc;
  813. int coalesced, filled = 0;
  814. unsigned long flags;
  815. unsigned long hint = hint_lookup[(int)direction];
  816. unsigned long prev_len = 0, current_len = 0;
  817. int i;
  818. BUG_ON(!dev);
  819. ioc = GET_IOC(dev);
  820. if (!ioc)
  821. return 0;
  822. DBG_RUN_SG("%s() START %d entries\n", __func__, nents);
  823. /* Fast path single entry scatterlists. */
  824. if (nents == 1) {
  825. sg_dma_address(sglist) = ccio_map_single(dev,
  826. sg_virt(sglist), sglist->length,
  827. direction);
  828. sg_dma_len(sglist) = sglist->length;
  829. return 1;
  830. }
  831. for(i = 0; i < nents; i++)
  832. prev_len += sglist[i].length;
  833. spin_lock_irqsave(&ioc->res_lock, flags);
  834. #ifdef CCIO_COLLECT_STATS
  835. ioc->msg_calls++;
  836. #endif
  837. /*
  838. ** First coalesce the chunks and allocate I/O pdir space
  839. **
  840. ** If this is one DMA stream, we can properly map using the
  841. ** correct virtual address associated with each DMA page.
  842. ** w/o this association, we wouldn't have coherent DMA!
  843. ** Access to the virtual address is what forces a two pass algorithm.
  844. */
  845. coalesced = iommu_coalesce_chunks(ioc, dev, sglist, nents, ccio_alloc_range);
  846. /*
  847. ** Program the I/O Pdir
  848. **
  849. ** map the virtual addresses to the I/O Pdir
  850. ** o dma_address will contain the pdir index
  851. ** o dma_len will contain the number of bytes to map
  852. ** o page/offset contain the virtual address.
  853. */
  854. filled = iommu_fill_pdir(ioc, sglist, nents, hint, ccio_io_pdir_entry);
  855. spin_unlock_irqrestore(&ioc->res_lock, flags);
  856. BUG_ON(coalesced != filled);
  857. DBG_RUN_SG("%s() DONE %d mappings\n", __func__, filled);
  858. for (i = 0; i < filled; i++)
  859. current_len += sg_dma_len(sglist + i);
  860. BUG_ON(current_len != prev_len);
  861. return filled;
  862. }
  863. /**
  864. * ccio_unmap_sg - Unmap the scatter/gather list from the IOMMU.
  865. * @dev: The PCI device.
  866. * @sglist: The scatter/gather list to be unmapped from the IOMMU.
  867. * @nents: The number of entries in the scatter/gather list.
  868. * @direction: The direction of the DMA transaction (to/from device).
  869. *
  870. * This function implements the pci_unmap_sg function.
  871. */
  872. static void
  873. ccio_unmap_sg(struct device *dev, struct scatterlist *sglist, int nents,
  874. enum dma_data_direction direction, unsigned long attrs)
  875. {
  876. struct ioc *ioc;
  877. BUG_ON(!dev);
  878. ioc = GET_IOC(dev);
  879. if (!ioc) {
  880. WARN_ON(!ioc);
  881. return;
  882. }
  883. DBG_RUN_SG("%s() START %d entries, %p,%x\n",
  884. __func__, nents, sg_virt(sglist), sglist->length);
  885. #ifdef CCIO_COLLECT_STATS
  886. ioc->usg_calls++;
  887. #endif
  888. while (nents && sg_dma_len(sglist)) {
  889. #ifdef CCIO_COLLECT_STATS
  890. ioc->usg_pages += sg_dma_len(sglist) >> PAGE_SHIFT;
  891. #endif
  892. ccio_unmap_page(dev, sg_dma_address(sglist),
  893. sg_dma_len(sglist), direction, 0);
  894. ++sglist;
  895. nents--;
  896. }
  897. DBG_RUN_SG("%s() DONE (nents %d)\n", __func__, nents);
  898. }
  899. static const struct dma_map_ops ccio_ops = {
  900. .dma_supported = ccio_dma_supported,
  901. .alloc = ccio_alloc,
  902. .free = ccio_free,
  903. .map_page = ccio_map_page,
  904. .unmap_page = ccio_unmap_page,
  905. .map_sg = ccio_map_sg,
  906. .unmap_sg = ccio_unmap_sg,
  907. .get_sgtable = dma_common_get_sgtable,
  908. .alloc_pages = dma_common_alloc_pages,
  909. .free_pages = dma_common_free_pages,
  910. };
  911. #ifdef CONFIG_PROC_FS
  912. static int ccio_proc_info(struct seq_file *m, void *p)
  913. {
  914. struct ioc *ioc = ioc_list;
  915. while (ioc != NULL) {
  916. unsigned int total_pages = ioc->res_size << 3;
  917. #ifdef CCIO_COLLECT_STATS
  918. unsigned long avg = 0, min, max;
  919. int j;
  920. #endif
  921. seq_printf(m, "%s\n", ioc->name);
  922. seq_printf(m, "Cujo 2.0 bug : %s\n",
  923. (ioc->cujo20_bug ? "yes" : "no"));
  924. seq_printf(m, "IO PDIR size : %d bytes (%d entries)\n",
  925. total_pages * 8, total_pages);
  926. #ifdef CCIO_COLLECT_STATS
  927. seq_printf(m, "IO PDIR entries : %ld free %ld used (%d%%)\n",
  928. total_pages - ioc->used_pages, ioc->used_pages,
  929. (int)(ioc->used_pages * 100 / total_pages));
  930. #endif
  931. seq_printf(m, "Resource bitmap : %d bytes (%d pages)\n",
  932. ioc->res_size, total_pages);
  933. #ifdef CCIO_COLLECT_STATS
  934. min = max = ioc->avg_search[0];
  935. for(j = 0; j < CCIO_SEARCH_SAMPLE; ++j) {
  936. avg += ioc->avg_search[j];
  937. if(ioc->avg_search[j] > max)
  938. max = ioc->avg_search[j];
  939. if(ioc->avg_search[j] < min)
  940. min = ioc->avg_search[j];
  941. }
  942. avg /= CCIO_SEARCH_SAMPLE;
  943. seq_printf(m, " Bitmap search : %ld/%ld/%ld (min/avg/max CPU Cycles)\n",
  944. min, avg, max);
  945. seq_printf(m, "pci_map_single(): %8ld calls %8ld pages (avg %d/1000)\n",
  946. ioc->msingle_calls, ioc->msingle_pages,
  947. (int)((ioc->msingle_pages * 1000)/ioc->msingle_calls));
  948. /* KLUGE - unmap_sg calls unmap_page for each mapped page */
  949. min = ioc->usingle_calls - ioc->usg_calls;
  950. max = ioc->usingle_pages - ioc->usg_pages;
  951. seq_printf(m, "pci_unmap_single: %8ld calls %8ld pages (avg %d/1000)\n",
  952. min, max, (int)((max * 1000)/min));
  953. seq_printf(m, "pci_map_sg() : %8ld calls %8ld pages (avg %d/1000)\n",
  954. ioc->msg_calls, ioc->msg_pages,
  955. (int)((ioc->msg_pages * 1000)/ioc->msg_calls));
  956. seq_printf(m, "pci_unmap_sg() : %8ld calls %8ld pages (avg %d/1000)\n\n\n",
  957. ioc->usg_calls, ioc->usg_pages,
  958. (int)((ioc->usg_pages * 1000)/ioc->usg_calls));
  959. #endif /* CCIO_COLLECT_STATS */
  960. ioc = ioc->next;
  961. }
  962. return 0;
  963. }
  964. static int ccio_proc_bitmap_info(struct seq_file *m, void *p)
  965. {
  966. struct ioc *ioc = ioc_list;
  967. while (ioc != NULL) {
  968. seq_hex_dump(m, " ", DUMP_PREFIX_NONE, 32, 4, ioc->res_map,
  969. ioc->res_size, false);
  970. seq_putc(m, '\n');
  971. ioc = ioc->next;
  972. break; /* XXX - remove me */
  973. }
  974. return 0;
  975. }
  976. #endif /* CONFIG_PROC_FS */
  977. /**
  978. * ccio_find_ioc - Find the ioc in the ioc_list
  979. * @hw_path: The hardware path of the ioc.
  980. *
  981. * This function searches the ioc_list for an ioc that matches
  982. * the provide hardware path.
  983. */
  984. static struct ioc * ccio_find_ioc(int hw_path)
  985. {
  986. int i;
  987. struct ioc *ioc;
  988. ioc = ioc_list;
  989. for (i = 0; i < ioc_count; i++) {
  990. if (ioc->hw_path == hw_path)
  991. return ioc;
  992. ioc = ioc->next;
  993. }
  994. return NULL;
  995. }
  996. /**
  997. * ccio_get_iommu - Find the iommu which controls this device
  998. * @dev: The parisc device.
  999. *
  1000. * This function searches through the registered IOMMU's and returns
  1001. * the appropriate IOMMU for the device based on its hardware path.
  1002. */
  1003. void * ccio_get_iommu(const struct parisc_device *dev)
  1004. {
  1005. dev = find_pa_parent_type(dev, HPHW_IOA);
  1006. if (!dev)
  1007. return NULL;
  1008. return ccio_find_ioc(dev->hw_path);
  1009. }
  1010. #define CUJO_20_STEP 0x10000000 /* inc upper nibble */
  1011. /* Cujo 2.0 has a bug which will silently corrupt data being transferred
  1012. * to/from certain pages. To avoid this happening, we mark these pages
  1013. * as `used', and ensure that nothing will try to allocate from them.
  1014. */
  1015. void __init ccio_cujo20_fixup(struct parisc_device *cujo, u32 iovp)
  1016. {
  1017. unsigned int idx;
  1018. struct parisc_device *dev = parisc_parent(cujo);
  1019. struct ioc *ioc = ccio_get_iommu(dev);
  1020. u8 *res_ptr;
  1021. ioc->cujo20_bug = 1;
  1022. res_ptr = ioc->res_map;
  1023. idx = PDIR_INDEX(iovp) >> 3;
  1024. while (idx < ioc->res_size) {
  1025. res_ptr[idx] |= 0xff;
  1026. idx += PDIR_INDEX(CUJO_20_STEP) >> 3;
  1027. }
  1028. }
  1029. #if 0
  1030. /* GRANT - is this needed for U2 or not? */
  1031. /*
  1032. ** Get the size of the I/O TLB for this I/O MMU.
  1033. **
  1034. ** If spa_shift is non-zero (ie probably U2),
  1035. ** then calculate the I/O TLB size using spa_shift.
  1036. **
  1037. ** Otherwise we are supposed to get the IODC entry point ENTRY TLB
  1038. ** and execute it. However, both U2 and Uturn firmware supplies spa_shift.
  1039. ** I think only Java (K/D/R-class too?) systems don't do this.
  1040. */
  1041. static int
  1042. ccio_get_iotlb_size(struct parisc_device *dev)
  1043. {
  1044. if (dev->spa_shift == 0) {
  1045. panic("%s() : Can't determine I/O TLB size.\n", __func__);
  1046. }
  1047. return (1 << dev->spa_shift);
  1048. }
  1049. #else
  1050. /* Uturn supports 256 TLB entries */
  1051. #define CCIO_CHAINID_SHIFT 8
  1052. #define CCIO_CHAINID_MASK 0xff
  1053. #endif /* 0 */
  1054. /* We *can't* support JAVA (T600). Venture there at your own risk. */
  1055. static const struct parisc_device_id ccio_tbl[] __initconst = {
  1056. { HPHW_IOA, HVERSION_REV_ANY_ID, U2_IOA_RUNWAY, 0xb }, /* U2 */
  1057. { HPHW_IOA, HVERSION_REV_ANY_ID, UTURN_IOA_RUNWAY, 0xb }, /* UTurn */
  1058. { 0, }
  1059. };
  1060. static int ccio_probe(struct parisc_device *dev);
  1061. static struct parisc_driver ccio_driver __refdata = {
  1062. .name = "ccio",
  1063. .id_table = ccio_tbl,
  1064. .probe = ccio_probe,
  1065. };
  1066. /**
  1067. * ccio_ioc_init - Initialize the I/O Controller
  1068. * @ioc: The I/O Controller.
  1069. *
  1070. * Initialize the I/O Controller which includes setting up the
  1071. * I/O Page Directory, the resource map, and initalizing the
  1072. * U2/Uturn chip into virtual mode.
  1073. */
  1074. static void __init
  1075. ccio_ioc_init(struct ioc *ioc)
  1076. {
  1077. int i;
  1078. unsigned int iov_order;
  1079. u32 iova_space_size;
  1080. /*
  1081. ** Determine IOVA Space size from memory size.
  1082. **
  1083. ** Ideally, PCI drivers would register the maximum number
  1084. ** of DMA they can have outstanding for each device they
  1085. ** own. Next best thing would be to guess how much DMA
  1086. ** can be outstanding based on PCI Class/sub-class. Both
  1087. ** methods still require some "extra" to support PCI
  1088. ** Hot-Plug/Removal of PCI cards. (aka PCI OLARD).
  1089. */
  1090. iova_space_size = (u32) (totalram_pages() / count_parisc_driver(&ccio_driver));
  1091. /* limit IOVA space size to 1MB-1GB */
  1092. if (iova_space_size < (1 << (20 - PAGE_SHIFT))) {
  1093. iova_space_size = 1 << (20 - PAGE_SHIFT);
  1094. #ifdef __LP64__
  1095. } else if (iova_space_size > (1 << (30 - PAGE_SHIFT))) {
  1096. iova_space_size = 1 << (30 - PAGE_SHIFT);
  1097. #endif
  1098. }
  1099. /*
  1100. ** iova space must be log2() in size.
  1101. ** thus, pdir/res_map will also be log2().
  1102. */
  1103. /* We could use larger page sizes in order to *decrease* the number
  1104. ** of mappings needed. (ie 8k pages means 1/2 the mappings).
  1105. **
  1106. ** Note: Grant Grunder says "Using 8k I/O pages isn't trivial either
  1107. ** since the pages must also be physically contiguous - typically
  1108. ** this is the case under linux."
  1109. */
  1110. iov_order = get_order(iova_space_size << PAGE_SHIFT);
  1111. /* iova_space_size is now bytes, not pages */
  1112. iova_space_size = 1 << (iov_order + PAGE_SHIFT);
  1113. ioc->pdir_size = (iova_space_size / IOVP_SIZE) * sizeof(u64);
  1114. BUG_ON(ioc->pdir_size > 8 * 1024 * 1024); /* max pdir size <= 8MB */
  1115. /* Verify it's a power of two */
  1116. BUG_ON((1 << get_order(ioc->pdir_size)) != (ioc->pdir_size >> PAGE_SHIFT));
  1117. DBG_INIT("%s() hpa 0x%p mem %luMB IOV %dMB (%d bits)\n",
  1118. __func__, ioc->ioc_regs,
  1119. (unsigned long) totalram_pages() >> (20 - PAGE_SHIFT),
  1120. iova_space_size>>20,
  1121. iov_order + PAGE_SHIFT);
  1122. ioc->pdir_base = (u64 *)__get_free_pages(GFP_KERNEL,
  1123. get_order(ioc->pdir_size));
  1124. if(NULL == ioc->pdir_base) {
  1125. panic("%s() could not allocate I/O Page Table\n", __func__);
  1126. }
  1127. memset(ioc->pdir_base, 0, ioc->pdir_size);
  1128. BUG_ON((((unsigned long)ioc->pdir_base) & PAGE_MASK) != (unsigned long)ioc->pdir_base);
  1129. DBG_INIT(" base %p\n", ioc->pdir_base);
  1130. /* resource map size dictated by pdir_size */
  1131. ioc->res_size = (ioc->pdir_size / sizeof(u64)) >> 3;
  1132. DBG_INIT("%s() res_size 0x%x\n", __func__, ioc->res_size);
  1133. ioc->res_map = (u8 *)__get_free_pages(GFP_KERNEL,
  1134. get_order(ioc->res_size));
  1135. if(NULL == ioc->res_map) {
  1136. panic("%s() could not allocate resource map\n", __func__);
  1137. }
  1138. memset(ioc->res_map, 0, ioc->res_size);
  1139. /* Initialize the res_hint to 16 */
  1140. ioc->res_hint = 16;
  1141. /* Initialize the spinlock */
  1142. spin_lock_init(&ioc->res_lock);
  1143. /*
  1144. ** Chainid is the upper most bits of an IOVP used to determine
  1145. ** which TLB entry an IOVP will use.
  1146. */
  1147. ioc->chainid_shift = get_order(iova_space_size) + PAGE_SHIFT - CCIO_CHAINID_SHIFT;
  1148. DBG_INIT(" chainid_shift 0x%x\n", ioc->chainid_shift);
  1149. /*
  1150. ** Initialize IOA hardware
  1151. */
  1152. WRITE_U32(CCIO_CHAINID_MASK << ioc->chainid_shift,
  1153. &ioc->ioc_regs->io_chain_id_mask);
  1154. WRITE_U32(virt_to_phys(ioc->pdir_base),
  1155. &ioc->ioc_regs->io_pdir_base);
  1156. /*
  1157. ** Go to "Virtual Mode"
  1158. */
  1159. WRITE_U32(IOA_NORMAL_MODE, &ioc->ioc_regs->io_control);
  1160. /*
  1161. ** Initialize all I/O TLB entries to 0 (Valid bit off).
  1162. */
  1163. WRITE_U32(0, &ioc->ioc_regs->io_tlb_entry_m);
  1164. WRITE_U32(0, &ioc->ioc_regs->io_tlb_entry_l);
  1165. for(i = 1 << CCIO_CHAINID_SHIFT; i ; i--) {
  1166. WRITE_U32((CMD_TLB_DIRECT_WRITE | (i << ioc->chainid_shift)),
  1167. &ioc->ioc_regs->io_command);
  1168. }
  1169. }
  1170. static void __init
  1171. ccio_init_resource(struct resource *res, char *name, void __iomem *ioaddr)
  1172. {
  1173. int result;
  1174. res->parent = NULL;
  1175. res->flags = IORESOURCE_MEM;
  1176. /*
  1177. * bracing ((signed) ...) are required for 64bit kernel because
  1178. * we only want to sign extend the lower 16 bits of the register.
  1179. * The upper 16-bits of range registers are hardcoded to 0xffff.
  1180. */
  1181. res->start = (unsigned long)((signed) READ_U32(ioaddr) << 16);
  1182. res->end = (unsigned long)((signed) (READ_U32(ioaddr + 4) << 16) - 1);
  1183. res->name = name;
  1184. /*
  1185. * Check if this MMIO range is disable
  1186. */
  1187. if (res->end + 1 == res->start)
  1188. return;
  1189. /* On some platforms (e.g. K-Class), we have already registered
  1190. * resources for devices reported by firmware. Some are children
  1191. * of ccio.
  1192. * "insert" ccio ranges in the mmio hierarchy (/proc/iomem).
  1193. */
  1194. result = insert_resource(&iomem_resource, res);
  1195. if (result < 0) {
  1196. printk(KERN_ERR "%s() failed to claim CCIO bus address space (%08lx,%08lx)\n",
  1197. __func__, (unsigned long)res->start, (unsigned long)res->end);
  1198. }
  1199. }
  1200. static void __init ccio_init_resources(struct ioc *ioc)
  1201. {
  1202. struct resource *res = ioc->mmio_region;
  1203. char *name = kmalloc(14, GFP_KERNEL);
  1204. snprintf(name, 14, "GSC Bus [%d/]", ioc->hw_path);
  1205. ccio_init_resource(res, name, &ioc->ioc_regs->io_io_low);
  1206. ccio_init_resource(res + 1, name, &ioc->ioc_regs->io_io_low_hv);
  1207. }
  1208. static int new_ioc_area(struct resource *res, unsigned long size,
  1209. unsigned long min, unsigned long max, unsigned long align)
  1210. {
  1211. if (max <= min)
  1212. return -EBUSY;
  1213. res->start = (max - size + 1) &~ (align - 1);
  1214. res->end = res->start + size;
  1215. /* We might be trying to expand the MMIO range to include
  1216. * a child device that has already registered it's MMIO space.
  1217. * Use "insert" instead of request_resource().
  1218. */
  1219. if (!insert_resource(&iomem_resource, res))
  1220. return 0;
  1221. return new_ioc_area(res, size, min, max - size, align);
  1222. }
  1223. static int expand_ioc_area(struct resource *res, unsigned long size,
  1224. unsigned long min, unsigned long max, unsigned long align)
  1225. {
  1226. unsigned long start, len;
  1227. if (!res->parent)
  1228. return new_ioc_area(res, size, min, max, align);
  1229. start = (res->start - size) &~ (align - 1);
  1230. len = res->end - start + 1;
  1231. if (start >= min) {
  1232. if (!adjust_resource(res, start, len))
  1233. return 0;
  1234. }
  1235. start = res->start;
  1236. len = ((size + res->end + align) &~ (align - 1)) - start;
  1237. if (start + len <= max) {
  1238. if (!adjust_resource(res, start, len))
  1239. return 0;
  1240. }
  1241. return -EBUSY;
  1242. }
  1243. /*
  1244. * Dino calls this function. Beware that we may get called on systems
  1245. * which have no IOC (725, B180, C160L, etc) but do have a Dino.
  1246. * So it's legal to find no parent IOC.
  1247. *
  1248. * Some other issues: one of the resources in the ioc may be unassigned.
  1249. */
  1250. int ccio_allocate_resource(const struct parisc_device *dev,
  1251. struct resource *res, unsigned long size,
  1252. unsigned long min, unsigned long max, unsigned long align)
  1253. {
  1254. struct resource *parent = &iomem_resource;
  1255. struct ioc *ioc = ccio_get_iommu(dev);
  1256. if (!ioc)
  1257. goto out;
  1258. parent = ioc->mmio_region;
  1259. if (parent->parent &&
  1260. !allocate_resource(parent, res, size, min, max, align, NULL, NULL))
  1261. return 0;
  1262. if ((parent + 1)->parent &&
  1263. !allocate_resource(parent + 1, res, size, min, max, align,
  1264. NULL, NULL))
  1265. return 0;
  1266. if (!expand_ioc_area(parent, size, min, max, align)) {
  1267. __raw_writel(((parent->start)>>16) | 0xffff0000,
  1268. &ioc->ioc_regs->io_io_low);
  1269. __raw_writel(((parent->end)>>16) | 0xffff0000,
  1270. &ioc->ioc_regs->io_io_high);
  1271. } else if (!expand_ioc_area(parent + 1, size, min, max, align)) {
  1272. parent++;
  1273. __raw_writel(((parent->start)>>16) | 0xffff0000,
  1274. &ioc->ioc_regs->io_io_low_hv);
  1275. __raw_writel(((parent->end)>>16) | 0xffff0000,
  1276. &ioc->ioc_regs->io_io_high_hv);
  1277. } else {
  1278. return -EBUSY;
  1279. }
  1280. out:
  1281. return allocate_resource(parent, res, size, min, max, align, NULL,NULL);
  1282. }
  1283. int ccio_request_resource(const struct parisc_device *dev,
  1284. struct resource *res)
  1285. {
  1286. struct resource *parent;
  1287. struct ioc *ioc = ccio_get_iommu(dev);
  1288. if (!ioc) {
  1289. parent = &iomem_resource;
  1290. } else if ((ioc->mmio_region->start <= res->start) &&
  1291. (res->end <= ioc->mmio_region->end)) {
  1292. parent = ioc->mmio_region;
  1293. } else if (((ioc->mmio_region + 1)->start <= res->start) &&
  1294. (res->end <= (ioc->mmio_region + 1)->end)) {
  1295. parent = ioc->mmio_region + 1;
  1296. } else {
  1297. return -EBUSY;
  1298. }
  1299. /* "transparent" bus bridges need to register MMIO resources
  1300. * firmware assigned them. e.g. children of hppb.c (e.g. K-class)
  1301. * registered their resources in the PDC "bus walk" (See
  1302. * arch/parisc/kernel/inventory.c).
  1303. */
  1304. return insert_resource(parent, res);
  1305. }
  1306. /**
  1307. * ccio_probe - Determine if ccio should claim this device.
  1308. * @dev: The device which has been found
  1309. *
  1310. * Determine if ccio should claim this chip (return 0) or not (return 1).
  1311. * If so, initialize the chip and tell other partners in crime they
  1312. * have work to do.
  1313. */
  1314. static int __init ccio_probe(struct parisc_device *dev)
  1315. {
  1316. int i;
  1317. struct ioc *ioc, **ioc_p = &ioc_list;
  1318. struct pci_hba_data *hba;
  1319. ioc = kzalloc(sizeof(struct ioc), GFP_KERNEL);
  1320. if (ioc == NULL) {
  1321. printk(KERN_ERR MODULE_NAME ": memory allocation failure\n");
  1322. return -ENOMEM;
  1323. }
  1324. ioc->name = dev->id.hversion == U2_IOA_RUNWAY ? "U2" : "UTurn";
  1325. printk(KERN_INFO "Found %s at 0x%lx\n", ioc->name,
  1326. (unsigned long)dev->hpa.start);
  1327. for (i = 0; i < ioc_count; i++) {
  1328. ioc_p = &(*ioc_p)->next;
  1329. }
  1330. *ioc_p = ioc;
  1331. ioc->hw_path = dev->hw_path;
  1332. ioc->ioc_regs = ioremap(dev->hpa.start, 4096);
  1333. if (!ioc->ioc_regs) {
  1334. kfree(ioc);
  1335. return -ENOMEM;
  1336. }
  1337. ccio_ioc_init(ioc);
  1338. ccio_init_resources(ioc);
  1339. hppa_dma_ops = &ccio_ops;
  1340. hba = kzalloc(sizeof(*hba), GFP_KERNEL);
  1341. /* if this fails, no I/O cards will work, so may as well bug */
  1342. BUG_ON(hba == NULL);
  1343. hba->iommu = ioc;
  1344. dev->dev.platform_data = hba;
  1345. #ifdef CONFIG_PROC_FS
  1346. if (ioc_count == 0) {
  1347. proc_create_single(MODULE_NAME, 0, proc_runway_root,
  1348. ccio_proc_info);
  1349. proc_create_single(MODULE_NAME"-bitmap", 0, proc_runway_root,
  1350. ccio_proc_bitmap_info);
  1351. }
  1352. #endif
  1353. ioc_count++;
  1354. return 0;
  1355. }
  1356. /**
  1357. * ccio_init - ccio initialization procedure.
  1358. *
  1359. * Register this driver.
  1360. */
  1361. void __init ccio_init(void)
  1362. {
  1363. register_parisc_driver(&ccio_driver);
  1364. }